Digital System Design
Lecture # 5
Introduction to Logic Circuits
ENGR. DR. MUHAMMAD AQEEL ASLAM
ASSISTANT PROFESSOR
SCHOOL OF ENGINEERING AND APPLIED SCIENCES
ELECTRICAL ENGINEERING DEPARTMENT
GIFT UNIVERSITY
GUJRANWALA
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Styles
Structural - instantiation of primitives and modules
RTL/Dataflow - continuous assignments
Behavioral - procedural assignments
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Style Example - Structural
module full_add (A, B, CI, S, CO) ; module half_add (X, Y, S, C);
input A, B, CI ; input X, Y ;
output S, CO ;
output S, C ;
wire N1, N2, N3;
half_add HA1 (A, B, N1, N2), xor (S, X, Y) ;
HA2 (N1, CI, S, N3); and (C, X, Y) ;
or P1 (CO, N3, N2);
endmodule endmodule
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Style Example - RTL/Dataflow
module fa_rtl (A, B, CI, S, CO) ;
input A, B, CI ;
output S, CO ;
assign S = A ^ B ^ CI; //continuous assignment
assign CO = A & B | A & CI | B & CI; //continuous
assignment
endmodule
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Style Example - Behavioral
module fa_bhv (A, B, CI, S, CO) ;
input A, B, CI ;
output S, CO ;
reg S, CO; // required to “hold” values between events.
always@(A or B or CI) //;
begin S <= A ^ B ^ CI; // procedural assignment
CO <= A & B | A & CI | B & CI; // procedural assignment
end
endmodule
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Blocks
Concurrent Blocks
Blocks of code that seem to execute in the same point in time
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Concurrent Blocks
Types
Procedural
Initial
Always
Continuous assignments
assign
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Procedural blocks
Two Types
Initial:: executes only once at time zero
always: block is active throughout the simulation
Within each block, all statements executed sequentially
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Initial Block
Definition: Executes once at time zero
Example
module test;
reg a, b;
wire out;
2inputAND (out, a, b); // AND gate instance
initial
begin a = 0;
b = 0;
end
endmodule
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Always Block
Definition: Executes every time a Example
specified event occurs e.g
clock edge module ANDgate;
Syntax wire a, b;
always @ (sensitivity list / event) always @ (a or b) b i
begin
begin
……
End
out = a & b;
end
endmodule
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Continuous Assignments
Continuous assignments
Single statement which executes continuously and does not
wait for any event to occur
Syntax
assign a = b + c;
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Concurrent Execution
All procedural blocks execute
concurrently
Allows you to model the
inherent concurrency in
hardware
All procedural blocks are
activated at time 0, waiting to
be executed upon specified
conditions
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Signal Values and Resolution
‘0’: Zero, Low, False, Logic Low, Ground, VSS, Negative Assertion
‘1’: One, High, True, Logic High, Power, VDD, VCC, Positive
Assertion
‘X’: Unknown: Occurs at Logical Conflict which cannot be
resolved
‘Z’: Hi-Z: High Impedance, Tri-stated, Disabled Driver
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Sensitivity List
Signals or events that trigger the execution of a
statement or a block of statements
Constantly monitored by the simulator
A large sensitivity list degrades simulation performance
Example:: always @ (posedge clock or reset)
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Numbers in Verilog
Format number of bits’ radix value
Number of bits and radix are optional
Default no. of bits = 32, default radix = decimal
Letter used for radix b binary, d decimal, o octal, h hexadecimal.
Case insensitive.
White spaces OK, except between ‘ and radix
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Data Types in Verilog
Wire: Connect modules or primitives in a design, Can’t
retain their value
Registers: Can hold their value
Integers: 32 bit signed numbers
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Data Types in Verilog: Wire
Wire:
Connects modules or primitives
Wires can’t store their values, must be driven
Wire can be one bit wide or more than one bit wide (vector)
Examples,
wire a; // declares a as a wire
wire x, y, z; // declares x, y, z as three wires
wire [7:0] b, c, d; // declares b, c, d as three 8-bit vector wires
default data type in Verilog
module ports are implicitly defined as wire by Verilog
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Data Types in Verilog: Wire
Wire (example 1)
c is explicitly defined as a wire
three other wires in this module, y,
a, b, are also port modules
y, a, b are implicitly defined as
wires
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Data Types in Verilog : Reg
Registers: Examples,
Registers (unlike wires) can reg a; // declares a as a
store values register
Registers
can be one bit, or reg x, y; // defines x and y
more than one bit (vectors) as two registers
Driven Outputs need to be of reg [4:0] b; // declares b
type reg as a 5-bit (vector) register
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Data Types in Verilog (contd.)
Registers (example):
The output port q is defined as
a one bit register
q is assigned the value of
input d at the positive edge of
the input clk
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Data Types in Verilog (contd.)
Integers
Integers are 32 bit wide in Verilog
Integers are signed numbers
example,
integer j, k, l; // declares three integers
Keyword ‘integer’, NOT ‘int’
Main difference between integer and reg is signed, reg is unsigned
Integers cannot have bit-selects ie. J [4:0]
Integers are not recommended for synthesis
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Data Types in Verilog (contd.)
Integer: examples
integer j, k, l; // declares j, k, l as three integer
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Difference between scalar and a
vector
Scalar: reg a, b
Vector: reg [4:0] A, B;
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Strings
No explicit data type
Must be stored in reg whose size is 8*(num. of
characters)
reg [255:0] buffer; //stores 32 characters
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Constants (Paramters)
Declaration of parameters
parameter A = 2’b00, B = 2’b01, C = 2’b10;
parameter regsize = 8;
reg [regsize - 1:0]; /* illustrates use of parameter regsize */
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FPGA Device Present on the Digilent
Spartan-3E Starter Kit Board
