INTERNSHIP

ANDHRA PRADESH
STATE COUNCIL OF HIGHER EDUCATION
(A STATUTORY BODY OF GOVERNMENT OF ANDHRA PRADESH)
 PROGRAM BOOK FOR
INTERNSHIP
Name of the Student : E. PRASANTH

Name of the College : CHIRALA ENGINEERING COLLEGE

Registration Number : 21E95A0407

Period of Internship : 16 Weeks

From: 7-02-2024 To: 24-05-2024

Name & Address of the Intern Organization: Maven Silicon Ind Pvt
Ltd, Bangalore

CHIRALA ENGINEERING COLLEGE, CHIRALA

Year: 2024
 Internship Report on

VLSI DESIGN USING VERILOG HDL

An internship report in partial fulfilment of the requirements for the Award of the Degree of
BACHELOR OF TECHNOLOGY
in
ELECTRONICS AND COMMUNICATION ENGINEERING
Submitted
by

E. PRASANTH– 21E95A0407

Under the Esteemed Guidance of

Ms. R. Radha Kumari M. Tech (Ph.D.).,
Associate Professor

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

CHIRALA ENGINEERING COLLEGE

(Approved by AICTE - New Delhi, Affiliated to JNTU - Kakinada,
Awarded 'A' Grade by APSCHE, An ISO 9001:2008 Certified
Institution)
RAMAPURAM BEACH ROAD, CHIRALA – 523157, ANDHRA PRADESH
Academic Year: 2023 – 2024
 Instructions to Students

Please read the detailed Guidelines on Internship hosted on the website of AP State Council of
Higher Education https://apsche.ap.gov.in

1. It is mandatory for all the students to complete Semester internship either in V

Semester or in VI Semester.
2. Every student should identify the organization for internship in consultation with
the College Principal/the authorized person nominated by the Principal.
3. Report to the intern organization as per the schedule given by the College. You must
make your own arrangements for transportation to reach the organization.
4. You should maintain punctuality in attending the internship. Daily attendance is
compulsory.
5. You are expected to learn about the organization, policies, procedures, and
processes by interacting with the people working in the organization and by
consulting the supervisor attached to the interns.
6. While you are attending the internship, follow the rules and regulations of the intern
organization.
7. While in the intern organization, always wear your College Identity Card.
8. If your college has a prescribed dress as uniform, wear the uniform daily, as you
attend to your assigned duties.
9. You will be assigned a Faculty Guide from your College. He/She will be creating a
WhatsApp group with your fellow interns. Post your daily activity done and/or any
difficulty you encounter during the internship.
10. Identify five or more learning objectives in consultation with your Faculty Guide.
These learning objectives can address:
a. Data and Information you are expected to collect about the organization
and/or industry.
b. Job Skills you are expected to acquire.
c. Development of professional competencies that lead to future career success.
11. Practice professional communication skills with team members, co-interns, and your
supervisor. This includes expressing thoughts and ideas effectively through oral,
written, and non-verbal communication, and utilizing listening skills.
12. Be aware of the communication culture in your work environment. Follow up and
communicate regularly with your supervisor to provide updates on your progress
with work assignments.
13. Never be hesitant to ask questions to make sure you fully understand
what you need to do your work and to contribute to the organization.
14. Be regular in filling up your Program Book. It shall be filled up in your
own handwriting. Add additional sheets wherever necessary.
15. At the end of internship, you shall be evaluated by your Supervisor
of the intern organization.
16. There shall also be evaluation at the end of the internship by the
Faculty Guide and the Principal.
17. Do not meddle with the instruments/equipment you work with.
18. Ensure that you do not cause any disturbance to the regular activities of
the intern organization.
19. Be cordial but not too intimate with the employees of the intern
organization and your fellow interns.
20. You should understand that during the internship programme, you are the
ambassador of your college, and your behavior during the internship
programmed is of at most importance.
21. If you are involved in any discipline related issues, you will be withdrawn
from the internship programme immediately and disciplinary action shall
be initiated.
22. Do not forget to keep up your family pride and prestige of your college.
 Student’s Declaration

I, E. PRASANTH a student of B. Tech Program, Reg. No. 21E95A0407 of

Department of Electronics and Communication Engineering, CHIRALA
ENGINEERING COLLEGE do hereby declare that I have completed the
mandatory internship from 7-2-2023 to 24-05-2024 in Maven Silicon Ind Pvt Ltd,
Bangalore under the Faculty Guideship of Ms. R. RADHA KUMARI M. Tech
(Ph.D)., Department of Electronics and communication Engineering, Chirala
Engineering College.

(Signatory with Date and Seal)

Endorsements

Faculty Guide :

Head of the Department :

Principal :
Certificate from Intern Organization
 Acknowledgements

An Endeavour over a long period can be successful only with and advice and support of many
well-wishers. I take this opportunity to express our gratitude and appreciation to all of those
who encouraged us for successfully completion of the Semester Internship.

Our special thanks to our Principal Dr. D. Jagadish M. Tech, Ph.D who provide all the
required facilities and helped in accomplishing the Semester Internship report with in time.

We are thankful to our Head of the Department Ms. R. RADHA KUMARI M. Tech (Ph.D).,
for her valuable guidance and effects throughout the Semester Internship.

We are thankful to our Project Co-Ordinator Ms. R. RADHA KUMARI M. Tech (Ph.D)., for
her valuable guidance and effects throughout the project work.

I am also thankful to Maven Silicon, for their encourage to us throughout this Semester
Internship.

Finally, I would like to extend my deep sense of gratitude to all faculty members, friends and
last but not greatly indebted to our parents who inspired us at all circumstances.

INTERNSHIP ASSOCIATE

E. Prasanth
 CONTENTS

S. No Name of the chapter Pg. No

1. Executive Summary 1-2

2. Overview of the Project 3-5

3. Internship Part 4-7

4. Activity Logs & Weekly Reports 8-39

5. Project Specifications 40-48

6. Implementation of Project 49-62

7. Outcomes Description 63-68

8. Conclusion 69

9. Photos & Video Links 70

 CHAPTER- 1

EXECUTIVE SUMMARY

The internship experience at Maven Silicon Pvt Ltd Banglore provided valuable
insights and hands-on experience in leveraging VLSI design. This executive
summary encapsulates the key learnings and outcomes achieved during the
internship period.

Learning Objectives

Fundamental Concepts: Understand the fundamental principles and

concepts of VLSI design and verification, including digital electronics, CMOS
technology, and ASIC design flow.

RTL Design: Learn Register Transfer Level (RTL) coding using hardware
description languages like Verilog and VHDL, including synthesis, simulation, and
optimization techniques.

ASIC Design Flow: Gain a comprehensive understanding of the entire ASIC

design flow, from specification through synthesis, place and route, to timing
analysis and sign-off.

Functional Verification: Master the art of functional verification, including

testbench development, simulation, debugging, and verification methodologies
like UVM (Universal Verification Methodology).

Timing Analysis: Learn advanced timing analysis techniques, including static

timing analysis (STA), setup and hold time analysis, and constraints.

Outcomes Achieved

Skill Development: Maven Silicon aims to equip individuals with the necessary
skills and knowledge required to excel in the field of VLSI design. This includes
proficiency in hardware description languages (such as Verilog, VHDL), ASIC
design flow, RTL coding, and verification techniques.

1
Industry Readiness: The training programs focus on making participants
industry-ready by providing them with hands-on experience with industry-
standard tools and methodologies used in VLSI design. This includes tools for
synthesis, simulation, and physical design.

Employability: Maven Silicon endeavors to enhance the employability of its

participants by offering training that is aligned with the current requirements of
the semiconductor industry. This includes imparting knowledge about the latest
trends, technologies, and best practices in VLSI design.

Certification: Maven Silicon provides certification upon successful completion

of its training programs. These certifications validate the participants'
proficiency in VLSI design and can enhance their credibility in the job market.

Career Advancement: Participants are equipped with the skills and

knowledge necessary to pursue career opportunities in various roles within the
semiconductor industry, including VLSI design, verification, and validation.

2
 CHAPTER-2
OVERVIEW OF THE ORGANIZATION

2.1 Introduction of the Organization

Expert Faculty: Maven Silicon boasts a team of highly experienced and

industry-leading faculty members who bring with them a wealth of knowledge and
expertise in VLSI design. They provide personalized attention and guidance to
students, ensuring effective learning outcomes.

State-of-the-Art Infrastructure: The training facilities at Maven Silicon are

equipped with state-of-the-art infrastructure, including cutting-edge tools,
software, and laboratories, to provide students with a conducive learning
environment.

Hands-on Experience: Maven Silicon places a strong emphasis on hands-on

learning, allowing students to gain practical experience by working on real-
world projects and assignments. This practical exposure helps students develop
a deeper understanding of VLSI concepts and enhances their employability in
the industry.

2.2 Vision, Mission, and Values of the Organization

Vision: Maven Silicon's vision likely revolves around being a globally

recognized leader in VLSI design education and training.

Mission: Maven Silicon's mission is probably centered on providing high-

quality, industry-relevant education and training in VLSI design. This might
involve offering comprehensive courses, hands-on learning experiences, and
industry collaborations to equip students with the skills and knowledge needed
to succeed in the semiconductor field.

Values: Maven Silicon's values likely reflect its commitment to excellence,

integrity, and innovation. This could include a dedication to maintaining high
academic standards, upholding ethical principles in all aspects of its operations,
and embracing a culture of continuous improvement and adaptability.

3
2.3 Policy of the Organization, in relation to the intern role

Learning Objectives: Maven Silicon would establish clear learning objectives for
interns, aligning their experiences with the goals of their academic programs and
their career aspirations in VLSI design.

Structured Internship Program: Maven Silicon would likely offer a

structured internship program with defined timelines, responsibilities, and
milestones.

Mentorship and Guidance: Maven Silicon would assign mentors or supervisors

to interns who would provide guidance, support, and feedback throughout the
internship period.

2.4 Organizational Structure

Executive Leadership Team: At the top of the organizational hierarchy would

likely be an executive leadership team consisting of key decision-makers such as
the CEO, President, and other top-level executives.

Departments or Divisions: Maven Silicon may have several departments or

divisions responsible for different aspects of its operations.

Faculty and Instructors: Within the education and training department, there
would likely be a team of experienced faculty members and instructors
responsible for delivering courses, designing curriculum, and providing
mentorship to students.

2.5 Roles and responsibilities of the employees in which the

intern is placed

Education and Training Department:

2.5.1 Assist instructors and faculty members in preparing course materials,

assignments, and lab exercises.
2.5.2 Support students during hands-on lab sessions and provide guidance
on using VLSI design tools and software

4
Research and Development Team:

2.5.3 Assist engineers and researchers in conducting experiments, simulations,

and analysis related to VLSI design projects.
2.5.4 Contribute to the development of new algorithms, methodologies, or
design techniques through literature review and experimentation.

Marketing and Sales Department:

2.5.5 Support marketing campaigns and promotional activities by creating content

for social media, blogs, and newsletters related to VLSI design.
2.5.6 Assist in market research and analysis to identify potential customers,
competitors, and market trends.

2.6 Performance of the Organization in terms of turnover, profits,

market reach and market value

Turnover: Maven Silicon's turnover, or revenue, would depend on factors such

as the demand for its training programs, the number of students enrolled in
courses, and the pricing of its services.

Profits: Maven Silicon's profits would be influenced by its revenue and its
operating expenses, including costs related to faculty salaries, facilities,
marketing, and administrative overhead.

Market Reach: Maven Silicon's market reach refers to its ability to attract
students and clients from a wide geographic area and diverse demographics.

2.7 Future Plans of the Organization

Expansion of Course Offerings: Maven Silicon may consider expanding its course
offerings to cover a wider range of topics within the VLSI design domain.

Online Education Initiatives: Maven Silicon could explore opportunities to

expand its online education initiatives, catering to students who prefer flexible
learning options or who are unable to attend in-person classes.

5
 CHAPTER-3
INTERNSHIP PART

During a VLSI design internship at Maven Silicon, interns would typically engage
in a variety of activities and responsibilities aimed at providing them with practical
experience and exposure to the field of VLSI design. Here's a description of some
common activities and responsibilities interns might undertake:

RTL Coding: Interns may be involved in Register Transfer Level (RTL) coding
tasks, where they would write and debug hardware description language (HDL)
code using languages such as Verilog or VHDL. This could involve implementing
digital logic designs, finite state machines, or other functional blocks.

Simulation and Verification: Interns may participate in simulation and

verification activities to ensure the correctness and functionality of their RTL
designs. This could include running simulations using industry-standard tools,
creating testbenches, and analyzing simulation results to identify and fix design
issues.

Synthesis and Optimization: Interns may gain experience in logic synthesis

and optimization processes, where they would convert RTL code into a gate-
level netlist optimized for target hardware platforms. This could involve using
synthesis tools to achieve performance, area, and power objectives.

Physical Design: Interns may assist in physical design tasks, which involve the
placement and routing of logic gates and interconnects to meet timing, area, and
power constraints. This could include floor planning, placement optimization,
and routing using tools such as Cadence Innovus or Synopsys ICC.

Design Analysis: Interns may conduct design analysis to evaluate the

performance, power consumption, and timing characteristics of their designs.
This could involve using tools such as PrimeTime for static timing analysis
(STA) or power analysis tools to estimate power consumption.

6
Documentation and Reporting: Interns may be responsible for documenting their
design processes, methodologies, and results in technical reports or
presentations. This could include describing design specifications, summarizing
analysis findings, and presenting recommendations for design improvements.

Collaboration and Communication: Interns may collaborate with engineers,

mentors, and fellow interns to discuss design challenges, share ideas, and
troubleshoot issues. Effective communication skills, both verbal and written, are
essential for discussing technical concepts and presenting findings.

Professional Development: Interns may have opportunities for professional

development, including attending training sessions, workshops, or seminars on
topics related to VLSI design. They may also receive mentorship and guidance
from experienced professionals to support their learning and career growth.

Overall, the activities and responsibilities of interns during a VLSI design

internship at Maven Silicon would be designed to provide them with hands- on
experience, practical skills, and exposure to the various stages of the VLSI design
flow. Interns would have the opportunity to apply theoretical knowledge to real-
world projects and gain valuable insights into the semiconductor industry.

7
 CHAPTER-4
ACTIVITY LOGS & WEEKLY REPORTS
ACTIVITY LOG FOR FIRST WEEK (1st week)

Day Person In
& Brief description of Learning Outcome Charge
Date the daily activity Signature

Studied about Induction Learnt about overview

Day-1 programme of of internship
internship

Studied about Learnt about Digital

Day-2 Introduction to Digital Electronics
Electronics

Learnt about
Day-3 Studied about
fundamentals of
Fundamentals of Digital
Digital Electronics
Electronics

Day-4 Studied about number Learnt about

system number system

Studied about Learnt about

Day-5
introduction to logic gates introduction to Logic
gates

Day-6 Studied about designing Learnt about

of logic gates designing of logic
gates

8
 WEEKLY REPORT

WEEK – 1 (From Dt………..….. to Dt................... )

To know the basics of number systems and logic gates

In the realm of digital electronics, number systems and logic gates serve as the
fundamental building blocks, laying the groundwork for the intricate circuitry
that powers our modern technology. Number systems provide the framework
for representing and manipulating numerical data, with binary, decimal, octal,
and hexadecimal systems being the most prevalent. Binary, in particular, holds
significance as the backbone of digital computing, utilizing only two digits—0
and 1—to convey information in the form of electrical signals. These signals,
processed through logic gates, undergo Boolean operations to produce desired
outputs. Logic gates, comprising AND, OR, NOT, NAND, NOR, XOR, and
XNOR variations, act as the gatekeepers of digital circuits, orchestrating the
flow of data through manipulation of binary signals. An AND gate, for instance,
yields a high output only when all inputs are high, while an OR gate activates
if any input receives a high signal. These gates, constructed from electronic
components such as transistors, form the intricate networks that underpin our
digital infrastructure, from the simplest calculator to the most advanced
computer processor. In essence, number systems and logic gates constitute the
bedrock of digital technology, enabling the seamless transmission and
processing of information that defines our interconnected world.

9
 ACTIVITY LOG FOR SECOND WEEK (2nd week)

Day Person In
& Brief description of Learning Outcome Charge
Date the daily activity Signature

Studied about Learnt about

Day-1 Introduction to Introduction to
Combinational circuit Combinational circuit

Day-2 Studied about logic Learnt about logic

gates and Adders gates and Adders

Day-3 Studied about Learnt about

Multiplexers Multiplexers

Day-4 Studied about Learnt about

Demultiplexers Demultiplexers

Day-5 Studied about Encoders Learnt about Encoders

and Decoders and Decoders

Day-6 Studied about Learnt about

Comparators Comparators

10
 WEEKLY REPORT

WEEK – 2 (From Dt………..….. to Dt................... )

To know about the combinational circuits

Combinational circuits stand as the backbone of digital electronics, orchestrating the

manipulation and transformation of binary data in myriad applications, from arithmetic
operations in calculators to data processing in computers. Unlike sequential circuits, which
incorporate memory elements to store past inputs, combinational circuits operate solely
based on the current input values. These circuits, constructed from logic gates, form the
cornerstone of digital logic design, executing Boolean operations to produce outputs
determined solely by the present input states. Through the seamless integration of logic
gates—such as AND, OR, NOT, NAND, NOR, XOR, and XNOR—combinational circuits
enact a symphony of logical functions, with each gate playing a unique role in shaping the
circuit's behaviour. An AND gate, for instance, yields a high output only when all inputs
are high, while an OR gate activates if any input receives a high signal. The arrangement
and interconnection of these gates imbue combinational circuits with unparalleled
versatility, enabling them to execute a vast array of computational tasks with remarkable
efficiency. From simple adders and multipliers to intricate data processing units,
combinational circuits serve as the unsung heroes of digital technology, underpinning the
functionality of countless devices that permeate our daily lives.

11
 ACTIVITY LOG FOR THIRD WEEK (3rd week)

Day Person In
& Brief description of Learning Outcome Charge
Date the daily activity Signature

Studied about Learnt about

Day-1 Introduction to Introduction to
Sequential Circuit I Sequential Circuit I

Day-2
Studied about flip flops Learnt about flip flops

Day-3
Studied about Latches Learnt about Latches

Day-4 Learnt about

Studied about Registers
Registers

Day-5 Learnt about

Studied about Clocks
Clocks

Studied about Counters

Day-6 Learnt about
Counters

12
 WEEKLY REPORT

WEEK – 3 (From Dt………..….. to Dt................... )

To know about the sequential circuit-I

Sequential circuits, the stalwarts of digital electronics, represent a sophisticated

marriage of logic and memory, imbuing digital systems with the ability to retain
and process information over time. Unlike their combinatorial counterparts, which
operate solely based on the present input, sequential circuits incorporate memory
elements, typically flip-flops or latches, to store past input states, enabling the
circuit to exhibit dynamic behavior and perform complex sequential operations. At
the heart of sequential circuits lies the concept of feedback, wherein the output of
the circuit feeds back into its input, creating a closed loop of information flow. This
feedback loop, governed by clock signals, orchestrates the precise timing and
sequencing of operations within the circuit, ensuring synchronized execution of
tasks. Whether it's counting pulses in a digital counter, storing data in a register, or
executing instructions in a processor, sequential circuits serve as the backbone of
modern digital systems, enabling them to perform intricate tasks with precision and
reliability. Through the interplay of logic gates, memory elements, and clock
signals, sequential circuits epitomize the synergy between computation and
memory, driving innovation and progress in the realm of digital technology.

13
 ACTIVITY LOG FOR FOURTH WEEK (4th week)
Day Person In
& Brief description of Learning Outcome Charge
Date the daily activity Signature

Studied about Learnt about

Day-1 Introduction to Introduction to
Sequential Circuit II Sequential Circuit II

Studied about universal Learnt about universal

Day-2 shift registers and Ring shift
counters registers and Ring
counters

Day-3 Studied about Johnson Learnt about Johnson

counter and also designing counter and also
designing
Studied about Ripple Learnt about
Day-4 counter and binary Ripple counter and
ripple counter binary ripple counter

Learnt about
Day-5 Studied about BCD ripple about BCD ripple
counter and counter and
functionalities of latches functionalities of
latches

Day-6 Studied about Decade Learnt about Decade

counter counter

14
 WEEKLY REPORT

WEEK – 4 (From Dt………..….. to Dt................... )

To know about the sequential circuit II

Sequential circuits represent a cornerstone of digital electronics, integrating

logic and memory to facilitate complex sequential operations essential for
digital systems. Unlike combinational circuits, which respond instantly to input
changes, sequential circuits incorporate memory elements, typically flip-flops
or latches, to retain past input states and exhibit dynamic behaviour over time.
These circuits are characterized by their ability to store and process information
sequentially, allowing them to execute tasks such as counting, storing data, and
executing instructions. Central to the operation of sequential circuits is the
concept of clock signals, which synchronize the timing and sequencing of
operations within the circuit. These clock signals govern the transition of states
within the memory elements, ensuring precise coordination of data flow and
enabling the circuit to function reliably. Whether it's implementing state machines
in digital controllers, storing program instructions in microprocessors, or
facilitating data transfer in communication systems, sequential circuits play a
pivotal role in the operation of countless digital devices, driving innovation and
advancement in the field of electronics.

15
 ACTIVITY LOG FOR FIFTH WEEK (5th week)

Day Person In
& Brief description of Learning Outcome Charge
Date the daily activity Signature

Studied about to Finite Learnt about

Day-1 state machines (FSMs) Introduction to Finite
state machines
(FSMs)

Day-2 Studied about Mealy Learnt about Mealy

machine machine

Day-3 Studied about Moore Learnt about Moore

machine machine

Studied about Memories

Day-4 Learnt about
Memories

Studied about Random Learnt about

Day-5 access memory (RAM) about Random access
memory (RAM)

Day-6 Studied about Read only Learnt about Read

memory (ROM) only memory (ROM)

16
 WEEKLY REPORT

WEEK – 5 (From Dt………..….. to Dt................... )

To know about the FSMs and Memories

Finite State Machines (FSMs) are models used in computer science and
engineering to represent systems with a finite number of states, transitioning
between these states based on inputs. They are composed of a set of states, a set
of transitions between these states, and a set of inputs that trigger these
transitions. FSMs find applications in various fields including digital logic
design, software engineering, and artificial intelligence. Memories, on the other
hand, are fundamental components of computing systems used to store data and
instructions. Memories come in various types such as RAM (Random Access
Memory), ROM (Read-Only Memory), and cache memory. RAM is volatile and
used for temporary data storage during program execution, while ROM stores
permanent data that cannot be altered. Cache memory acts as a high-speed
intermediary between the CPU and main memory, storing frequently accessed
data to reduce access time. Both FSMs and memories play critical roles in the
operation of digital systems, contributing to their functionality and
performance.

17
 ACTIVITY LOG FOR SIXTH WEEK (6th week)

Day Person In
& Brief description of Learning Outcome Charge
Date the daily activity Signature

Studied about Learnt about

Day-1 introduction to Verilog HDL introduction to Verilog
HDL

Studied about Learnt about

Day-2 programming structure of programming structure
Verilog HDL of Verilog
HDL
Studied about Verilog Learnt about Verilog
Day-3 data types data types

Learnt about
Day-4 Studied about Verilog Verilog programming
programming of data types of data types

Studied about Learnt about about

Day-5 introduction of Verilog introduction of
labs Verilog labs

Studied about Lab 1 Learnt about Lab 1

Day-6 verilog programmes verilog programmes
includes adders etc includes adders etc

18
 WEEKLY REPORT

WEEK – 6 (From Dt………..….. to Dt................... )

To know about introduction of Verilog HDL

Verilog Hardware Description Language (HDL) is a widely-used language in

digital design and verification, allowing engineers to describe and simulate
electronic systems. It provides a means to model complex digital circuits,
including combinational and sequential logic, using a syntax reminiscent of
programming languages. Verilog facilitates the design of hardware at various
levels of abstraction, from high-level behavioural descriptions to detailed gate-
level implementations. Its key features include modules for hierarchical design,
data types for representing signals and variables, and constructs for specifying
timing constraints and control flow. Verilog is extensively used in the design
and verification of digital systems, ranging from simple logic gates to complex
integrated circuits. Its popularity stems from its ease of use, scalability, and
compatibility with various simulation and synthesis tools, making it an
indispensable tool in the field of digital design.

19
 ACTIVITY LOG FOR SEVENTH WEEK (7th week)

Day Person In
& Brief description of Learning Outcome Charge
Date the daily activity Signature

Studied about Learnt about

Day-1 introduction to Verilog introduction to Verilog
operators operators

Learnt about Verilog

Day-2 Studied about Verilog Arithmetic operators
Arithmetic operators

Studied about Verilog Learnt about Verilog

Day-3 relational operators and relational operators
Verilog equality and Verilog equality
operators operators
Learnt about Verilog
Day-4 Studied about Verilog logical operators and
logical operators and Verilog bitwise
Verilog bitwise operators operators
Studied about Verilog Learnt about
Day-5 shift operators and Verilog shift operators
introduction of Verilog and introduction of
labs Verilog labs
Studied about Lab 2 Learnt about Lab 2
Day-6 verilog programmes verilog programmes
includes Verilog includes Verilog
operators etc operators etc

20
 WEEKLY REPORT

WEEK – 7 (From Dt………..….. to Dt................... )

To know about Verilog operators

Verilog operators are essential components of the Verilog Hardware

Description Language (HDL), enabling designers to perform various
operations on signals and data within digital circuits. These operators
encompass a wide range of functionalities, including arithmetic, logical,
bitwise, and relational operations. Arithmetic operators like addition,
subtraction, multiplication, and division are used to perform mathematical
computations. Logical operators such as AND, OR, NOT, and XOR are
employed for boolean logic operations, manipulating binary data. Bitwise
operators operate on individual bits of data, enabling operations like shifting,
rotating, and masking. Relational operators like equality, inequality, greater
than, and less than are utilized for comparing values and determining the
outcome of conditional statements. Verilog operators play a crucial role in
specifying the behavior and functionality of digital circuits, allowing designers
to express complex operations concisely and efficiently within their HDL
designs.

21
 ACTIVITY LOG FOR EIGHTH WEEK(8th week)

Day Person In
& Brief description of Learning Outcome Charge
Date the daily activity Signature

Studied about Learnt about

Day-1 introduction to introduction to
Advanced Verilog for Advanced Verilog for
Verification Verification
Learnt about
Day-2 Studied about Arithmetic circuits
Arithmetic circuits and and data processing
data processing circuits circuits
Studied about universal Learnt about
Day-3 logic elements and universal logic
combinational circuits- elements and
design and analysis combinational
circuits-design and
analysis
Learnt about Latches,
Day-4 Studied about Latches, flip flops and shift
flip flops and shift registers, counters
registers, counters
Studied about Advanced Learnt about Advanced
Day-5 Verilog for Verification Verilog for Verification
labs labs

Studied about Lab 3 Learnt about Lab 3

Day-6 verilog programmes Advanced Verilog for
Verification labs

22
 WEEKLY REPORT

WEEK – 8 (From Dt………..….. to Dt................... )

To know about Advanced Verilog for Verification

Advanced Verilog for Verification extends the capabilities of Verilog HDL

specifically for verification purposes in digital design. It encompasses a variety of
features and methodologies aimed at improving the efficiency and effectiveness
of verification processes. This includes constructs for creating complex test
scenarios, such as randomization and constraint-based random testing, which
enable thorough testing of digital designs by generating a diverse set of test
cases automatically. Additionally, Advanced Verilog for Verification
incorporates techniques for creating reusable and scalable verification
environments, such as the Universal Verification Methodology (UVM), which
provides a standardized framework for creating modular, reusable testbenches.
Furthermore, it includes features for functional coverage analysis, allowing
verification engineers to measure the completeness of their test suites by
tracking which parts of the design have been exercised during simulation.
Overall, Advanced Verilog for Verification equips verification engineers with
powerful tools and methodologies to ensure the correctness and reliability of
digital designs through comprehensive verification processes.

23
 ACTIVITY LOG FOR NINETH WEEK (9th week)

Day Person In
& Brief description of Learning Outcome Charge
Date the daily activity Signature

Learnt about
Day-1 Studied about introduction to
introduction to Verilog Verilog assignments
assignments
Learnt about types of
Day-2 Studied about types of Verilog assignments includes
Verilog assignments includes procedural, continuous
procedural, continuous assignments etc
assignments etc

Studied about Learnt about

Day-3 introduction to introduction to
structured procedures structured
procedures
Learnt about types of
Day-4 Studied about types of structured procedures
structured procedures includes always
includes always statement, statement, function and
function and task etc task etc

Studied about Verilog Learnt about

Day-5 assignments labs Verilog assignments
labs

Studied about Lab 4 Learnt about Lab 4

Day-6 verilog assignment verilog assignment
programmes programmes

24
 WEEKLY REPORT

WEEK – 9 (From Dt………..….. to Dt................... )

To know about Verilog assignments

Verilog assignments are fundamental operations used to assign values to signals

or variables within a hardware description. These assignments facilitate the
modelling of digital circuits by specifying the behavior and interactions of
signals over time. Verilog supports various types of assignments, including
continuous assignments using the ‘assign’ keyword, which define a continuous
connection between a signal and an expression. Blocking assignments (‘=’) and
non-blocking assignments (‘<=’) are used within procedural blocks such as
‘always’ blocks to specify the order of execution and update of signals.
Blocking assignments update signals immediately within the current time step,
whereas non-blocking assignments schedule updates to occur at the end of the
time step, enabling sequential execution. Verilog assignments play a crucial role
in defining the functionality and behaviour of digital circuits, allowing designers
to model complex interactions and logic within their designs accurately.

25
 ACTIVITY LOG FOR TENTH WEEK (10th week)

Day Person In
& Brief description of Learning Outcome Charge
Date the daily activity Signature

Learnt about
Day-1 Studied about
introduction to verilog
introduction to verilog
Synthesis Coding styles
Synthesis Coding styles

Day-2 Studied about Learnt about

Behavioural modelling Behavioural
modelling
Studied about gate/switch Learnt about
Day-3 level modelling gate/switch level
modelling

Learnt about data flow

Day-4 Studied about data flow modelling
modelling

Studied about verilog Learnt about

Day-5 Synthesis Coding styles verilog Synthesis
labs Coding styles labs

Studied about Lab 5 Learnt about Lab 5

Day-6 verilog Synthesis Coding verilog Synthesis
styles labs Coding styles labs

26
 WEEKLY REPORT

WEEK – 10 (From Dt………..….. to Dt. .................. )

To know about verilog Synthesis Coding styles

Verilog Synthesis Coding styles are methodologies employed in writing Verilog

code specifically optimized for synthesis, aiming to produce efficient hardware
implementations from the description. These coding styles involve techniques and
conventions that facilitate the translation of Verilog code into physical
hardware, maximizing performance, minimizing area utilization, and reducing
power consumption. One prevalent coding style is RTL (Register Transfer
Level) coding, which focuses on describing the behavior of a digital circuit in
terms of data transfers between registers. RTL coding emphasizes the use of
synchronous logic, where operations are synchronized to a clock signal,
enabling efficient and predictable hardware synthesis. Another common
approach is structural coding, which involves explicitly specifying the
interconnection of primitive hardware components like gates, multiplexers, and
flip-flops. Structural coding provides fine-grained control over the hardware
implementation and can be advantageous for optimizing critical paths or
meeting specific design constraints. Additionally, there's behavioral coding,
which describes the desired functionality of a circuit without specifying the
underlying hardware implementation. While behavioral coding offers flexibility
and ease of design, it may require additional effort in synthesis optimization to
achieve efficient hardware implementations. Overall, Verilog Synthesis Coding
styles are tailored to the requirements of hardware synthesis, allowing designers
to produce optimized and reliable hardware from their Verilog descriptions.

27
ACTIVITY LOG FOR ELEVENTH WEEK (11th week)

Day Person In
& Brief description of Learning Outcome Charge
Date the daily activity Signature

Learnt about
Day-1 Studied about
introduction to FSMs
introduction to FSMs

Day-2 Studied about design of Learnt about design of

FSMs using Verilog FSMs using Verilog
synthesis code styles synthesis code styles

Studied about design of Learnt about design of

Day-3 mealy machine using mealy machine using
Verilog synthesis code Verilog
styles synthesis code styles
Studied about design of Learnt about design of
Day-4 moore machine using moore machine using
Verilog synthesis code Verilog
styles synthesis code styles

Day-5 Studied about verilog Learnt about

FSMs labs verilog FSMs labs

Studied about Lab 6 Learnt about Lab 6

Day-6 verilog FSMs labs verilog FSMs labs

28
 WEEKLY REPORT

WEEK – 11 (From Dt………..….. to Dt. .................. )

To know about FSMs using Verilog synthesis coding styles

Finite State Machines (FSMs) implemented using Verilog synthesis coding

styles leverage various techniques to produce efficient and optimized hardware
designs. RTL (Register Transfer Level) coding is commonly employed to describe
the behaviour of FSMs in terms of state transitions and output generation based
on inputs and current states. By using synchronous logic and describing state
transitions as clocked processes within ‘always’ blocks, RTL coding ensures
predictable and efficient hardware synthesis. FSMs can also be implemented
using structural coding, where the FSM's states, transitions, and outputs are
explicitly defined using primitive hardware components such as flip-flops and
combinational logic gates. This approach offers fine-grained control over the
hardware implementation, enabling designers to optimize critical paths and
minimize resource usage. Additionally, behavioral coding allows FSMs to be
described at a higher level of abstraction, focusing on the functionality without
specifying the hardware implementation details. While behavioural coding
provides flexibility, it may require additional synthesis optimization efforts to
achieve efficient hardware designs. Overall, Verilog synthesis coding styles offer
designers the flexibility to implement FSMs in a manner that meets their design
requirements while ensuring efficient hardware synthesis and optimal
performance.

29
ACTIVITY LOG FOR TWELVETH WEEK (12th week)

Day Person In
& Brief description of Learning Outcome Charge
Date the daily activity Signature

Day-1 Studied about project Learnt about project

analysis analysis

Day-2 Studied about block of

Learnt about block of
SPI SPI

Day-3 Studied about top Learnt about top

level module level module

Day-4 Studied about Learnt about

types of sub types of sub
modules modules
Studied about top Learnt about
Day-5 level RTL top level RTL
schematic schematic

Studied about Learnt about

Registers and IO ports
Day-6 Registers and IO Ports

30
 WEEKLY REPORT

WEEK – 12 (From Dt………..….. to Dt. .................. )

Objective of the activity done: To know about project as a designing SPI

Detailed Report: The serial peripheral interface is a serial communication protocol used for
short distance communication primary between microcontroller sensors and other peripheral
device implementing SPI involves both hardware and software components. In the
implementation of SPI controller initiates and store device are the key components. Typically,
a microcontroller are dedicated SPI controller initiates and control a communication. If
generates the clock signals and co-ordinates data transfer. Peripheral components such as
sensors, Memory chips or other microcontrollers that respond to commands from the master
device.
In SPI follows the same of communication lines such as serial clock generated by master core.
If synchronizes data transfer, transmits data from master to the slave, master in slave out
transmit data from the store to mask. The simious that selected slave device to short
communication by slave select.
The Scenario of implementation of SPI, where a microcontroller, acting as the
master, initiates. The SPI bus, configures communication protocols & selects each peripheral
device Sequentially using the slave select lines. If sends requests data to the selected device
via the master of the slave in (MOSI) line which while simultaneously receiving responses
from the device through the master in slave out (MISO) line. The SPI communication protocol
is defined based on the specifications of each peripheral device including clock speed, data
format and command structure. By effectively managing the SPI bus and co-ordinating data
exchange between the master and slave. The Microcontroller retrieves sensor readings, store
data on to SD card and perform various other tasks, demonstrating the versatility & efficiency
of the SPI control in the facility serial communication between multiple devices within an
embedded system.

31
ACTIVITY LOG FOR THIRTEENTH WEEK (13th week)

Day Person In
& Brief description of Learning Outcome Charge
Date the daily activity Signature

Learnt about
Day-1 Studied about
implementation of
implementation of
project
project

Learnt about Serial

Day-2 Studied about Serial
clock genrator
clock generator

Studied about RTL code Learnt about RTL

Day-3 in Serial clock code in Serial clock
generator generator

Studied about test Learnt about test

Day-4 bench code in Serial bench code in Serial
clock generator clock generator

Studied about Clock Learnt about

generator Divider
Day-5 generator Divider
length
length

Studied about RTL Learnt about RTL

&Test bench code in
Day-6 &Test bench code in
Shift register
Shift register

32
 WEEKLY REPORT

WEEK – 13 (From Dt………..….. to Dt. .................. )

Objective of the Activity Done:

To know about implementation of project in serial clock generator of SPI
using RTL and TB code
Detailed Report: Analysing the project specification for an SPI design involves breaking
down the requirements into functional components. it includes:
1)function requirement: the core functionalities such as setting the time, setting SPI, SPI
triggering and functionality
2) user interface: Specify the user inputs and outputs required for interfacing the SPI
3) Power management: Address power sources requirements, power saving modes and backup
power options.
4)Integration: The compatibility with other devices and systems, such as synchronization with
smart phones.
5)Reliability and safety: Ensure reliability in time keeping accuracy, SPI triggering like over
heat protection.
6)SPI Features: Details the SPI settings including multiple alarms SPI volume control and SPI
tone selection

33
ACTIVITY LOG FOR FOURTEENTH WEEK (14th week)

Day Person In
& Brief description of Learning Outcome Charge
Date the daily activity Signature

Learnt about test

Day-1 Studied about RTL
bench code in Shift
&Test bench code in Register
Learnt about
Shift register
implementation of
project
Learnt about
Studied about Shift
Day-2
Register Shift Register
Divider length Divider length
Studied about Learnt about
Day-3 implementation of project implementation of
project

Studied about Learnt about SPI Top

Day-4
SPI Top

Studied about Learnt about RTL code

Day-5
RTL code in in SPI Top
SPI Top

Studied about Learnt about

Day-6
Test bench code in Test bench code in
SPI Top SPI Top

34
 WEEKLY REPORT

WEEK – 14 (From Dt………..….. to Dt. .................. )

Objective of the Activity Done:

To know about implementation of project in shift register using RTL
and TB code
Detailed Report: The SPI registers are used to save the data receive registers hold the value
of received of the data of the last executed. Valid bits depend on the character length field on
the CTRL, Register. If this bit is set, the LSB is sent first on the line and the first bit received
from the line will be put in the LSB positive in the Rx Register.
This field specifies how many bits are transmitted in one transfer. Up to 64 bits can be
transmitted. The value in this field is the frequency divider of the system clock. Wb – clk – I
to generate the serial clock on the output sclk-pad-o. The desired frequency is obtained
according to the bit is set; the interrupt output is set active after a transfer is finished. The
interrupt signal is decreased after a Read or Write to any Register.

35
ACTIVITY LOG FOR FIFTEENTH WEEK (15th Week)

Day Person In
& Brief description of Learning Outcome Charge
Date the daily activity Signature

Day-1
Studied about the Learnt about the
Wishbone Interface Wishbone Interface

Learnt about RTL code in Learnt about RTL

Day-2
Wishbone Interface code in Wishbone
Interface

Learnt about test

Day-3 Studied about test bench bench code in
code in Wishbone Wishbone Interface
Interface

Studied about Learnt about

Day-4
SPI Slave SPI Slave

Learnt about RTL

Day-5 Studied about RTL
code in SPI Slave
code in SPI Slave

Studied about Test bench Learnt about Test

Day-6
code in SPI Slave bench code in SPI
Slave

36
 WEEKLY REPORT

WEEK – 15 (From Dt……...….. to Dt. ..................... )

Objective of the Activity Done:

To know about implementation of project in SPI Top module, SPI master
core
SPI slave using RTL and TB code
Detailed Report: SPI master core refers to the control component or module within a
microcontroller and dedicated hardware unit responsible for initial controlling SPI
communication. In an SPI setup, there are typically two entities. The master device and the
slave device. The SPI master core governs the entire SPI communication process including
clock generation. It generates the clock signal that synchronizes. Data transfer between the
master & slave devices the clock signal frequency and other parameters may be configurable.
Data transmission: The master core handles the transmission of data to the slave device via
master out slave IN line OUT. slave selection reception by master IN slave OUT slave
selection the master core controls the selection of the store device with which it to wants
communicate.

37
 ACTIVITY LOG FOR SIXTEENTH WEEK (16th week)

Day Person In
& Brief description of Learning Outcome Charge
Date the daily activity Signature

Learnt about
Day-1 Studied about
implementation of
implementation of
project
project

Learnt about
Day-2 Studied about designing
designing of SPI Top
of SPI top Module Module verification
verification
Studied about RTL code Learnt about RTL
Day-3 in SPI top Module code in SPI Top
verification Module verification

Studied about Top test Learnt about Top test

Day-4 bench code with bench code with
negations in SPI top negations in SPI Top
Module verification Module verification

Learnt about
Day-5 Studied about the
simulation analysis
simulation analysis using model sim
software
using model sim
software
Studied about Learnt about
simulation analysis
Day-6 simulation analysis
using Quartus lite
using Quartus lite software
software

38
 WEEKLY REPORT

WEEK – 16 (From Dt………..….. to Dt. .................. )

Objective of the Activity Done:

To know about implementation of project in SPI top level verification
Detailed Report:
Wishbone interface
The SPI core has five 32-bit registers through the wishbone rev. BI compatible
interface. All access to SPI registers must be 32-bit ((wb-self) [3:0] =OXF). Please refer to the
Wishbone.
Serial Interface:
The serial interface consists of slave select lines, serial clock lines, as well as input and
output data lines. All transfers access to SPI must be compared to SPI (Microwave protocol).
This core has some additional functionality, it can derive data to the output data lines in respect
to the following functionality. It is important to know that the RxX and TxX registers slave
the same flip-flops, which means that what is received from the input data lines in one transfer
will be transmitted on the output data lines.
Analysis in SPI communication aims to ensure reusable data exchange, optimize
performance and detect communication edging these aspects. Engineers can validate the
functionality and robustness of the SPI implementation

39
 CHAPTER-5
PROJECT SPECIFICATION

INTRODUCTION
This provides specifications for the SPI (Serial Peripheral Interface) Master core. Synchronous
serial interfaces are widely used to provide economical board-level interfaces between
different devices such as microcontrollers, DACS, ADCs and other. Although there is no
single standard for a synchronous serial bus, there are industry-wide accepted guidelines based
on two most popular implementations:
▪ SP1 (a trademark of Motorola Semiconductor)
▪ Microwire/Plus (a trademark of National Semiconductor)

Many IC manufacturers produce components that are compatible with SPI and
Microwire/Plus.
The SPI Master core is compatible with both above-mentioned protocols as master with some
additional functionality. At the hosts side, the core acts like a WISHBONE compliant slave
device.

Features:

▪ Full duplex synchronous serial data transfer

▪ Variable length of transfer word up to 128 bits
▪ MSB or LSB first data transfer
▪ Rx and Tx on both rising or falling edge of serial clock independently
▪ 8 slave select lines
▪ Fully static synchronous design with one clock domain
▪ Technology independent Verilog
▪ Fully synthesizable

40
IO PORTS

2.1 Wishbone interface signals

Port Width Direction Description

wb_clk_i 1 input Master clock
wb_rst_i 1 input Synchronous reset, active high
wb_adr_i 5 input Lower address bits
wb_dat_i 32 input Data towards the core
wb_dat_o 32 output Data from the core
wb_sel_i 4 input Byte select signals
wb_we_i 1 input Write enable input
wb_stb_i 1 input Strobe signal/core select input
wb_cyc_i 1 input Valid bus cycle input
wb_ack_o 1 output Bus cycle acknowledge output
wb_err_o 1 output Bus cycle error output
wb_int_o 1 output Interrupt signal output

Table 1: wishbone interface signals

All output WISHBONE signals are registered and driven on the rising edge of wb_clk_i. All
input WISHBONE signals are latched on the rising edge of wb_clk_i.

41
2.4 SPI external connections

Port Width Direction Description

/ss_pad_o 8 output Slave select output signals
Sclk_pad_o 1 output Serial clock generator
mosi_pad_o 1 output Master out slave in data signal output
miso_pad_i 1 input Master in slave out data signal input

Table 2: SPI external connections

REGISTERS
3.1 Core registers list
Name Address Width Access Description
RX0 0x00 32 R Data receive register 0
RX1 0x04 32 R Data receive register 1
RX2 0x08 32 R Data receive register 2
RX3 0x0c 32 R Data receive register 3
TX0 0x00 32 R/W Data receive register 0
TX1 0x04 32 R/W Data receive register 1
TX2 0x08 32 R/W Data receive register 2
TX3 0x0c 32 R/W Data receive register 3
CTRL 0x10 32 R/W Control and status register
DIVIDER 0x14 32 R/W Clock divider register
SS 0x18 32 R/W Slave select register

Table 3: List of core registers

All registers are 32-bit wide and accessible only with 32 bits (all wh_sel_i signals must be
active).

42
3.2 Data receive registers[rxX]
Bit # 31:0

Access R

Name RX

Table 4: Data receive register

Reset value:0x00000000

RxX The Data Receive registers hold the value of received data of the last executed transfer.
Valid bits depend on the character length field in the CTRL register (i.e. if CTRL [9:3] is set
to 0x08, bit RxL[7:0] holds the received data). If character length is less or equal to 32 bits,
Rx1, Rx2 and Rx3 are not used, if character length is less than 64 bits. Rx2 and Rx3 are not
used and so on.
NOTE: The Data Received registers are read-only registers. A Write to these registers will
actually modify the Transmit registers because those registers share the same FFs.

3.3 Data transmit register[TxX]

Bit # 31:0
Access R/W
Name Tx

Table 5: Data Transmit register

Reset Value: 0x00000000

TxX
The Data Receive registers hold the data to be transmitted in the next transfer. Valid bits
depend on the character length field in the CTRL register (ie. if CTRL[9:3] is set to 0x08, the
bit Tx0[7:0] will be transmitted in next transfer). If character length is less or equal to 32 bits,
Tx1, Tx2 and Tx3 are not used, if character len is less than 64 bits, Tx2 and Tx3 are not used
and so on.

43
3.4 Control and status register [CTRL]

Bit # 31:14 13 12 11 10 9 8 7 6.0

Access R R/W R/W R/W R/W R/W R/W R R/W

Name Reserved ASS IE LSB TX_NEG RX_NEG GO_BSY Reserved CHAR_LEN

Table 6: Control and Status register

Reset Value: 0x00000000
ASS
If this bit is set, ss_pad_o signals are generated automatically. This means that slave select
signal, which is selected in SS register is asserted by the SPI controller, when transfer is started
by setting CTRL[GO_BSY] and is de-asserted after transfer is. Finished. If this bit is cleared,
slave select signals are asserted and de-aserted by writing and clearing bits in SS register.
IE
If this bit is set, the interrupt output is set active after a transfer is finished. The Interrupt
signal is deasserted after a Read or Write to any register.
LSB
If this bit is set, the LSB is sent first on the line (bit TxL[0]), and the first bit received from
the line will be put in the LSB position in the Rx register (bit RxL[0]). If this bit is cleared, the
MSB is transmitted/received first (which bit in TxX/RxX register that is depends on the CHAR
LEN field in the CTRL register).
Tx_NEG
If this bit is set, the mosi pad o signal is changed on the falling edge of a sclk_pad_o clock
signal, or otherwise the mosi_pad_o signal is changed on the rising edge of sclk_pad_o.
Rx NEG
If this bit is set, the miso_pad_i signal is latched on the falling edge of a sclk_pad_o clock
signal, or otherwise the miso_pad_i signal is latched on the rising edge of sclk_pad_o.
GO_BSY
Writing 1 to this bit starts the transfer. This bit remains set during the transfer and is
automatically cleared after the transfer finished. Writing 0 to this bit has no effect.
NOTE: All registers, including the CTRL. register, should be set before writing 1 to the
GO_BSY bit in the CTRL register. The configuration in the CTRI. register must be changed
44
with the GO BSY bit cleared, Le. two Writes to the CTRL register must be executed when
changing the configuration and performing the next transfer, firstly with the GO BSY bit
cleared and secondly with GO BSY bit set to start the transfer. When a transfer is in progress,
writing to any register of the SPI Master core has no effect.
CHAR_LEN
This field specifies how many bits are transmitted in one transfer. Up to 64 bits can be
transmitted.
CHAR LEN = 0x01... 1 bit
CHAR LEN 0x02... 2 hits
CHAR LEN=0x7f... 127 bits
CHAR LEN = 0x00... 128 bits
3.5 Divider register [DIVIDER]
Bit # 31:16 15:0
Access R R/W
Name Reserved DIVIDER

Table 7: Divider register

Reset Value: 0x0000ffff

DIVIDER
The value in this field is the frequency divider of the system clock wb_clk_i to generate the
serial clock on the output sclk_pad_o. The desired frequency is obtained according to the
following equation:

3.6 Slave select register [SS]

Bit # 31:8 7:0

Access R R/W

Table 8: Slave Select register

Reset Value: 0x00000000

45
SS
If CTRL[ASS] bit is cleared, writing 1 to any bit location of this field sets the proper ss_pad_o
line to an active state and writing 0 sets the line back to inactive state. If CTRL[ASS] bit is
set, writing 1 to any bit location of this field will select appropriate ss_pad_o line to be
automatically driven to active state for the duration of the transfer, and will be driven to
inactive state for the rest of the time.

Operation
This core is an SPI and Microwire/Plus compliant synchronous serial controller. At the host
side, it is controlled via registers accessible through a WISHBONE rev. B1 interface.

4.1 wishbone interface

The SPI core has five 32-bit registers through the WISHBONE rev. B1 compatible interface.
All accesses to SPI registers must be 32-bit (wb_sel[3:0] = 0xf). Please refer to the
WISHBONE specification.

4.2 Serial interface

The serial interface consists of slave select lines, serial clock lines, as well as input and output
data lines. All transfers are full duplex transfers of a programmable number of bits per transfer
(up to 64 bits). Compared to the SPI/Microwire protocol, this core has some additional
functionality. It can drive data to the output data line in respect to the falling (SPI/Microwire
compliant) or rising edge of the serial clock, and it can latch data on an input data line on the
46
rising (SP1/Microwire compliant) or falling edge of a serial clock line. It also can transmit
(receive) the MSB first (SPI/Microwire compliant) or the LSB first. It is important to know
that the RxX and TxX registers share the same flip-flops, which means that what is received
from the input data line in one transfer will be transmitted on the output data line in the next
transfer if no write access to the TxX register is executed between the transfers.

Architecture of SPI Master Core

The SPI Master core consists of three parts shown in the following figure:

47
Core configuration
To meet specific system requirements and size constraints on behalf of the core functionality,
the SPI Master core can be configuredby setting the appropriate define directives in the
spi_defines.v source file. The directives are as follows:
SPI_DIVIDER_BIT_NB
This parameter defines the maximum number of bits needed for the divider. Set this parameter
accordingly to the maximum system frequency and lowest serial clock frequency:
Default value is 16.
SPI_MAX_CHAR
This parameter defines the maximum number of bits that can be received/transmitted in one
transfer.
The default value is 64.
SPI _SS _NB
This parameter defines the number of slave select lines.
The default value is 8.

48
 CHAPTER 6
IMPLEMENTATION OF PROJECT

Implementation of serial clock generator

Block diagram of clock generator:

Functionality of clock generator:

In SPI (Serial Peripheral Interface), the serial clock generator plays a crucial role in
synchronizing data transmission between the master and slave devices. Here's a detailed
explanation:
1. Clock Signal Generation: The serial clock generator produces a clock signal that dictates
the timing of data transmission+n. This clock signal ensures that both the master and slave
devices are synchronized during data exchange.
2. Clock Speed Control: The serial clock generator allows for control over the clock speed,
determining how fast data is transferred between devices. This control is vital for ensuring
compatibility between devices with different processing capabilities.
3. Timing Accuracy: The serial clock generator maintains precise timing accuracy, ensuring
that data bits are transmitted and received at the correct intervals. This accuracy is essential
for reliable communication, especially in high-speed applications.

49
4. Clock Polarity and Phase: The serial clock generator allows configuration of clock polarity
and phase. Clock polarity determines the idle state of the clock signal (high or low), while
clock phase determines when data is sampled relative to the clock signal transitions. These
configurations ensure compatibility between devices with different timing requirements.

5. Master-Slave Synchronization: By generating a consistent clock signal, the serial clock

generator facilitates synchronization between the master and slave devices. This
synchronization ensures that data is transmitted and received correctly without errors.
Overall, the serial clock generator is a critical component of SPI design, providing precise
timing control and synchronization to enable efficient data communication between devices.

Simulation waveform for clock generator:

50
Synthesized Netlist for Serial Clock Generator:

51
Implementation of shift register

Block diagram of shift register:

Functionality of Shift Register:

In SPI (Serial Peripheral Interface) design, a shift register is a fundamental component used
for serial data transmission and reception between the master and slave devices. Here's how it
works:
1. Serial Data Storage: The shift register stores data in a serial fashion, typically one bit at a
time. This allows the master device to send data to the slave device or receive data from the
slave device sequentially.
2. Serial Data Transfer: When transmitting data from the master to the slave, the shift register
receives the data serially from the master device. Each bit of data is shifted into the register
one at a time.

3. Clock-Controlled Operation: The shift register operates in synchronization with the clock
signal generated by the serial clock generator. Each clock pulse causes the shift register to shift
52
the data stored in its internal memory by one bit.
4. Parallel Output: Once all the bits have been shifted into the shift register, the data can be
outputted in parallel to the slave device for processing. This parallel output allows for efficient
transfer of data to the slave device.
5. Serial Input: Similarly, when receiving data from the slave device, the shift register accepts
the data serially and stores it internally. The clock signal controls the shifting of data into the
register.
6. Buffering: The shift register often acts as a buffer between the master and slave devices,
allowing for temporary storage of data during transmission or reception. This buffering helps
to smooth out any timing differences between the master and slave devices.
Overall, the shift register plays a crucial role in SPI design by enabling serial data transmission
and reception between the master and slave devices while maintaining synchronization and
efficient data transfer.

Simulation waveform for shift register:

53
Synthesized netlist:

54
SPI DESIGN
Block diagram of SPI:

Block diagram of Wishbone Master:

55
Block diagram of SPI Master Core

56
Block diagram of SPI Serial Slave

Functionality of SPI top, Wishbone interface, SPI slave:

The functionality of each Block in detail:
SPI (Serial Peripheral Interface) Top:
The SPI top module serves as the main controller for the SPI communication system.
It typically includes components such as the serial clock generator, shift register, and control
logic.
The SPI top module coordinates data transmission and reception between the master and slave
devices.
It generates the necessary control signals and manages the timing of data transfer.
Wishbone Interface:
The Wishbone interface is a widely-used bus architecture for connecting different hardware
components within a system-on-chip (SoC).
In the context of SPI, the Wishbone interface allows for integration of the SPI controller
(master) with other components in the SoC, such as memory, processors, or other peripherals.
It provides a standardized method for communication and data transfer between different
modules in the system.
The Wishbone interface defines signals such as data, address, control, and acknowledgment
signals to facilitate communication between modules.

57
SPI Slave:
The SPI slave module is the device that communicates with the SPI master.
It typically includes components such as a shift register, control logic, and possibly a serial
clock generator.
The SPI slave listens for commands from the master device and responds accordingly.
When receiving data from the master, the SPI slave stores the data in its shift register and
processes it as needed.
When transmitting data to the master, the SPI slave retrieves data from its internal storage
and sends it serially to the master device.
The SPI slave module also manages its own timing and synchronization with the master
device to ensure reliable communication.
Overall, in an SPI system with a Wishbone interface, the SPI top module serves as the
controller for SPI communication, the Wishbone interface facilitates communication
between different modules in the SoC, and the SPI slave module communicates with the SPI
master device. Together, these components enable efficient and reliable data transfer in SPI-
based systems.

Synthesized netlist for SPI Slave

58
Synthesized netlist for Wishbone Master

59
Synthesized Netlist for Top Module

60
Waveform for Top Module:

Top Testbench
tx_neg =1, rx_neg=0, LSB =1, char_len =4

61
tx_neg =0, rx_neg=1, LSB =0, char_len =4

62
 CHAPTER- 7
OUTCOMES DESCRIPTION
Describe the work environment you have experienced
People Interactions: Collaborative and supportive interactions are encouraged, with
team members readily available to answer questions, provide guidance and offer help.
Facilities Available and Maintenance: The company offers remote work
facilities, including virtual collaboration tools and circuit and chip designing
development environments. Regular maintenance ensures functionality and
accessibility for all team members during the internship.
Clarity of Job Roles: Clear job roles and responsibilities are defined for interns,
outlining the tasks, projects, and learning objectives they are expected to accomplish
during the internship.
Protocols, Procedures, Processes: Interns receive training and orientation on these
protocols and procedures to ensure consistency and efficiency in their work.
Discipline and Time Management: Interns are expected to demonstrate discipline
and time management skills to meet project deadlines and deliverables.
Harmonious Relationships: The work environment promotes harmonious
relationships among team members, fostering a culture of respect,
collaboration, and mutual support.
Socialization and Mutual Support: Opportunities for socialization and mutual
support are provided through virtual team-building activities, informal chats,
and shared experiences.
Teamwork and Collaboration: Collaboration and teamwork are essential components of
the work environment, with interns working closely with team members on projects and task.
Motivation: The work environment is designed to motivate interns by providing
meaningful work assignments, opportunities for skill development, and recognition
for achievements.
Space and Ventilation: While working remotely, interns are responsible for creating a
conducive workspace with adequate space, ventilation, and ergonomic setup to support
productivity and well-being.

63
Describe the real time technical skills you have acquired
During my VLSI design internship in Maven silicon Pvt Ltd banglore, I acquired
a range of real-time technical skills and hands-on experience, including:
Strong Digital Design Fundamentals: This includes understanding digital logic
design, Boolean algebra, and sequential and combinational circuits.
RTL Coding: Proficiency in Register Transfer Level (RTL) coding using hardware
description languages like Verilog or VHDL.
ASIC/FPGA Design Flow: Knowledge of the design flow for ASIC (Application-
Specific Integrated Circuit) and FPGA (Field-Programmable Gate Array), including
synthesis, simulation, place and route, and timing analysis.
Low Power Design Techniques: Familiarity with techniques to reduce power
consumption in VLSI designs, such as power gating, clock gating, and voltage
scaling.
Analog/Mixed-Signal Design: Understanding of both analog and digital design
principles, signal integrity, noise, and mixed-signal interactions.
Verification Methodologies: Knowledge of approaches and techniques used to
verify the correctness, functionality, and reliability of digital designs.
ASIC Design: Knowledge of ASIC (Application-Specific Integrated Circuit)
design principles, including custom cells, standard cells, and libraries, is essential.
Familiarity with tools like Design Compiler and Genus is beneficial.
FPGA Prototyping: Proficiency in FPGA-base prototyping allows engineers to
validate their designs before ASIC fabrication. Tools like Xilinx Vivado or
Intel Quartus are commonly used for FPGA design.
CMOS Technology: Understanding CMOS (Complementary Metal-Oxide- Semiconductor)
technology, including transistor behavior, process variations, and scaling effects, is fundamental.

64
Describe the managerial skills you have acquired
During my VLSI design internship, I levelled various managerial skills essential
for effective project execution and team collaboration. These skills are:
Planning: Developed the ability to create comprehensive project plans, outlining
tasks, milestones, and deadlines, ensuring smooth project execution and alignment
with organizational objectives.
Leadership: Demonstrated leadership qualities by providing guidance, support,
and motivation to team members, fostering a collaborative and high- performance
work environment.
Teamwork: Collaborated effectively with cross-functional teams, leveraging diverse
skill sets and perspectives to achieve common goals and deliver successful
outcomes.
Professional Behavior: Maintained professionalism and integrity in all
interactions with colleagues, clients, and stakeholders, fostering trust and
credibility within the team and organization.
Workmanship: Demonstrated a strong work ethic and commitment to excellence
in all tasks and responsibilities, consistently delivering high- quality work and
exceeding expectations.
Productive Use of Time: Managed time efficiently, prioritizing tasks and activities
to maximize productivity and achieve project deadlines, while maintaining a healthy
work-life balance.
Weekly Improvement in Competencies: Actively pursued continuous learning and
self-improvement, dedicating time each week to acquire new skills, deepen existing
knowledge, and stay updated on industry trends and best practices.
Goal Setting: Set clear and achievable goals for myself and the team, aligning
them with organizational objectives and tracking progress regularly to ensure
successful outcomes.
Decision Making: Developed strong decision-making skills by evaluating
multiple options, assessing risks, and taking decisive actions to propel projects
forward.

65
Describe how you could improve your communication skills
The various ways in which the communication skills can be improved are
Oral Communication: Practice speaking clearly, confidently, and concisely,
focusing on articulating ideas effectively and maintaining a natural pace.
Written Communication: Enhance written skills by actively seeking
feedback on written work, refining grammar and vocabulary, and structuring
messages logically and coherently.
Conversational Abilities: Engage in conversations regularly, actively listening
to others, asking questions, and expressing thoughts and opinions clearly and
respectfully.
Confidence Levels: Boost confidence by preparing thoroughly for discussions and
presentations, practicing relaxation techniques to manage anxiety, and embracing
opportunities to speak up in group settings.
Anxiety Management: Develop coping strategies for managing communication
related anxiety, such as deep breathing exercises, positive self-talk, and
visualization techniques.
Understanding Others: Improve understanding by practicing active listening,
empathizing with others perspectives, and seeking clarification when needed to
ensure clear comprehension.
Getting Understood by Others: Use clear and concise language, provide
relevant examples or analogies to enhance understanding, and encourage feedback
to ensure messages are conveyed effectively.
Extempore Speech: Hone extemporaneous speaking skills by practicing important
speeches on various topics, focusing on organizing thoughts quickly and delivering coherent
messages under pressure.

66
Describe how could you could enhance your abilities in group
discussions, participation in teams, contribution as a team member,
leading a team/activity.
It can be achieved by using the following strategies
Active Listening: Practice active listening during group discussions, focusing on
understanding others perspectives and ideas before formulating responses.
Effective Communication: Improve communication skills by expressing
thoughts and ideas clearly and concisely, using appropriate language and tone for
the audience.
Contribution as a Team Member: Contribute actively to team discussions by
sharing insights, asking thoughtful questions, and offering constructive feedback
to support team goals.
Collaboration: Foster collaboration by being open to others ideas, working
collaboratively to solve problems, and leveraging diverse skill sets within the team.
Empathy and Respect: Demonstrate empathy and respect towards team members by
valuing their contributions, acknowledging their expertise, and treating everyone with
dignity and courtesy.
Conflict Resolution: Develop skills in conflict resolution by addressing
differences of opinion calmly and constructively, finding common ground, and
working towards mutually acceptable solutions.
Adaptability: Cultivate adaptability by being flexible and receptive to change,
adjusting to new ideas or approaches, and embracing innovation and creativity within
the team.
Leadership Qualities: Develop leadership qualities by taking initiative, inspiring
others through actions and words, and fostering a positive and inclusive team
culture.
Decision-Making: Enhance decision-making skills by weighing various options,
considering input from team members, and making informed decisions that align
with team objectives.
Time Management: Improve time management skills by setting priorities,
allocating time effectively for tasks and discussions, and ensuring deadlines.

67
Describe the technological developments you have observed and
relevant to the subject area of training.
During my VLSI design, I observed several technological developments relevant to
digital technologies and cloud computing, aligning with my job role. They are:
Comprehensive VLSI Design Training: Maven Silicon offers a range of VLSI
Design courses that cover various aspects of chip design, including VLSI Design
Methodologies, Verilog HDL, VLSI System On Chip Design, FPGA, and Design
for Testability. These courses aim to make college graduates and VLSI aspirants
employable and billable quickly.
Blended Learning Programs: The institute has introduced blended VLSI courses
that combine online and in-person components. This approach provides a
comprehensive understanding of VLSI systems’ design and implementation,
considering the needs and availability of engineers.
Hands-on Experience with EDA Tools: Trainees get exposure to various
EDA tools from Synopsys and Siemens Mentor used in the VLSI design flow,
such as simulation, verification, and layout tools. This practical experience is
crucial for understanding the real-world applications of VLSI design.
Final Projects on Complex Systems: Students work on final projects where they
design and implement complex systems like a RISC-V Core Processor, ARM,
and BUS architecture. This hands-on project work is integral to the learning
process, providing experience in designing real-world VLSI systems.
Professional Development: The courses also include sessions on business
communication and professional development, preparing students for the
challenges of working in the VLSI industry.
Project Work: Trainees work on a final project, designing and implementing more
complex systems like a RISC-V Core Processor, ARM etc.

68
 CHAPTER- 8

CONCLUSION

In conclusion, my VLSI design internship at Maven Silicon has been an invaluable

learning experience that has provided me with practical insights and hands-on skills
in the field of semiconductor design. Throughout the internship, I have had the
opportunity to work on real-world projects, collaborate with experienced
professionals, and gain exposure to industry- leading tools and methodologies. The
supportive environment at Maven Silicon has enabled me to explore different aspects
of VLSI design, refine my technical abilities, and develop a deeper understanding of
the intricacies involved in chip development. I am grateful for the guidance and
mentorship I received during my time at Maven Silicon, and I am confident that the
knowledge and expertise gained will serve as a solid foundation for my future career
endeavor in the field of VLSI Design.

69
 PHOTOS & VIDEO LINKS
https://elearn.maven-silicon.com/myaccount/#/classes

70
71
 Student Self Evaluation of the Short-Term Internship

Student Name: Registration No:

Term of Internship: From: To:

Organization Name & Address:

Please rate your performance in the following areas:

Rating Scale: Letter grade of CGPA calculation to be provided

1 Oral communication 1 2 3 4 5
2 Written communication 1 2 3 4 5
3 Proactiveness 1 2 3 4 5
4 Interaction ability with community 1 2 3 4 5
5 Positive Attitude 1 2 3 4 5
6 Self-confidence 1 2 3 4 5
7 Ability to learn 1 2 3 4 5
8 Work Plan and organization 1 2 3 4 5
9 Professionalism 1 2 3 4 5
10 Creativity 1 2 3 4 5
11 Quality of work done 1 2 3 4 5
12 Time Management 1 2 3 4 5
13 Understanding the Community 1 2 3 4 5
14 Achievement of Desired Outcomes 1 2 3 4 5
15 OVERALL PERFORMANCE 1 2 3 4 5

Date: Signature of the Student

 Evaluation by the Supervisor of the Intern Organization

Student Name: Registration No:

Term of Internship: From: To:

Date of Evaluation:

Organization Name & Address:

Please rate the student’s performance in the following areas:

Please note that your evaluation shall be done independent of the Student’s self-
evaluation

Rating Scale: 1 is lowest and 5 is highest rank

1 Oral communication 1 2 3 4 5
2 Written communication 1 2 3 4 5
3 Proactiveness 1 2 3 4 5
4 Interaction ability with community 1 2 3 4 5
5 Positive Attitude 1 2 3 4 5
6 Self-confidence 1 2 3 4 5
7 Ability to learn 1 2 3 4 5
8 Work Plan and organization 1 2 3 4 5
9 Professionalism 1 2 3 4 5
10 Creativity 1 2 3 4 5
11 Quality of work done 1 2 3 4 5
12 Time Management 1 2 3 4 5
13 Understanding the Community 1 2 3 4 5
14 Achievement of Desired Outcomes 1 2 3 4 5
15 OVERALL PERFORMANCE 1 2 3 4 5

Date: signature of the supervisor

 MARKS STATEMENT
(To be used by the Examiner)
 INTERNAL ASSESSMENT STATEMENT

Name Of the Student:

Programme of Study:
Year of Study:
Group:

Register No/H.T. No:

Name of the College:
University:

Sl.No Evaluation Criterion Maximum Marks

Marks Awarded

1. Activity Log 10

2. Internship Evaluation 30

3. Oral Presentation 10

GRAND TOTAL 50

Date: Signature of the Faculty Guide

 EXTERNAL ASSESSMENT STATEMENT

Name Of the Student:

Programme of Study:
Year of Study:
Group:

Register No/H.T. No:

Name of the College:
University:

Maximum Marks
Sl.No Evaluation Criterion
Marks Awarded

1. Internship Evaluation 80
For the grading giving by the Supervisor of
2. the Intern Organization 20

3. Viva-Voce 50

TOTAL 150

GRAND TOTAL (EXT. 50 M + INT. 100M) 200

Signature of the Faculty Guide

Signature of the Internal Guide

Signature of the external Expert

Signature of the Principal with Seal