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bq24251: Not Recommended For New Designs

bq24250, bq24251, bq24253

SLUSBA1H – OCTOBER 2012 – REVISED AUGUST 2015

bq2425x 2A Single-Input I2C, Stand-Alone Switched-Mode Li-Ion Battery Charger With

Power-Path Management
1

1 Features
• High-Efficiency Switched-Mode Charger With • Synchronous Fixed-Frequency PWM Controller
Separate Power Path Operating at 3 MHz for Small Inductor Support
• Startup System From Deeply Discharged or • AnyBoot Robust Battery Detection Algorithm
Missing Battery • Charge Time Optimizer for Improved Charge
• USB Charging Compliant Times at Any Given Charge Current
– Selectable Input Current Limit of 100 mA, • 2.40-mm x 2.00-mm 30-Ball DSBGA and 4-mm x
500 mA, 900 mA, 1.5 A, and 2 A 4-mm 24-Pin QFN Packages
• BC1.2 Compatible D+, D– Detection
• In Host Mode (After I2C Communication Starts 2 Applications
and Before Watchdog Timer Times Out) • Mobile Phones and Smart Phones
– Programmable Battery Charge Voltage, • MP3 Players
VBATREG • Portable Media Players
– Programmable Charge Current (ICHG) • Handheld Devices
– Programmable Input Current Limit (ILIM)
– Programmable Input Voltage-Based Dynamic 3 Description
Power Management Threshold, (VIN_DPM) The bq24250, bq24251, and bq24253 are highly
integrated single-cell Li-Ion battery chargers and
– Programmable Input Overvoltage Protection
system power-path management devices targeted for
Threshold (VOVP) space-limited, portable applications with high-capacity
– Programmable Safety Timer batteries. The single-cell charger has a single input
• Resistor Programmable Defaults for: that operates from either a USB port or an AC wall
adapter for a versatile solution.
– ICHG up to 2 A With Current Monitoring Output
(ISET) Device Information(1)
– ILIM up to 2 A With Current Monitoring Output PART NUMBER PACKAGE BODY SIZE (NOM)
(ILIM) bq24250 VQFN (24) 4.00 mm x 4.00 mm
– VIN_DPM (VDPM) bq24251
bq24253 DSBGA (30) 2.40 mm x 2.00 mm
• Watchdog Timer Disable Bit
(1) For all available packages, see the orderable addendum at
• Integrated 4.9 V, 50 mA LDO the end of the datasheet.
• Complete System-Level Protection
CPMID

– Input UVLO, Input Overvoltage Protection 1 µF

(OVP), Battery OVP, Sleep Mode, VIN_DPM IN

PMID
SW
LO
1.0 µH
VIN System Load

– Input Current Limit CIN

2.2 µF
R1

3 MHz
CBOOT
VDPM 33 nF
PWM
– Charge Current Limit R2
BOOT
LDO PGND

– Thermal Regulation 1 µF SYS

22 μF

– Thermal Shutdown STAT

– Voltage-Based, JEITA Compatible NTC

VGPIO BAT
Monitoring Input 1 μF
LDO

– Safety Timer SCL SCL R3

TEMP PACK+
SDA SDA TS

• 22 V Absolute Maximum Input Voltage Rating Host

GPIO1 INT R4 RNTC
+

PACK-
GPIO2 /CE
• 10.5 V Maximum Operating Input Voltage GPIO3 EN1

• Low RDS(on) Integrated Power FETs for a Charging GPIO4 EN2

ILIM ISET

Rate of up to 2 A
• Open-Drain Status Outputs

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
 bq24251: Not Recommended For New Designs
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SLUSBA1H – OCTOBER 2012 – REVISED AUGUST 2015 www.ti.com

Table of Contents
1 Features .................................................................. 1 9.4 Device Functional Modes........................................ 30
2 Applications ........................................................... 1 9.5 Programming........................................................... 31
3 Description ............................................................. 1 9.6 Register Maps ........................................................ 33
4 Revision History..................................................... 2 10 Application and Implementation........................ 39
10.1 Application Information.......................................... 39
5 Description (continued)......................................... 4
10.2 Typical Application ............................................... 39
6 Device Options....................................................... 4
11 Power Supply Recommendations ..................... 42
7 Pin Configuration and Functions ......................... 5
12 Layout................................................................... 42
8 Specifications......................................................... 8
12.1 Layout Guidelines ................................................. 42
8.1 Absolute Maximum Ratings ..................................... 8
12.2 Layout Example .................................................... 43
8.2 ESD Ratings.............................................................. 8
12.3 Thermal Considerations ........................................ 44
8.3 Recommended Operating Conditions....................... 8
8.4 Thermal Information .................................................. 9 13 Device and Documentation Support ................. 45
13.1 Related Links ........................................................ 45
8.5 Electrical Characteristics........................................... 9
13.2 Trademarks ........................................................... 45
8.6 Typical Characteristics ............................................ 14
13.3 Electrostatic Discharge Caution ............................ 45
9 Detailed Description ............................................ 16
13.4 Glossary ................................................................ 45
9.1 Overview ................................................................. 16
9.2 Functional Block Diagram ....................................... 17 14 Mechanical, Packaging, and Orderable
Information ........................................................... 45
9.3 Feature Description................................................. 18
14.1 Package Summary................................................ 46

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision G (January 2015) to Revision H Page

• Changed 20 V Maximum Input Voltage Rating Feature bullet to 22 V to match Absolute Maximum Ratings table.............. 1
• Changed Figure 11 and Figure 12 image X-axis labels from "Temperature (fC)" to "Temperature (°C)" ........................... 15

Changes from Revision F (December 2014) to Revision G Page

• Deleted Lead temperature (soldering) spec from Absolute Maximum Ratings table. See Package Option Addendum. ..... 8
• Changed table heading from Handling Ratings to ESD Ratings. Moved Tstg spec to the Absolute Maximum Ratings table 8
• Changed the test condition of IBAT- Battery discharge current in SYSOFF mode: Removed “(BAT, SW, SYS)” ................ 9
• Added spec for IIN/IILIM ratio ................................................................................................................................................. 11

Changes from Revision E (December 2013) to Revision F Page

• Added Handling Rating table, Feature Description section, Device Functional Modes, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation
Support section, and Mechanical, Packaging, and Orderable Information section ............................................................... 1
• Deleted the minimum spec for RILIM-SHORT and changed the typical value to 55 ohm and maximum spec to 75 ohm. 11
• Changed VLDO values to (4.65, 4.85, 5.04) and added description in the second column “bq24250”. Added one row
below for “bq24251 and bq24253” and added values (4.65, 4.95, 5.25). ............................................................................ 12

Changes from Revision D (July 2013) to Revision E Page

• Changed VDPM pin desctiption from "......sets a default of 4.36V" to ".......sets a default of 4.68V" .................................... 6
• Changed text string in the VIN_DLM settings description from: "The ISET resistor must be floated in order to avoid an
internal fault." to: "The ISET resistor must be connected in order to avoid an unstable charging state."............................ 20
• Changed text string in the Sleep Mode description from: "...sends a single 256μs pulse is sent on the STAT and INT
outputs..." to: "...sends a single 256µs pulse on the STAT and INT outputs..." ................................................................... 26

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• Changed text string in the Input Over-Voltage Protection description from: "...turns the battery FET, sends a single
256μs pulse is sent on the STAT and INT outputs..." to "...turns the battery FET, sends a single 256μs pulse on the
STAT and INT outputs...."..................................................................................................................................................... 26
• Added Serial Interface Description ....................................................................................................................................... 31
• Changed Register #3 description, B1(4)(5) Name from: "USB_DET_1/EN1" to: "USB_DET_1/EN2" ................................ 35
• Changed Register #3 description, B0(LSB) Name from: "USB_DET_0/EN0" to: "USB_DET_0/EN1" ................................ 35
• Changed Register #3 description, B1(4)(5) and B0(LSB) FUNCTION entries from: "Return USB detection result or
pin EN1/EN0 status –" to "Return USB detection result or pin EN2/EN1 status –" ; changed 00 - DCP detected /
from: "EN1=0, EN0=0" to: "EN2=0, EN1=0"; changed 01 - CDP detected / from: "EN1=0, EN0=1" to: "EN2=0,
EN1=1"; changed 10 - SDP detected / from: "EN1=1, EN0=0" to: "EN2=1, EN1=0"; and changed 11 - Apple/TT or
non-standard adaptor detected / from: "EN1=1, EN0=1" to: "EN2=1, EN1=1", respectively. .............................................. 35

Changes from Revision C (June 2013) to Revision D Page

• Changed VDPM Pin Description regulator reference from "1.23V" to "1.2" .......................................................................... 6
• Changed text string in D+/D- pin description from "....will remain low..." to "...will remain high impedance..." ...................... 7
• Added SCL and SDA to Pin Voltage Range spec in the Absolute Maximum Ratings table .................................................. 8
• Changed spec conditions for Output Current (Continuous), from "IN, SW, SYS, BAT" to "IN, SYS, BAT " in ABS
Max Ratings table .................................................................................................................................................................. 8
• Changed Figure 20 .............................................................................................................................................................. 25
• Added text to NTC Monitor description for clarification. ....................................................................................................... 28
• Added text to Safety Timer description for clarification. ....................................................................................................... 28
• Changed Fault Condition from "Input Good" to "Input Fault & LDO Low" in Fault Conditions table.................................... 29
• Changed Register #2 Reset state from "1010 1100" to "xxxx 1100" ................................................................................... 34
• Changed Register #4 Reset state from "0000 0000" to "1111 1000"................................................................................... 35
• Changed Bit B7, B6, B5, B4, B3 FUNCTION description from "(default 0)" to "(default 1)" ................................................ 35
• Changed Register #4 Footnote (1) text from "...current is 500ma...." to " .....current is external.."...................................... 35
• Changed TS_EN description from "When set to a ‘1' the TS function is disabled ....." to "When set to a ‘0’, the TS
function is disabled..."........................................................................................................................................................... 37
• Added text to TS_STAT description for clarification............................................................................................................. 37
• Changed Register #7, Bit B3 FUNCTION description from "...if TERM is true or EN_PTM is true..." to "if TERM is
true or Force PTM s true..." .................................................................................................................................................. 38

Changes from Revision B (May 2013) to Revision C Page

• Deleted PREVIEW status note from devices bq24250YFF, bq24251YFF, bq24251RGE, and bq24253RGE ................... 45

Changes from Revision A (March 2013) to Revision B Page

• Added PREVIEW status to devices in the Ordering Information table, except the bq24250RGER and bq24250RGET .... 45

Changes from Original (October 2012) to Revision A Page

• Changed From: Product Brief To: Full data sheet.................................................................................................................. 1

• Added Typical Characteristics graphs .................................................................................................................................. 14
• Added Typical Characteristics graphs .................................................................................................................................. 15
• Added Typical Characteristics graphs .................................................................................................................................. 16
• Changed Equation (3) .......................................................................................................................................................... 20
• Changed text in the F/S Mode Protocol section from "...to either transmit data to the slave (R/W bit 1) or receive
data from the slave (R/W bit 0" to "...to either transmit data to the slave (R/W bit 0) or receive data from the slave

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(R/W bit 1)" for clarification................................................................................................................................................... 32

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5 Description (continued)
The power-path management feature allows the bq24250, bq24251, and bq24253 to power the system from a
high-efficiency DC-DC converter while simultaneously and independently charging the battery. The charger
monitors the battery current at all times and reduces the charge current when the system load requires current
above the input current limit. This reduced charge current allows for proper charge termination and enables the
system to run with a defective or absent battery pack. Additionally, this reduced charge current enables instant
system turnon even with a totally discharged battery or no battery. The architecture of the power-path
management also permits the battery to supplement the system current requirements when the adapter cannot
deliver the peak system currents. This supplementation of current requirements enables the use of a smaller
adapter.
The battery is charged in four phases: trickle charge, precharge, constant current, and constant voltage. In all
charge phases, an internal control loop monitors the IC junction temperature and reduces the charge current if
the internal temperature threshold is exceeded. Additionally, a voltage-based, JEITA compatible battery pack
thermistor monitoring input (TS) that monitors battery temperature for safe charging is included.

6 Device Options

I2C OR
DEFAULT D+/D- OR DEFAULT I2C
DEVICE INT OR PG MINSYS TS PROFILE STAND
OVP EN1/EN2 VOREG ADDRESS
ALONE
bq24250 10.5V EN1/EN2 INT 4.2V 3.5V JEITA I2C + SA 0x6A
2
bq24251 10.5V D+/D- PG 4.2V 3.5V JEITA I C + SA 0x6A
bq24253 10.5V D+/D- PG 4.2V 3.5V JEITA SA Only N/A
and
EN1/EN2

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7 Pin Configuration and Functions

DSBGA/QFN
30 Pins/24 Pins
Top View
1 2 3 4 5

VDPM

BOOT
PMID
LDO

ILIM

IN
A BAT SYS PGND SW IN
24 23 22 21 20 19

B BAT SYS PGND SW IN

CE 1 18 SW
EN1 2 17 SW
C BAT SYS PGND SW IN
EN2 3 16 PGND
bq24250
AGND 4 QFN 15 PGND
D ISET EN2 EN1 /CE PMID
SDA 5 14 SYS
SCL 6 13 SYS
E INT SCL STAT VDPM BOOT

7 8 9 10 11 12

INT
TS
ISET
BAT
BAT
STAT
F TS SDA PGND LDO ILIM

bq24250 DSBGA

1 2 3 4 5

VDPM

BOOT
PMID
LDO

ILIM

IN
A BAT SYS PGND SW IN

24 23 22 21 20 19

B BAT SYS PGND SW IN

CE 1 18 SW
D+ 2 17 SW
C BAT SYS PGND SW IN
D– 3
bq24251 16 PGND
QFN
AGND 4 15 PGND
D ISET D- D+ /CE PMID
SDA 5 14 SYS

E /PG SCL STAT VDPM BOOT SCL 6 13 SYS

7 8 9 10 11 12

F
TS
ISET
PG

BAT
BAT
STAT

TS SDA PGND LDO ILIM

bq24251 DSBGA

1 2 3 4 5
VDPM

BOOT
PMID
LDO

ILIM

IN

A BAT SYS PGND SW IN

24 23 22 21 20 19

B BAT SYS PGND SW IN

CE 1 18 SW
D+ 2 17 SW
C BAT SYS PGND SW IN
D– 3
bq24253
16 PGND
QFN
AGND 4 15 PGND
D ISET D- D+ /CE PMID
EN1 5 14 SYS

E /PG EN2 /CHG VDPM BOOT

EN2 6 13 SYS

7 8 9 10 11 12
TS
ISET
PG

BAT
CHG

BAT

F TS EN1 PGND LDO ILIM

bq24253 DSBGA

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Pin Functions
PIN
NAME bq24250 bq24251 bq24253 I/O DESCRIPTION
YFF RGE YFF RGE YFF RGE
Input power supply. IN is connected to the
IN A5,B5,C5 19 A5,B5,C5 19 A5,B5,C5 19 I external DC supply (AC adapter or USB port).
Bypass IN to PGND with >2μF ceramic capacitor
Connection between blocking FET and high-side
PMID D5 20 D5 20 D5 20 I
FET.
A4, B4, A4, B4, A4, B4, Inductor Connection. Connect to the switching
SW 17–18 17–18 17–18 O
C4 C4 C4 side of the external inductor.
High Side MOSFET Gate Driver Supply. Connect
a 0.033μF ceramic capacitor (voltage rating >
BOOT E5 21 E5 21 E5 21 I
15V) from BOOT to SW to supply the gate drive
for the high side MOSFETs.
A3, B3, A3, B3, A3, B3, Ground terminal. Connect to the ground plane of
PGND 15–16 15–16 15–16
C3, F3 C3, F3 C3, F3 the circuit.
System Voltage Sense and switched-mode power
A2, B2, A2, B2, A2, B2, supply (SMPS) output filter connection. Connect
SYS 13–14 13–14 13–14 I
C2 C2 C2 SYS to the system output at the output bulk
capacitors. Bypass SYS locally with >20μF.
Battery Connection. Connect to the positive
A1, B1, A1, B1, A1, B1,
BAT 11–12 11–12 11–12 I/O terminal of the battery. Additionally, bypass BAT
C1 C1 C1
with a >1μF capacitor.
Battery Pack NTC Monitor. Connect TS to the
center tap of a resistor divider from LDO to GND.
The NTC is connected from TS to GND. The TS
TS F1 9 F1 9 F1 9 I function provides 4 thresholds for JEITA or PSE
compatibility. See the NTC Monitor section for
more details on operation and selecting the
resistor values.
Input DPM Programming Input. Connect a resistor
divider between IN and GND with VDPM
connected to the center tap to program the Input
Voltage based Dynamic Power Management
threshold (VIN_DPM). The input current is reduced
VDPM E4 23 E4 23 E4 23 I
to maintain the supply voltage at VIN_DPM. The
reference for the regulator is 1.2V. Short pin to
GND if external resistors are not desired—this
sets a default of 4.68V for the input DPM
threshold.
Charge Current Programming Input. Connect a
resistor from ISET to GND to program the fast
ISET D1 10 D1 10 D1 10 I
charge current. The charge current is
programmable from 300mA to 2A.
Input Current Limit Programming Input. Connect a
resistor from ILIM to GND to program the input
current limit for IN. The current limit is
ILIM F5 22 F5 22 F5 22 I
programmable from 0.5A to 2A. ILIM has no
effect on the USB input. If an external resistor is
not desired, short to GND for a 2A default setting.
Charge Enable Active-Low Input. Connect CE to
CE D4 1 D4 1 D4 1 I a high logic level to place the battery charger in
standby mode.
EN1 D3 2 – – F2 5 I Input Current Limit Configuration Inputs. Use
EN1, and EN2 to control the maximum input
EN2 D2 3 – – E2 6 I current and enable USB compliance. See Table 1
for programming details.
Charge Status Open Drain Output. CHG is pulled
low when a charge cycle starts and remains low
CHG – – – – E3 7 O while charging. CHG is high impedance when the
charging terminates and when no supply exists.
CHG does not indicate recharge cycles.

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Pin Functions (continued)

PIN
NAME bq24250 bq24251 bq24253 I/O DESCRIPTION
YFF RGE YFF RGE YFF RGE
Power Good Open Drain Output. PG is pulled low
when a valid supply is connected to IN. A valid
PG – – E1 8 E1 8 O supply is between VBAT+VSLP and VOVP. If no
supply is connected or the supply is out of this
range, PG is high impedance.
Status Output. STAT is an open-drain output that
signals charging status and fault interrupts. STAT
pulls low during charging. STAT is high
impedance when charging is complete or the
charger is disabled. When a fault occurs, a 256μs
STAT E3 7 E3 7 – – O pulse is sent out as an interrupt for the host.
STAT is enabled/disabled using the EN_STAT bit
in the control register. STAT will indicate recharge
cycles. Connect STAT to a logic rail using an LED
for visual indication or through a 10kΩ resistor to
communicate with the host processor.
Status Output. INT is an open-drain output that
signals charging status and fault interrupts. INT
pulls low during charging. INT is high impedance
when charging is complete or the charger is
INT E1 8 – – – – O disabled. When a fault occurs, a 256μs pulse is
sent out as an interrupt for the host. INT will
indicate recharge cycles. Connect INT to a logic
rail through a 10kΩ resistor to communicate with
the host processor.
I2C Interface Clock. Connect SCL to the logic rail
SCL E2 6 E2 6 – – I
through a 10kΩ resistor.
I2C Interface Data. Connect SDA to the logic rail
SDA F2 5 F2 5 – – I/O
through a 10kΩ resistor.
D+ – – D3 2 D3 2 I BC1.2 compatible D+/D– Based Adapter
Detection. Detects DCP, SDP, and CDP. Also
complies with the unconnected dead battery
provision clause. D+ and D- are connected to the
D+ and D– outputs of the USB port at power up.
D– – – D2 3 D2 3 I Also includes the detection of Apple™ and
TomTom™ adapters where a 500mA input
current limit is enabled. The PG pin will remain
high impedance until the detection has
completed.
LDO output. LDO is regulated to 4.9V and drives
up to 50mA. Bypass LDO with a 1μF ceramic
LDO F4 24 F4 24 F4 24 O
Capacitor. LDO is enabled when VUVLO < VIN
<18V.
Analog Ground for QFN only. Connect to the
AGND – 4 – 4 – 4
thermal pad and the ground plane of the circuit.

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8 Specifications
8.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
IN –0.3 22 V
SW –0.7 12 V
Pin Voltage Range (with BOOT –0.3 20 V
respect to GND)
LDO,STAT, INT, /CHG, /PG, EN1, EN2, EN3, /CE, D+, D-, ILIM, ISET, VDPM,
–0.3 7 V
TS, SCL, SDA
SYS, BAT –0.3 5 V
BOOT relative to SW –0.3 7 V
Output Current IN 2
A
(Continuous) SYS, BAT 4
Output Sink Current STAT, /CHG, /PG 5 mA
Operating free-air temperature range –40 85 °C
Junction temperature, TJ –40 125 °C
Input Power IN 15 W
Storage temperature, Tstg –65 150 °C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

8.2 ESD Ratings

VALUE UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) ±2000
V(ESD) Electrostatic discharge Charged device model (CDM), per JEDEC specification JESD22- ±500 V
C101, all pins (2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

8.3 Recommended Operating Conditions

All voltages are with respect to PGND if not specified. Currents are positive into, negative out of the specified terminal.
Consult Packaging Section of the data book for thermal limitations and considerations of packages
MIN MAX UNIT
VIN IN voltage range 4.35 18 (1)
V
IN operating voltage range 4.35 10.5
IIN Input current 2 A
ICHG Current in charge mode, BAT 2 A
IDISCHG Current in discharge mode, BAT 4 A
RISET Charge current programming resistor range 75 Ω
RILIM Input current limit programming resistor range 105 Ω
PIN Input Power 12 W
TJ Operating junction temperature range 0 125 °C

(1) The inherent switching noise voltage spikes should not exceed the absolute maximum rating on either the BOOT or SW pins. Small
routing loops for the power nets in layout minimize switching noise.

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8.4 Thermal Information

YFF RGE
THERMAL METRIC (1) UNIT
(30 PINS) (24 PINS)
RθJA Junction-to-ambient thermal resistance 76.5 32.9 °C/W
RθJCtop Junction-to-case (top) thermal resistance 0.2 32.8 °C/W
RθJB Junction-to-board thermal resistance 44 10.6 °C/W
ψJT Junction-to-top characterization parameter 1.6 0.3 °C/W
ψJB Junction-to-board characterization parameter 43.4 10.7 °C/W
RθJCbot Junction-to-case (bottom) thermal resistance N/A 2.3 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.

8.5 Electrical Characteristics

VUVLO < VIN < VOVP and VIN > VBAT+VSLP, TJ = 0ºC-125°C and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT CURRENTS
VDPM < VIN < VOVP AND VIN >
VBAT+VSLP PWM switching, 13
CE Enable
mA
VDPM < VIN < VOVP AND VIN >
IIN Supply current from IN
VBAT+VSLP PWM switching, 5
CE Disable
VIN= 5.5V, 0°C< TJ < 85°C,
170 225 μA
High-Z Mode
0°C< TJ < 85°C, VBAT = 4.2
Battery discharge current in high impedance mode, V,
16 22
(BAT, SW, SYS)
VIN = 0V or 5V, High-Z Mode
IBAT μA
0°C< TJ < 85°C, VBAT = 4.2
Battery discharge current in SYSOFF mode V, 1
VIN < UVLO, SYSOFF Mode
POWER-PATH MANAGEMENT
MINSYS stage (no DPM or
–1% 3.52 1%
DPPM)
MINSYS stage (DPM or DPPM VMINSYS
–1.50% 1.50%
active) –200mV

VSYSREG System Regulation Voltage VBAT V

BATREG stage + ICHG
Ron
VBATRE
VBATREG VBATREG
SYSREG stage G
+2.1% +3.1%
+4.1%
VBAT –
VSPLM Enter supplement mode voltage threshold VBAT = 3.6V V
40mV
ISPLM Exit supplement mode current threshold VBAT = 3.6V 20 mA
Deglitch Time, OUT Short Circuit during Discharge Measured from (VBAT – VSYS)
tDGL(SC1) 740 μs
or Supplement Mode = 300 mV
Recovery Time, OUT Short Circuit during
tREC(SC1) 64 ms
Discharge or Supplement Mode
BATTERY CHARGER
Measured from BAT to SYS,
20 30
RON(BAT- VBAT = 4.2V (WCSP)
Internal battery charger MOSFET on-resistance mΩ
SYS) Measured from BAT to SYS,
30 40
VBAT = 4.2V (QFN)

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Electrical Characteristics (continued)

VUVLO < VIN < VOVP and VIN > VBAT+VSLP, TJ = 0ºC-125°C and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Operating in voltage
I2C host mode regulation, Programmable 3.5 4.44 V
Range
VBATREG SA mode or I2C default mode 4.2
TJ = 25°C –0.5% 0.5%
Voltage Regulation Accuracy
TJ = 0°C to 125°C –0.75% 0.75%
ICHG Fast Charge Current Range VLOWV ≤ VBAT < VBAT(REG) 500 2000 mA
2
Fast Charge Current Accuracy I C mode –7% 7%
ICHG-LOW Low Charge Current Setting Set via I2C 297 330 363 mA
KISET
KISET Programmable Fast Charge Current Factor ICHG = 232.5 250 267.5 AΩ
RISET
VISET Maximum ISET pin voltage (in regulation) 0.42 V
RISET-
Short circuit resistance threshold 45 55 75 Ω
SHORT
Pre-charge to fast charge threshold Rising 2.9 3 3.1 V
VLOWV
Hysteresis for VLOWV Battery voltage falling 100 mV
Ipre-chg is a precentile of the
IPRECHG Pr-charge current (VBATUVLO < VBAT < VLOWV) 8 10 12 %
external fast charge settings.
Deglitch time for pre-charge to fast charge
tDGL(LOWV) 32 ms
transition
VBAT_UVLO Battery Under voltage lockout threshold VBAT rising 2.37 2.5 2.63 V
Battery UVLO hysteresis 200 mV
VBATSHRT Trickle charge to pre-charge threshold 1.9 2 2.1 V
Hysteresis for VBATSHRT Battery voltage falling 100 mV
Trickle charge mode charge current (VBAT <
IBATSHRT 25 35 50 mA
VBATSHRT)
tDGL(BATSH Deglitch time for trickle charge to pre-charge
256 us
RT) transition
Termination Current Threshold Termination current on SA only 10 %ICHG
ITERM
Termination Current Threshold Tolerance –10% 10%
Both rising and falling, 2-mV
tDGL(TERM) Deglitch time for charge termination over-drive, tRISE, tFALL = 100 64 ms
ns
VRCH Recharge threshold voltage Below VBATREG 70 115 160 mV
VBAT falling below VRCH, tFALL
tDGL(RCH) Deglitch time 32 ms
= 100 ns
BATTERY DETECTION
VBATREG_HI Battery Detection High Regulation Voltage Same as VBATREG VBATREG V
VBATREG_L VBATREG
Battery Detection Low Regulation Voltage 360 mV offset from VBATREG V
O –480mV
VBATREG
VBATDET Hi Battery detection comparator VBATREG = VBATREG_HI V
–120mV
VBATREG
VBATDET LO Battery detection comparator VBATREG = VBATREG_LO V
+120mV
Always on during battery
IDETECT Battery Detection Current Sink 7.5 mA
detection
For both VBATREG_HI and
tDETECT Battery detection time 32 ms
VBATREG_LO
Tsafe Safety Timer Accuracy –10% +10%

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Electrical Characteristics (continued)

VUVLO < VIN < VOVP and VIN > VBAT+VSLP, TJ = 0ºC-125°C and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT PROTECTION
IIN_LIMIT = 100 mA 90 95 100 mA
IIN_LIMIT = 150 mA 135 142.5 150
IIN_LIMIT = 500 mA 450 475 500
IIN_LIMIT = 900 mA 810 860 910
IIN Input current limiting
IIN_LIMIT = 1500 mA 1400 1475 1550
IIN_LIMIT = 2000 mA 1850 1950 2050
KILIM
IIN_LIMIT = External ILIM =
RILIM
Maximum input current limit programmable range
ILIM 500 2000 mA
for IN input
KILIM Maximum input current factor for IN input ILIM = 500 mA to 2.0 A 240 270 300 AΩ
VILIM Maximum ILIM pin voltage (in regulation) 0.42 V
IIN /IILIM Ratio between input current and the ILIM pin External ILIM control or stand 540 A/A
current in external control or stand alone mode alone
RILIM-
Short circuit resistance threshold 55 75 Ω
SHORT
SA mode 4.2 10
VIN_DPM threshold range
I2C mode 4.2 4.76
USB100, USB150, USB500,
VIN_DPM threshold for USB Input in SA mode USB900, current limit selected. 4.27 4.36 4.45 V
VIN_DPM Also I2C register default.
Must set to external resistor VIN_DPM VIN_DPM
VIN_DPM threshold with adaptor current limit and
settings via the EN1/EN2 pins . VIN_DPM .
VDPM shorted to GND
or the I2C register interface. –2% +2%
VIN_DPM threshold Accuracy Both I2C and SA mode –2% 2%
VREF_DPM DPM regulation voltage External resistor setting only 1.15 1.2 1.25 V
If VDPM is shorted to ground,
VDPM_SHRT VIN_DPM short threshold VIN_DPM threshold will use 0.3 V
internal default value
IC active threshold voltage VIN rising 3.15 3.35 3.5 V
VUVLO
IC active hysteresis VIN falling from above VUVLO 175 mV
2.0 V ≤ VBAT ≤ VBATREG, VIN
Sleep-mode entry threshold, VIN-VBAT 0 50 100 mV
VSLP falling
Sleep-mode exit hysteresis, VIN-VBAT 2.0 V ≤ VBAT ≤ VBATREG 40 100 160 mV
Rising voltage, 2-mV over
tDGL(SLP) Deglitch time for IN rising above VIN+VSLP_EXIT 32 ms
drive, tRISE = 100 ns
Input
Input
Input OVP
Input supply OVP threshold voltage IN rising OVP V
VOVP OVP +200m
–200mV
V
VOVP hysteresis IN falling from VOVP 100 mV
IN rising voltage, tRISE = 100
tDGL(OVP) Deglitch time for IN Rising above VOVP 32 ms
ns
VBAT threshold over VBATREG %
Battery OVP threshold voltage to turn off charger during 102.5 105 107.5 VBATRE
charge G
VBOVP
%
Lower limit for VBAT falling
VBOVP hysteresis 1 VBATRE
from above VBOVP
G
tDGL(BOVP) BOVP Deglitch Battery entering/exiting BOVP 1 ms

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Electrical Characteristics (continued)

VUVLO < VIN < VOVP and VIN > VBAT+VSLP, TJ = 0ºC-125°C and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PWM CONVERTER
Measured from IN to PMID
RON(BLK) Internal blocking MOSFET on-resistance 60 100 mΩ
(WCSP & QFN)
Measured from PMID to SW
RON(HS) Internal high-side MOSFET on-resistance 100 150 mΩ
(WCSP & QFN)
Measured from SW to PGND
RON(LS) Internal low-side MOSFET on-resistance 110 165 mΩ
(WCSP & QFN)
ICbC Cycle-by-cycle current limit VSYS shorted 2.6 3.2 3.8 A
fOSC Oscillator frequency 2.7 3 3.3 MHz
DMAX Maximum duty cycle 95%
DMIN Minimum duty cycle 0%
Thermal trip 150 °C
TSHTDWN
Thermal hysteresis 10
Charge current begins to cut
TREG Thermal regulation threshold 125
off
LDO (LINEAR DROPOUT)
bq24250 4.65 4.85 5.04
VLDO LDO Output Voltage VIN = 5.5 V, ILDO = 0 to 50 mA V
bq24251 and bq24253 4.65 4.95 5.25
ILDO Maximum LDO Output Current 50 mA
VDO LDO Dropout Voltage (VIN – VLDO) VIN = 5.0 V, ILDO = 50 mA 200 300 mV
BATTERY-PACK NTC MONITOR (1)
VHOT High temperature threshold VTS falling 29.6 30 30.4
VHYS(HOT) Hysteresis on high threshold VTS rising 1
VWARM Warm temperature threshold VTS falling 37.9 38.3 38.7
VHYS(WARM
Hysteresis on warm temperature threshold VTS rising 1
)
VCOOL Cool temperature threshold VTS rising 56.1 56.5 56.9
% VLDO
VHSY(COOL) Hysteresis on cool temperature threshold VTS falling 1
VCOLD Low temperature threshold VTS rising 59.6 60 60.4
VHYS(COLD) Hysteresis on low threshold VTS falling 1
VFRZ Freeze temperature threshold VTS rising 62 62.5 63
VHYS(FRZ) Hysteresis on freeze threshold VTS falling 1
VTS_DIS TS disable threshold 70 73
tDGL(TS) Deglitch time on TS change 32 ms
INPUTS (EN1, EN2, EN2, CE, CE1, CE2, BATREG, SCL, SDA, DBP)
VIH Input high threshold 1 V
VIL Input low threshold 0.4 V
STATUS OUTPUTS (CHG, PG, STAT, INT, BATRDY)
VOL Low-level output saturation voltage IO = 5 mA, sink current 0.4 V
IIH High-level leakage current Hi-Z and 5V applies 1 µA
TIMERS
45 min safety timer 2700
tSAFETY 6 hr safety timer 21600 s
9 hr safety timer 32400
tWATCH-
Watch dog timer 50 s
DOG

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Electrical Characteristics (continued)

VUVLO < VIN < VOVP and VIN > VBAT+VSLP, TJ = 0ºC-125°C and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
D+/D– DETECTION
IDP_SRC D+ current source for DCD DCD 7 13 µA
RDM_DWN D– pull-down resistance for DCD DCD 14.25 24.8 kΩ
VDP_LOW D+ low comparator threshold for DCD DCD 0.85 0.9 0.95 V
VDP_SRC D+ source voltage for Primary Detection Primary Detection 0.5 0.6 0.7 V
D+ source voltage output current for Primary
IDP_SRC_PD Primary Detection 200 µA
Detection
IDM_SINK D– sink current for Primary Detection Primary Detection 50 100 150 µA
VDAT_REF Primary Detection threshold Primary Detection 250 325 400 mV
VLGC Primary Detection threshold Primary Detection 0.85 0.9 0.95 V
VDM_SRC D- source voltage for Secondary Detection Secondary Detection 0.5 0.6 0.7 V
D- source voltage output current for Secondary
IDM_SRC_PD Secondary Detection 200 µA
Detection
IDP_SINK D+ sink current for Secondary Detection Secondary Detection 50 100 150 µA
VDAT_REF Secondary Detection threshold Secondary Detection 250 325 400 mV
VATT_LO Apple/TomTom detection low threshold Apple/TomTom Detection 1.8 1.85 1.975 V
VATT_HI Apple/TomTom detection high threshold Apple/TomTom Detection 3.2 3.5 3.8 V
D– , switch open 4.5
CI Input Capacitance pF
D+, switch open 4.5
D–, switch open –1 1
ID_LKG Leakage Current into D+/D– µA
D+, switch open –1 1

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8.6 Typical Characteristics

VBAT = 3.8 V VIN = 5 V VREG = 4.2 V VBAT = 3.8 V VIN = 6 V VREG = 4.2 V
ICHG = 0.5 A ILIM = 1 A ICHG = 1 A ILIM = 1 A

Figure 1. Battery Detection Figure 2. Battery Removal

88 4.350
86 4.345

84 4.340
4.335
82
Efficiency (%)

VSYS-REG (V)

4.330
80
4.325
78
4.320
76
4.315
74 4.310
72 4.305
70 4.300
2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 0.0 0.5 1.0 1.5 2.0 2.5
VBAT (V) C001 ISYS (A) C004

ICHG = 2 A VIN = 5 V VREG = 4.2 V VIN = 5 V No Battery ILIM = 2 A

VREG = 4.2 V Charge Disable

Figure 3. Efficiency vs Battery Voltage Figure 4. System Voltage Regulation vs Load Current
100 100
95 95
90 90
85 85
Efficiency (%)

Efficiency (%)

80 80
75 75
70 70
65 65
60 VIN V
VIN ==55V 60 VIN V
VIN ==55V
VIN ==77V
VIN V VIN ==77V
VIN V
55 55
VIN ==10
VIN V
10V VIN ==10
VIN V
10V
50 50
0 200 400 600 800 1000 1200 1400 1600 1800 2000 0 200 400 600 800 1000 1200 1400 1600 1800 2000
Output Current (mA) C002 Output Current (mA) C003

VREG = 4.2 V VREG = 3.6 V

Figure 5. Efficiency vs Output Current Figure 6. Efficiency vs Output Current

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Typical Characteristics (continued)

18 0.7
16
0.6
14
12 0.5

10

IBAT ( A)
IBAT ( A)

0.4
8
0.3
6
4 0.2
2
0.1
0
±2 0.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
VBAT (V) C007 VBAT (V) C010

VIN = 0 V SYSOFF = 0 Charge Enabled VIN = 0 V SYSOFF = 1 Charge Enabled

BAT & SYS are Shorted BAT & SYS are Shorted

Figure 7. BAT IQ, SYSOFF = 0 Figure 8. BAT IQ, SYSOFF = 1

20 500
CE EN
18 450
CE DIS
16 400
Input Current (mA)

14
Input Current ( A)

350
12 300
10 250
8 200
6 150
4 100
2 50
0 0
0 5 10 15 20 25 0 5 10 15 20 25
Input Voltage (V) C008 Input Voltage (V) C009

Charge EN and DIS No Battery and System Charge EN Hi-Z EN

Figure 9. Input IQ With Charge DIS and EN Figure 10. Input IQ with Charge Enable and Hi-Z
2.5 3.0

2.5
2.0
2.0
1.5
1.5
Accuracy (%)

Accuracy (%)

1.0 1.0

0.5 0.5

0.0
0.0
±0.5
500 mA 500 mA
±0.5
1A ±1.0 1A
1.5 A 1.5 A
±1.0 ±1.5
0 10 20 30 40 50 60 70 80 90 100 110 120 130 0 10 20 30 40 50 60 70 80 90 100 110 120 130
Temperature (°C) C011 Temperature (°C) C012

VBAT = 3.3 V VIN = 5 V VREG = 4.2 V VBAT = 3.8 V VIN = 5 V VREG = 4.2 V
ILIM = 2 A ILIM = 2 A

Figure 11. ICHG Accuracy with Internal Settings, VBAT = 3.3 V Figure 12. ICHG Accuracy with Internal Settings, VBAT = 3.8 V

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Typical Characteristics (continued)

0.6

0.5

0.4
VILIM/IIN

0.3

0.2

0.1 RILIM = 257 Ÿ

RILIM = 140 Ÿ
0.0
0.23 0.24 0.24 0.24 0.24 0.28
Input Current C013

VBAT = 3.9 V VOVP = 10.5 V

ICHG = 1 A ILIM = 1 A
Figure 13. Ratio Between VILIM and IIN With External ILIM
Control Figure 14. Input OVP Event with INT

9 Detailed Description

9.1 Overview
The bq24250 is a highly-integrated, single-cell, Li-Ion battery charger with integrated current sense resistors
targeted for space-limited, portable applications with high-capacity batteries. The single-cell charger has a single
input that operates from either a USB port or AC wall adapter for a versatile solution.
The bq24250 device has two modes of operation: 1) I2C mode, and 2) standalone mode. In I2C mode, the host
adjusts the charge parameters and monitors the status of the charger operation. In standalone mode, the
external resistor sets the input-current limit, and charge current limit. Standalone mode also serves as the default
settings when a DCP adapter is present. It enters host mode while the I2C registers are accessed and the
watchdog timer has not expired (if enabled). The battery is charged in four phases: trickle charge, pre-charge,
constant current and constant voltage. In all charge phases, an internal control loop monitors the IC junction
temperature and reduces the charge current if the internal temperature threshold is exceeded.

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9.2 Functional Block Diagram

PMID

Q1 LDO LDO

IN

Charge
Pump
Q2

VREF_CBCLIM
ILIM

+ BOOT

_
CbC
Comparator

IIN_LIM
Amp
_
VREF_INLIM
+

VIN_DPM
+ Amp
VDPM VREF_DPM _ PWM
LOOP SELECT
Host COMPENSATION
DRIVER
+
SW
_
VDPM_DAC
V LDO
I2C Only
Q3
TJ
125 C
+ PGND

MINSYS
Amp _

+ VREF_MINSYS +
ICHG
Amp VSYSMIN
_
ISET
+
VBATREG
Amp
_
SYS
Sleep
Comparator +
_ VREF_BATREG

VBAT +V SLP + VREF_ICHG

VREF_TERM
+
EN1 / D+ Input Termination LDO
current limit Comparator
Batt Detect Or
decoder / V MINSYS Q4 Precharge
EN2 / D- D+ and D- Reference
Recharge Comparator
Decoder Current Source
+ VBATREG – 0.12V
VBAT MINSYS
ICHG Amp
SCL BAT
V OUTMIN Comparator +
I2C
Controller + V OUT
SDA Charge
Pump
CHARGE
CONTROLLER
INT / PG MINSYS Comparator
+ V SYS
V MINSYS
BATSHORT Comparator

+ V BAT
STAT/CHG
VBATSHRT

Supplement Comparator
+ VSYS
VBAT V BSUP VLDO
DISABLE

+
/CE
TS -10°C

TS 0°C

TS 10°C
+

TS 45°C

TS 60°C

TS

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9.3 Feature Description

9.3.1 Charge Profile
The bq2425x family provides a switch-mode buck regulator with output power path and a charge controller to
provide optimum performance over the full battery charge cycle. The control loop for the buck regulator has 7
primary feedback loops that can set the duty cycle:
1. Constant Current (CC)
2. Constant Voltage (CV)
3. Minimum System Voltage (MINSYS)
4. Input Current (IILIM)
5. Input Voltage (VIN_DPM)
6. Die Temperature
7. Cycle by Cycle Current
The feedback with the minimum duty cycle will be chosen as the active loop. The bq24250, 1, 3 support a
precision Li-Ion or Li-Polymer charging system for single-cell applications. The Dynamic Power Path
Management (DPPM) feature regulates the system voltage to a minimum of VMINSYS, so that startup is enabled
even with a missing or deeply discharged battery. This provides a much better overall user experience in mobile
applications. Figure 15 illustrates a typical charge profile while also demonstrating the minimum system output
voltage regulation.

Trickle Pre- Current Regulation Voltage Regulation

Termination
Charge charge Phase(CC) Phase(CV)

V BATREG

ICHG
ICHG

V MINSYS VSYS
(3.5 V)
VBAT

V LOWV

V BATSHRT
I PRECHG
I TERM
I BATSHRT
Linear trickle Linear Linear
BATFET on-- PWM fast charge BATFET off
charge Pre- charge fast charger

MINSYS BATREG SYSREG

regulation regulation regulation

Figure 15. bq24250 Charge Profile and Minimum System Output Voltage Regulation

Figure 16 demonstrates a measured charge profile with the bq2425X while charging a 2700mAh Li-Ion battery at
a charge rate of 1A.

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Feature Description (continued)

5.0 1.2
4.5 1.1
1.0
4.0
0.9

Charge Current (A)

3.5
0.8
Voltage (V)

3.0 0.7
2.5 0.6
2.0 0.5
0.4
1.5 V
VBAT
BAT 0.3
1.0
VSYS
V SYS 0.2
0.5 0.1
IIBAT
BAT
0.0 0.0
0 2k 4k 6k 8k 10k 12k 14k 16k
Time (s) C005

ICHG = 1 A

Figure 16. bq24250 Charge Profile while Charging a 2700-mAh Battery at a 1A Charge Rate

Figure 17 illustrates the precharge behavior of the above charge profile by narrowing the time axis to 0 – 120
seconds.
3.7 1.2
1.1
3.5 1.0
0.9 Charge Current (A)
3.3 0.8
Voltage (V)

0.7
3.1 0.6
0.5
2.9 0.4
V
VBAT
BAT
0.3
2.7 V
VSYS
SYS 0.2
IIBAT 0.1
BAT
2.5 0.0
0 20 40 60 80 100 120
Time (s) C006

ICHG = 1 A

Figure 17. bq24250 Charge Profile While Charging a 2700-mAh Battery at a 1A Charge During Precharge

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Feature Description (continued)

9.3.2 EN1 and EN2 Pins
The bq24250 is I2C and Stand Alone part. The EN1 and EN2 pins are available in this IC spin to support USB
2.0 compliance. These pins are used for Input Current Limit Configuration I. Set EN1 and EN2 to control the
maximum input current and enable USB compliance. See Table 1 below for programming details.
The bq24251 is also an I2C and Stand Alone part. The EN1 and EN2 are not available for this spin but the D+/D-
are available to support the BC1.2 D+/D- Based Adapter Detection. It detects DCP, SDP, and CDP. Also it
complies with the unconnected dead battery provision clause. D+ and D- pins are connected to the D+ and D-
outputs of the USB port at power up. Also includes the detection of AppleTM and TomTomTM adapters where a
500mA input current limit is enabled. The /PG pin will remain high impedance state until the detection is
completed.
The bq24253 is only Stand Alone part. Both of the D+/D- and EN1/EN2 are available for this spin. During power
up, the device checks first for the D+/D-. The EN1 and EN2 do not take effect until D+/D- detection routine is
over and a change on the status of the EN1 and EN2 occurred.
When the input current limit pins change state, the VIN_DPM threshold changes as well. See Table 1 for the
detailed truth table:

Table 1. EN1 and EN2 Truth Table (1)

EN2 EN1 Input Current Limit VIN_DPM Threshold
0 0 500mA 4.36V
0 1 Externally programmed by ILIM (up to 2.0A) Externally programmed VDPM
1 0 100mA 4.36V
1 1 Input Hi-Z None

(1) USB3.0 support available. Contact your local TI representative for details.

9.3.3 External Settings: ISET, ILIM and VIN_DPM

If the external resistor settings are used, the following equations can be followed to configure the charge settings.
The fast charge current resistor (RISET) can be set by using the following formula:
K 250
RISET = ISET =
IFC IFC (1)
Where IFC is the desired fast charge current setting in Amperes.
The input current limit resistor (RILIM) can be set by using the following formula:
K 270
RILIM = ILIM =
IIC IIC (2)
Where IIC is the desired input current limit in Amperes.
Based on the application diagram reference designators, the resistor R1 and R2 can be calculated as follows to
set VIN_DPM:
R + R2 R + R2
VIN _ DPM = VREF _ DPM ´ 1 = 1.2V ´ 1
R2 R2 (3)
VIN_DPM should be chosen first along with R1. Choosing R1 first will ensure that R2 will be greater than the
resistance chosen. This is the case since VIN_DPM should be chosen to be greater than 2x VREF_DPM.
If external resistors are not desired in order to reduce the BOM count, the VDPM and the ILIM pins can be
shorted to set the internal defaults. The ISET resistor must be connected in order to avoid an unstable charging
state. Note that floating the ILIM pin will result in zero charge current if the external ISET is configured via the I2C
register. Table 2 summarizes the settings when the ILIM, ISET, and VIN_DPM pins are shorted to GND:

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Table 2. ILIM, VDPM, and ISET Short Behaviors

PIN SHORTED BEHAVIOR
ILIM Input current limit = 2A
VDPM VIN_DPM = 4.68V
ISET Fault—Charging Suspended

9.3.4 BC1.2 D+/D– Detection

The bq24251 and the bq24253 include a fully BC1.2 compatible D+/D– source detection. This detection supports
the following types of ports:
• DCP (dedicated charge port)
• CDP (charging downstream port)
• SDP (standard downstream port)
• Apple™/TomTom™ ports
This D+/D– detection algorithm does not support ACA (accessory charge adapter) identification, but the input
current will default to 500mA when a charge port is attached to the ACA and bq24251/3 is connected to the OTG
port.
The D+/D– detection algorithm is only active when the device is in standalone mode (e.g. the host is not
communicating with the device and the watch dog timer has expired). However, when the device is in host mode
(e.g. host is communicating via I2C to the device) writing a ‘1’ to register 0x04 bit location 4 (DPDM_EN) forces
the device to perform a D+/D– detection. This allows the D+/D– detection to be enabled in both host mode and
default mode. The current limit will not be implemented in host mode.
As described previously, the bq24253 is only a Stand Alone part. Both of the D+/D- and EN1/EN2 are available
for this spin. The below flow diagram illustrates the behavior of the bq24253 in D+/D- detection and the effect of
the EN1/EN2. During power up, the device checks first for the D+/D-. The EN1 and EN2 do not take effect until
D+/D- detection routine is over and a change on the status of the EN1 and EN2 occurred.

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Battery or Input
Is Inserted

No
VIN or VBAT Good?

Yes

Enable D+/D-
Detection Algorithm

Set SDP, CDP, DCP,

or Non-Standard port
settings

EN1/EN2 Change State? VIN < UVLO

No No
Yes
Yes

EN1/EN2 Truth Table

VIN < UVLO
Becomes Active No
Yes

Figure 18. bq24253 D+/D- and EN1/EN2

The D+/D– detection algorithm has 5 primary states. These states are termed the following:
1. Data Contact Detect
2. Primary Detection
3. Secondary Detection
4. Non-standard Adapter Detection (for Apple™ / TomTom™)
5. Detection Configuration
The DCD state determines if the device has properly connected to the D+/D– lines. If the device is not in host
mode and VBUS is inserted (or DPDM_EN is true) the device enters the DCD state and enable the appropriate
algorithm. If the DCD timer expires, the device enters the Non-standard Adapter Detection (for Apple™ /
TomTom™) state. Otherwise it enters the Primary Detection state.

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When entering the Primary Detection state, the appropriate algorithm is enabled to determine whether to enter
the secondary detection state for DCP and CDP or the secondary detection state for SDP/Non-Standard
adaptors.
The non-standard adapter detection state for Apple™ / TomTom™ tests for the unique conditions for these non-
standard adapters. If the algorithm passes the unique conditions found with these adapters, it proceeds to the
Detection Configuration state. Otherwise it reverts back to the primary detection state.
The secondary detection state determines whether the input port is a DCP, CDP, SDP, or other non-standard
adapters. If the Primary Detection state indicated that the input port is either a DCP or CDP, the device enables
the appropriate algorithm to differentiate between the two. If the Primary Detection state indicated that the input
port is either a SDP or non-standard adapter, the device enables the appropriate algorithm to differentiate
between these two ports. Once complete, the device continues to the Detection Configuration state.

DCP CDP SDP Non

Settings Settings Settings Standard
Adapter

No Yes Yes
VBAT > VBATGD? VBAT > VBATGD

Turn on VDP_SRC No
And keep it on until Turn on VDP_SRC
CLR_VDP is set to ‘1’ in I2C And keep it on until
CLR_VDP is set to ‘1’

CDP and CDP and SDP and SDP and Apple/TT or

DCP weak battery Non-Standard
External ILIM weak battery good battery good battery
IILIM =100 mA IILIM =1500 mA IILIM =100 mA IILIM=0.5 A
Start 6 hr timer Hi-Z mode
Start 45 min timer Start 6 hr timer Start 45 min timer Start 6 hr timer

Detection Done.
Set detection
status in register

Figure 19. Detection Configuration State

The detection configuration state sets the input current limit of the device along with the charge timer. The
exception to the CDP and the SDP settings are due to the Dead Battery Provision (DBP) clause for unconnected
devices. This clause states that the device can pull a maximum of 100mA when not connected due to a dead
battery. During the battery wakeup time, the device sources a voltage on the D+ pin in order to comply with the
DBP clause. Once the battery is good, the system can clear the D+ pin voltage by writing a ‘1’ to address 0x07
bit position 4 (CLR_VDP). The device must connect to the host within 1sec of clearing the D+ pin voltage per the
DPB clause.
A summary of the input current limits and timer configurations for each charge port type are found in Table 3.

Table 3. D+/D– Detection Results per Charge Port Type

CHARGE PORT TYPE INPUT CURRENT LIMIT CHARGE TIMER
DCP External ILIM 6 hours
CDP Dead Battery 100 mA 45 minutes
CDP Good Battery 1500 mA 6 hours
SDP Dead Battery 100 mA 45 minutes
SDP Good Battery Hi-Z N/A
Non-Standard 500 mA 6 hours

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9.3.5 Transient Response

The BQ24250/1/3 includes an advanced hybrid switch mode control architecture. When the device is regulating
the charge current (fast-charge), a traditional voltage mode control loop is used with a Type-3 compensation
network. However, the BQ24250/1/3 switches to a current mode control loop when the device enters voltage
regulation. Voltage regulation occurs in three charging conditions: 1) Minimum system voltage regulation (battery
below MINSYS), 2) Battery voltage regulation (IBAT < ICHG), and 3) Charge Done (VSYS = VBAT + 3.5%). This
architecture allows for superior transient performance when regulating the voltage due to the simplification of the
compensation when using current mode control. The below transient response plot illustrates a 0A to 2A load
step with 4.7ms full cycle and 12% duty cycle. A 3.9V Li-Ion battery is used. The input voltage is set to 5V,
charge current is set to 0.5A and the input current is limited to 0.5A. Note that a high line impedance input supply
was used to indicate a realistic input scenario (adapter and cable). This is illustrated by the change in VIN seen at
the input of the IC.
Figure 33 shows a ringing at both the input voltage and the input current. This is caused by the input current limit
speed up comparator.

9.3.6 AnyBoot Battery Detection

The bq2425x family includes a sophisticated battery detection algorithm used to provide the system with the
proper status of the battery connection. The AnyBoot battery algorithm also guarantees the detection of voltage
based battery protectors that may have a long closure time (due to the hysteresis of the protection switch and the
cell capacity). The AnyBoot battery detection algorithm utilizes a dual-voltage based detection methodology
where the system rail switches between two primary voltage levels. The period of the voltage level shift is 64ms
and therefore the power supply rejection of the down-system electronics detects this shift as essentially DC.
The AnyBoot algorithm has essentially 3 states. The 1st state is used to determine if the device has terminated
with a battery attached. If it has terminated due to the battery not being present, then the algorithm moves to the
2nd and 3rd states. The 2nd and 3rd states shift the system voltage level between 4.2V and 3.72V. In each state
there are comparator checks to determine if a battery has been inserted. The two states guarantees the
detection of a battery even if the voltage of the cell is at the same level of the comparator thresholds. The
algorithm will remain in states 2 and 3 until a battery has been inserted. The flow diagram details for the Anyboot
algorithm are shown in Figure 20.

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Enter Battery
Detection

BATREG = Vreg
setting – 480 mV

No

VBAT > Yes Battery Detected, STAT

Yes
BATREG+120 mV? 32 ms Timer Expired? register updated, and PTM
mode aborted (if enabled)

No

No
32 ms Timer Expired?

Yes

BATREG = 4.2 V

No

Yes Battery Detected, STAT

Yes
VBAT < 4.08 V? 32 ms Timer Expired? register updated and
Exit Battery Detection

No

No
32ms Timer Expired?

Yes

ONLY ON FIRST LOOP ITERATION

“No Battery” Condition
BATREG = 4.2 V
Update STAT Registers and send Fault Pulse

Yes Enter PTM mode

Force PTM = 1?
Exit Battery Detection

No

BATREG = 3.72 V

No

Yes Battery Detected, STAT

Yes
VBAT > 3.84 V? 32 ms Timer Expired? register updated and
Exit Battery Detection
No

No
32 ms Timer Expired?

Yes

Figure 20. AnyBoot Battery Detection Flow Diagram

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9.3.7 Input Voltage Based DPM

During normal charging process, if the input power source is not able to support the programmed or default
charging current, the supply voltage deceases. Once the supply drops to VIN_DPM, the input current limit is
reduced down to prevent the further drop of the supply. When the IC enters this mode, the charge current is
lower than the set. This feature ensures IC compatibility with adapters with different current capabilities without a
hardware change.

9.3.8 Sleep Mode

The bq2425x enters the low-power sleep mode if the voltage on VIN falls below sleep-mode entry threshold,
VBAT+VSLP, and VIN is higher than the under-voltage lockout threshold, VUVLO. This feature prevents draining
the battery during the absence of VIN. When VIN < VBAT+VSLP, the bq2425x turns off the PWM converter,
turns on the battery FET, sends a single 256µs pulse on the STAT and INT outputs and the FAULT/STAT bits of
the status registers are updated in the I2C. Once VIN > VBAT+VSLP with the hysteresis, the FAULT bits are
cleared and the device initiates a new charge cycle.

9.3.9 Input Over-Voltage Protection

The bq2425x provides over-voltage protection on the input that protects downstream circuitry. The built-in input
over-voltage protection to protect the device and other components against damage from overvoltage on the
input supply (Voltage from VIN to PGND). When VIN > VOVP, the bq2425x turns off the PWM converter, turns
on the battery FET, sends a single 256μs pulse on the STAT and INT outputs and the FAULT/STAT bits of the
status registers and the battery/supply status registers are updated in the I2C. Once the OVP fault is removed,
the FAULT bits are cleared and the device returns to normal operation. The OVP threshold for the bq24250 is
programmable from 6.5V to 10.5V using VOVP bits in register #7.

9.3.10 NTC Monitor

The bq24250/1/3 includes the integration of an NTC monitor pin that complies with the JEITA specification (PSE
also available upon request). The voltage based NTC monitor allows for the use of any NTC resistor with the use
of the circuit shown in Figure 21.

LDO
R2
TS
NTC R3

Figure 21. Voltage Based NTC Circuit

The use of R3 is only necessary when the NTC does not have a beta near 3500K. When deviating from this
beta, error will be introduced in the actual temperature trip thresholds. The trip thresholds are summarized below
which are typical values provided in the specification table.

Table 4. Ratiometric TS Trip Thresholds for JEITA Compliant Charging

TS THRESHOLDS VTS/VLDO
VHOT 30.0%
VWARM 38.3%
VCOOL 56.5%
VCOLD 60%

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When sizing for R2 and R3, it is best to solve two simultaneous equations that ensure the temperature profile of
the NTC network will cross the VHOT and VCOLD thresholds. The accuracy of the VWARM and VCOOL thresholds will
depend on the beta of the chosen NTC resistor. The two simultaneous equations are shown below:
æ R3 RNTC ö
ç TCOLD ÷
ç R3 + RNTC ÷
TCOLD ø
%VCOLD = è ´ 100
æ R3 RNTC ö
TCOLD ÷
ç + R2
ç R3 + RNTC ÷
è TCOLD ø

æ R3 RNTC ö
ç THOT ÷
ç R3 + RNTC ÷
THOT ø
%VHOT = è ´ 100
æ R3 RNTC ö
THOT ÷
ç + R2
ç R3 + RNTC ÷
è THOT ø (4)
Where the NTC resistance at the VHOT and VCOLD temperatures must be resolved as follows:
b 1 ( -1 )
RNTC = Ro e TCOLD To
TCOLD
β 1 ( -1 )
RNTC =Ro e THOT To
THOT (5)
To be JEITA compliant, TCOLD must be 0°C and THOT must be 60°C. If an NTC resistor is chosen such that the
beta is 4000K and the nominal resistance is 10kΩ, the following R2 and R3 values result from the above
equations:
R2 = 5 kΩ
R3 = 9.82 kΩ
Figure 22 illustrates the temperature profile of the NTC network with R2 and R3 set to the above values.
Example NTC Network Profile of %LDO vs. TEMP
60

Tcool
55
LDO Percent (%)

50

45

40
Twarm

35

30
0 10 20 30 40 50 60
Temperature (C)

Figure 22. Voltage Based NTC Circuit Temperature Profile

For JEITA compliance, the TCOOL and TWARM levels are to be 10°C and 45°C respectively. However, there is
some error due to the variation in beta from 3500K. As shown above, the actual temperature points at which the
NTC network crosses the VCOOL and VWARM are 13°C and 47°C respectively. This error is small but should be
considered when choosing the final NTC resistor.

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Once the resistors are configured, the internal JEITA algorithm will apply the below profile at each trip point for
battery voltage regulation and charge current regulation. In order to ensure continuation of the charge process
when an almost-full battery stops charging due to a cold temperature fault, it is recommended that a CE toggle is
done on the I2C or CE pin.

4.10V max
Programmed VBAT_REG 4.06V typ

No Charge No Charge

Programmed ICHG
(1C)

0.5C

No Charge No Charge

TS_DIS VCOLD VCOOL VWARM VHOT

Figure 23. JEITA Profile for Voltage and Current Regulation Loops

9.3.11 Production Test Mode

To aid in end mobile device product manufacturing, the bq2425x includes a Production Test Mode (PTM), where
the device is essentially a DC-DC buck converter. In this mode the input current limit to the charger is disabled
and the output current limit is limited only by the inductor cycle-by-cycle current (e.g. 3.5A). The PTM mode can
be used to test systems with high transient loads such as GSM transmission without the need of a battery being
present.
As a means of safety, the Anyboot algorithm will determine if a battery is not present at the output prior to
enabling the PTM mode. If a battery is present and the software attempts to enter PTM mode, the device will not
enable PTM mode.

9.3.12 Safety Timer

At the beginning of charging process, the bq24250/1/3 starts the safety timer. This timer is active during the
entire charging process. If charging has not terminated before the safety timer expires, the IC enters suspend
mode where charging is disabled. The safety timer time is selectable using the I2C interface. A single 256μs
pulse is sent on the STAT and INT outputs and the FAULT/ bits of the status registers are updated in the I2C.
This function prevents continuous charging of a defective battery if the host fails to reset the safety timer. When
2xTMR_EN bit is set to “1”, the safety timer runs at a rate 2x slower than normal (the timer is extended) under
the following conditions:
• Pre-charge or linear mode (minimum system voltage mode),
• During thermal regulation where the charge current is reduced,
• During TS fault where the charge current is reduced due to temperature rise on the battery, input current limit
The safety timer is suspended during OVP, TS fault where charge is disabled, thermal shut down, and sleep
mode. Removing the battery causes the safety timer to be reset and NOT halted/paused.

9.3.13 Watchdog Timer

In addition to the safety timer, the bq24250/1 contains a 50-second watchdog timer that monitors the host
through the I2C interface. Once a write is performed on the I2C interface, a watchdog timer is reset and started.
The watchdog timer can be disabled by writing “0” on WD_EN bit of register #1. Writing “1” on that bit enables
and resets the timer.

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If the watchdog timer expires, the IC enters DEFAULT mode where the default charge parameters are loaded
and charging continues. The I2C may be accessed again to re-initialize the desired values and restart the
watchdog timer as long as the safety timer has not expired. Once the safety timer expires, charging is disabled.

9.3.14 Fault Modes

The bq2425x family includes several hardware fault detections. This allows for specific conditions that could
cause a safety concern to be detected. With this feature, the host can be alleviated from monitoring unsafe
charging conditions and also allows for a “fail-safe” if the host is not present. The table below summarizes the
faults that are detected and the resulting behavior.

FAULT CONDITION CHARGER BEHAVIOR SAFETY TIMER BEHAVIOR

Input OVP VSYS and ICHG Disabled Suspended
Input UVLO VSYS and ICHG Disabled Reset
Sleep (VIN < VBAT) VSYS and ICHG Disabled Suspended
TS Fault (Batter Over Temp) VSYS Active and ICHG Disabled Suspended
Thermal Shutdown VSYS and ICHG Disabled Suspended
Timer Fault VSYS Active and ICHG Disabled Reset
No Battery VSYS Active and ICHG Disabled Suspended
ISET Short VSYS Active and ICHG Disabled Suspended
Input Fault & LDO Low VSYS and ICHG Disabled Suspended

9.3.15 Dynamic Power Path Management

The bq24250/1/3 features a SYS output that powers the external system load connected to the battery. This
output is active whenever a valid source is connected to IN or BAT. The following discusses the behavior of SYS
with a source connected to the supply or a battery source only.
When a valid input source is connected to the input and the charge is enabled, the charge cycle is initiated. In
case of VBAT > ~3.5V, the SYS output is connected to VBAT. If the SYS voltage falls to VMINSYS, it is
regulated to the VSYSREG threshold to maintain the system output even with a deeply discharged or absent
battery. In this mode, the SYS output voltage is regulated by the buck converter and the battery FET is linearly
regulated to regulate the charge current into the battery. The current from the supply is shared between charging
the battery and powering the system load at SYS.
The dynamic power path management (DPPM) circuitry of the bq24250/1/3 monitors the current limits
continuously and if the SYS voltage falls to the VMINSYS voltage, it adjusts charge current to maintain the
minimum system voltage and supply the load on SYS. If the charge current is reduced to zero and the load
increases further, the bq24250/1/3 enters battery supplement mode. During supplement mode, the battery FET is
turned on and the battery supplements the system load.
If the battery is ever 5% above the regulation threshold, the battery OVP circuit shuts the PWM converter off and
the battery FET is turned on to discharge the battery to safe operating levels. Battery OVP FAULT is shown in
the I2C FAULT registers.
When no input source is available at the input and the battery is connected, the battery FET is turned on similar
to supplement mode. The battery must be above VBATUVLO threshold to turn on the SYS output. In this mode,
the current is not regulated; however, there is a short circuit current limit. If the short circuit limit is reached, the
battery FET is turned off for the deglitch time. After the deglitch time, the battery FET is turned on to test and see
if the short has been removed. If it has not, the FET turns off and the process repeats until the short is removed.
This process is to protect the internal FET from over current.

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9.4 Device Functional Modes

9.4.1 I2C Operation (Host Mode / Default Mode)
There are two primary modes of operation when interacting with the charge parameters of the bq24250 and
bq24251 chargers: 1) Host mode operation where the I2C registers set the charge parameters, and 2) Default
mode where the register defaults set the charge parameters.
Figure 24 illustrates the behavior of the bq24250 when transitioning between host mode and stand alone mode:

Battery or Input
is Inserted

No
VIN or VBAT GOOD?

Yes

No ILIM=EN1/EN2
I2C command received? VDPM=External Default
ISET=External Default

Yes
ILIM=Register Value
VDPM=Register Value
ISET=Register Value

No Yes
50s Watchdog Expired?

Host Mode

Figure 24. Host Mode and Stand Alone Mode Handoff

Once the battery or input is inserted and above the good thresholds, the device determines if an I2C command
has been received in order to discern whether to operate from the I2C registers or the internal register defaults. In
stand-alone mode the input current limit is set by the EN1/EN2 pins. If the watch dog timer is enabled, the device
will enter stand alone operation once the watchdog timer expires and re-initiate the default charge settings.

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9.5 Programming
9.5.1 Serial Interface Description
The bq2425x uses an I2C compatible interface to program charge parameters. I2C ™ is a 2-wire serial interface
developed by NXP (formerly Philips Semiconductor, see I2C-Bus Specification, Version 5, October 2012). The
bus consists of a data line (SDA) and a clock line (SCL) with pull-up structures. When the bus is idle, both SDA
and SCL lines are pulled high. All the I2C compatible devices connect to the I2C bus through open drain I/O pins,
SDA and SCL. A master device, usually a microcontroller or a digital signal processor, controls the bus. The
master is responsible for generating the SCL signal and device addresses. The master also generates specific
conditions that indicate the START and STOP of data transfer. A slave device receives and/or transmits data on
the bus under control of the master device.
The bq2425x device works as a slave and supports the following data transfer modes, as defined in the I2C
Bus™ Specification: standard mode (100 kbps) and fast mode (400 kbps). The interface adds flexibility to the
battery charge solution, enabling most functions to be programmed to new values depending on the
instantaneous application requirements. The I2C circuitry is powered from IN when a supply is connected.
The data transfer protocol for standard and fast modes is exactly the same; therefore, they are referred to as the
F/S-mode in this document. The bq24250/1 device only supports 7-bit addressing. The device 7-bit address is
defined as ‘1101010’ (0x6Ah).
To avoid I2C hang-ups, a timer (tI2CRESET) runs during I2C transactions. If the transaction takes longer than
tI2CRESET, any additional commands are ignored and the I2C engine is reset. The timeout is reset with START
and repeated START conditions and stops when a valid STOP condition is sent.

9.5.1.1 F/S Mode Protocol

The master initiates data transfer by generating a start condition. The start condition is when a high-to-low
transition occurs on the SDA line while SCL is high, as shown in Figure 25. All I2C -compatible devices should
recognize a start condition.

DATA

CLK
S P
START Condition STOP Condition

Figure 25. START and STOP Condition

The master then generates the SCL pulses, and transmits the 7-bit address and the read/write direction bit R/W
on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires
the SDA line to be stable during the entire high period of the clock pulse (see Figure 26). All devices recognize
the address sent by the master and compare it to their internal fixed addresses. Only the slave device with a
matching address generates an acknowledge (see Figure 27) by pulling the SDA line low during the entire high
period of the ninth SCL cycle. Upon detecting this acknowledge, the master knows that communication link with a
slave has been established.

DATA

CLK

Data Line Change

Stable; of Data
Data Valid Allowed

Figure 26. Bit Transfer on the Serial Interface

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Programming (continued)
The master generates further SCL cycles to either transmit data to the slave (R/W bit 0) or receive data from the
slave (R/W bit 1). In either case, the receiver needs to acknowledge the data sent by the transmitter. So an
acknowledge signal can either be generated by the master or by the slave, depending on which one is the
receiver. The 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as
necessary. To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line
from low to high while the SCL line is high (see Figure 25). This releases the bus and stops the communication
link with the addressed slave. All I2C compatible devices must recognize the stop condition. Upon the receipt of
a stop condition, all devices know that the bus is released, and wait for a start condition followed by a matching
address. If a transaction is terminated prematurely, the master needs to send a STOP condition to prevent the
slave I2C logic from remaining in a incorrect state. Attempting to read data from register addresses not listed in
this section will result in 0xFFh being read out.

Data Output
by Transmitter

Not Acknowledge

Data Output
by Receiver
Acknowledge

SCL From 1 2 8 9
Master

Clock Pulse for

START Acknowledgement
Condition

Figure 27. Acknowledge on the I2C Bus

Recognize START or Recognize STOP or

REPEATED START REPEATED START
Condition Condition
Generate ACKNOWLEDGE
Signal

SDA
MSB Acknowledgement Sr
Signal From Slave
Address

R/W

SCL
S Sr
or ACK ACK or
Sr P

Figure 28. Bus Protocol

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9.6 Register Maps

9.6.1 Register #1
Memory location: 00, Reset state: x0xx xxxx

BIT NAME READ/WRITE FUNCTION

Read:0 – No fault
B7(MSB) WD_FAULT Read only
1 – WD timeout if WD enabled
0 – Disable
B6 WD_EN Read/Write
1 – Enable (also resets WD timer)
B5 STAT_1 Read only 00 – Ready
01 – Charge in progress
B4 STAT_0 Read only 10 – Charge done
11 – Fault
B3 FAULT_3 Read only 0000 – Normal
B2 FAULT_2 Read only 0001 – Input OVP
0010 – Input UVLO
B1 FAULT_1 Read only 0011 – Sleep
0100 – Battery Temperature (TS) Fault
0101 – Battery OVP
0110 – Thermal Shutdown
B0(LSB) FAULT_0 Read only 0111 – Timer Fault
1000 – No Battery connected
1001 – ISET short
1010 – Input Fault and LDO low
• WD_FAULT – ‘0’ indicates no watch dog fault has occurred, where a ‘1’ indicates a fault has previously
occurred.
• WD_EN – Enables or disables the internal watch dog timer. A ‘1’ enables the watch dog timer and a ‘0’
disables it. '1' is default for bq24251 only.
• STAT – Indicates the charge controller status.
• FAULT – Indicates the faults that have occurred. If multiple faults occurred, they can be read by sequentially
addressing this register (e.g. reading the register 2 or more times). Once all faults have been read and the
device is in a non-fault state, the fault register will show “Normal”. Regarding the "Input Fault & LDO Low" the
IC indicates this if LDO is low and at the same time the input is below UVLO or coming out of UVLO with
LDO still low.

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9.6.2 Register #2
Memory location: 01, Reset state: xxxx 1100

BIT NAME READ/WRITE FUNCTION

Write:
B7(MSB) Reset Write only 1 – Reset all registers to default values
0 – No effect
B6 IIN_ILIMIT_2 Read/Write 000 – USB2.0 host with 100mA current limit
B5 IIN_ILIMIT_1 Read/Write 001 – USB3.0 host with 150mA current limit
010 – USB2.0 host with 500mA current limit
011 – USB3.0 host with 900mA current limit
100 – Charger with 1500mA current limit
B4 IIN_ILIMIT _0 Read/Write 101 – Charger with 2000mA current limit
110 – External ILIM current limit
111- No input current limit with internal clamp at 3A (PTM MODE)
0 – Disable STAT function
B3 EN_STAT Read/Write
1 – Enable STAT function
0 – Disable charge termination
B2 EN_TERM Read/Write
1 – Enable charge termination
0 – Charging is enabled
B1 CE Read/Write
1 – Charging is disabled
0 – Not high impedance mode
B0 (LSB) HZ_MODE Read/Write
1 – High impedance mode
• IIN_LIMIT – Sets the input current limit level. When in host mode this register sets the regulation level. However,
when in standalone mode (e.g. no I2C writes have occurred after power up or the WD timer has expired) the
external resistor setting for IILIM sets the regulation level.
• EN_STAT – Enables and disables the STAT pin. When set to a ‘1’ the STAT pin is enabled and function
normally. When set to a ‘0’ the STAT pin is disabled and the open drain FET is in HiZ mode.
• EN_TERM – Enables and disables the termination function in the charge controller. When set to a ‘1’ the
termination function will be enabled. When set to a ‘0’ the termination function will be disabled. When
termination is disabled, there are no indications of the charger terminating (i.e. STAT pin or STAT registers).
• CE – The charge enable bit which enables or disables the charge function. When set to a ‘0’, the charger
operates normally. When set to a ‘1’, the charger is disables by turning off the BAT FET between SYS and
BAT. The SYS pin continues to stay active via the switch mode controller if an input is present.
• HZ_MODE – Sets the charger IC into low power standby mode. When set to a ‘1’, the switch mode controller
is disabled but the BAT FET remains ON to keep the system powered. When set to a ‘0’, the charger
operates normally.

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9.6.3 Register #3
Memory location: 02, Reset state: 1000 1111

BIT NAME READ/WRITE FUNCTION

B7(MSB) VBATREG_5 (1) Read/Write Battery Regulation Voltage: 640mV (default 1)
B6 VBATREG_4 (1) Read/Write Battery Regulation Voltage: 320mV (default 0)
(1)
B5 VBATREG_3 Read/Write Battery Regulation Voltage: 160mV (default 0)
B4 VBATREG_2 (1) Read/Write Battery Regulation Voltage: 80mV (default 0)
B3 VBATREG_1 (1) Read/Write Battery Regulation Voltage: 40mV (default 1)
B2 VBATREG_0 (1) Read/Write Battery Regulation Voltage: 20mV (default 1)
B1(4)(5) USB_DET_1/EN2 Read Only Return USB detection result or pin EN2/EN1 status –
00 – DCP detected / EN2=0, EN1=0
01 – CDP detected / EN2=0, EN1=1
B0(LSB) USB_DET_0/EN1 Read Only 10 – SDP detected / EN2=1, EN1=0
11 – Apple/TT or non-standard adaptor detected / EN2=1, EN1=1

(1) Charge voltage range is 3.5V—4.44V with the offset of 3.5V and step of 20mV (default 4.2V)
• VBATREG – Sets the battery regulation voltage
• USB_DET/EN – Provides status of the D+/D– detection-results for spins that include the D+/D– pins or the
state of EN1/EN2 for spins that include the EN1/EN2 pins

9.6.4 Register #4
Memory location: 03, Reset state: 1111 1000

BIT NAME READ/WRITE FUNCTION

Charge current
B7(MSB) ICHG_4 (1) (2)
Read/Write
800mA – (default 1)
Charge current:
B6 ICHG_3 (1) (2)
Read/Write
400mA – (default 1)
Charge current:
B5 ICHG_2 (1) (2)
Read/Write
200mA – (default 1)
Charge current:
B4 ICHG_1 (1) (2)
Read/Write
100mA – (default 1)
Charge current:
B3 ICHG_0 (1) (2)
Read/Write
50mA – (default 1)
B2 ITERM_2 (3) Read/Write Termination current sense threshold: 100mA (default 0)
(3)
B1 ITERM_1 Read/Write Termination current sense threshold: 50mA (default 0)
B0(LSB) ITERM_0 (3) Read/Write Termination current sense threshold: 25mA (default 0)

(1) Charge current offset is 500 mA and default charge current is external (maximum is 2.0A)
(2) When all bits are 1’s, it is external ISET charging mode
(3) Termination threshold voltage offset is 50mA. The default termination current is 50mA if the charge is selected from I2C. Otherwise,
termination is set to 10% of ICHG in external I_set mode with +/-10% accuracy.
• ICHG – Sets the charge current regulation
• ITERM – Sets the current level at which the charger will terminate

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9.6.5 Register #5
Memory location: 04, Reset state: xx00 x010

BIT NAME READ/WRITE FUNCTION

B7(MSB) LOOP_STATUS1 (1) Read Only 00 – No loop is active that slows down timer
01 – VIN_DPM regulation loop is active
B6 LOOP_STATUS0 (1) Read Only 10 – Input current limit loop is active
11 – Thermal regulation loop is active
0 – Normal charge current set by 03h
B5 LOW_CHG Read/Write
1 – Low charge current setting 330mA (default 0)
0 – Bit returns to 0 after D+/D– detection is performed
B4 DPDM_EN Read/Write
1 – Force D+/D– detection (default 0)
0 – CE low
B3 CE_STATUS Read Only
1 – CE high
(2)
B2 VINDPM_2 Read/Write Input VIN-DPM voltage: 320mV (default 0)
(2)
B1 VINDPM_1 Read/Write Input VIN-DPM voltage: 160mV (default 1)
(2)
B0(LSB) VINDPM_0 Read/Write Input VIN-DPM voltage: 80mV (default 0)

(1) LOOP_STATUS bits show if there are any loop is active that slow down the safety timer. If a status occurs, these bits announce the
status and do not clear until read. If more than one occurs, the first one is shown.
(2) VIN-DPM voltage offset is 4.20V and default VIN_DPM threshold is 4.36V.
• LOOP_STATUS – Provides the status of the active regulation loop. The charge controller allows for only one
loop can regulate at a time.
• LOW_CHG – When set to a ‘1’, the charge current is reduced 330mA independent of the charge current
setting in register 0x03. When set to ‘0’, the charge current is set by register 0x03.
• DPDM_EN – Forces a D+/D- detection routine to be executed once a ‘1’ is written. This is independent of the
input being supplied.
• CE_STATUS – Provides the status of the CE pin level. If the CE pin is forced high, this bit returns a ‘1’. If the
CE pin is forced low, this bit returns a ‘0’.
• VINDPM – Sets the input VDPM level.

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9.6.6 Register #6
Memory location: 05, Reset state: 101x 1xxx

BIT NAME READ/WRITE FUNCTION

0 – Timer not slowed at any time
B7(MSB) 2XTMR_EN Read/Write
1 – Timer slowed by 2x when in thermal regulation, VIN_DPM or DPPM (default 1)
B6 TMR_1 Read/Write Safety Timer Time Limit
00 – 0.75 hour fast charge
01 – 6 hour fast charge (default 01)
B5 TMR_2 Read/Write 10 – 9 hour fast charge
11 – Disable safety timers
0 – SYSOFF disabled
B4 SYSOFF Read/Write
1 – SYSOFF enabled
0 – TS function disabled
B3 TS_EN Read/Write
1 – TS function enabled (default 1)
B2 TS_STAT2 Read only TS Fault Mode:
B1 TS_STAT1 Read only 000 – Normal, No TS fault
001 – TS temp > THOT (Charging suspended for JEITA and Standard TS)
010 – TWARM < TS temp < THOT (Regulation voltage is reduced for JEITA standard)
011 – TCOLD < TS temp < TCOOL (Charge current is reduced for JEITA standard)
100 – TS temp < TCOLD (Charging suspended for JEITA and Standard TS)
B0(LSB) TS_STAT0 Read only 101 – TFREEZE < TS temp < TCOLD (Charging at 3.9V and 100mA and only for PSE option
only)
110 – TS temp < TFREEZE (Charging suspended for PSE option only)
111 – TS open (TS disabled)
• 2xTMR_EN – When set to a ‘1’, the 2x Timer function is enabled and allows for the timer to be extended if a
condition occurs where the charge current is reduced (i.e. VIN_DPM, thermal regulation, etc.). When set to a ‘0’,
this function is disabled and the normal timer will always be executed independent of the current reduce
conditions.
• SYSOFF – When set to a ‘1’ and the input is removed, the internal battery FET is turned off in order to reduce
the leakage from the BAT pin to less than 1µA. Note that this disconnects the battery from the system. When
set to a ‘0’, this function is disabled.
• TS_EN – Enables and disables the TS function. When set to a ‘0’ the TS function is disabled otherwise it is
enabled. Only applies to spins that have a TS pin.
• TS_STAT – Provides status of the TS pin state for versions that have a TS pin. “100” indicates the TS temp
< TCOLD and charging suspended for JEITA Standard. In order to ensure continuation of the charge process
when an almost-full battery stops charging due to a cold temperature fault, it is recommended that a CE
toggle is done on the I2C or CE pin.

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9.6.7 Register #7
Memory location: 06, Reset state: 1110 0000

BIT NAME READ/WRITE FUNCTION

B7(MSB) VOVP_2 Read/Write OVP voltage:
B6 VOVP_1 Read/Write 000 – 6.0V; 001 – 6.5V; 010 – 7.0V; 011 – 8.0V
B5 VOVP_0 Read/Write 100 – 9.0V; 101 – 9.5V; 110 – 10.0V; 111 –10.5V

0 – Keep D+ voltage source on during DBP charging

B4 CLR_VDP Read/Write
1 – Turn off D+ voltage source to release D+ line
FORCE_BAT 0 – Enter the battery detection routine only if TERM is true or Force PTM is true
B3 Read/Write
DET 1 – Enter the battery detection routine
0 – PTM mode is disabled
B2 FORCE_PTM Read/Write
1 – PTM mode is enabled
B1 N/A Read/Write Not available. Keep set to 0.
B0(LSB) N/A Read/Write Not available. Keep set to 0.
• VOVP – Sets the OVP level
• CLR_VDP – When the D+/D– detection has finished, some cases require the D+ pin to force a voltage of
0.6V. This bit allows the system to clear the voltage prior to any communication on the D+/D– pins. A ‘1’
clears the voltage at the D+ pin if present.
• FORCE_BATDET – Forces battery detection and provides status of the battery presence. A logic ‘1’ enables
this function.
• FORCE_PTM – Puts the device in production test mode (PTM) where the input current limit is disabled. Note
that a battery must not be present prior to using this function. Otherwise the function will not be allowed to
execute. A logic ‘1’ enables the PTM function.

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10 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

10.1 Application Information

The bq2425x devices are high-efficiency switched-mode chargers. The device has integrated power FETs that
are able to charge at up to a 2-A charging rate, and an integrated 50-mA LDO. In I2C mode (bq24250/1), the
device has programmable battery charge voltage (VBATREG), charge current (ICHG), input current limit (ILIM),
and input over-voltage protection threshold (VOVP). The charge current and the input current limit are
programmed using external resistors (RISET and RILIM) connected from the ISET and ILIM pins to ground. The
range of these resistors can be found in the datasheet. Both of these currents can be programmed up to 2 A.
The device also has complete system-level protection such as input under-voltage lockout (UVLO), input over-
voltage protection (OVP), battery OVP, sleep mode, thermal regulation and thermal shutdown, voltage-based
NTC monitoring input, and safety timers.

10.2 Typical Application

CPMID
1 µF

PMID LO
IN SW 1.0 PH
VBUS System Load
D- CIN
D+ R1
2.2 µF CBOOT
GND VDPM 3 MHz 33 nF
PWM
R2
BOOT
PGND
D- SYS

D+ 22 F
VSYS

LDO

1 PF

BAT
/PG
1 F
LDO
VGPIO
R3
TEMP PACK+
TS
R4 RNTC
SCL SCL
PACK-
SDA SDA
Host GPIO1
STAT

GPIO2 /CE

ILIM ISET

Figure 29. bq24251 Typical Application Circuit

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Typical Application (continued)

10.2.1 Design Requirements
Use the following typical application design procedure to select external components values for the bq24251
device.

Table 5. Design Parameters

SPECIFICATION TEST CONDITION MIN TYP MAX UNIT
Input DC voltage, VIN Recommended input voltage range 4.35 10.5 V
Input current Recommended input current range 2 A
Charge current Fast charge current range 0.5 2 A
Output regulation voltage Standalone mode or I2C default mode 4.2 V
I2C host mode: operating in voltage regulation,
Output regulation voltage 3.5 4.44 V
programmable range
LDO LDO output voltage 4.9 V

10.2.2 Detailed Design Procedure

10.2.2.1 Inductor Selection

The inductor selection depends on the application requirements. The bq24250 is designed to operate at around 1
µH. The value will have an effect on efficiency, and the ripple requirements, stability of the charger, package
size, and DCR of the inductor. The 1μH inductor provides a good tradeoff between size and efficiency and ripple.
Once the inductance has been selected, the peak current is needed in order to choose the saturation current
rating of the inductor. Make sure that the saturation current is always greater than or equal to the calculated
IPEAK. The following equation can be used to calculate the current ripple:
ΔIL = {VBAT (VIN – VBAT)}/(VIN x ƒs x L) (6)
Then use current ripple to calculate the peak current as follows:
IPEAK = Load x (1 + ΔIL/2) (7)
In this design example, the regulation voltage is set to 4.2V, the input voltage is 5V and the inductance is
selected to be 1µH. The maximum charge current that can be used in this application is 1A and can be set by
I2C command. The peak current is needed in order to choose the saturation current rating of the inductor. Using
equation 6 and 7, ΔIL is calculated to be 0.224A and the inductor peak current is 1.112A. A 1µF BAT cap is
needed and 22µF SYS cap is needed on the system trace.
The default settings for external fast charge current and external setting of current limit are chosen to be
IFC=500mA and ILIM=1A. RISET and RILIM need to be calculated using equation 1 and 2 in the data sheet.
The fast charge current resistor (RISET) can be set as follows:
RISET=250/0.5A=500Ω
The input current limit resistor (RILIM) can be set as follows:
RILIM= 270/1A=270Ω
The external settings of VIN_DPM can be designed by calculating R1 and R2 according to equation 3 in this data
sheet and the typical application circuit. VIN_DPM should be chosen first along with R1. VIN_DPM is chosen to
be 4.48V and R1 is set to 274KΩ in this design example. Using equation 3, the value of R2 is calculated to be
100KΩ.
In this design example, the application needs to be JEITA compliant. Thus, TCOLD must be 0°C and THOT must be
60°C. If an NTC resistor is chosen such that the beta is 4500K and the nominal resistance is 13KΩ, the
calculated R3 and R4 values are 5KΩ and 8.8KΩ respectively. These results are obtained from equation 4 and 5
in this data sheet.

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10.2.3 Application Curves

VBAT = 3.8 V ICHG = 1 A VBAT = 3.6 V ICHG = 2 A VDPM = 4.36 V

ISYS = 0 A ILIM = 1.5 A ISYS = 0 A ILIM = 0.5 A

Figure 30. Startup Figure 31. VDPM Startup, 4.2 V

VBAT = 3.3 V ICHG = 1 A VIN = 5.2 V

ISYS = 0 A

Figure 32. 1.0 µH CCM Operation Figure 33. 2-A Load Step Transient

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11 Power Supply Recommendations

The devices are designed to operate from an input voltage range between 4.35V and 10.5V. This input supply
must be well regulated. If the input supply is located more than a few inches from the bq24250 charger,
additional bulk capacitance may be required in addition to the ceramic bypass capacitors.

12 Layout

12.1 Layout Guidelines

1. Place the BOOT, PMID, IN, BAT, and LDO capacitors as close as possible to the IC for optimal performance.
2. Connect the inductor as close as possible to the SW pin, and the SYS/CSIN cap as close as possible to the
inductor minimizing noise in the path.
3. Place a 1-μF PMID capacitor as close as possible to the PMID and PGND pins, making the high frequency
current loop area as small as possible.
4. The local bypass capacitor from SYS/CSIN to GND must be connected between the SYS/CSIN pin and
PGND of the IC. This minimizes the current path loop area from the SW pin through the LC filter and back to
the PGND pin.
5. Place all decoupling capacitors close to their respective IC pins and as close as possible to PGND (do not
place components such that routing interrupts power-stage currents). All small control signals must be routed
away from the high-current paths.
6. To reduce noise coupling, use a ground plane if possible, to isolate the noisy traces from spreading its noise
all over the board. Put vias inside the PGND pads for the IC.
7. The high-current charge paths into IN, Micro-USB, BAT, SYS/CSIN, and from the SW pins must be sized
appropriately for the maximum charge current to avoid voltage drops in these traces.
8. For high-current applications, the balls for the power paths must be connected to as much copper in the
board as possible. This allows better thermal performance because the board conducts heat away from the
IC.

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12.2 Layout Example

Figure 34. Recommended bq2425x PCB Layout for DSBGA Package

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12.3 Thermal Considerations

During the charging process, to prevent overheat of the chip, bq24250/1/3 monitors the junction temperature, TJ,
of the die and begins to taper down the charge current once TJ reaches the thermal regulation threshold, TREG.
The charge current is reduced when the junction temperature increases above TREG. Once the charge current is
reduced, the system current is reduced while the battery supplements the load to supply the system. This may
cause a thermal shutdown of the IC if the die temperature rises too. At any state, if TJ exceeds TSHTDWN,
bq2425x suspends charging and disables the buck converter. During thermal shutdown mode, PWM is turned
off, all safety timers are suspended, and a single 256μs pulse is sent on the STAT and INT outputs and the
FAULT/STAT bits of the status registers are updated in the I2C. A new charging cycle begins when TJ falls below
TSHTDWN by approximately 10°C.

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13 Device and Documentation Support

13.1 Related Links

The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.

Table 6. Related Links

TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER SAMPLE & BUY
DOCUMENTS SOFTWARE COMMUNITY
bq24250 Click here Click here Click here Click here Click here
bq24251 Click here Click here Click here Click here Click here
bq24253 Click here Click here Click here Click here Click here

13.2 Trademarks
All trademarks are the property of their respective owners.
13.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

13.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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14.1 Package Summary

YFF Package YFF Package Symbol
(Top View) (Top Side Symbol for bq2425x)

A1 A2 A3 A4 A5

B1 B2 B3 B4 B5

C1 C2 C3 C4 C5
TI YMLLLLS
bq24250
D1 D2 D3 D4 D5 D
E1 E2 E3 E4 E5

F1 F2 F3 F4 F5

E
TI YMLLLLS
bq24251

TI YMLLLLS
bq24253

0-Pin A1 Marker, TI-TI Letters, YM- Year Month Date Code,

LLLL-Lot Trace Code, S-Assembly Site Code

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PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

BQ24250RGER ACTIVE VQFN RGE 24 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR BQ24250
& no Sb/Br)
BQ24250RGET ACTIVE VQFN RGE 24 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR BQ24250
& no Sb/Br)
BQ24250YFFR ACTIVE DSBGA YFF 30 3000 Green (RoHS SNAGCU Level-1-260C-UNLIM -40 to 85 BQ24250
& no Sb/Br)
BQ24250YFFT ACTIVE DSBGA YFF 30 250 Green (RoHS SNAGCU Level-1-260C-UNLIM -40 to 85 BQ24250
& no Sb/Br)
BQ24251RGER NRND VQFN RGE 24 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 BQ24251
& no Sb/Br)
BQ24251RGET NRND VQFN RGE 24 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 BQ24251
& no Sb/Br)
BQ24251YFFR NRND DSBGA YFF 30 3000 Green (RoHS SNAGCU Level-1-260C-UNLIM -40 to 85 BQ24251
& no Sb/Br)
BQ24251YFFT NRND DSBGA YFF 30 250 Green (RoHS SNAGCU Level-1-260C-UNLIM -40 to 85 BQ24251
& no Sb/Br)
BQ24253RGER ACTIVE VQFN RGE 24 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 BQ24253
& no Sb/Br)
BQ24253RGET ACTIVE VQFN RGE 24 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 BQ24253
& no Sb/Br)
BQ24253YFFR ACTIVE DSBGA YFF 30 3000 Green (RoHS SNAGCU Level-1-260C-UNLIM -40 to 85 BQ24253
& no Sb/Br)
BQ24253YFFT ACTIVE DSBGA YFF 30 250 Green (RoHS SNAGCU Level-1-260C-UNLIM -40 to 85 BQ24253
& no Sb/Br)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 6-Feb-2020

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 29-Sep-2019

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
BQ24250RGER VQFN RGE 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
BQ24250RGET VQFN RGE 24 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
BQ24250YFFR DSBGA YFF 30 3000 180.0 8.4 2.09 2.59 0.78 4.0 8.0 Q1
BQ24250YFFT DSBGA YFF 30 250 180.0 8.4 2.09 2.59 0.78 4.0 8.0 Q1
BQ24251RGER VQFN RGE 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
BQ24251RGET VQFN RGE 24 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
BQ24251YFFR DSBGA YFF 30 3000 180.0 8.4 2.09 2.59 0.78 4.0 8.0 Q1
BQ24251YFFT DSBGA YFF 30 250 180.0 8.4 2.09 2.59 0.78 4.0 8.0 Q1
BQ24253RGER VQFN RGE 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
BQ24253RGET VQFN RGE 24 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
BQ24253YFFR DSBGA YFF 30 3000 180.0 8.4 2.09 2.59 0.78 4.0 8.0 Q1
BQ24253YFFT DSBGA YFF 30 250 180.0 8.4 2.09 2.59 0.78 4.0 8.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 29-Sep-2019

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
BQ24250RGER VQFN RGE 24 3000 367.0 367.0 35.0
BQ24250RGET VQFN RGE 24 250 210.0 185.0 35.0
BQ24250YFFR DSBGA YFF 30 3000 182.0 182.0 20.0
BQ24250YFFT DSBGA YFF 30 250 182.0 182.0 20.0
BQ24251RGER VQFN RGE 24 3000 367.0 367.0 35.0
BQ24251RGET VQFN RGE 24 250 210.0 185.0 35.0
BQ24251YFFR DSBGA YFF 30 3000 182.0 182.0 20.0
BQ24251YFFT DSBGA YFF 30 250 182.0 182.0 20.0
BQ24253RGER VQFN RGE 24 3000 367.0 367.0 35.0
BQ24253RGET VQFN RGE 24 250 210.0 185.0 35.0
BQ24253YFFR DSBGA YFF 30 3000 182.0 182.0 20.0
BQ24253YFFT DSBGA YFF 30 250 182.0 182.0 20.0

Pack Materials-Page 2
 GENERIC PACKAGE VIEW
RGE 24 VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4204104/H
 PACKAGE OUTLINE
RGE0024H VQFN - 1 mm max height
PLASTIC QUAD FLATPACK- NO LEAD

4.1 A
B
3.9

4.1
PIN 1 INDEX AREA 3.9

1 MAX C

SEATING PLANE
0.05
0.00 0.08 C

2X 2.5 (0.2) TYP

7 12

20X 0.5
6
13

2X 25 SYMM
2.5

1 18
PIN 1 ID 24X 0.30
0.18
(OPTIONAL) 24 19 0.1 C A B
SYMM
24X 0.48
0.28
0.05 C
4219016 / A 08/2017
NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com
 EXAMPLE BOARD LAYOUT
RGE0024H VQFN - 1 mm max height
PLASTIC QUAD FLATPACK- NO LEAD
(3.825)

( 2.7)
24 19

24X (0.58)

24X (0.24)
1
18
20X (0.5)

SYMM 25
(3.825)

2X
(1.1)
TYP

6 13

(R0.05)

7 12
2X(1.1)
SYMM

LAND PATTERN EXAMPLE

SCALE: 20X

0.07 MAX 0.07 MIN

ALL AROUND METAL ALL AROUND
SOLDER MASK
OPENING
SOLDER MASK METAL UNDER
OPENING SOLDER MASK

NON SOLDER MASK

DEFINED SOLDER MASK
(PREFERRED) DEFINED

SOLDER MASK DETAILS

4219016 / A 08/2017

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments
literature number SLUA271 (www.ti.com/lit/slua271).
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
RGE0024H VQFN - 1 mm max height
PLASTIC QUAD FLATPACK- NO LEAD

(3.825)

4X ( 1.188)
24 19

24X (0.58)
24X (0.24)
1
18
20X (0.5)

SYMM (3.825)
(0.694)
TYP

6 13

(R0.05) TYP 25

METAL
TYP 7 12
(0.694)
TYP
SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD
78% PRINTED COVERAGE BY AREA
SCALE: 20X

4219016 / A 08/2017

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations..

www.ti.com
 PACKAGE OUTLINE
YFF0030 SCALE 4.500
DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY

B E A

BUMP A1
CORNER

C
0.625 MAX
SEATING PLANE
BALL TYP 0.05 C
0.30
0.12

1.6 TYP

SYMM

F
E
D: Max = 2.418 mm, Min =2.357 mm

E: Max = 2.018 mm, Min =1.957 mm

D SYMM
2
TYP C

A
0.4 TYP 1 2 3 4 5
0.3 0.4 TYP
30X
0.2
0.015 C A B

4219433/A 03/2016

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.

www.ti.com
 EXAMPLE BOARD LAYOUT
YFF0030 DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY

(0.4) TYP
30X ( 0.23)
1 2 3 4 5

A
(0.4) TYP

C
SYMM

SYMM

LAND PATTERN EXAMPLE

SCALE:25X

( 0.23) 0.05 MAX 0.05 MIN

METAL ( 0.23)
SOLDER MASK
OPENING

SOLDER MASK METAL UNDER

OPENING SOLDER MASK
NON-SOLDER MASK SOLDER MASK
DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS

NOT TO SCALE

4219433/A 03/2016

NOTES: (continued)

3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).

www.ti.com
 EXAMPLE STENCIL DESIGN
YFF0030 DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY

(0.4) TYP
(R0.05) TYP
30X ( 0.25)
1 2 3 4 5
A

(0.4)
TYP
B

METAL
TYP C
SYMM

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL
SCALE:30X

4219433/A 03/2016

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.

www.ti.com
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