Appendix : Instruction Set of 8051 Microcontroller

Mnemonics, Arranged Alphabetically

MNEMONIC DESCRIPTION BYTES CYCLES FLAGS

ACALL addr11 PC + 2 → (SP); addr11 → PC 2 2
ADD A, direct A + (direct) → A 2 1 C OV AC
ADD A, @Ri A + (Ri) → A 1 1 C OV AC
ADD A, #data A + #data → A 2 1 C OV AC
ADD A, Rn A + Rn → A 1 1 C OV AC
ADDC A, direct A + (direct) + C → A 2 1 C OV AC
ADDC A, @Ri A + (Ri) + C → A 1 1 C OV AC
ADDC A, #data A + #data + C → A 2 1 C OV AC
ADDC A, Rn A + Rn + C → A 1 1 C OV AC
AJMP addr11 Addr11 → PC 2 2
ANL A, direct A AND (direct) → A 2 1
ANL A, @Ri A AND (Ri) → A 1 1
ANL A, #data A AND #data → A 2 1
ANL A, Rn A AND Rn → A 1 1
ANL direct, A (direct) AND A → (direct) 2 1
ANL direct, #data (direct) AND #data → (direct) 3 2
ANL C, bit C AND bit → C 2 2 C
ANL C, bit C AND bit → C 2 2 C
CJNE A, direct, rel [A <> (direct)]: PC + 3 + rel → PC 3 2 C
CJNE A, #data, rel [A <> data]: PC + 3 + rel → PC 3 2 C
CJNE @Ri, #data, rel [(Ri) <> data]: PC + 3 + rel → PC 3 2 C
CJNE Rn, #data, rel [Rn <> data]: PC + 3 + rel → PC 3 2 C
CLR A 0→A 1 1
CLR bit 0 → bit 2 1
CLR C 0→C 1 1 0
CPL A A→A 1 1
CPL bit bit → bit 2 1
CPL C C→C 1 1 C
DA A Abin → Adec 1 1 C
DEC A A–1→A 1 1
DEC direct (direct) – 1 → (direct) 2 1
DEC @Ri (Ri) – 1 →(Ri) 1 1
DEC Rn Rn – 1 → Rn 1 1
DIV AB A/B → AB 1 4 0 OV
DJNZ direct, rel [(direct) – 1 <> 00]: PC + 3 + rel → PC 3 2
DJNZ Rn, rel [Rn – 1 <> 00]: PC + 2 + rel → PC 2 2
INC A A+1→A 1 1
INC direct (direct) + 1 → (direct) 2 1
INC DPTR DPTR + 1 → DPTR 1 2
INC @Ri (Ri) + 1 → (Ri) 1 1
INC Rn Rn + 1→ Rn 1 1
JB bit, rel [b=1]: PC + 3 + rel → PC 3 2
JBC bit, rel [b=1]: PC + 3 + rel → PC; 0 → bit 3 2
JC rel [C=1]: PC + 2 + rel → PC 2 2
JMP @A + DPTR DPTR + A → PC 1 2
JNB bit, rel [b=0]: PC + 3 + rel → PC 3 2
JNC rel [C=0]: PC + 2 + rel → PC 2 2
JNZ rel [A>00]: PC + 2 + rel → PC 2 2
JZ rel [A=00]: PC + 2 + rel → PC 2 2
LCALL addr16 PC + 3 → (SP); addr16 → PC 3 2
LJMP addr16 Addr16 → PC 3 2
MOV A, direct (direct) → A 2 1
MOV A, @Ri (Ri) → A 1 1
MOV A, #data #data → A 2 1
MOV A, Rn Rn → A 1 1
MOV direct, A A → (direct) 2 1
MOV direct, direct (direct) → (direct) 3 2
MOV direct, @Ri (Ri) → (direct) 2 2
MOV direct, #data #data → (direct) 3 2
MOV direct, Rn Rn → (direct) 2 2
MOV bit, C C → bit 2 2 C
MOV C, bit bit → C 2 1
MOV @Ri, A A → (Ri) 1 1
MOV @Ri, direct (direct) → (Ri) 2 2

EEE3410 Microcontroller Applications – TEST (2006/2007) Page 5

 MNEMONIC DESCRIPTION BYTES CYCLES FLAGS
MOV Rn, #data #data → Rn 2 1
MOVC A, @A+DPTR (A+DPTR) → A 1 2
MOVC A, @A+PC (A+PC) → A 1 2
MOVX A, @DPTR (DPTR)^ → A 1 2
MOVX A, @Ri (Ri)^ → A 1 2
MOVX @DPTR, A A → (DPTR)^ 1 2
MOVX @Ri, A A →(Ri)^ 1 2
NOP PC + 1 → PC 1 1
MUL AB A x B → AB 1 4 0 OV
ORL A, direct A OR (direct) → A 2 1
ORL A, @Ri A OR (Ri) → A 1 1
ORL A, #data A OR #data → A 2 1
ORL A, Rn A OR Rn → A 1 1
ORL direct, A (direct) OR A → (direct) 2 1
ORL direct, #data (direct) OR #data → (direct) 3 2
ORL C, bit C OR bit → C 2 2 C
ORL C, bit C OR bit → C 2 2 C
POP direct (SP) → (direct) 2 2
PUSH direct (direct) → (SP) 2 2
RET (SP) → PC 1 2
RETI (SP) → PC; EI 1 2
RL A A0←A7←A6..←A1←A0 1 1
RLC A C←A7←A6..←A0←C 1 1 C
RR A A0→A7→A6..→A1→A0 1 1
RRC A C→A7→A6..→A0→C 1 1 C
SETB bit 1 → bit 2 1
SETB C 1→C 1 1 1
SJMP rel PC + 2 + rel→ PC 2 2
SUBB A, direct A − (direct)−C → A 2 1 C OV AC
SUBB A, @Ri A − (Ri)−C → A 1 1 C OV AC
SUBB A, #data A − #data−C → A 2 1 C OV AC
SUBB A, Rn A − Rn−C → A 1 1 C OV AC
SWAP A Alsn ↔ Amsn 1 1
XCH A, direct A ↔ (direct) 2 1
XCH A, @Ri A ↔ (Ri) 1 1
XCH A, Rn A ↔ Rn 1 1
XCHD A, @Ri Alsn ↔ (Ri)lsn 1 1
XRL A, direct A XOR (direct) → A 2 1
XRL A, @Ri A XOR (Ri) → A 1 1
XRL A #data A XOR #data → A 2 1
XRL A, Rn A XOR Rn → A 1 1
XRL direct, A (direct) XOR A → (direct) 2 1
XRL direct, #data (direct) XOR #data → (direct) 3 2

ACRONYMS
addr11 Page address of 11 bits, which is in the same 2K page as the address of the following instruction.
addr16 Address for any location in the 64K memory space.
bit The address of a bit in the internal RAM bit address area or a bit in an SFR.
C The carry flag.
#data An 8-bit binary number from 00 to FFh.
#data16 A 16-bit binary number from 0000 to FFFFh.
direct An internal RAM address or an SFR byte address.
lsn Least significant nibble.
msn Most significant nibble.
rel Number that is added to the address of the next instruction to form an address +127d to −128d from the
address of the next instruction.
Rn Any of registers R0 to R7 of the current register bank.
@Ri Indirect address using the contents of R0 or R1.
[ ]: IF the condition inside the brackets is true, THEN the action listed will occur; ELSE go to the next instruction.
^ EXTERNAL memory location.
() Contents of the location inside the parentheses.

Note that flags affected each instruction are shown where appropriate; any operations which affect the PSW address
may also affect the flags.

EEE3410 Microcontroller Applications – TEST (2006/2007) Page 6