VLSI DESIGN FLOW: RTL TO

GDS

Lecture 29
Power Analysis
Sneh Saurabh
Electronics and Communications
Engineering
IIIT Delhi
Lecture Plan
Power Analysis:

▪ Components of Power Dissipation

▪ Power Models in Library

▪ Estimating Power Dissipation

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh

Components of Power Dissipation

Power dissipation is broadly of two types:

1. Dynamic Power Dissipation:

➢ Occurs when a circuit performs computation actively

2. Static Power Dissipation:

➢ When the circuit is powered on (supply voltages are applied), but it does not perform
active computation

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh

Dynamic Power Dissipation: Switching Power

Switching power dissipated in a

synchronous circuit:
2
𝑃𝑠𝑤 = 𝐶𝐿 𝑉𝐷𝐷 𝛼𝑓𝑐𝑙𝑘
where,
▪ 𝑓𝑐𝑙𝑘 =frequency of the clock in
the circuit
▪ 𝛼 =activity of the signal
➢ define 𝛼 = 1 when the output
completes one cycle of
transition (1→0→1) in one
▪ Energy dissipated in one
cycle of 0→1→0 clock period
transition:
2
𝐸𝑠𝑤 = 𝐶𝐿 𝑉𝐷𝐷

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh

Dynamic Power Dissipation: Short circuit Power

▪ Short circuit power dissipation:

𝑃𝑠𝑐 = 𝑉𝐷𝐷 𝐼𝑆𝐶

▪ Power dissipated when short circuit condition

occur:
𝑃𝑑𝑦𝑛 = 𝑃𝑠𝑤 + 𝑃𝑠𝑐

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh

Static Power Dissipation

▪ Static power dissipation occurs because of:

➢ Subthreshold current
➢ Gate Leakage
➢ Junction Leakage
▪ 𝑃𝑠𝑡𝑎𝑡 = 𝑉𝐷𝐷 𝐼𝑙𝑒𝑎𝑘

Total power dissipation in a circuit:

𝑃𝑡𝑜𝑡 = 𝑃𝑑𝑦𝑛 + 𝑃𝑠𝑡𝑎𝑡

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh

Technology Library Models: Dynamic Power
Energy dissipated in one cycle of 0→1→0 transition:
2
𝐸𝑑𝑦𝑛 = 𝐶𝐿 𝑉𝐷𝐷 + 𝑉𝐷𝐷 𝐼𝑆𝐶 𝜏𝑆𝐶
2
𝐸𝑑𝑦𝑛 = (𝐶𝑑 +𝐶𝑤 + 𝐶𝐼 )𝑉𝐷𝐷 + 𝑉𝐷𝐷 𝐼𝑆𝐶 𝜏𝑆𝐶
We can write:
2 2
𝐸𝑑𝑦𝑛 = 𝐶𝑑 𝑉𝐷𝐷 + 𝑉𝐷𝐷 𝐼𝑆𝐶 𝜏𝑆𝐶 + (𝐶𝑤 +𝐶𝐼 )𝑉𝐷𝐷 = 𝐸𝑖𝑛𝑡 +𝐸𝑒𝑥𝑡

▪ Energy dissipated inside a cell 𝐸𝑖𝑛𝑡 is the property of the cell and
modelled in the library
▪ Energy dissipated outside a cell 𝐸𝑒𝑥𝑡 depends on the
environment (external load)
➢ Tools can compute it after (𝐶𝑤 +𝐶𝐼 ) is known
▪ Power can be estimated using energy per transition by
multiplying with activity and clock frequency

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh

Non-linear Power Model (NLPM)
▪ Internal power dissipation depends on the
output-load and input slew u_table_template(index_1) {
▪ Modelled as two-dimensional table named variable_1 : input_net_transition ;
internal_power variable_2 : total_output_net_capacitance ;
index_1( "10, 20, 30" ) ;
➢ Referred to as Non-linear Power index_2( "1.2, 5.0,15.0, 37.5) ;
Model (NLPM) }
….
pin(Z) {
internal_power() {
related_pin : “A" ;
rise_power(index_1) {
values( "4, 5, 7, 12, …3x4 table);
}
▪ Rise and fall power can be represented as …
}
different arcs }

▪ Values represent energy dissipated per S. Saurabh, “Introduction to VLSI Design Flow”.Cambridge
University Press, 2023.
transition

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh

Technology Library Models: Static Power

▪ Static power dissipated inside a CMOS

logic gate depends on the value (0 or 1) cell (NAND2) { ...
at its input pin cell_leakage_power : 125;
leakage_power () {
▪ Modeled using when condition in the when : “!A & !B”; value : 20; }
library leakage_power () {
when : “A & !B”; value : 150; }
leakage_power () {
when : “!A & B”; value : 200; }
leakage_power () {
when : “A & B”; value : 300; } ...
S. Saurabh, “Introduction to VLSI Design Flow”.Cambridge
University Press, 2023.

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh

Estimating Power Dissipation
2
𝑃𝑡𝑜𝑡 = 𝐶𝐿 𝑉𝐷𝐷 𝛼𝑓𝑐𝑙𝑘 + 𝑉𝐷𝐷 𝐼𝑆𝐶 + 𝑉𝐷𝐷 𝐼𝑙𝑒𝑎𝑘
▪ Computing power dissipation is a
where, challenging problem.
▪ 𝑉𝐷𝐷 = supply voltage ➢ Capacitance estimation
▪ 𝐶𝐿 = load capacitance ➢ Accounting for the activity of signals
▪ 𝑓𝑐𝑙𝑘 = frequency of the clock in the circuit
▪ 𝛼 = activity of the signal
Activity of a signal depends on:
▪ Application being run on an IC
▪ Logical structure and the circuit topology

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh

Estimation of Activity
Simulation-based Techniques (Vector-based Technique):
▪ Perform simulation using test bench.
▪ Simulator generates the output response for all the nets [value change dump (VCD) files]
➢ Convert a VCD file into a format from which the activity measures can be easily
extracted [switching activity interchange format (SAIF)]
➢ Provide the SAIF file to the power analysis tool
➢ Tools can also assume default activity [such as 0.2]
Probabilistic Techniques (Vector-less Technique):
▪ Propagate the activity measures through the circuit by considering the logic function of the
gates encountered in the path
▪ Example: Assume that static probabilities of signals A and B are 𝑃1𝐴 = 0.5 and 𝑃1𝐵 = 0.3
➢ If they propagate through an AND gate: 𝑃1𝐴.𝐵 = 𝑃1𝐴 . 𝑃1𝐵 = 0.5 × 0.3 = 0.15
➢ If they propagate through an OR gate: 𝑃1𝐴+𝐵 = 1 − (1 − 𝑃1𝐴 ) 1 − 𝑃1𝐵 = 1 − 0.5 × 0.7 =
0.65

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh

 References
▪ N. H. Weste and D. Harris. “CMOS VLSI Design: A Circuits and Systems Perspective”. Pearson
Education India, 2015.
▪ S. Saurabh, “Introduction to VLSI Design Flow”. Cambridge: Cambridge University Press,
2023.

soprotection.com VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh