Lab 6

Low Noise Amplifier (LNA)

Contents
Introduction ................................................................................................................................................ 2
Objective .................................................................................................................................................... 2
Cascode Common Gate Low Noise Amplifier ........................................................................................... 2
Selected Topology ...................................................................................................................................... 3
Design Steps ............................................................................................................................................... 4
Step 1 ...................................................................................................................................................... 4
Step 2 ...................................................................................................................................................... 5
Step 3 ...................................................................................................................................................... 5
Step 4 ...................................................................................................................................................... 6
Step 5 ...................................................................................................................................................... 6
Simulation .................................................................................................................................................. 7
Gain (S21), NF, and S11 simulation. ...................................................................................................... 7
Hb Analysis (to plot IIP3). .................................................................................................................... 10
PSS Analysis (to plot the P1dB). .......................................................................................................... 13

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Introduction
LNA is the abbreviation for Low-Noise Amplifier. It is a type of amplifier but with significantly
lower Noise Figure (NF). That’s why LNAs are widely used in all receivers due to their low NF. An
LNA is employed at the beginning of each receiver chain to reduce the overall noise performance of
the receiver. It is known that the NF of the initial stage mostly dominates the overall noise
performance. Hence, to decrease the NF of the entire chain, reducing the NF of the first stage is
necessary.
LNAs have many different circuit topologies such as common source stage with inductive load,
common gate stage with resistive feedback, common gate stage, and common gate stage with
inductive degeneration. The choice of a specific topology is made based on the required specifications
from the design.
The design of the LNA starts by checking the required specifications, which in this case are the gain
of the amplifier, Noise Figure (NF), input reflection coefficient (S11), input third intercept point
(IIP3), and the 1-dB compression point (P1dB). The following step is calculating the circuit
parameters, which leads to determining the aspect ratio (𝑊/𝐿) of the transistors.
Objective
The aim of this lab is to design and simulate a Cascode Common Gate Low Noise Amplifier with
inductive degeneration. The specifications of the LNA are shown in Table 1.
Cascode Common Gate Low Noise Amplifier
The low input impedance of the common-gate (CG) stage makes it attractive for LNA design. Which
is valid only if channel-length modulation is neglected, otherwise the input impedance becomes too
high. Several circuit techniques have been introduced to deal with the former case but in today’s
technology, we face the latter case.
To alleviate the above issue, the channel length of the transistor can be increased, thus reducing
channel-length modulation, and raising the achievable 𝑔𝑚 𝑟𝑜 . Since the device width must also
increase proportionally to retain the transconductance value, the gate-source capacitance of the
transistor rises considerably, degrading the input return loss. An alternative approach to lowering the
input impedance is to incorporate a cascode device which will isolate the input from the output
1
yielding 𝑅𝐷 to be divided by two intrinsic gains, yielding an input impedance 𝑅𝑖𝑛 ≈ 𝑔 .
𝑚

Table 1. LNA Specifications

𝑉𝐷𝐷 1𝑉
𝐼𝑅𝑒𝑓 100 𝜇𝐴
𝐶𝑝𝑎𝑑 50 𝑓𝐹
𝐶𝐿 50 𝑓𝐹
Gain ≥ 15 𝑑𝐵
NF ≤ 4 𝑑𝐵
S11 ≤ −15 𝑑𝐵
IIP3 ≥ 0 𝑑𝐵𝑚
P1dB ≥ −10 𝑑𝐵𝑚

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Selected Topology
The topology to be implemented is the Cascode Common Gate LNA. The low input impedance of
the common gate makes it preferrable for the LNA design as in this case the input impedance will be
equal to one over the transconductance of the amplifier as shown in (1), voltage gain as shown in (2)
and a noise figure as shown in (3).

1
𝑅𝑖𝑛 = (1)
𝑔𝑚1
𝑅𝐷
𝐴𝑣 = (2)
2𝑅𝑠
𝑅𝑠
𝑁𝐹 = 1 + 𝛾 + 4 (3)
𝑅𝐷
The topology consists of the input CG transistor and a cascode device which is used for isolation
between the input and the output so as to lower the input impedance. A resistor was placed in parallel
with the tank at the load to adjust the gain and bandwidth of the amplifier. Inductance degeneration
is used for biasing the amplifier instead of using an active current source or a resistance which will
both degrade the noise performance. The schematic of the LNA is shown in Figure 1. In it a VCVS
is added before the output port in order to isolate the resistance of the port and prevent it from loading
the amplifier.
Notice the cap (𝐶𝑝 ) inserted in the middle of the mirror pair is to block the noise of the biasing circuit
from affecting the LNA.

Figure 1. LNA Schematic

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Design Steps
The design of the cascode CG LNA could be made following the steps below.
Step 1
Getting the dimensions and bias current of transistor M1. This should be made such that to guarantee
that 1/𝑔𝑚1 equals to 50 Ω. For M1, set its length to be equal to the minimum length allowable by the
technology to decrease its parasitic capacitances.
To determine the width and the drain current, some simulations will be performed. Create a testbench
for the used MOSFET as shown in Figure 2, setting the length to be 60 𝑛𝑚 (min length) and an initial
width value of 10 𝜇𝑚 (which will be scaled and tuned later). Set the global variables as shown in
Figure 3.
Notice that the width is set to 5 𝜇𝑚 because this is the width per finger of the transistor and by default
the number of fingers of this transistor is 2 yielding a total width of 10 𝜇𝑚.
Run DC Analysis and set its settings as shown in Figure 4.

Figure 2. NMOS Testbench

Figure 3. Global Variables Values

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 Figure 4. DC Analysis Settings

Plot the 𝑔𝑚 versus 𝐼𝐷 curve from which the bias point for the transistor will be selected, from the
graph it will be noted that increasing 𝐼𝐷 increases 𝑔𝑚 to a specific point, after which 𝑔𝑚 saturates and
increasing the current is not useful anymore. An optimum operating point could be chosen to
guarantee the highest speed of the amplifier will avoiding excessive current consumption, which is
the current that provides 80 to 90% of the saturated 𝑔𝑚 . Take the bias current to be 2 𝑚𝐴 (which
corresponds to approximately 0.9 of 𝑔𝑚 𝑚𝑎𝑥 ) and find the corresponding 𝑔𝑚 .
Now we have a value for 𝑔𝑚 and width for a specific bias point (i.e. for a specific current). Scale 𝑔𝑚
so that it reaches 50 Ω and hence scale the width and current as well.
Hint:
W → 𝒈𝒎 W → 𝑰𝑫
10 𝜇𝑚 → 𝑔𝑚 𝑓𝑟𝑜𝑚 𝑠𝑖𝑚𝑢𝑙𝑎𝑡𝑜𝑟 10 𝜇𝑚 → 2 𝑚𝐴
𝑊𝑟𝑒𝑞𝑢𝑖𝑟𝑒𝑑 → 20 𝑚𝐴/𝑉 𝑊𝑟𝑒𝑞𝑢𝑖𝑟𝑒𝑑 → 𝐼𝐷 𝑎𝑐𝑡𝑢𝑎𝑙

Step 2
Compute the value of the degeneration inductance 𝐿𝐵 . Notice that 𝐿𝐵 will resonate with 𝐶𝑝𝑎𝑑 +
𝐶𝑆𝐵1 + 𝐶𝐺𝑆1 and its own cap at the frequency of interest. From the following rule, 𝐿𝐵 can be computed
1
𝑓 = 2𝜋√𝐿𝐶 , the frequency of operation is 5.5 𝐺𝐻𝑧, and the capacitance = 𝐶𝑝𝑎𝑑 + 𝐶𝑆𝑆1 where 𝐶𝑠𝑠1
may be computed from the previous testbench created in the previous step.
Hint:
W → 𝑪𝒔𝒔
10 𝜇𝑚 → 𝐶𝑠𝑠 𝑜
𝑊𝑟𝑒𝑞𝑢𝑖𝑟𝑒𝑑 → 𝐶𝑠𝑠 𝑎𝑐𝑡𝑢𝑎𝑙

Step 3
The width of M0 must be chosen (the length is also the minimum allowable value). An optimum
width (initial choice) of M0 is likely to be near that of M1 so as to not contribute high parasitic
capacitances (in case of high width) nor to require a very large 𝑉𝑔𝑠 (in case of low width value).

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Step 4
Computing the value of the load inductor 𝐿1 . Notice that 𝐿1 will resonate with 𝐶𝐺𝐷2 + 𝐶𝐷𝐵2 , the input
capacitance of the next stage, and its own capacitance. From the following rule, 𝐿1 can be computed
1
𝑓 = 2𝜋√𝐿 𝐶 , where the frequency of operation is 5.5 𝐺𝐻𝑧. Since the voltage gain is proportional
1 𝐷𝐷0
to R1, then R1 must be sufficiently large (e.g. 600 Ω).
Step 5
Designing the current mirror circuitry (Biasing Circuit). The schematic for the biasing circuit is shown
in Figure 5. The design begins by determining the current in all branches. The reference current is
equal to 100 𝜇𝐴 (𝐼𝐵𝑖𝑎𝑠 is the schematic), and the bias current for the LNA is 4 𝑚𝐴.
Distribute the current such as transistors PM2 (which is the mirror for transistor M1) and PM1 will
have a bias current of 1 𝑚𝐴. And transistor PM0 will have a bias current equal to the reference current
whish is 100 𝜇𝐴
By means of the width and current values of transistor M1 which forms a current mirror with M2,
and the current ratio between the two mirror transistors, the width of M2 can be calculated. (Notice
that they are current mirror pair, so length will be the same).
Hence, the design of PM0 and PM1 are what is left. Pick 𝐿 = 600 𝑛𝑚 (to ensure good mirroring),
𝑔
𝑉𝐷𝑆 = 0.5 𝑉, and 𝐼𝑚 = 5, then find the width of transistor PM1 from 𝐼𝐷 /𝑊 curve. And the width of
𝐷
PM0 can be found by means of the mirroring ratio.

Figure 5. Schematic of the Biasing Circuit

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Simulation
Perform the following simulations on your designed LNA to validate your design.
1. Gain (S21), NF, and S11 simulation.
- Set the properties of the input port as follows.

Figure 6. Properties of the Input Port

- And the properties of the output port are similar but without ac magnitude value.
- Run DC Analysis, SP analysis, and Noise Analysis to check that the biasing is correct and to
plot the gain (S21), NF and S11.
- The following steps show the properties of the SP Analysis and Noise Analysis settings.

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 - Adjust the SP Analysis parameters as follows.

Figure 7. SP Analysis Settings

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 - Adjust the Noise Analysis parameters as follows.

Figure 8. Noise Analysis Settings

Hint: to plot the outputs, click on Results → Direct Plot → Main Form, then choose the
analysis that you want to plot the output from.

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 2. Hb Analysis (to plot IIP3).
- Modify the parameters of the input port as shown in Figure 9 to perform hb analysis.

Hint: observe the channel spacing between the adjacent channels is 20 𝑀𝐻𝑧 which is
specified by the standard (IEEE 802.11 a).
The Intermodulation test requires inputting two adjacent signals or interferences to the system
and checking the IM products level and how it will affect the desired signal. The power level
of these interferences is specified by the standard (which is −60 𝑑𝐵𝑚 in this case).

Figure 9. Input Port Parameters

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 - Adjust the hb analysis parameters as follows.

Figure 10. hb Analysis Settings

- Sweep over Pin inside the analysis setup.

- From the direct plot menu, plot the IPN compression curve versus input power.

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 - Adjust the parameters of the direct plot menu as follows.

Figure 11. Direct Plot Form Settings to Plot the IPN Curves

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 3. PSS Analysis (to plot the P1dB).
- Modify the parameters of the input port as follows to perform PSS analysis.

Figure 12. Input Port Parameters

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 - Adjust the PSS analysis parameters as follows.

Figure 13. PSS Analysis Settings

- From the direct plot menu, plot the P1dB compression curve versus input power.

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 - Adjust the parameters of the direct plot menu as follows.

Figure 14. Direct Plot Form to plot the P1dB Curve

- After simulation you will find that the P1dB spec is not achieved, hence some tunning is
required. Decrease the resistance value a little (𝑅𝑛𝑒𝑤 = 400Ω) in order to enhance the
linearity of the LNA.
- Perform all simulations again to verify that all specs are achieved.

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