Effective Timing closure of multimillion gate design

with Advance Usage of Primetime Clock Fix ECO

Utility and it’s results statistics

Milap Darji
Umesh Nair
Pushpendra Patel

Qualcomm India Pvt. Ltd.

Bagmane Constellation Bus. Park Cir, Marathalli Outer Ring Road,
Doddanekkundi, Bengaluru, Karnataka-560037

https://www.qualcomm.com/

ABSTRACT
We generally deal with timing analysis and closure of complex designs with multimillion gates
and hundreds of PVT corners. With the increase in design clock frequency requirement, the
timing paths complexity is increasing with its ECO cycles getting shorter. During the ECOs cycle,
one of important and time-consuming part is working on clock network ECOs because of
manual intervention. To reduce the manual effort and reduce the ECO iteration we have used
Primetime Physical Aware Clock ECO Utility on a multimillion high frequency design. This paper
discusses on the methodology used to achieve the best result and the challenges faced. It also
discusses the usage of this utility on test clock skew balancing using ECO phase. In addition, we
will discuss the PrimeTime and PNR tool correlation. Finally, we will conclude with the results,
advantages w.rt.t the current mythology and the future work.
SNUG 2018

Table of Contents

1. Introduction ..........................................................................................................................................................4
1.1 Traditional clock fixing Techniques………………………………………………………………………….. 5
2. Traditional Methodology for Timing fixes................................................................................................6
3. Proposed Methodology ...................................................................................................................................7
3.1 Approach for Clock ECO…………………………………………………………………………………………….8
3.2 Important commands ……………………………………………………………….…………………………..….9
4. Results……………………………………………………………………………………………………………..……….10
4.1 DMSA run results …….....................................................................................................................................11
4.1.1 DMSA Setup fix ……………………………………………………………………………………………………..12
4.1.2 DMSA Hold fix ………………………………………………………………………………………………………12
4.2 Test mode hold ECO …..................................................................................................................................13
4.3 Clock ECO fixes statistics after implementing the ECOs in PNR ………………………………....14
5. Issues faced and Troubleshooting .............................................................................................................16
6. Conclusion ............................................................................................................................................................16
7. References………………………………………………………………………………………………………………...16

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Table of Figures

Figure 1: Clock ECO Setup Fixing Techniques ……………………………………………………………………………….5

Figure 2. Clock ECO Hold Fixing Techniques ………………………………………………………………………………...5
Figure 3. Traditional timing fixes methodology flow …………………………………………………………………….6
Figure 4. Proposed timing fixes methodology flow ……………………………………………………………………….7
Figure 5. Approach for clock ECO ………………………………………………………………………………………………...8
Figure 6. Design under Test ………………………………………………………………………………………………………10
Figure 7. Graph showing comparison of size_cell count and FEPs count for only data and
clock+data ECO………………………………………………………………………………………………………………………….11
Figure 8. Graph showing comparison of insert_buffer and FEPs count for only data and
clock+data ECO ………………………………………………………………………………………………………………………...12
Figure 9. Graph showing comparison of insert_buffer and FEPs for test mode hold ECO ………………14
Figure 10. insert_buffer, area increase and leakage power comparison post P&R implementation .15

Table of Tables
Table 1. QOR comparison between only data and clock+ data ECO ………………………………………….….11
Table 2. QOR comparison for DMSA hold ECO ……………………………………………………………………….…..12
Table 3. insert_buffer and area increase comparison for DMSA hold fixes ……………………………….…12
Table 4. QOR comparison for test mode hold fix ………………………………………………………………………...13
Table 5. insert_buffer and area increase comparison for test mode hold ECO ………………………….…..13
Table 6. QOR comparison post P&R implementation …………………………………………………………….……14
Table 7. insert_buffer, area increase and leakage power comparison post P&R implementation ….15
Table 8. Runtime and memory used comparison ………………………………………………………………….…...15

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Primetime Clock Fix ECO Utility and it’s results statistics
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1. Introduction
We generally deal with timing analysis and closure of complex designs with multimillion gates and
hundreds of PVT corners. By considering the SOC Design Cycles are getting shrink, challenges of
moving to lower technology nodes, Timing closure is becoming critical phase of design.

With the increase in design clock frequency requirement, the timing paths complexity is increasing
with its ECO cycles getting shorter, so meat the timelines the Timing ECOs convergence heat rate
should be fast. Traditional timing analysis includes setup, hold, Timing DRCs fixes. To address the
setup timing paths, we generally prefer the data path Optimization first, which includes upsize the
cell to higher drive and swap the cells to lower VTs to improve the cell delay, which has adverse
impact of Leakage power hit. Many times, these data path ecos will not hold good enough to fix the
setup failures, where we will need to touch the clock path for fixing, which includes methods like
push the Capture clock path or early the launch clock path. Same way to address the hold timing
paths, we normally prefer to add delay in data path based on positive setup margin available, but as
understood addition of buffers in data path will increase the leakage power, so other Option is clock
path fix where we will either push the launch clock path or early the Capture clock path. but these
are not easy solutions, they require extensive analysis and what if needs to perform across multiple
dominant PD corners.

Performing such complex clock ECOs manually is becoming time consuming and there are chances
for reverse impact. One of pain point is Test mode clock balancing, sometimes due to inherent clock
skew problem based on floorplan, we ended up in adding thousands of buffers in data path for hold
fixes. So, we planned to use the physical aware clock ECO feature of PrimeTime-SI (PTSI). We have
done multiple experiments to address the setup and hold timing issues through clock fixes and the
results are encouraging. Since this clock ECO feature works well during physical aware mode, we
took these ECOs through PNR implementation and again timed back in PTSI and we have seen similar
timing results while comparing with PrimeTime what if.

In this paper, we have given more weightage on timing results achieved through PrimeTime clock
ECO on clock groups with thousands of sinks from Designs implemented with different lower
technology nodes. We have put more stress towards Hold timing fixes in this paper for area and
leakage power savings purposes.

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2. Traditional clock fixing Techniques

Showing the Clock ECO Setup and hold Fixing Techniques in pictorial view.

Figure 1. Clock ECO Setup Fixing Techniques

Figure 2. Clock ECO Hold Fixing Techniques

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2. Traditional Methodology for Timing fixes

In Backend from of Timing closure, we enable the PTSI Timing sessions with necessary Inputs which
includes the Library, Netlist, SPEFs and Timing Constraints. Once the timing sessions are ready, we
generate the setup, hold, TDRC violating reports. Since the TDRCs like Clock Trans fix can change the
overall timing status, we prefer to fix them in starting of TECO cycle. Then we go for data path fixes.
there are paths if any not fixable through data path, then finally we go for clock path fix.

Figure 3. Traditional timing fixes methodology flow

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3. Proposed Methodology
In Proposed method of Timing fixes, Till TDRCs fixes stage it remains same as traditional
method. But change comes in while starting the data path/clock path ECOs. Here we are
using the Clock path fixes in initial stage of ECO cycle itself. Since this is physical aware ECO,
it requires the PD inputs like DEFs, LEFs etc.

Figure 4. Proposed timing fixes methodology flow

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3.1 Approach for Clock ECO

Figure 5. Approach for clock ECO

3.1.1 Physical Mode

Open_site - Timing fixing sizes a cell only if there is enough room available around the cell and inserts
a buffer only if there is an empty site with enough room to accept the new cell without moving nearby
cells. This mode retains the placement of existing cells. This is suggested to be used in later stages of
ECO
Occupied_site - Timing fixing can size a cell and insert a buffer that overlaps existing neighbor cells,
as long as the cell density (area utilization) is low enough that the nearby cells can be moved to make
the required space. After the change is made, you must use a physical implementation tool such as IC
Compiler II to move the existing cells and create room for the sized or inserted cell. This is suggested
to be used in early stages of design and for aggressive fixing.

3.1.2 Timing analysis mode

For our current experiments we have used pba_mode path for the setup fixes and pba_mode
exhaustive for hold paths fixes

3.1.3 Network type

There are two approaches for performing the clock ECOs- 1. Clock ECO plus data ECO 2.data path
ECOs. In first approach, first we will do clock path fixes for reported timing violations, then for
remaining violations, we will do the data path fixes. In Second approach, we will only do the data
path fixes. Through above, we can make judgement on which eco method is more effective in terms
of PPA.

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3.2 Important commands

#ECO Settings
set eco_alternative_area_ratio_threshold 1
set eco_report_unfixed_reason_max_endpoints 10000
set timing_save_pin_arrival_and_slack true
set sh_continue_on_error true
set pba_recalculate_full_path false
set eco_strict_pin_name_equivalence true
set read_parasitics_load_locations true
set eco_insert_buffer_search_distance_in_site_rows 8

#Setting for Clock ECO

set eco_physical_enable_clock true
set eco_clock_minimum_timing_violation_threshold 4
set eco_clock_maximum_tree_level_for_timing_fix 0

set_eco_options \
-physical_enable_clock_data \
-physical_lib_path $LEF_LIST \
-physical_design_path $DEF_LIST \
-log_file ./lef_def.log

source dont_touch_list.tcl
source dont_use_list.tcl

#Setup Fix
fix_eco_timing -cell_type clock_network -type setup -method
{size_cell} -verbose -pba_mode path -physical_mode open_site \
-hold_margin -0.020 -group $CLK_GRP

fix_eco_timing -cell_type clock_network -type setup -method

{size_cell} -verbose -pba_mode path -physical_mode open_site \
-hold_margin -0.020 -to $ENDPOINT_LIST

#Hold Fix
fix_eco_timing -cell_type clock_network -type hold -verbose -pba_mode
exhaustive -physical_mode open_site -method {insert_buffer} -
buffer_list $HOLD_FIX_BUFF_LIST –group $CLK_GRP

fix_eco_timing -cell_type clock_network -type hold -verbose -pba_mode

exhaustive -physical_mode open_site -method {insert_buffer} -
buffer_list $HOLD_FIX_BUFF_LIST –to $ENDPOINT_LIST

write_changes -format icctcl -output eco_icc_setuphold.tcl

write_changes -format eco -output eco_binary_setuphold.tcl

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4. Results

We took test cases from Designs with high clock frequency, POCV and SI enabled implemented with
lower technology nodes. We done multiple runs on setup, hold fixing. We took different stage PD
Databases and analyzed the clock ECO impact. Like PD DB just after CTS, PD DB after routing, PD DB
with Base tape out quality. We also tried out different experiments with setting different values for
variable eco_clock_minimum_timing_violation_threshold, like 4,2,1 etc. In our experiments we
enabled clock fixing till root.

We have done experiments with giving whole clock group for fixing as well as giving selective
endpoints, there we are seeing whole clock group fixing is giving better results than endpoint-based
fixing.

Figure 6. Design under Test

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4.1 DMSA run results.

4.1.1 DMSA Setup fix

We took clock group with ~50k sinks for Setup timing paths fixes from One High frequency block. we
performed the DMSA in 10 corners. As below Table shows, in only data path ECO approach, there are
300 size cells, while in clock plus data path ECO approach, size cells count has been reduced to 250.
FEPs and TNS wise also there is improvement in clock plus data path fixes approach.

Table 1. QOR comparison between only data and clock+ data ECO

#size_cell WNS (ns) TNS (ns) FEPs

PRE ECO -0.032 -15 500

DATA 300 -0.012 -2.8 250

CLOCK+DATA 250 -0.011 -2.3 224

Figure 7. Graph showing comparison of size_cell count and FEPs count for only data and clock+data ECO

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4.1.2 DMSA Hold ECO

We took clock group with ~50k sinks for Hold timing paths fixes from One High frequency block. We
performed the DMSA in 10 corners. As below table shows, in clock plus data path fixes approach,
over all buffer insert count has been reduced by 12% compare to only data path fixes approach.
As well as FEPs fixing count is more by 18% in clock plus data path approach. Area saving also
can be seen but in mean time need to track the leakage and dynamic power numbers while
performing the ECO.
Table 2. QOR comparison for DMSA hold ECO

WNS (ns) TNS (ns) FEPs

PRE ECO -0.239 -160.15 5357

DATA -0.194 -79.77 2256

CLOCK+DATA -0.194 -71.47 1901

Table 3. insert_buffer and area increase comparison for DMSA hold fixes

#Buffers Area Increase

Clock Data Total Clock Data Total

DATA 7691 7691 830 830

CLK + DATA 881 5969 6850 104 657 761

Figure 8. Graph showing comparison of insert_buffer and FEPs count for only data and clock+data ECO

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4.2 Test mode hold ECO

We took clock group with ~200k sinks for Hold timing paths fixes from Highly Utilized Design. we
performed the hold ECO on dominant corner as violating FEPs count is high. As below table shows,
in clock plus data path fixes approach, over all buffer insert count has been reduced by 11%
compare to only data path fixes approach. As well as FEPs fixing count is more by 34% in clock
plus data path approach. Area saving also can be seen but in mean time need to track the leakage
and dynamic power numbers while performing the ECOs
Table 4. QOR comparison for test mode hold fix

Hold Setup

WNS (ns) TNS(ns) FEPs

PRE ECO -0.03 -29.35 24818 Clean

DATA -0.01 -3.42 3176 Clean

CLK + DATA -0.01 -2.43 2366 Clean

Table 5. insert_buffer and area increase comparison for test mode hold ECO

#Buffers Area Increase

Clock Data Total Clock Data Total

DATA 21660 21660 4339 4339

CLK + DATA 4369 15136 19505 933 3031 3964

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Figure 9. Graph showing comparison of insert_buffer and FEPs for test mode hold ECO

4.3 Clock ECO fixes statistics after implementing the ECOs in PNR
We took clock group with ~300k sinks for Hold timing paths fixes from Highly Utilized Design. we
performed the hold ECO on dominant corner as violating FEPs count is high. As below table shows,
in clock plus data path fixes approach, over all buffer insert count has been reduced by 13% compare
to only data path fixes approach. We took the PrimeTime clock plus data ECO and implemented in
PNR and again timed back it in PrimeTime. since it’s physical aware ECO, PD wise there is very
minimal disturbance seen as well as Timing is also correlating with what if.
While extracting the leakage power info, we are seeing leakage got shoot up by 2%, but in mean time
we saved 10% area with clock ECO approach.

Table 6. QOR comparison post P&R implementation

Hold Setup

WNS (ns) TNS (ns) FEPs

PRE ECO -0.03 -29.29 24786 Clean

DATA (PT) 0.001 0.005 6 Clean

CLK + DATA (PT) 0.001 0.001 1 Clean

CLK + DATA (ICC2) -0.002 -0.025 15 Clean

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Table 7. insert_buffer, area increase and leakage power comparison post P&R implementation

#Buffers Area Increase Leakage

Clock Data Total Clock Data Total

DATA 24945 24945 5001 5001 0.3704

CLK + DATA 5076 16992 22068 1084 3406 4490 0.3781

Figure 10. insert_buffer, area increase and leakage power comparison post P&R implementation

Table 8. Runtime and memory used comparison

Runtime (in mins) Peak Memory( in GB)

Clock Data Total

DATA 40 40 194

CLK + DATA 50 30 80 196

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5. Issues and Troubleshooting

 Low fix rate

Examine unfixable reasons to determine cause of remaining violations. Setup and hold timing
margins can be tweak for aggressive fixes. Increase search distance for buffer insertion.
 Large cell displacement
Physical constraint file with blockage defined can be provided in set_eco_options command
option.
 Duty cycle distortion
As of now there is no specific tool setting to detect DCD issues. We can control the number of
stages from leaf-level for buffer insertion to minimize Duty cycle distortion for high frequency
clocks.
 Threshold for delay added to clock network
We want to control the amount of delay being added for timing fixes while performing the
setup/hold timing fixes, as of now it checks for adequate timing margin and add the amount of
delay based on failing slack value and other side timing margin available. for which work is in
progress.

6. Conclusion
PrimeTime Clock ECO is really helping in expediting the Clock path fixes with saving of area without
any adverse impact. It delivers a scalable, effective, signoff-accurate methodology for multiple
corners. With the use of physically-aware ECO improves single-pass fix rate and ensures predictable
implementation results. Need to guide PrimeTime to achieve high fix rate

7. References
• PrimeTime User Guide- 2016.12
• https://solvnet.synopsys.com/retrieve/customer/application_notes/attached_files/158317
2/PrimeTime_IC_Compiler_ECO_flow_physical_1.1.pdf

Page 16 Effective Timing closure of multimillion gate design with Advance Usage of
Primetime Clock Fix ECO Utility and it’s results statistics