LM5157

ZHCSOB0A – JULY 2021 – REVISED AUGUST 2023

采用双随机展频技术的 LM5157 2.2MHz 宽 VIN 50V 升压/SEPIC/反激式转换器

1 特性 3 说明
• 适用于电池应用中的宽工作电压范围 LM5157 器件是一款具有集成式 50V 电源开关和宽输
– 输入电压工作范围为 2.9V 至 45V 入范围的非同步升压转换器。
– 最大输出电压为 48V（最大绝对电压为 50V） 该器件可用于升压、SEPIC 和反激式拓扑。该器件可
– BIAS 电压大于等于 2.9V 时最小升压电源电压为 通过电压至少为 2.9V 的单节电池启动。如果 BIAS 引
1.5V
脚的电压高于 2.9V，该器件可在低至 1.5V 的输入电源
– 高达 50V 的输入瞬态保护
电压下运行。
– 最小电池消耗
• 低关断电流 (IQ ≤ 2.6µA) BIAS 引脚可在高达 45V（最大绝对值为 50V）的电压
• 低工作电流 (IQ ≤ 670µA) 下运行。用户可通过外部电阻器对开关频率进行动态编
• 解决方案尺寸小、成本低 程，编程范围为 100kHz 至 2.2MHz。2.2 MHz 的开关
– 开关频率高达 2.2MHz（最大值） 频率可最大限度地降低 AM 频带干扰，并支持实现小
– 16 引脚 QFN 封装 (3mm × 3mm) 解决方案尺寸和快速瞬态响应。为降低电源的 EMI，
– 集成的误差放大器支持在没有光耦合器的情况下 该器件提供可选择的双随机展频，可在宽频率范围内降
进行初级侧稳压（反激） 低 EMI。
– 精确的电流限制（请参阅器件比较表） 该器件在输入电压范围内具有准确的峰值电流限制，可
• 缓减 EMI 避免对功率电感器进行过度设计。运行低电流和脉冲跳
– 可选双随机展频 跃模式可在轻负载时提高效率。
– 无引线封装
该器件具有内置保护特性，例如过压保护、线路
• 低功耗、高效率
UVLO、热关断和可选的断续模式过载保护。其他特性
– 45mΩ RDSON 开关
包括低关断 IQ 、可编程软启动、精密补偿、电源正常
– 快速开关，开关损耗低
指示器以及外部时钟同步。
• 避免 AM 频带干扰和串扰
– 可选的时钟同步 器件信息
– 100kHz 至 2.2MHz 的动态可编程宽开关频率范 器件型号 封装(1) 封装尺寸（标称值）
围 LM5157 WQFN (16) 3.00mm × 3.00mm
• 集成型保护特性
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
– 在输入电压范围内具有恒定电流限制 录。
– 可选间断模式过载保护
VSUPP LY VLOAD
– 可编程线路 UVLO
– OVP 保护
– 热关断保护
Option al

BIAS VCC SW

• 精确的 ±1% 精度反馈基准 UVLO FB

• 可调软启动 RT COMP
SS PGO OD
• PGOOD 指示器 PGND AGND MODE
• 使用 LM5157x 并借助 WEBENCH® Power
Designer 创建定制设计方案
2 应用 典型 SEPIC 应用

• 电池供电的宽输入升压、SEPIC 和反激式转换器
• LED 偏置电源
• 无光耦合器的多输出反激式应用
• 便携式扬声器应用
• 电源模块
• 工业 PLC
• 保持电容器充电器
• 音频放大器电源
• 压电式驱动器/电机驱动器偏置电源

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
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Table of Contents
1 特性................................................................................... 1 9 Application and Implementation.................................. 26
2 应用................................................................................... 1 9.1 Application Information............................................. 26
3 说明................................................................................... 1 9.2 Typical Application.................................................... 26
4 Revision History.............................................................. 2 9.3 System Examples..................................................... 29
5 Device Comparison Table...............................................3 10 Power Supply Recommendations..............................34
6 Pin Configuration and Functions...................................4 11 Layout........................................................................... 35
7 Specifications.................................................................. 6 11.1 Layout Guidelines................................................... 35
7.1 Absolute Maximum Ratings ....................................... 6 11.2 Layout Examples.....................................................36
7.2 ESD Ratings .............................................................. 6 12 Device and Documentation Support..........................37
7.3 Recommended Operating Conditions ........................6 12.1 Device Support....................................................... 37
7.4 Thermal Information ...................................................7 12.2 Documentation Support.......................................... 37
7.5 Electrical Characteristics ............................................7 12.3 接收文档更新通知................................................... 37
7.6 Typical Characteristics................................................ 9 12.4 支持资源..................................................................37
8 Detailed Description......................................................12 12.5 Trademarks............................................................. 38
8.1 Overview................................................................... 12 12.6 静电放电警告.......................................................... 38
8.2 Functional Block Diagram......................................... 13 12.7 术语表..................................................................... 38
8.3 Feature Description...................................................13 13 Mechanical, Packaging, and Orderable
8.4 Device Functional Modes..........................................25 Information.................................................................... 39

4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision * (July 2021) to Revision A (August 2023) Page
• Updated Quick Start Calculator links................................................................................................................ 26

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5 Device Comparison Table

DEVICE OPTION MINIMUM PEAK CURRENT LIMIT MAXIMUM SW VOLTAGE
LM5157 6.5 A
48 V (50-V abs max)
LM51571 4.33 A

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6 Pin Configuration and Functions

PGND

SW
SW
NC
16 15 14 13

PGND 1 12 SW

VCC 2 11 MODE
EP
BIAS 3 10 SS

PGOOD 4 9 FB

5 6 7 8

COMP
AGND
EN/UVLO/SYNC
RT

图 6-1. 16-Pin WQFN RTE Package (Top View)

表 6-1. Pin Functions

PIN
TYPE(1) DESCRIPTION
NO. NAME
1, 16 PGND P Power ground pin. Source connection of the internal N-channel power MOSFET
Output of the internal VCC regulator and supply voltage input of the internal MOSFET driver.
2 VCC P
Connect a 5-Ω resistor in series with a 1-µF ceramic bypass capacitor from this pin to PGND.
3 BIAS P Supply voltage input to the VCC regulator. Connect a bypass capacitor from this pin to PGND.
Power-good indicator. An open-drain output that goes low if FB is below the undervoltage threshold
4 PGOOD O
(VUVTH). Connect a pullup resistor to the system voltage rail.
Switching frequency setting pin. The switching frequency is programmed by a single resistor
5 RT I
between RT and AGND.
Enable pin. The converter shuts down when the pin is less than the enable threshold (VEN).
Undervoltage lockout programming pin. The converter start-up and shutdown levels can be
programmed by connecting this pin to the supply voltage through a voltage divider. If a
UVLO/
6 I programmable UVLO is used, connect the low-side UVLO resistor to AGND. This pin must not be left
SYNC/EN
floating. Connect to the BIAS pin if not used.
External synchronization clock input pin. The internal clock can be synchronized to an external clock
by applying a negative pulse signal into the pin.
7 AGND G Analog ground pin. Connect to the analog ground plane through a wide and short path.
Output of the internal transconductance error amplifier. Connect the loop compensation components
8 COMP O
between this pin and AGND.
Inverting input of the error amplifier. Connect a voltage divider to set the output voltage in boost,
9 FB I SEPIC, or primary-side regulated flyback topologies. Connect the low-side feedback resistor close to
AGND.
Soft-start time programming pin. An external capacitor and an internal current source set the ramp
10 SS I rate of the internal error amplifier reference during soft start. Connect the ground connection of the
capacitor to AGND.

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表 6-1. Pin Functions (continued)

PIN
TYPE(1) DESCRIPTION
NO. NAME
MODE = 0 V or connect to AGND during initial power up. Hiccup mode protection is disabled and
spread spectrum is disabled.
MODE = 370 mV or connect a 37.4-kΩ resistor between this pin and AGND during initial power up.
Hiccup mode protection is enabled and spread spectrum is enabled.
11 MODE I
MODE = 620 mV or connect a 62.0-kΩ resistor between this pin and AGND during initial power up.
Hiccup mode protection is enabled and spread spectrum is disabled.
MODE > 1 V or connect a 100-kΩ resistor between this pin and AGND during initial power up.
Hiccup mode protection is disabled and spread spectrum is enabled.
12, 13,
SW Switch pin. Drain connection of the internal N-channel power MOSFET
14
15 NC — No internal electrical contact. Optionally connect to PGND for improved thermal conductivity.
Exposed pad of the package. The exposed pad must be connected to AGND and the large ground
— EP — copper plane to decrease thermal resistance.

(1) G = Ground, I = Input, O = Output, P = Power

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7 Specifications
7.1 Absolute Maximum Ratings
Over the recommended operating junction temperature range(1)
MIN MAX UNIT
BIAS to AGND –0.3 50
UVLO to AGND –0.3 VBIAS + 0.3
SS, RT to AGND(2) –0.3 3.8
Input
FB to AGND –0.3 4.0
MODE to AGND –0.3 3.8
PGND to AGND –0.3 0.3 V
VCC to AGND –0.3 5.8(3)
PGOOD to AGND(4) –0.3 18
Output COMP to AGND(5) –0.3
SW to AGND (DC) –0.3 50
SW to AGND (6-ns transient) –4.0
Junction temperature, TJ (6) –40 150
°C
Storage temperature, Tstg –55 150

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) This pin is not specified to have an external voltage applied.
(3) Operating lifetime is de-rated when the pin voltage is greater than 5.5 V.
(4) The maximum current sink is limited to 1 mA when VPGOOD > VBIAS.
(5) This pin has an internal max voltage clamp which can handle up to 1.6 mA.
(6) High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.

7.2 ESD Ratings

VALUE UNIT

Electrostatic Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000
V(ESD) V
discharge Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

Over the recommended operating junction temperature range(1)
MIN NOM MAX UNIT
VSUPPLY Boost converter input (when BIAS ≥ 2.9 V) 1.5 45 V
VLOAD Boost converter output VSUPPLY 48 (2) V
VBIAS BIAS input(3) 2.9 45 V
VUVLO UVLO input 0 45 V
VFB FB input 0 4.0 V
ISW Switch current 0 See note(4) A
fSW Typical switching frequency 100 2200 kHz
fSYNC Synchronization pulse frequency 100 2200 kHz
TJ Operating junction temperature –40 125 °C

(1) Recommended Operating Conditions are conditions under the device is intended to be functional. For specifications and test
conditions, see Electrical Characteristics.

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(2) Boost converter output can be up to 48 V, but the SW pin voltage should be less than or equal to 50-V during transient.
(3) BIAS pin operating range is from 2.9 V to 45 V when VCC is supplied from the internal VCC regulator. When the VCC pin is directly
connected to the BIAS pin, the device requires minimum 2.85 V at the BIAS pin to start up, and the BIAS pin operating range is from
2.75 V to 5.5 V after starting up.
(4) Maximum switch currrent is limited by pre-programmed peak current limit (ILIM) , and is guaranteed when TJ < TTSD.

7.4 Thermal Information

LM5157x
THERMAL METRIC(1) RTE(QFN) UNIT
16 PINS
RθJA Junction-to-ambient thermal resistance (LM5157EVM-BST) 32.7 °C/W
RθJA Junction-to-ambient thermal resistance 44.4 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 42.1 °C/W
RθJB Junction-to-board thermal resistance 17.3 °C/W
ΨJT Junction-to-top characterization parameter (LM5157EVM-BST) 0.6 °C/W
ΨJT Junction-to-top characterization parameter 0.8 °C/W
ΨJB Junction-to-board characterization parameter (LM5157EVM-BST) 14.8 °C/W
ΨJB Junction-to-board characterization parameter 17.3 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 6.7 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

7.5 Electrical Characteristics

Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over TJ = –40°C to 125°C. Unless otherwise
stated, VBIAS = 12 V, RT = 9.09 kΩ
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
ISHUTDOWN(BIAS) BIAS shutdown current VBIAS = 12 V, VUVLO = 0 V 2.6 5 μA
VBIAS = 12 V, VUVLO = 2.0 V, VFB = VREF,
IOPERATING(BIAS) BIAS operating current 700 850 μA
RT = 220 kΩ
VCC REGULATOR
VVCC-REG VCC regulation VBIAS = 8 V, IVCC = 18 mA 4.66 4.9 5.14 V
VVCC-
VCC UVLO threshold VCC rising 2.75 2.8 2.85 V
UVLO(RISING)

VCC UVLO hysteresis VCC falling 0.1 V

ENABLE
VEN(RISING) Enable threshold EN rising 0.4 0.52 0.7 V
VEN(FALLING) Enable threshold EN falling 0.33 0.49 0.63 V
VEN(HYS) Enable hysteresis EN falling 0.03 V
UVLO/SYNC
VUVLO(RISING) UVLO / SYNC threshold UVLO rising 1.425 1.5 1.575 V
VUVLO(FALLING) UVLO / SYNC threshold UVLO falling 1.370 1.45 1.520 V
VUVLO(HYS) UVLO / SYNC threshold hysteresis UVLO falling 0.05 V
IUVLO UVLO hysteresis current VUVLO = 1.6 V 4 5 6 μA
MODE, SPREAD SPECTRUM
FSW modulation (upper limit) 7.8%
FSW modulation (lower limit) –7.8%
SS

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7.5 Electrical Characteristics (continued)

Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over TJ = –40°C to 125°C. Unless otherwise
stated, VBIAS = 12 V, RT = 9.09 kΩ
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ISS Soft-start current 9 10 11 μA
SS pulldown switch RDSON 50 Ω
PULSE WIDTH MODULATION
fsw1 Switching frequency RT = 220 kΩ 85 100 115 kHz
fsw2 Switching frequency RT = 49.3 kΩ 388 440 492 kHz
fsw3 Switching frequency RT = 9.09 kΩ 1980 2200 2420 kHz
tON(MIN) Minimum on time RT = 9.09 kΩ 80 ns
DMAX1 Maximum duty cycle limit RT = 9.09 kΩ 80% 85% 90%
DMAX2 Maximum duty cycle limit RT = 220 kΩ 90% 93% 96%
RT regulation voltage 0.5 V
CURRENT LIMIT
ILIM Internal MOSFET current limit LM5157 6.5 7.5 8.5 A
Internal MOSFET current limit LM51571 4.33 5 5.67 A
HICCUP MODE PROTECTION
Hiccup enable cycles 64 Cycles
Hiccup timer reset cycles 8 Cycles
ERROR AMPLIFIER
VREF FB reference 0.99 1 1.01 V
Gm Transconductance 2 mA/V
COMP sourcing current VCOMP = 1.2 V 180 μA
COMP clamp voltage COMP rising (VUVLO = 2.0 V) 2.5 2.8 V
COMP clamp voltage COMP falling 1 1.1 V
ACS ΔVCOMP / ΔISW 0.095
OVP
VOVTH Overvoltage threshold FB rising (referece to VREF) 107% 110% 113%
Overvoltage threshold FB falling (referece to VREF) 105%
PGOOD
PGOOD pulldown switch RDSON 1 mA sinking 70 Ω
VUVTH Undervoltage threshold FB falling (referece to VREF) 87% 90% 93%
Undervoltage threshold FB rising (referece to VREF) 95%
POWER SWITCH
rDS(ON) Internal MOSFET on-resistance VBIAS = 12 V 45 90 mΩ
VBIAS = 3.5 V 47 95 mΩ
Leakage current VSW = 12 V 1200 nA
THERMAL SHUTDOWN
TTSD Thermal shutdown threshold Temperature rising 175 °C
Thermal shutdown hysteresis 15 °C

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7.6 Typical Characteristics

图 7-1. BIAS Shutdown Current vs VBIAS 图 7-2. BIAS Shutdown Current vs Temperature

图 7-3. BIAS Operating Current vs Temperature

图 7-4. VVCC vs VBIAS

图 7-5. VVCC vs IVCC 图 7-6. ISS vs Temperature

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图 7-7. EN Threshold vs Temperature 图 7-8. UVLO Threshold vs Temperature

图 7-9. FB Reference vs Temperature 图 7-10. Frequency vs RT Resistance

图 7-11. Frequency vs Temperature 图 7-12. Current Limit Threshold vs Temperature

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图 7-13. Peak Current Limit vs Duty Cycle

图 7-14. Internal MOSFET Drain Source On-state
Resistance vs Temperature

图 7-15. Minimum On Time vs Frequency 图 7-16. Maximum Duty Cycle Limit vs Frequency

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8 Detailed Description
8.1 Overview
The LM5157x device is a wide input range, non-synchronous boost converter that uses peak-current-mode
control. The device can be used in boost, SEPIC, and flyback topologies.
The device can start up from a single-cell battery with a minimum of 2.9 V. It can operate with input supply
voltage as low as 1.5 V if the BIAS pin is greater than 2.9 V. The internal VCC regulator also supports BIAS pin
operation up to 45 V (50-V absolute maximum). The switching frequency is dynamically programmable with an
external resistor from 100 kHz to 2.2 MHz. Switching at 2.2 MHz minimizes AM band interference and allows for
a small solution size and fast transient response. To reduce the EMI of the power supply, the device provides an
optional dual random spread spectrum, which reduces the EMI over a wide frequency span.
The device features an accurate current limit over the input voltage range. Low operating current and pulse
skipping operation improve efficiency at light loads.
The device also has built-in protection features such as overvoltage protection, line UVLO, and thermal
shutdown. Selectable Hiccup mode overload protection protects the converter during prolonged current limit
conditions. Additional features include the following:
• Low shutdown IQ
• Programmable soft start
• Precision reference
• Power good indicator
• External clock synchronization

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8.2 Functional Block Diagram

VSUPP LY LM D1 VLOAD

CIN COUT
R FBT
RLOAD
FB

VUVTH PGO OD BIAS SW RFBB

+
IUVL O
±
VCC_OK FB
VSUPP LY + AGND
± TSD Ready OVP
VUVL O VOVTH ±
RUVL OT + BIAS
SYNC
Detector Clock_ Syn c VCC
EN VCC
RUVL OB +
/UVLO VCC_EN Regula tor
VCC_EN
/SYNC ± RVCC
VEN Hiccup
C/L Comparator Mode VCC
VCC_OK
ICS + UVLO
CVCC
ILIM S Q
±

ISS PWM ICS

R Q
1.1V+VSLOPE Comparator
VCS - + Gai n
SS +
= A CS
+
VREF + ± Clock Gen erator MODE
CSS VCS
± Spr ead Spectrum Sele ction
Gm Clock_ Syn c
FB AGND PGND
COMP RT MODE

RT
RCOMP

CCOMP

8.3 Feature Description

8.3.1 Line Undervoltage Lockout (UVLO/SYNC/EN Pin)
The device has a dual-level EN/UVLO circuit. During power on, if the BIAS pin voltage is greater than 2.7 V and
the UVLO pin voltage is between the enable threshold (VEN) and the UVLO threshold (VUVLO) for more than 1.5
µs (see 节 8.3.6 for more details), the device starts up and an internal configuration starts. The device typically
requires a 90-µs internal start-up delay before entering Standby mode. In Standby mode, the VCC regulator and
RT regulator are operational, the SS pin is grounded, and there is no switching at the SW pin.

IUVLO

VSUPPLY
±
VUVLO
RUN
RUVLOT +

RUVLOB EN
/UVLO +
/SYNC VCC_EN
±
VEN

图 8-1. Line UVLO and Enable

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When the UVLO pin voltage is above the UVLO threshold, the device enters Run mode. In Run mode, a soft-
start sequence starts if the VCC voltage is greater than the VCC UV threshold (VVCC-UVLO). UVLO hysteresis is
accomplished with an internal 50-mV voltage hysteresis and an additional 5-μA current source that is switched
on or off. When the UVLO pin voltage exceeds the UVLO threshold, the UVLO hysteresis current source is
enabled to quickly raise the voltage at the UVLO pin. When the UVLO pin voltage falls below the UVLO
threshold, the current source is disabled, causing the voltage at the UVLO pin to fall quickly. When the UVLO pin
voltage is less than the enable threshold (VEN), the device enters Shutdown mode after a 40-µs (typical) delay
with all functions disabled.
90-µs (typical) > 3 cycles
internal start-up delay

BIAS 2.7 V
= VSUPPLY
VUVLO

VEN
UVLO
VVCC-UVLO
Shutdown

VREF
VCC
1.5 µs
SS is grounded
UVLO should be greater than with 2 cycles
VEN more than 1.5 µs to start-up delay
SS

SW

TSS
SS VLOAD
=
1V VLOAD(TARGET)

VLOAD

图 8-2. Boost Start-Up Waveforms Case 1: Start-Up by VCC UVLO, UVLO Toggle After Start-Up

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> 40us(typical) 90us (typical)

90-µs (typical)
internal start-up delay
internal start-up delay

BIAS 2.7 V
= VSUPPLY
VUVLO

VEN

UVLO
VVCC-UVLO
Shutdown
VREF
VCC
1.5 µs
SS is grounded
UVLO should be greater than with 2 cycles
0.55 V more than 1.5 µs to start-up delay
SS

SW

TSS
SS VLOAD
=
1V VLOAD(TARGET)

VLOAD

图 8-3. Boost Start-Up Waveforms Case 2: Start-Up by VCC UVLO, EN Toggle After Start-Up

The external UVLO resistor divider must be designed so that the voltage at the UVLO pin is greater than 1.5 V
(typical) when the input voltage is in the desired operating range. The values of RUVLOT and RUVLOB can be
calculated as shown in 方程式 1 and 方程式 2.

VUVLO(FALLING)
VSUPPLY(ON) u VSUPPLY(OFF)
VUVLO(RISING)
RUVLOT
IUVLO
(1)

where
• VSUPPLY(ON) is the desired start-up voltage of the converter
• VSUPPLY(OFF) is the desired turn-off voltage of the converter

VUVLO(RISING) u RUVLOT
RUVLOB
VSUPPLY(ON) VUVLO(RISING)
(2)

A UVLO capacitor (C UVLO) is required in case the input voltage drops below the VSUPPLY(OFF) momentarily during
start-up or during a severe load transient at the low input voltage. If the required UVLO capacitor is large, an
additional series UVLO resistor (RUVLOS) can be used to quickly raise the voltage at the UVLO pin when the 5-
μA hysteresis current turns on.

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IUVLO

VSUPPLY

VUVLO
RUVLOT ±
RUVLOS RUN
+
RUVLOB
CUVLO EN/UVLO/SYNC

图 8-4. Line UVLO using Three UVLO Resistors

Do not leave the UVLO pin floating. Connect to the BIAS pin if not used.
8.3.2 High Voltage VCC Regulator (BIAS, VCC Pin)
The device has an internal wide input VCC regulator that is sourced from the BIAS pin. The wide input VCC
regulator allows the BIAS pin to be connected directly to supply voltages from 2.9 V to 45 V (transient protection
up to 50 V).
The VCC regulator turns on when the device is in Standby or Run mode. When the BIAS pin voltage is below the
VCC regulation target, the VCC output tracks BIAS with a small dropout voltage. When the BIAS pin voltage is
greater than the VCC regulation target, the VCC regulator provides a 5-V supply (typical) for the device and the
internal N-channel MOSFET driver.
The VCC regulator sources current into the capacitor connected to the VCC pin. Connect a 5-Ω resistor in
series with a 1-µF ceramic bypass capacitor from this pin to PGND.
The minimum supply voltage after start-up can be further decreased by supplying the BIAS pin from the boost
converter output or from an external power supply as shown in 图 8-5. Also, this configuration allows the device
to handle more power when VSUPPLY is less than 5 V. Practical minimum supply voltage after start-up is decided
by the maximum duty cycle limit (DMAX).
VSUPP LY VLOAD

VLOAD
Option al

BIAS VCC SW

UVLO FB
RT COMP
SS PGO OD
PGND AGND MODE

图 8-5. Decrease the Minimum Operating Voltage After Start-Up

In flyback topology, the internal power dissipation of the device can be decreased by supplying the BIAS using
an additional transformer winding, especially in PSR flyback. In this configuration, the external BIAS supply
voltage (VAUX) must be greater than the regulation target of the external LDO, and the BIAS pin voltage must
always be greater than 2.9 V.

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VSUPP LY VLOAD =1 2V

Option al
VAUX =1 2V

<1 1V

VAUX

BIAS VCC SW

UVLO FB
RT COMP
SS PGO OD
PGND AGND MODE

图 8-6. External BIAS Supply (PSR Flyback)

8.3.3 Soft Start (SS Pin)

The soft-start feature helps the converter gradually reach the steady state operating point, thus reducing start-up
stresses and surges. The device regulates the FB pin to the SS pin voltage or the internal reference, whichever
is lower.
At start-up, the internal 10-μA soft-start current source (ISS) turns on after the VCC voltage exceeds the VCC
UV threshold. The soft-start current gradually increases the voltage on an external soft-start capacitor connected
to the SS pin. This results in a gradual rise of the output voltage. The SS pin is pulled down to ground by an
internal switch when the VCC is less than VCC UVLO threshold, the UVLO is less than the UVLO threshold,
during Hiccup mode off time or thermal shutdown.
In boost topology, soft-start time (tSS) varies with the input supply voltage. The soft-start time in boost topology is
calculated as shown in 方程式 3.

CSS VSUPPLY
tSS = × (1
) × VREF
ISS VLOAD (3)

In SEPIC topology, the soft-start time (tSS) is calculated as follows.

CSS
tSS = ×VREF
ISS (4)

TI recommends choosing the soft-start time long enough so that the converter can start up without going into an
overcurrent state. See 节 8.3.11 for more detailed information.
图 8-7 shows an implementation of primary side soft start in flyback topology.

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FB SS COMP

图 8-7. Primary-Side Soft Start in Flyback

图 8-8 shows an implementation of secondary side soft-start in flyback topology.

VLOAD

Secondary Side
Soft-start

图 8-8. Secondary-Side Soft Start in Flyback

8.3.4 Switching Frequency (RT Pin)

The switching frequency of the device can be set by a single RT resistor connected between the RT and the
AGND pins. The resistor value to set the RT switching frequency (fRT) is calculated as shown in 方程式 5.

2.21u 1010
RT 955
fRT(TYPICAL)
(5)

The RT pin is regulated to 0.5 V by the internal RT regulator when the device is enabled.
8.3.5 Dual Random Spread Spectrum – DRSS (MODE Pin)
The device provides a digital spread spectrum, which reduces the EMI of the power supply over a wide
frequency range. This function is enabled by a single resistor (37.4 kΩ or 100 kΩ) between the MODE pin and
the AGND pin or by programming the MODE pin voltage (370 mV or greater than 1.0 V) during initial power up.
When the spread spectrum is enabled, the internal modulator dithers the internal clock. When an external
synchronization clock is applied to the SYNC pin, the internal spread spectrum is disabled. DRSS (a) combines
a low frequency triangular modulation profile (b) with a high frequency cycle-by-cycle random modulation profile
(c). The low frequency triangular modulation improves performance in lower radio frequency bands (for example,
AM band), while the high frequency random modulation improves performance in higher radio frequency bands
(for example, FM band). In addition, the frequency of the triangular modulation is further modulated randomly to
reduce the likelihood of any audible tones. In order to minimize output voltage ripple caused by spread
spectrum, duty cycle is modified on a cycle-by-cycle basis to maintain a nearly constant duty cycle when
dithering is enabled (see 图 8-9).

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Frequency

0.156 x fSW
fSW (a) Low + High Frequency
Random Modulation

(b) Low Frequency

Random Modulation

(c) High Frequency

Random Modulation

Spread Spectrum Spread Spectrum

OFF ON

图 8-9. Dual Random Spread Spectrum

8.3.6 Clock Synchronization (UVLO/SYNC/EN Pin)

The switching frequency of the device can be synchronized to an external clock by pulling down the EN/UVLO/
SYNC pin. The internal clock of the device is synchronized at the falling edge, but ignores the falling edge input
during the forced off time, which is determined by the maximum duty cycle limit. The external synchronization
clock must pull down the EN/UVLO/SYNC pin voltage below VUVLO(FALLING). The duty cycle of the pulldown
pulse is not limited, but the minimum pulldown pulse width must be greater than 150 ns. The minimum pullup
pulse width must be greater than 250 ns. 图 8-10 shows an implementation of the remote shutdown function.
The UVLO pin can be pulled down by a discrete MOSFET or an open-drain output of an MCU. In this
configuration, the device stops switching immediately after the UVLO pin is grounded, and the device shuts
down 40 µs (typical) after the UVLO pin is grounded.
VSUPPLY

MCU

UVLO/SYNC
SHUTDOWN

图 8-10. UVLO and Shutdown

图 8-11 shows an implementation of shutdown and clock synchronization functions together. In this configuration,
the device immediately stops switching when the UVLO pin is grounded, and the device shuts down if the fSYNC
stays in high logic state for longer than 40 µs (typical). UVLO is in low logic state for more than 40 µs (typical).
The device runs at fSYNC if clock pulses are provided after the device is enabled.

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VSUPPLY

MCU

UVLO/SYNC

FSYNC

图 8-11. UVLO, Shutdown, and Clock Synchronization

图 8-13 and 图 8-14 show implementations of standby and clock synchronization functions together. In this
configuration, The device stops switching immediately if fSYNC stays in high logic state and enters Standby mode
if fSYNC stays in high logic state for longer than two switching cycles. The device runs at fSYNC if clock pulses are
provided. Since the device can be enabled when the UVLO pin voltage is greater than the enable threshold for
more than 1.5 µs, the configurations in 图 8-13 and 图 8-14 are recommended if the external clock
synchronization pulses are provided from the start before the device is enabled. This 1.5-µs requirement can be
relaxed when the duty cycle of the synchronization pulse is greater than 50%. 图 8-12 shows the required
minimum duty cycle to start up by synchronization pulses. When the switching frequency is greater than 1.1
MHz, the UVLO pin voltage must be greater than the enable threshold for more than 1.5 µs before applying the
external synchronization pulse.
80
75
70
65
60
Duty Cycle [%]

55
50
45
40
35
30
25
20
15
100 200 300 400 500 600 700 800 900 1000 1100
fSW [kHz] SUby

图 8-12. Required Duty Cycle to Start-Up by External Synchronization Clock

VSUPPLY

MCU

UVLO/SYNC
>0.7V

FSYNC

图 8-13. UVLO, Standby, and Clock Synchronization (a)

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VSUPPLY

MCU UVLO/SYNC

FSYNC

图 8-14. UVLO, Standby, and Clock Synchronization (b)

If the UVLO function is not required, the shutdown and clock synchronization functions can be implemented
together by using one push-pull output of the MCU. In this configuration, the device shuts down if fSYNC stays in
low logic state for longer than 40 µs (typical). The device is enabled if fSYNC stays in high logic state for longer
than 1.5 µs. The device runs at fSYNC if clock pulses are provided after the device is enabled. Also, in this
configuration, it is recommended to apply the external clock pulses after the BIAS is supplied. By limiting the
current flowing into the UVLO pin below 1 mA using a current limiting resistor, the external clock pulses can be
supplied before the BIAS is supplied (see 图 8-15).

MCU

10
UVLO/SYNC

FSYNC

图 8-15. Shutdown and Clock Synchronization

图 8-16 shows an implementation of inverted enable using external circuit.

VSUPPLY

UVLO/SYNC

LMV431

图 8-16. Inverted UVLO

The external clock frequency (fSYNC) must be within +25% and –30% of fRT(TYPICAL). Since the maximum duty
cycle limit and the peak current limit with a slope resistor (RSL) are affected by the clock synchronization, take
extra care when using the clock synchronization function. See 节 8.3.7 and 节 8.3.12 for more information.
8.3.7 Current Sense and Slope Compensation
The device senses switch current which flows into the SW pin, and provides a fixed internal slope compensation
ramp, helping prevent subharmonic oscillation at high duty cycle. The internal slope compensation ramp is
added to the sensed switch current for the PWM operation, but no slope compensation ramp is added to the

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sensed inductor current for the current limit operation to provide an accurate peak current limit over the input
supply voltage (see 图 8-17).

SW
Current Limit
Comparator
± ILIM
ICS
+
1.1V+VSLOPE
+ -
+
VCS
I-to-V
PWM ±
Gain = ACS
Comparator
COMP

CHF RCOMP
(optional)

CCOMP

图 8-17. Current Sensing and Slope Compensation

V VCOMP

Slope
Compensation VSLOPE x D + 1.1V
Ramp

ACS x ICS

图 8-18. Current Sensing and Slope Compensation (a) at PWM Comparator Inputs
I
ILIM

Sensed Inductor
Current (ICS)

图 8-19. Current Sensing (b) at Current Limit Comparator Inputs

Use 方程式 6 to calculate the value of the peak slope voltage (VSLOPE).

fRT
VSLOPE 500mV u
fSYNC (6)

where
• fSYNC is fRT if clock synchronization is not used
According to peak current mode control theory, the slope of the compensation ramp must be greater than half of
the sensed inductor current falling slope to prevent subharmonic oscillation at high duty cycle. Therefore, the
minimum amount of slope compensation in boost topology must satisfy the following inequality:

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VLOAD VF VSUPPLY
0.5 u u ACS u Margin 500mV u fSW
LM (7)

where
• VF is a forward voltage drop of D1, the external diode
Typically, 82% of the sensed inductor current falling slope is known as an optimal amount of the slope
compensation. By increasing the margin to 1.6, the amount of slope compensation becomes close to the optimal
amount.
If clock synchronization is not used, the fSW frequency equals the fRT frequency. If clock synchronization is used,
the fSW frequency equals the fSYNC frequency.
8.3.8 Current Limit and Minimum On Time
The device provides cycle-by-cycle peak current limit protection that turns off the internal MOSFET when the
inductor current reaches the current limit threshold (ILIM). To avoid an unexpected Hiccup mode operation during
a harsh load transient condition, it is recommended to have more margin when programming the peak-current
limit.
Boost converters have a natural pass-through path from the supply to the load through the high-side power
diode (D1). Because of this path and the minimum on-time limitation of the device, boost converters cannot
provide current limit protection when the output voltage is close to or less than the input supply voltage. The
minimum on time is is calculated as 方程式 8.

800 u 10 15
t ON(MIN) |
1 6
4 u 10
8 u RT
(8)

8.3.9 Feedback and Error Amplifier (FB, COMP Pin)

The feedback resistor divider is connected to an internal transconductance error amplifier that features high
output resistance (RO = 10 MΩ) and wide bandwidth (BW = 7 MHz). The internal transconductance error
amplifier sources current, which is proportional to the difference between the FB pin and the SS pin voltage or
the internal reference, whichever is lower. The internal transconductance error amplifier provides symmetrical
sourcing and sinking capability during normal operation and reduces its sinking capability when the FB is greater
than OVP threshold.
To set the output regulation target, select the feedback resistor values as shown in 方程式 9.

§R ·
VLOAD VREF u ¨ FBT 1¸
© RFBB ¹ (9)

The output of the error amplifier is connected to the COMP pin, allowing the use of a Type 2 loop compensation
network. RCOMP, CCOMP, and optional CHF loop compensation components configure the error amplifier gain and
phase characteristics to achieve a stable loop response. The absolute maximum voltage rating of the FB pin is
4.0 V. If necessary, the feedback resistor divider input can be clamped by using an external zener diode.
The COMP pin features internal clamps. The maximum COMP clamp limits the maximum COMP pin voltage
below its absolute maximum rating even in shutdown. The minimum COMP clamp limits the minimum COMP pin
voltage to start switching as soon as possible during no load to heavy load transition. The minimum COMP
clamp is disabled when FB is connected to ground in flyback topology.

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8.3.10 Power-Good Indicator (PGOOD Pin)

The device has a power-good indicator (PGOOD) to simplify sequencing and supervision. The PGOOD switches
to a high impedance open-drain state when the FB pin voltage is greater than the feedback undervoltage
threshold (VUVTH), the VCC is greater than the VCC UVLO threshold and the UVLO/EN is greater than the EN
threshold. A 25-μs deglitch filter prevents any false pulldown of the PGOOD due to transients. The
recommended minimum pullup resistor value is 10 kΩ.
Due to the internal diode path from the PGOOD pin to the BIAS pin, the PGOOD pin voltage cannot be greater
than VBIAS + 0.3 V.
8.3.11 Hiccup Mode Overload Protection (MODE Pin)
To further protect the converter during prolonged current limit conditions, the device provides selectable Hiccup
mode overload protection. This function is enabled by a single resistor (37.4 kΩ or 62.0 kΩ) between the MODE
pin and the AGND pin or by programming the MODE pin voltage (370 mV or 620 mV) during initial power up.
The internal Hiccup mode fault timer of the device counts the PWM clock cycles when the cycle-by-cycle current
limiting occurs after soft start is finished. When the Hiccup mode fault timer detects 64 cycles of current limiting,
an internal Hiccup mode off timer forces the device to stop switching and pulls down SS. Then, the device
restarts after 32 768 cycles of Hiccup mode off time. The 64-cycle Hiccup mode fault timer is reset if eight
consecutive switching cycles occur without exceeding the current limit threshold. The soft-start time must be long
enough not to trigger the Hiccup mode protection after the soft start is finished.
4 cycles of
7 normal current limit
64 cycles of 32768 hiccup 60 cycles of switching 32768 hiccup
current limit mode off cycles current limit cycles mode off cycles

Inductor Current

Time

图 8-20. Hiccup Mode Overload Protection

8.3.12 Maximum Duty Cycle Limit and Minimum Input Supply Voltage
The practical duty cycle is greater than the estimated due to voltage drops across the MOSFET and sense
resistor. The estimated duty cycle is calculated as shown in 方程式 10.

VSUPPLY
D 1
VLOAD VF
(10)

When designing boost converters, the maximum required duty cycle must be reviewed at the minimum supply
voltage. The minimum input supply voltage that can achieve the target output voltage is limited by the maximum
duty cycle limit, and it can be estimated as follows:

VSUPPLY(MIN) | VLOAD VF u 1 DMAX ISUPPLY(MAX) u RDCR ISUPPLY(MAX) u 110m u DMAX (11)

where
• ISUPPLY(MAX) is the maximum input current
• RDCR is the DC resistance of the inductor

fSYNC
DMAX1 1 0.1u
fRT
(12)

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DMAX2 1 100ns u fSW

(13)

The minimum input supply voltage can be further decreased by supplying fSYNC, which is less than fRT. Practical
DMAX is DMAX1 or DMAX2, whichever is lower.
8.3.13 Internal MOSFET (SW Pin)
The device provides an internal switch with an rDS(ON) that is typically 45 mΩ when the BIAS pin is greater than
5 V. The rDS(ON) of the internal switch is increased when the BIAS pin is less than 5 V. The device temperature
must be checked at the minimum supply voltage especially when the BIAS pin is less than 5 V.
The dV/dT of the SW pin must be limited during the 90-µs internal start-up delay to avoid a false turn-on, which
is caused by the coupling through CDG parasitic capacitance of the internal MOSFET switch.
8.3.14 Overvoltage Protection (OVP)
The device has OVP for the output voltage. OVP is sensed at the FB pin. If the voltage at the FB pin rises above
the overvoltage threshold (VOVTH), OVP is triggered and switching stops. During OVP, the internal error amplifier
is operational, but the maximum source and sink capability is decreased to 60 µA.
8.3.15 Thermal Shutdown (TSD)
An internal thermal shutdown turns off the VCC regulator, disables switching, and pulls down the SS when the
junction temperature exceeds the thermal shutdown threshold (TTSD). After the junction temperature is
decreased by 15°C, the VCC regulator is enabled again and the device performs a soft start.
8.4 Device Functional Modes
8.4.1 Shutdown Mode
If the UVLO/EN/SYNC pin voltage is below VEN for longer than 40 µs (typical), the device goes into Shutdown
mode with all functions disabled. In Shutdown mode, the device decreases the BIAS pin current consumption to
below 2.6 μA (typical).
8.4.2 Standby Mode
If the UVLO/EN/SYNC pin voltage is greater than VEN and below VUVLO for longer than 1.5 µs, the device enters
Standby mode with the VCC regulator operational, RT regulator operational, SS pin grounded, and no switching.
The PGOOD is activated when the VCC voltage is greater than the VCC UV threshold.
8.4.3 Run Mode
If the UVLO pin voltage is above VUVLO and the VCC voltage is sufficient, the device enters Run mode.
8.4.3.1 Spread Spectrum Enabled
The spread spectrum function is enabled by a single resistor (37.4 kΩ ±5% or 100 kΩ ±5%) between the MODE
pin and the AGND pin or by programming the MODE pin voltage (370 mV ±10% or greater than 1.0 V) during
initial power up. To switch the spread spectrum function, EN must be grounded for more than 60 µs, or VCC
must be fully discharged.
8.4.3.2 Hiccup Mode Protection Enabled
The Hiccup mode protection is enabled by a single resistor (37.4 kΩ ±5% or 62.0 kΩ ±5%) between the MODE
pin and the AGND pin or by programming the MODE pin voltage (370 mV ±10% or 620 mV ±10%) during initial
power up. To switch the Hiccup mode protection function, EN should be grounded for more than 60 µs, or VCC
must be fully discharged.

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9 Application and Implementation

备注
以下应用部分中的信息不属于 TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。

9.1 Application Information

TI provides three application notes that explain how to design boost, SEPIC, and flyback converters using the
device. These comprehensive application notes include component selections and loop response optimization.
See these application reports for more information on loop response and component selection:
• How to Design a Boost Converter Using LM5157x
• How to Design an Isolated Flyback Converter Using LM5157x
• How to Design a SEPIC Converter Using LM5157x
9.2 Typical Application
图 9-1 shows all optional components to design a boost converter.
RSNB CSNB

VSUPP LY LM VLOAD

CBIAS RBIAS D1
RVCC CVCC
CIN
COUT1 COUT2
RUVL OT
BIAS VCC SW + RLOAD
RUVL OS RFBT ±
UVLO FB
RT PGO OD MCU_V CC
RUVL OB
SS COMP RFBB
CUVL O CSS
RT PGND AGND MODE
CHF
RMODE RCOMP

CCOMP

图 9-1. Typical Boost Converter Circuit With Optional Components

9.2.1 Design Requirements

表 9-1 shows the intended input, output, and performance parameters for this application example.
表 9-1. Design Example Parameters
DESIGN PARAMETER VALUE
Minimum input supply voltage (VSUPPLY(MIN)) 6V
Target output voltage (VLOAD) 12 V
Maximum load current (ILOAD) 1.6 A (≈ 19.2 Watt)
Typical switching frequency (fSW) 2100 kHz

9.2.2 Detailed Design Procedure

Use the Quick Start Calculator to expedite the process of designing of a regulator for a given application.
Download these Quick Start Calculator for more information on loop response and component selection:
• LM5157x Boost Quick Start Calculator
• LM5157x Flyback Quick Start Calculator

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• LM5157x SEPIC Quick Start Calculator

The device is also WEBENCH® Designer enabled. The WEBENCH software uses an iterative design procedure
and accesses comprehensive data bases of components when generating a design.
9.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
9.2.2.2 Recommended Components
表 9-2 shows a recommended list of materials for this typical application.
表 9-2. List of Materials
REFERENCE
QTY. SPECIFICATION MANUFACTURER(1) PART NUMBER
DESIGNATOR
RT 1 RES, 9.53 k, 1%, 0.1 W, AEC-Q200 Grade 0, 0603 Vishay-Dale CRCW06039K53FKEA
RFBT 1 RES, 49.9 k, 1%, 0.1 W, 0603 Yageo America RC0603FR-0749K9L
RFBB 1 RES, 4.53 k, 1%, 0.1 W, AEC-Q200 Grade 0, 0603 Vishay-Dale CRCW06034K53FKEA
Inductor, Shielded, Composite, 1.5 μH, 14 A,
LM 1 Coilcraft XEL6030-152MEB
0.01052 Ω, AEC-Q200 Grade 1, SMD
COUT1 6 CAP, CERM, 4.7 µF, 50 V, ±10%, X7R, 1210 TDK C3225X7R1H475K250AB
CAP, Aluminum Polymer, 100 µF, 50 V, ±20%, 0.025
COUT2 (Bulk) 2 Chemi-Con HHXB500ARA101MJA0G
Ω, AEC-Q200 Grade 2, D10xL10mm SMD
CIN1 4 CAP, CERM, 10 µF, 50 V, ±10%, X7R, 1210 MuRata GRM32ER71H106KA12L
CAP, AL, 22 uF, 100 V, ±20%, 1.3 Ω, AEC-Q200
CIN2 (Bulk) 1 Panasonic EEE-FK2A220P
Grade 2, SMD
D1 1 Diode, Schottky, 45 V, 10 A, AEC-Q101, CFP15 Nexperia PMEG045V100EPDAZ
RCOMP 1 RES, 2.61 k, 1%, 0.1 W, 0603 Yageo America RC0603FR-072K61L
CCOMP 1 CAP, CERM, 0.01 μF, 50 V, ±10%, X7R, 0603 Kemet C0603X103K5RACTU
CAP, CERM, 100 pF, 50 V, ±5%, C0G/NP0, AEC-
CHF 1 TDK CGA3E2NP01H101J080AA
Q200 Grade 0, 0603
RUVLOT 1 RES, 61.9 k, 1%, 0.1 W, AEC-Q200 Grade 0, 0603 Vishay-Dale CRCW060361K9FKEA
RUVLOB 1 RES, 71.5 k, 1%, 0.1 W, AEC-Q200 Grade 0, 0603 Vishay-Dale CRCW060371K5FKEA
RUVLOS 1 RES, 0, 5%, 0.1 W, 0603 Yageo America RC0603JR-070RL
CSS 1 CAP, CERM, 0.022 μF, 50 V, ±10%, X7R, 0603 Kemet C0603X223K5RACTU
RBIAS 1 RES, 0, 5%, 0.1 W, 0603 Yageo America RC0603JR-070RL
CAP, CERM, 0.1 μF, 100 V, ±10%, X7R, AEC-
CBIAS 1 MuRata GCJ188R72A104KA01D
Q200 Grade 1, 0603
CAP, CERM, 1 µF, 16 V, ±10%, X7R, AEC-Q200
CVCC 1 TDK CGA3E1X7R1C105K080AC
Grade 1, 0603

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表 9-2. List of Materials (continued)

REFERENCE
QTY. SPECIFICATION MANUFACTURER(1) PART NUMBER
DESIGNATOR
RVCC 1 RES, 5.1, 5%, 0.1 W, 0603 Yageo America RC0603JR-075R1L
RPG 1 RES, 100 k, 1%, 0.1 W, AEC-Q200 Grade 0, 0603 Vishay-Dale CRCW0603100KFKEA
RMODE 1 RES, 0, 5%, 0.1 W, 0603 Yageo America RC0603JR-070RL

(1) See the Third-Party Products Disclaimer.

9.2.2.3 Inductor Selection (LM)

When selecting the inductor, consider three key parameters: inductor current ripple ratio (RR), falling slope of the
inductor current, and RHP zero frequency (fRHP).
Inductor current ripple ratio is selected to have a balance between core loss and copper loss. The falling slope of
the inductor current must be low enough to prevent subharmonic oscillation at high duty cycle (additional RSL
resistor is required if not). Higher fRHP (lower inductance) allows a higher crossover frequency and is always
preferred when using a small value output capacitor.
The inductance value can be selected to set the inductor current ripple between 30% and 70% of the average
inductor current as a good compromise between RR, FRHP, and inductor falling slope.
9.2.2.4 Output Capacitor (COUT)
There are a few ways to select the proper value of output capacitor (COUT). The output capacitor value can be
selected based on output voltage ripple, output overshoot, or undershoot due to load transient.
The ripple current rating of the output capacitors must be enough to handle the output ripple current. By using
multiple output capacitors, the ripple current can be split. In practice, ceramic capacitors are placed closer to the
diode and the MOSFET than the bulk aluminum capacitors in order to absorb the majority of the ripple current.
9.2.2.5 Input Capacitor
The input capacitors decrease the input voltage ripple. The required input capacitor value is a function of the
impedance of the source power supply. More input capacitors are required if the impedance of the source power
supply is not low enough.
9.2.2.6 Diode Selection
A Schottky is the preferred type for a D1 diode due to its low forward voltage drop and small reverse recovery
charge. Low reverse leakage current is an important parameter when selecting the Schottky diode. The diode
must be rated to handle the maximum output voltage plus any switching node ringing. Also, it must be able to
handle the average output current.

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 LM5157
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9.2.3 Application Curve

100

90

80

Efficiency (%)
70

60
VSUPPLY =9V
50 VSUPPLY =6V
VSUPPLY =4V
VSUPPLY =3V
40
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6
Output Current (A)

图 9-2. Efficiency versus Output Current

9.3 System Examples

VSUPP LY VLOAD

BIAS VCC SW

UVLO FB
RT COMP
SS PGO OD
PGND AGND MODE

图 9-3. Typical Boost Application

VSUPP LY = 2.9V - 45V
VLOAD
- +
Car
Battery BIAS VCC SW
To MCU
From MCU PGO OD FB
UVLO COMP
RT SS
PGND AGND MODE

图 9-4. Typical Start-Stop Application

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VSUPP LY = Min 2.9 V

VLOAD = 12V

+
BIAS VCC SW
1-cell or
2-cell PGO OD FB
Battery
From MCU UVLO COMP
- RT SS
PGND AGND MODE

图 9-5. Emergency-Call/Boost On-Demand/Portable Speaker

VSUPP LY VLOAD

Option al
BIAS VCC SW

UVLO FB
RT COMP
SS PGO OD
PGND AGND MODE

图 9-6. Typical SEPIC Application

Inducta nce shoul d b e small enoug h
VSUPP LY to o perate in DCM a t ful l loa d VLOAD = 15V - 48V

BIAS VCC SW

UVLO FB
RT COMP From MCU
SS PGO OD
PGND AGND MODE

图 9-7. LiDAR Bias Supply 1 (DCM Operation)

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VLOAD = 90V - 144 V

Voltage
Tripler

Inducta nce shoul d b e b ig e nough

to o perate in CCM
VSUPP LY

BIAS VCC SW
From MCU
UVLO FB
RT COMP
SS PGO OD
PGND AGND MODE

图 9-8. LiDAR Bias Supply 2 (CCM Operation)

VSUPP LY VLOAD

BIAS VCC SW

UVLO FB
RT COMP
SS PGO OD
PGND AGND MODE

Ena ble Sprea d S pectru m

图 9-9. Low-Cost Single String LED Driver

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VSUPP LY VLOAD = 5V/12V

BIAS SW
UVLO/SYNC
PGND
AGND
VCC
PGO OD
MODE

RT

FB SS COMP

Optiona l P rimary-Side
Soft-Start

图 9-10. Secondary-Side Regulated Isolated Flyback

VLOAD 2 = +1 2V

VSUPP LY

V LOAD 3 = -8.5V
BIAS SW
UVLO/SYNC
Optiona l DC Coupli ng
Capacitor for Low EMI
AGND Isol ated S epic
PGND
To MCU
System Power PGO OD
MODE VLOAD1 = 3.3V/5V +/-2%
RT
FB
SS COMP VCC

图 9-11. Primary-Side Regulated Multiple-Output Isolated Flyback/Isolated SEPIC

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VSUPP LY VLOAD = 5V/12V

BIAS SW
UVLO/SYNC
PGND
AGND
To MCU
System Power PGO OD VCC
MODE

RT

SS COMP FB

图 9-12. Typical Non-Isolated Flyback

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10 Power Supply Recommendations

The device is designed to operate from a power supply or a battery whose voltage range is from 1.5 V to 45 V.
The input power supply must be able to supply the maximum boost supply voltage and handle the maximum
input current at 1.5 V. The impedance of the power supply and battery including cables must be low enough that
an input current transient does not cause an excessive drop. Additional input ceramic capacitors can be required
at the supply input of the converter.

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11 Layout
11.1 Layout Guidelines
The performance of switching converters heavily depends on the quality of the PCB layout. The following
guidelines will help users design a PCB with the best power conversion performance, thermal performance, and
minimize generation of unwanted EMI.
• Put the D1 component on the board first.
• Use a small size ceramic capacitor for COUT.
• Make the switching loop (COUT to D1 to SW to PGND to COUT) as small as possible.
• Leave a copper area near the D1 diode for thermal dissipation.
• Put the RVCC resistor in series with the CVCC capacitor as near the device as possible between the VCC and
PGND pins.
• Connect the COMP pin to the compensation components (RCOMP and CCOMP).
• Connect the CCOMP capacitor to the analog ground trace.
• Connect the AGND pin directly to the analog ground plane. Connect the AGND pin to the RMODE, RUVLOB, RT,
CSS, and RFBB components.
• Connect the exposed pad to the AGND pin under the device.
• Add several vias under the exposed pad to help conduct heat away from the device. Connect the vias to a
large ground plane on the bottom layer.

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11.2 Layout Examples

Thermal Dissipation
VSUPPLY GND
Area

VLOAD Do not connect input and

output capacitor grounds
underneath the device

D1

CVIN

LM
COUT2 COUT1
GND
CVIN
PGND

Power Ground Plane

SW
SW
NC

(Connect to EP via PGND pin)

16 15 14 13 Connect to the ground connection
of COUT using inner layer
CVCC PGND 1 12 SW Connect
EP
to VLOAD
RVCC 2 11 MODE RMODE
VCC
Connect to the ground
Connect to
connection of CIN using BIAS 3 10 SS CSS
RFBT

VLOAD / VSUPPLY
inner layer
PGO OD 4 9 FB
RFBB
Connect to
pull-up resistor 5 6 7 8
COMP
UVLO
RT

AGND

RCOMP CCOMP

RT
RUVLOB

Analog Ground Plane

(Connect to EP via AGND pin)

RUVLOT Connect
to VSUPPLY

图 11-1. PCB Layout Example

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12 Device and Documentation Support

12.1 Device Support
12.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此
类产品或服务单独或与任何 TI 产品或服务一起的表示或认可。
12.1.2 Development Support
12.1.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LM5157x device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
12.1.3 Export Control Notice
Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data (as
defined by the U.S., EU, and other Export Administration Regulations) including software, or any controlled
product restricted by other applicable national regulations, received from disclosing party under nondisclosure
obligations (if any), or any direct product of such technology, to any destination to which such export or re-export
is restricted or prohibited by U.S. or other applicable laws, without obtaining prior authorization from U.S.
Department of Commerce and other competent Government authorities to the extent required by those laws.
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation see the following:
• Texas Instruments, How to Design a Boost Converter Using LM5157x
• Texas Instruments, How to Design an Isolated Flyback Converter Using LM5157x
• Texas Instruments, How to Design a SEPIC Converter Using LM5157x
• Texas Instruments, LM5157EVM-BST User's Guide
• Texas Instruments, LM5157EVM-FLY User's Guide
• Texas Instruments, LM5157EVM-SEPIC User's Guide
12.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。

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12.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
WEBENCH® is a registered trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.6 静电放电警告
静电放电 (ESD) 会损坏这个集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。

12.7 术语表
TI 术语表 本术语表列出并解释了术语、首字母缩略词和定义。

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13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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English Data Sheet: SNVSBK7
 PACKAGE OPTION ADDENDUM

www.ti.com 16-Aug-2023

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

LM51571RTER ACTIVE WQFN RTE 16 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 L51571 Samples

LM5157RTER ACTIVE WQFN RTE 16 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LM5157 Samples

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 16-Aug-2023

OTHER QUALIFIED VERSIONS OF LM5157 :

• Automotive : LM5157-Q1

NOTE: Qualified Version Definitions:

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 16-Aug-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM51571RTER WQFN RTE 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
LM5157RTER WQFN RTE 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 16-Aug-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LM51571RTER WQFN RTE 16 3000 367.0 367.0 35.0
LM5157RTER WQFN RTE 16 3000 367.0 367.0 35.0

Pack Materials-Page 2
 GENERIC PACKAGE VIEW
RTE 16 WQFN - 0.8 mm max height
3 x 3, 0.5 mm pitch PLASTIC QUAD FLATPACK - NO LEAD

This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4225944/A

www.ti.com
 PACKAGE OUTLINE
RTE0016C SCALE 3.600
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

3.1 B
A
2.9

PIN 1 INDEX AREA

3.1
2.9

SIDE WALL
METAL THICKNESS
DIM A
OPTION 1 OPTION 2
0.1 0.2
C
0.8 MAX

SEATING PLANE
0.05
0.00 0.08

1.68 0.07 (DIM A) TYP

5 8
EXPOSED
THERMAL PAD
12X 0.5
4
9

4X 17 SYMM
1.5

1
12
0.30
16X
0.18
PIN 1 ID 16 13 0.1 C A B
(OPTIONAL) SYMM
0.05

0.5
16X
0.3

4219117/B 04/2022

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com
 EXAMPLE BOARD LAYOUT
RTE0016C WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

( 1.68)
SYMM
16 13

16X (0.6)

1
12

16X (0.24)
17 SYMM
(2.8)
(0.58)
TYP
12X (0.5)
9
4

( 0.2) TYP
VIA

5 8
(R0.05) (0.58) TYP
ALL PAD CORNERS
(2.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:20X

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

SOLDER MASK
METAL OPENING

EXPOSED EXPOSED
SOLDER MASK METAL METAL UNDER
METAL
OPENING SOLDER MASK

NON SOLDER MASK

SOLDER MASK
DEFINED
DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4219117/B 04/2022

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com
 EXAMPLE STENCIL DESIGN
RTE0016C WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

( 1.55)
16 13

16X (0.6)

1
12

16X (0.24)

17 SYMM
(2.8)

12X (0.5)

9
4

METAL
ALL AROUND

5 8
SYMM
(R0.05) TYP

(2.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 17:

85% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X

4219117/B 04/2022

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

www.ti.com
 重要声明和免责声明
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