A high-resolution self-timed zero-

crossing-based Incremental ∆Σ
ADC

Georgios Karykis
Master of Science Thesis

EEMCS
 A high-resolution self-timed
zero-crossing-based Incremental ∆Σ
ADC

Master of Science Thesis

For the degree of Master of Science in Electrical Engineering -

Microelectronics at Delft University of Technology

Georgios Karykis

May 18, 2015

Faculty of Electrical Engineering, Mathematics and Computer Science · Delft University of

Technology
 The work in this thesis was supported by NXP Semiconductors, Eindhoven. Their coop-
eration is hereby gratefully acknowledged.

Copyright © Faculty of Electrical Engineering, Mathematics and Computer Science. All

rights reserved.
 Delft University of Technology
Faculty of
Electrical Engineering, Mathematics and Computer Science

The undersigned hereby certify that they have read and recommend to the Faculty of
Electrical Engineering, Mathematics and Computer Science for acceptance a thesis
entitled
A high-resolution self-timed zero-crossing-based Incremental ∆Σ ADC
by
Georgios Karykis
in partial fulfillment of the requirements for the degree of
Master of Science Electrical Engineering - Microelectronics

Dated: May 18, 2015

Supervisor(s):
Dr.ir. Michiel A.P. Pertijs

Chao Chen, M.Sc.

Reader(s):
Dr.ir. Michiel A.P. Pertijs

Dr. Marco Spirito

Dr.ir. Jaap Hoekstra

Dr.ir. Robert H.M. van Veldhoven

 Abstract

This thesis discusses the design and verification of a high-resolution self-timed incremental
∆Σ ADC. The first self-timed incremental ∆Σ ADC was presented by C.Chen et.al at ISSCC
2013 and this work targets to improve the resolution, linearity and energy-efficiency of a
self-timed ADC. Unlike conventional ∆Σ ADCs, a self-timed ADC is capable of arranging
the timing itself and does not rely on a dedicated clock, saving energy and reducing system
complexity. This work is tailored for energy-constrained integrated sensor interfaces, where
resolution and linearity requirements are often above 16-bit.
For the implementation of the self-timed ADC, the knowledge of the charge-transfer com-
pletion of the switched-capacitor integrators of the loop-filter is necessary for the generation of
the self-timed control signals. Zero-crossing-based (ZCB) switched-capacitor integrators were
employed before in the design of the self-timed I∆Σ ADC because the knowledge of the end
of the charge-transfer is available. This thesis focuses on the systematic noise and linearity
design of the first ZCB integrator of the self-timed ADC, building on the implementation of
C.Chen et.al (ISSCC 2013), which is the state-of-the-art ∆Σ ADC design that is employing
comparator-based or zero-crossing-based switched capacitor (CBSC/ZCBSC) circuits up to
now.
An improved prototype chip of self-timed incremental ∆Σ ADC was implemented in
NXP 1P5M 0.16µm CMOS process. A second-order single-ended ∆Σ modulator was designed
accordingly and verified using pre-layout and post-layout simulations. The results of these
simulations show that the improved prototype achieves resolution of approximately 16.7-bit,
linearity of 1LSB with respect to 17-bit, when the modulator is operating for 1000 incremental
cycles. The conversion time is less than 1.01ms, while the chip consumes less than 26µA from
a 1V supply. This performance corresponds to a Schreier FOM of the ADC of 168.8dB, which
is the best among CBSC/ZCB ∆Σ ADCs and fairly close to the state-of-the-art of OTA-based
ADCs for Instrumentation & Measurement or audio applications.

Keywords: Energy-efficient, high-resolution, incremental ∆Σ ADC, self-timed, zero-

crossing-based integrator.

Master of Science Thesis Georgios Karykis

ii

Georgios Karykis Master of Science Thesis

 Table of Contents

1 Introduction 1
1-1 Concept: Self-timed Incremental ∆Σ ADC using ZCB SC circuits . . . . . . . 1
1-2 Challenges and target specifications . . . . . . . . . . . . . . . . . . . . . . . 3
1-3 Brief description of solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1-4 Thesis organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2 System-level overview of Incremental ∆Σ ADC and description of previous

prototype 7
2-1 ∆Σ ADC: Incremental operation . . . . . . . . . . . . . . . . . . . . . . . . . 7
2-2 Noise and linearity performance as function of Number of cycles N . . . . . . 10
2-3 Description of the first prototype of self-timed I∆Σ ADC . . . . . . . . . . . 13
2-3-1 Top-level description and self timed operation . . . . . . . . . . . . . . 13
2-3-2 ZCB SC integrator: Coarse-fine charge transfer mechanism . . . . . . 14
2-3-3 ZCB integrator: Correlated level shifting . . . . . . . . . . . . . . . . 16
2-3-4 Circuit-level implementation details . . . . . . . . . . . . . . . . . . . 18
2-4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3 Noise and linearity analysis of ZCB SC integrator with CLS 23

3-1 Closer overview of ZCD response to ramp input . . . . . . . . . . . . . . . . . 23
3-2 Noise analysis of the ZCB integrator . . . . . . . . . . . . . . . . . . . . . . . 26
3-2-1 Non steady-state noise analysis . . . . . . . . . . . . . . . . . . . . . . 26
3-2-2 Apparent noise contributors . . . . . . . . . . . . . . . . . . . . . . . . 26
3-2-3 Estimation of noise performance of the first prototype . . . . . . . . . 34
3-3 Linearity analysis of the ZCB integrator with CLS . . . . . . . . . . . . . . . 34
3-3-1 Non-linear error due to switches . . . . . . . . . . . . . . . . . . . . . 34
3-3-2 Non-linear error due to ramp-rate variation . . . . . . . . . . . . . . . 36
3-3-3 Non-linear error caused by turn-off transients of current sources . . . . 37
3-4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

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iv Table of Contents

4 Noise and linearity measurement results of the first prototype 39

4-1 Existing Measurement setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4-2 Noise measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4-3 Linearity measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4-4 Performance summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4-5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

5 Design for improved self-timed ZCB I∆Σ ADC 45

5-1 Design procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
5-2 System-level considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
5-2-1 Modulator order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
5-2-2 Matlab simulation of 2nd -order modulator with input-FF path . . . . 50
5-2-3 Design space exploration for the implementation of ZCB integrator . . 51
5-3 Noise and linearity design of the ZCB integrator . . . . . . . . . . . . . . . . 56
5-3-1 Noise design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
5-3-2 Linearity design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
5-4 Simulation results of the ZCB integrator . . . . . . . . . . . . . . . . . . . . . 61
5-4-1 Input-referred noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
5-4-2 Input-referred error over process corners . . . . . . . . . . . . . . . . . 62
5-4-3 Power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
5-5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

6 Final Realization 65
6-1 Design of the second ZCB integrator . . . . . . . . . . . . . . . . . . . . . . . 65
6-2 Further energy consumption reduction measures . . . . . . . . . . . . . . . . 67
6-3 Implementation of the other sub-blocks of the ADC . . . . . . . . . . . . . . 68
6-3-1 Generation of Vof f . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
6-3-2 Digital control of the charge-transfer . . . . . . . . . . . . . . . . . . . 69
6-3-3 Clock boosters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
6-3-4 Bitstream comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
6-3-5 Current reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
6-4 Configurability and testing features of the chip . . . . . . . . . . . . . . . . . 72
6-5 Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
6-6 Simulation results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
6-6-1 Pre-layout simulation results . . . . . . . . . . . . . . . . . . . . . . . 74
6-6-2 Post-layout simulation results . . . . . . . . . . . . . . . . . . . . . . . 76
6-7 Performance summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
6-8 Improved measurement setup proposal . . . . . . . . . . . . . . . . . . . . . . 78
6-9 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Georgios Karykis Master of Science Thesis

Table of Contents v

7 Conclusions 81
7-1 Thesis summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
7-2 Suggestions for future work . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

A Results of pre-layout and post-layout input sweeps 85

Bibliography 87

Master of Science Thesis Georgios Karykis

vi Table of Contents

Georgios Karykis Master of Science Thesis

 List of Figures

1-1 Circuit diagram (a) and waveforms of operation (b) of a ZCB SC integrator [5]. 2

2-1 Block diagram of an Incremental ∆Σ converter. . . . . . . . . . . . . . . . . . 8

2-2 Block diagram of second-order Boser-Wooley modulator with input feed-forward
path [25]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2-3 ENOB as a function of N considering only quantization noise or only thermal
noise. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2-4 Block diagram of the self-timed I∆Σ modulator used in [1]. . . . . . . . . . . 13
2-5 Asynchronous state machine for the generation of the self-timed clock signals
[25]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2-6 Dual-rate ZCB integrator implementation alternatives. . . . . . . . . . . . . . 15
2-7 ZCB integrator employing Correlated level shifting. . . . . . . . . . . . . . . . 17
2-8 Gated current sources implementation in [1]. . . . . . . . . . . . . . . . . . . 19
2-9 Circuit diagram and operation of the ZCD in [1]. . . . . . . . . . . . . . . . . 20

3-1 ZCB integrator employing Correlated level shifting. . . . . . . . . . . . . . . . 24

3-2 AZ Inverter-based preamp small-signal model during charge transfer phase. . 24
3-3 Waveforms of ZCD during charge transfer phase. . . . . . . . . . . . . . . . . 25
3-4 ZCD noise modelling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3-5 Effective noise bandwidth as function of ti and τ . . . . . . . . . . . . . . . . . 29
3-6 Current consumption and voltage response of inverter preamp during charge
transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3-7 Noise due to switch on-resistance during charge transfer of ZCB integrator. . 31
3-8 Feedback switches on-resistance induced error. . . . . . . . . . . . . . . . . . 35

4-1 Block diagram of the measurement setup of the first prototype [25]. . . . . . 39
4-2 Measurement result of the first prototype for the resolution (ENOB) as a func-
tion of N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Master of Science Thesis Georgios Karykis

viii List of Figures

4-3 Measurement result of the INL of the first prototype [1]. . . . . . . . . . . . . 42

4-4 Measurement results of the INL of the first prototype of 6 consecutive runs. . 42
4-5 Measurement of the sample-to-sample variation of the INL of the first prototype
[1]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

5-1 Linearity simulation results for the first integrator in [1]: (a) Signal-dependent
component of input-referred error of the first integrator in [1], (b) Simulated
INL of the first prototype [1] . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
5-2 Quantization noise and integrators’ swings for 2nd -order modulator with input
feed-forward path for N = 1000. . . . . . . . . . . . . . . . . . . . . . . . . . 50
5-3 Circuit diagram of the fully-differential ZCB integrator with CMFB. . . . . . 52
5-4 Signal waveforms of the fully-differential ZCB integrator during charge transfer. 53
5-5 Circuit diagram of the pseudo-differential ZCB integrator with CM correction. 54
5-6 Signal waveforms of the pseudo-differential ZCB integrator during charge trans-
fer phase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
5-7 Alternatives for the inverter-based implementation of the preamplifier: (a)
class-AB inverter amplifier, (b) the cascode-inverter amplifier and (c) the current-
starved inverter amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
5-8 Sizing of the inverter-based preamplifier for the first integrator. . . . . . . . . 58
5-9 Comparison of the operating points of ZCD inverter-based preamplifiers: (a)
proposed design, (b) preamplifier used in [1]. . . . . . . . . . . . . . . . . . . 59
5-10 Sizing and biasing of charging current sources. (a) Coarse current source, (b)
Fine current source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
5-11 Normalized input-referred error of the ZCB integrator. . . . . . . . . . . . . . 61
5-12 Simulation testbench for the input-referred noise of ZCB integrator. . . . . . 62
5-13 Simulation of current consumption of ZCB integrator during charge transfer. 63

6-1 Sizing and operating point of the inverter-based preamplifier of the second
integrator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
6-2 Schematic of a diode voltage reference for the generation of Vof f inside the ZCDs. 68
6-3 Schematics of (a) a single-output clock-booster and (b) a double-output clock
booster [25]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
6-4 Schematic of the dynamic bitstream comparator [25]. . . . . . . . . . . . . . . 71
6-5 Schematic of the current reference, including the start-up circuit [25]. . . . . . 71
6-6 Layout of the ADC in 0.16µm 1P5M CMOS. . . . . . . . . . . . . . . . . . . 73
6-7 Pre-layout simulated INL of the ADC. . . . . . . . . . . . . . . . . . . . . . . 75
6-8 Pre-layout simulated conversion time of the ADC as function of input voltage. 76
6-9 Post-layout simulated INL of the ADC. . . . . . . . . . . . . . . . . . . . . . 77
6-10 Post-layout simulated conversion time of the ADC as function of input voltage. 77

Georgios Karykis Master of Science Thesis

 List of Tables

1-1 Performance comparison of prior CBSC/ZCB ∆Σ ADCs . . . . . . . . . . . . 4

1-2 Performance comparison of state-of-the-art OTA-based Incremental ∆Σ ADCs
and audio ∆Σ ADCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1-3 Design specifications of improved self-timed ADC . . . . . . . . . . . . . . . . 5

2-1 Design parameters of the inverter-based preamplifiers of the ZCDs in [1] . . 21

2-2 Capacitor values used in ZCB integrators in [1] . . . . . . . . . . . . . . . . . 21

4-1 Updated Performance Summary of the first prototype [1] . . . . . . . . . . . 43

5-1 Simulated fine current source output impedance over process corners. . . . . . 62
5-2 Input-referred error of ZCB integrator over corners . . . . . . . . . . . . . . . 63

6-1 Design parameters of the inverter-based preamplifiers in the ZCDs . . . . . . 67

6-2 Performance Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6-3 Performance comparison with Prior CBSC/ZCB ∆Σ ADCs . . . . . . . . . . 79

A-1 Simulation results of pre-layout input sweep . . . . . . . . . . . . . . . . . . . 85

A-2 Simulation results of post-layout input sweep . . . . . . . . . . . . . . . . . . 86

Master of Science Thesis Georgios Karykis

x List of Tables

Georgios Karykis Master of Science Thesis

 Chapter 1

Introduction

Incremental ∆Σ Analog-to-Digital converters (ADCs) are an attractive choice for the digiti-
zation of low-frequency signals often found in sensor applications. Incremental ADCs rely on
a high-frequency dedicated oversampling clock. However, in energy-constrained sensor appli-
cations, where the signals of interest are infrequent and slowly varying (e.g. environmental
signals), the generation of the high frequency clock may be a bottleneck in terms of energy
consumption. In [1], a 14-bit self-timed incremental ∆Σ ADC has been proposed to solve this
problem. This thesis is building up on this, targeting to improve the resolution and linearity
of the self-timed I∆Σ ADC above 16-bit in an energy-efficient way. Special attention is paid
in the design of the first ZCB integrator of the loop-filter as it is the most performance critical
component of the entire ADC.
At the beginning of this chapter, the concept of the self-timed Incremental ∆Σ ADC
is briefly introduced, including its potential advantages and operating principle, highlighting
the crucial role of zero-crossing-based circuits in the implementation without any dedicated
oversampling clock. This is followed by a short discussion on the challenges and targets of this
work, based on related prior work. At this point the objectives of this project are summarized
and a brief description of the solution is presented. Finally, the structure of the rest of the
thesis is described.

1-1 Concept: Self-timed Incremental ∆Σ ADC using ZCB SC

circuits

This work is a follow-up of the world’s first self-timed incremental ∆Σ ADC [1], which demon-
strates the capability of operation without dedicated external clocks. The most important
benefit of this strategy is the reduction the overall system complexity and power consump-
tion. This comes from the fact that the oversampled clock generation circuitry (oscillators
and/or PLLs) can be avoided and the clock generation functionality can be replaced by an
asynchronous state machine. Furthermore, for input signals with very low activity (environ-
mental signals) the conversions are performed in an irregular manner and thus, the power

Master of Science Thesis Georgios Karykis

 2 Introduction

consumption of the clock generation circuitry can be an important factor of the overall energy
consumption.
The self-timed nature of the ADC in [1] was realized using a mixed-signal self-timed
approach, in which hand-shaking between the analog signal processing circuitry and digital
control is necessary. In this approach, the analog circuit has to be capable to generate
a completion signal of the underlying analog function (e.g. integration, amplification etc)
which is used by the digital control circuit in order to control the operation.
In the context of a discrete-time incremental ∆Σ modulator, the timing of the successive
sampling and charge transfer phases of the switched-capacitor integrators can be arranged
effectively by a 2-state asynchronous state machine, provided that the completion signals of
the charge-transfer process of the SC integrators are available. In a conventional OTA-based
implementation of a SC integrator, however, the signals are settling following an exponential
trajectory and because of that an indicator of completion is not available. This fundamental
limitation was bypassed in [1], by changing the charge-transfer mechanism utilizing zero-
crossing based switched-capacitor integrators. Zero-crossing based SC (ZCBSC) circuits are
based on the Comparator-based SC (CBSC) circuits that were introduced in [2]. Comparator-
based and zero-crossing-based SC circuits have been mainly used in the design of pipeline
ADCs in advanced CMOS technologies [2] [3] [4], in order to overcome the difficulties of
realizing high-performance and low-power OTAs that are operating with low supply voltage.
The circuit diagram of a ZCB SC integrator is shown in Figure 1-1(a). This circuit and its

VO
VDD
Settled
output

VSS
VX t
Φ2 CI VDD
VX0 Final
VDD
Overshoot
Φ1 CS
P Φ2 VCM
Vin Vout
VX D VO
CL VSS
Φ2 Φ1 E t
I Φ1
Φ2
Φ2
P
E
D
(a) (b)

Figure 1-1: Circuit diagram (a) and waveforms of operation (b) of a ZCB SC integrator [5].

operation are very similar to an OTA-based SC integrator, but the OTA is replaced by a zero-
crossing detector that is detecting the virtual-ground condition and a gated current source
that is responsible for the charge transfer. The operation of a ZCB integrator is visualized in

Georgios Karykis Master of Science Thesis

1-2 Challenges and target specifications 3

the waveforms of Figure 1-1(b). While the sampling phase Φ1 is identical with a OTA-based
integrator, the charge-transfer phase Φ2 of the ZCB integrator begins with presetting the
output node to the supply VDD . Because of this, the virtual-ground node VX is preset higher
than VCM to a level that depends on the charge sampled on CS and the previously integrated
charge on CI . Right after the preset, the gated current source is enabled to discharge the
capacitive feedback network of the integrator forcing the signals to follow a linear trajectory.
Once VX reaches VCM , the ZCD detects the virtual ground condition, the current source is
turned-off and the output voltage is sampled.
It is important to remark that it is not important how VO evolves towards its final value,
but only how accurate its final value is, since we are dealing with a sampled-data system. As
a result, the functionality of a ZCB integrator is identical with the OTA-based integrator and
furthermore, the knowledge of completion of the charge transfer is available which enables
purely self-timed operation in the ∆Σ ADC of [1].

1-2 Challenges and target specifications

As mentioned before, the main motivation for the development of ZCB circuits was the
difficulty to design high-gain and closed-loop stable opamps in advanced CMOS processes,
due to low supply voltages and degraded intrinsic gain of transistors. Apart from this, a
few important advantages are present in zero-crossing based circuits concerning their energy-
efficiency compared to the OTA-based structures. First, the ZCD only detects the virtual-
ground condition but it does not force it, so intuitively it is expected to be more energy-
efficient. Also, the ZCB circuits are open-loop, so frequency compensation is not needed to
guarantee stability. Furthermore, inspecting the noise analysis of ZCB circuits the effective
noise-bandwidth of the ZCD is lower than the steady-state noise bandwidth of an OTA [2],
which means that lower power is needed to meet a target specification for noise. Therefore,
circuitry based on zero-crossings is expected to demonstrate higher energy efficiency compared
to OTA-based designs.
In Table 1-1 the performance of all the reported ∆Σ ADCs based on CBSC/ZCBSC
circuits are summarized. Also, in Table 1-2 state-of-the-art designs of incremental ∆Σ ADCs
with application to integrated sensor interfaces or biomedical sensor arrays (including hybrid
ADCs and extended range incremental ADCs), along with two audio ∆Σ ADCs are summa-
rized in order to facilitate a comparison between ZCB ADCs with conventional OTA-based
ADCs.
When inspecting these two tables, it becomes directly clear that the reported energy-
efficiency (in terms of F OMS ) is much lower for the designs that are based on CBSC/ZCB
circuits, which contradicts the previously claimed advantages of these techniques. Also, the
achieved resolution and linearity are limited in case of CBSC/ZCB ∆Σ ADCs. The best design
is the first prototype self-timed ADC which achieves 14.8-bit resolution and INL of 1LSB w.r.t.
14-bit, demonstrating the highest energy efficiency among the CBSC/ZCB designs, but still
far from the state-of-the-art of high resolution ∆Σ ADCs.
Moreover, the demonstrated performance of the CBSC/ZCB ∆Σ ADCs is limited in terms
of linearity to at most 14-bit and resolution to at most 15-bit [1], although higher values are
required in integrated sensor interfaces. Therefore, it is very interesting to explore ways to

Master of Science Thesis Georgios Karykis

4 Introduction

Table 1-1: Performance comparison of prior CBSC/ZCB ∆Σ ADCs

[6] [7] [8] [9] [1]

Architecture ∆Σ2 - FD ∆Σ2 - FD ∆Σ4 - PD ∆Σ2 - SE IADC2 - SE
Process 0.18µm 45nmLP 90nm 3µmT F T 0.16µm
Area (mm2 ) 0.21 0.0448 0.33 26 0.45
VDD (V ) 1.8 1.1 1 11.2 1
Sampling frequency 2.56 MHz 50 MHz 1 MHz 400 kHz 750 kHz
OSR 64 30 48 128 500
Bandwidth (Hz) 20 kHz 833 kHz 1 MHz 1.56 kHz 667 Hz
Dynamic Range (dB) 71 54.3 70 69 81.9
Peak SNR (dB) 65.3 47.7 66 65.6 81.9
Power 0.42mW 630µW 5.94mW 63.3mW 20µW
FOMW (pJ/step) 6.98 1.91 1.82 13.03 1.46
FOMS (dB) 147.8 145.5 152.3 112.9 157.1
P ower · Tconv 1
F OMW = (SN R−1.76)/6.02 . F OMS = SNR + 10 · log .
2 Power · Tconv

improve the resolution and linearity of a ZCB ADC and bring them to a level higher than 16-
bit. Another interesting question is why the energy-efficiency of ZCB ∆Σ ADCs is far below
the state-of-the-art of ∆Σ ADCs. The limitations of the energy-efficiency have to be explored
targeting to an improvement of the achievable energy-efficiency, if possible to the level of OTA-
based ∆Σ ADCs. This can be done having as starting point the best design of ZCB ∆Σ ADCs
[1] and find out what is limiting the achievable performance. One straightforward approach
could be the extension of [1] to a third or higher-order ∆Σ modulator. Another interesting
research direction could be the extension of [1] to a fully-differential implementation.
All the previously mentioned alternatives should be carefully examined and based on
their feasibility the realization of an improved self-timed ZCB incremental ∆Σ ADC should be
possible. Achieving higher resolution and linearity (higher than 16-bit) is of primary interest
as well as demonstrate higher energy-efficiency. In Table 1-3, the target specifications of the
improved self-timed ∆Σ ADC are summarized.

1-3 Brief description of solution

This work has as basis the first prototype self-timed I∆Σ ADC [1] and focuses on finding ways
of improving its performance and energy-efficiency. The work was based on the analytical
estimation of noise and linearity of the first integrator, targeting to reveal trade-offs that are
useful for design. A fairly accurate noise model has been developed, which was verified by
revisiting the measurement of the first prototype, after fixing some accuracy problems of the
measurement setup. Also, the linearity of the ZCB integrator has been analyzed, but the
accuracy of this model is not good. As a result, a simulation-based linearity design procedure
has been followed.

Georgios Karykis Master of Science Thesis

 1-3 Brief description of solution 5

Table 1-2: Performance comparison of state-of-the-art OTA-based Incremental ∆Σ ADCs

and audio ∆Σ ADCs

[10] [11] [12] [13] [14]-III [15]

Architecture 10bit SAR + 6bit SAR + IADC2-FD IADC2-FD + ∆Σ3-PD: ∆Σ3-PD:
IADC1-FD IADC2-PD + 11bit SAR IADC1-FD inverter-based inverter-based
Process 0.6µm 0.16µm 0.18µm 65nm 0.18µm 0.35µm
Area (mm2 ) 1.64 0.375 3.5 0.2 0.715 0.207
VDD (V ) 3.3 1.8 1.8 1.2 0.7 1.5
Sampling freq. 5 MHz 50 kHz 45.2 MHz 96 kHz 4 MHz 2.4 MHz
OSR 256 400 45 192 200 120
Bandwidth 9.75 kHz 121.5 Hz 500 kHz 250 Hz 20 kHz 20 kHz
Dynamic range (dB) 84.6 119.8 90.1 99.8 85 92.6
Peak SNDR (dB) 70.7 119.8 86.3 90.8 81 87.9
Power 64µW 6.3µW 38.1mW 10.7µW 36µW 140µW
FOMW (pJ/step) 1.17 0.32 1.46 0.76 0.098 0.173
FOMS (dB) 166.4 182.8 157.1 173.5 172.4 174
P ower · Tconv 1
F OMW = (SN R−1.76)/6.02 . F OMS = SNR + 10 · log .
2 Power · Tconv
SE: single-ended, PD: pseudo-differential, FD: fully-differential.
IADCx: x-order Incremental ∆Σ ADC, ∆Σx: x-order ∆Σ ADC.
SAR: SAR ADC [16].

Table 1-3: Design specifications of improved self-timed ADC

Specification Performance
Technology NXP 0.16µm 1P5M CMOS
Active Chip Area (mm2 ) <0.7
Supply Voltage (V) 1
Supply Current (µA) lowest possible <26µA
Conversion Time (ms) <1.5
Resolution (bits) >16.5
SNR (dB) >90
INL (LSB) <1LSB w.r.t.16-bit
FOMW (pJ/conv.-step) lowest possible (<1.48)
FOMS (dB) highest possible (>164)

Then, the extension to a differential topology for the ZCB integrator was explored. It
turned out that a fully-differential implementation was not possible in this project, due to the
inability to bring the signal-dependent input-referred error of the integrator to an acceptable
level that would permit to meet the linearity requirement of <1LSB w.r.t 16-bit. However,
a pseudo-differential ZCB integrator was found not to be capable of meeting our linearity
specification, but it was not implemented, mainly due to shortage in design time during
this project. As a result, a single-ended implementation was decided to be utilized in this
prototype as well.

Master of Science Thesis Georgios Karykis

6 Introduction

Based on the noise analysis that has been developed, it was revealed that a 3rd -order
modulator is not necessarily going to help to fulfill the targets of this project, in a more energy-
efficient way, compared to a 2nd -order modulator. Also, due to an important implementation
issue of the 3rd -order CIFF topology when it is realized using ZCB integrators, the idea of
extending to a 3rd -order modulator was put aside. Using a second-order ∆Σ modulator,
similar to the first prototype and resizing accordingly the two ZCB integrators of the loop-
filter, the achievable resolution is 16.7-bit, while the achievable linearity is 1LSB w.r.t. 17-bit,
based on simulation results. To achieve this the modulator is operating for 1000 incremental
cycles, having a conversion time less than 1.01ms, while consuming less than 26µW from a
1V supply. As a result, the energy-efficiency was slightly improved and brought closer to the
state-of-the-art designs of OTA-based ∆Σ ADCs.

1-4 Thesis organization

Apart from this introductory chapter, the rest of the thesis is organized as follows.
Chapter 2 contains a brief introduction of the working principle and system-level consid-
eration of incremental ∆Σ ADCs, focusing on the noise behavior as a function of number of
the number of incremental cycles and the order of the modulator. This chapter, also, provides
a brief description of the circuit-level implementation of [1], focusing on the special circuit
techniques and design choices that enable to demonstrate state-of-the-art performance among
ZCB ∆Σ ADCs.
Chapter 3 tackles the extensive noise and linearity analysis of the most critical building
block of a ZCB ∆Σ ADC: the first ZCB SC integrator which utilizes correlated level-shifting
for linearity improvement. In this analysis, all the non-ideal effects of the circuit-level im-
plementation are taken into account, resulting to a design-oriented noise estimation that is
fairly accurate. Regarding the linearity estimation, it was observed that the analysis is not
very successful to capture the dominant source of non-linearity, so a simulation-based design
procedure was concluded to be suitable.
Chapter 4 discusses the accuracy limitations of the measurement setup that was designed
for the characterization of the design in [1]. The updated measurement results for noise and
linearity, along with an updated performance summary of the previous prototype are also
presented.
Chapter 5 describes the design of the first integrator of the improved self-timed ZCB
incremental ∆Σ ADC, after a broad design space exploration on the implementation of an
improved ZCB ADC including the options of extension to a higher-order modulator and the
realization of a fully-differential structure. The simulation results for noise and linearity of
the designed integrator are presented in the end.
Chapter 6 presents all the implementation details of the improved self-timed ADC pro-
totype, besides the design of the first integrator, followed by a description of the layout of the
ADC. Finally, the top-level pre-layout and post-layout simulation results of the implemented
ADC are attached, including a performance summary, along with a comparison with the other
state-of-the-art CBSC/ZCB and OTA-based ∆Σ designs.
This thesis ends with a short summary of this thesis work in Chapter 7. Also, suggestions
for future work and potential improvements are highlighted.

Georgios Karykis Master of Science Thesis

 Chapter 2

System-level overview of
Incremental ∆Σ ADC and
description of previous prototype

Since this project is a follow-up of the previously proposed world’s first self-timed Incremen-
tal ∆Σ ADC [1], it is instructional to briefly summarize the circuit techniques and design
choices used in [1] that led to achieve high performance at state-of-the-art energy efficiency
among the CBSC/ZCB designs. The impact of these choices will be clearly understood and
quantified after the in-depth analysis of ZCB SC integrator, that is following in Chapter 3.
The description of the first prototype follows after a brief overview of the working principle
and system-level considerations in the design of Incremental ∆Σ converters, focusing on the
noise and linearity behavior as a function of number of incremental cycles N and loop-filter
order.

2-1 ∆Σ ADC: Incremental operation

∆Σ ADC is the most-used architecture in applications that demand high resolution and
accuracy. This is because their operation is not relying on precise analog elements, unlike
their Nyquist rate counterparts, but employ simple analog blocks in order to achieve adequate
performance. The obtained performance of ∆Σ ADCs stems from two aspects: First of all,
the sampling of the input signals at a much higher rate than the bandwidth, which is called
oversampling, and results in attenuation of the total in-band noise density. In theory, the
obtained resolution increases by half a bit by doubling the oversampling ratio, which is defined
fs
as 2BW . Second, the loop filter is moving the quantization error outside the signal band, which
in the end it is filtered out by the decimation filter. This so-called noise-shaping results in
much higher increase in resolution than 0.5 bits per doubling of OSR, which has been proven
very attractive for implementation in CMOS technology; speed is being traded for resolution.
In the end, the oversampled data are decimated (low-pass filtered and re-sampled) producing

Master of Science Thesis Georgios Karykis

8 System-level overview of Incremental ∆Σ ADC and description of previous prototype

the Nyquist-rate multi-bit output of the ADC. The theory and operation of these classical
∆Σ ADCs is extensively discussed in [17] and [18].
These classical ∆Σ A/D conversion schemes are utilized in applications where a running
waveform needs to be digitized, for instance in telecommunications or audio applications.
In these cases, the output spectral properties are important and the performance is quanti-
fied in terms of dynamic range (DR) or Signal-to-noise ratio (SNR). In contrast, in sensor
applications the underlined signals have narrow bandwidth and extremely accurate sample-
by-sample mapping is necessary. Besides the high resolution, which is typically expressed in
Effective-number-of-bits (ENOB), low offset and gain errors and very high linearity, which is
characterized by Integral non-linearity (INL), are demanded under the stringent restriction
of low power consumption [19]. In this case, ∆Σ converters can be utilized in single-shot
fashion: The ADC is powering up, performs a single conversion and then is powers down
again. This special case of ∆Σ converters tailored for Instrumentation and Measurement
(I&M) applications are called Incremental ∆Σ ADCs, whose a block diagram is shown in
Figure 2-1. More detailed analysis on the concept, properties and design of Incremental ∆Σ
ADCs can be found in [19], [20],[21], [22] and [23]

CLK

vin ΔΣ bs Decimation
μout
vref Modulator Filter

Reset Reset

Figure 2-1: Block diagram of an Incremental ∆Σ converter.

The operation for a single conversion of an Incremental ∆Σ is as follows: First, all the
memory elements of the modulator, i.e., the switched capacitor (SC) integrators of the loop
filter, and the decimation filter are reset. Then, a fixed number of steps depending on the
target resolution are performed and in each cycle the bitstream output of the modulator is
determining the feedback signal of the loop filter. Also, the decimation filter which has much
simpler implementation compared to free-running ∆Σ ADCs, is working in parallel with the
modulator and filters out the quantization noise and produces the output of the ADC without
creating significant timing overhead. Typical implementations of the decimation filters of an
k-order ∆Σ are sinck filters [20] or a matched filter [24] (or so-called cascade-of-integrators
[20]) which has the same impulse response with the analog loop-filter. Another alternative,
when periodical noise needs to be suppressed is a higher-order sincm filter [20].
The operation of an Incremental ∆Σ converter is instructive to be described using time-
domain analysis and derivation of the output signal of the integrators of the loop filter at
cycle n. For example, this is demonstrated for the 2nd -order Boser-Wooley structure with an
input feed-forward path, which was used in [1] and shown in Figure 2-2.

Georgios Karykis Master of Science Thesis

2-1 ∆Σ ADC: Incremental operation 9

b
a1 = 0.25 a2 = 0.5 b = 0.5

a1 z-1/2 z-1/2
VIN a2 y
1-z-1 1-z-1
w1 w2

b DAC
Reset Reset

z-1/2

Figure 2-2: Block diagram of second-order Boser-Wooley modulator with input feed-forward
path [25].

As noticed before, both integrators are reset before each conversion and the input signal
is assumed constant throughout the conversion. The output samples of the two half-delay
integrators at the sample time index i are given by

w1 [i] = w1 [i − 1] + a1 Vin − a1 y[i]Vref (2-1)

w2 [i] = w2 [i − 1] + a2 w1 [i] + a2 b · Vin − a2 b · y[i]Vref (2-2)

where y[i] is the output of the single-bit quantizer and Vref is the reference voltage of the ADC.
These two expressions can be rearranged and the non-iterative outputs of the two integrators
after the n-th iteration are

n
X
w1 [n] = a1 n · Vin − a1 y[i] · Vref (2-3)
i=1

 n   n X
i n 
w20 [n]
X X X
= a1 a2 i + a2 b · n · Vin − a1 a2 y[j] + a2 b y[i] · Vref (2-4)
i=1 i=1 j=1 i=1

Hence, by operating the modulator for N cycles, we can derive the ratio of the input
voltage over the reference µout by re-arranging the expression (2-6), as follows

N X
i N
Vin 2a1 b X 2
X 
= y[j] + y[i] + w2 [N ]
Vref a1 N (N + 1) + 2b · N i=1 j=1
a1 i=1 a1 a2 N (N + 1) + 2a2 bN
(2-5)
where w2 [N ] is the final value of the second integrator. The first term of the previous expres-
sion is the estimation of the input voltage and the second term is representing the quantization
error. It is readily clear that the estimation of the input can be retrieved by a simple digital

Master of Science Thesis Georgios Karykis

10 System-level overview of Incremental ∆Σ ADC and description of previous prototype

filter which processes the output bitstream y[i] of the analog modulator. This filter is the
previously mentioned matched decimation filter. On the other hand, the quantization error
2
Qerr = · w2 [N ] · Vref (2-6)
a1 a2 N (N + 1) + 2a2 bN

determines the achieved resolution of the ADC; For an ADC with k-bit ENOB the quanti-
2Vref
zation error should be upper-bounded by the VLSB of k-bits: VLSB = . Thanks to the
2k
stability of the modulator, w2 [N ] is bounded by [−Vref , +Vref ], but in practical case this
cannot be used for an accurate estimation, as the exact output swing of the second integrator
at the last cycle is not known. However, the converter can be simulated using a MATLAB
script for the whole input range, as done in [25] and a much clearer picture of the quantization
error behavior can be obtained.

2-2 Noise and linearity performance as function of Number of

cycles N

The achievable resolution of an Incremental ∆Σ ADC is limited by two uncor related noise
processes: quantization noise of the ADC and intrinsic (thermal) noise generated by the
building blocks of the modulator (e.g. switched capacitor integrators). Most often, resolution
is quantified using the Effective-number-of-bits (ENOB) which is defined as

A
 
ENOB(bits) = 20 · log10 − 1.76 6.02 (2-7)
δrms
where δrms is the standard deviation of the decimated outputs and A is the stable input range
of the converter. An equivalent definition comes from the restriction that for an ENOB-bit
A
converter, the maximum error has to be lower than one LSB voltage: VLSB = ENOB , as
2
stated in [23].
Therefore, it is crucial to balance thermal and quantization noise properly in order to
arrive at a power efficient design. On one hand, the quantization noise depends on the order of
the modulator’s loop filter, as well on the number of cycles N ; Higher order loop filter shapes
the quantization noise more aggressively, leading to lower number of cycles N for a target
ENOB, considering only quantization noise. This seems beneficial, as operating for fewer
cycles means lower conversion time and apparently lower energy per conversion. On the other
hand, thermal noise exhibited by the integrators of the loop filter manifests itself as variance
of the decimated output, but its highly attenuated, thanks to oversampling and noise shaping:
The input-referred noise power of the first integrator is suppressed by a factor of N , while the
input-referred noise of the second integrator is suppressed by a factor N 2 and so on [12]. Thus,
in a proper design, since N  1, thermal noise is typically dominated by the noise of the first
integrator and the variance of the decimated output, considering only thermal noise, is equal
with the input-referred noise power of the first integrator attenuated approximately by a factor
N . It is evident that by operating for higher number of cycles, averaging attenuates thermal
noise and this could be exploited in order to relax the specification of the input-referred
noise of the first integrator. Also, since lowering input-referred noise power of an integrator

Georgios Karykis Master of Science Thesis

2-2 Noise and linearity performance as function of Number of cycles N 11

2
vn,in,IN T is associated with higher power consumption, it seems beneficial to exploit the
2
trade-off between N and vn,in,IN T in order to arrive in an optimal design in terms of power
efficiency. Therefore, it is suggested to achieve a ratio of 50% : 50% between the two noise
sources, although most often thermal noise is slightly dominant [24].
In order to quantify the noise performance as a function of N , the minimum N that is
required in order to achieve a specific ENOB is estimated for first, second and third order
loop filter, taking into account only quantization noise. This is done, having as basis the
analysis presented in [23], where the following expressions for ENOB of an Incremental ∆Σ
ADC were derived.

• For a 1st order Incremental ∆Σ modulator: ENOB1 = log2 (N − 1) ' log2 N [23].
N · (N − 1)
• For a 2nd order Incremental ∆Σ modulator: ENOB2 = log2 (A · ) [23]. This
2!
is approximated by ENOB2 ' 2 · log2 N + log2 A − 1, where A is the normalized stable
input range of the modulator with respect to the reference voltage Vref , which in this
case is limited to 0.75. Thus, ENOB2 ' 2 · log2 N − 1.415.

• For a 3rd order Incremental ∆Σ modulator implemented with Cascaded Integrators,

N · (N − 1) · (N − 2)
Feed-forward structure (CIFF) [20] [21]: ENOB3 = log2 (A · bc1 c2 ),
3!
which is approximated by ENOB3 ' 3 · log2 N + log2 A + log2 (bc1 c2 ) − 2.6, where b, c1 , c2
are the scaling factors of the integrators of the loop filter. For this 3rd order modulator,
the normalized stable input range is limited to A = 0.67 and for practical values of
the scaling factors [23], ENOB3 ' 3 · log2 N − 6.6. These expressions are visualized in
Figure 2-3.

Furthermore, the decimated output variance due to thermal noise is dominated by the
input-referred noise of the first integrator, as the effect of noise in preceding stages is strongly
attenuated by the loop filter [17]. It was proven in [23] that the decimated output variance
2
as a function of input-referred thermal noise power of the first integrator Vn,in,IN T 1 is

2
Vn,in,IN
2 T1
Vn,out,thermal =k· (2-8)
N
4 9
where k is a constant depending on the modulator’s order and k = 1, , for 1st , 2nd and
3 5
3rd order modulators, respectively. Thus, a simple estimation of the ENOB, considering only
thermal noise can be done as
A
ENOBthermal = log2 ( s ) (2-9)
2
Vn,in,IN T1
k·
N
For example, the estimation of ENOBthermal is shown as a function of N in Figure 2-3,
along with the achievable ENOB in case only quantization noise is taken into account for the
two cases where the input-referred RMS noise of the integrator is Vn,in,IN T 1 = 100µV and
Vn,in,IN T 1 = 400µV .

Master of Science Thesis Georgios Karykis

12 System-level overview of Incremental ∆Σ ADC and description of previous prototype

30
q−noise ENOB of 1st order modulator
q−noise ENOB of 2nd order modulator
25
q−noise ENOB of 3rd order modulator
thermal noise ENOB for Vn,INT=100uV

20 thermal noise ENOB for Vn,INT=400uV

ENOB (bits)

15

10

−5
4 8 16 32 64 128 256 512 1024 2048
Number of cycles (N)

Figure 2-3: ENOB as a function of N considering only quantization noise or only thermal
noise.

In Figure 2-3 the trade-off between quantization and thermal noise is clearly shown. Since
the achievable ENOB, is always below the lowest of the two curves, for a specific value of N ,
ENOB is limited either by quantization noise (low N ) or by thermal noise (high N ). Since
2
Vn,in,IN T 1 is determining the height (but not the slope) of the estimation of ENOBthermal , an
2
optimal design is established for the combination of N and Vn,in,IN T 1 for which the target
ENOB is met, under minimum power consumption. A more accurate approach, is to estimate
using MATLAB simulation the quantization noise power σq2 of a modulator and the decimated
2
output thermal noise power Vout,thermal and then calculate the ENOB based on the (2-7), using
q
δrms = 2
Vout,thermal + σq2 . (2-10)

The value of δrms is in essence the output-referred noise of the ADC, which is equal to its
input-referred noise.
The achievable linearity of the Incremental ∆Σ ADC that is using a single-bit quantiza-
tion is not suffering from the non-linearity induced by the feedback DAC and is, essentially,
limited by the signal-dependent input-referred error of the first integrator [12]. Thanks to
the noise shaping of the loop-filter, the contribution of the succeeding integrators is highly
suppressed [17]. In an OTA-based design, the signal dependency of the input-referred error
of the integrator comes from settling error, slewing and finite DC gain of the OTA and DC
gain variation with the output swing. Specifically, OTA’s finite DC gain and gain variation
are a recognized as the most critical error sources [11] [12]. In any case, the input-referred
error of the integrator has to be designed carefully in order to achieve the target linearity.

Georgios Karykis Master of Science Thesis

 2-3 Description of the first prototype of self-timed I∆Σ ADC 13

2-3 Description of the first prototype of self-timed I∆Σ ADC

2-3-1 Top-level description and self timed operation

The first prototype of self-timed Incremental ∆Σ ADC [1] was employing a second-order
modulator with input feed-forward path, which is shown in Figure 2-2 operating for N = 500.
The most important merit of this topology is that the first integrator only processes quantiza-
tion error (no signal component) and thus its output swing is stabilized and limited (around
0.3V)[25]. As a result, the design of the first integrator regarding its linearity performance is
relaxed, due its lower output swing.
The two integrators of the modulator are operating in a ping-pong fashion; while the
one integrator is sampling, the other one is integrating, and vice versa. The most important
building block is the zero-crossing-based SC integrator, whose basic operating principle was
briefly described in Chapter 1. A block diagram of the modulator used in [1], which employs
two Zero-crossing based integrators and a clocked comparator is shown in Figure 2-4. In this
implementation, the feedback signal of the second integrator is applied during the sampling
phase Φ2 of the integrator, while for the first integrator during its charge-transfer phase Φ2 .
This choice was preferred as this scheme doesn’t increase power consumption and doesn’t
introduce extra kT /C noise at the input of the first integrator.

Φ2d CFF

RST RST
Φ1d
Φ2 CI1 Φ1 CI2 VCM

Φ1d
Φ1d CS1 VX1 VO1 Φ2d CS2 VX2 VO2
Vin
CFB bs
ZCD ZCD
BS Φ1 Φ1d Φ2
Φ2 BS
Φ2 Evaluation
VREFP VREFN VREFP VREFN
1st Integrator 2nd Integrator

Figure 2-4: Block diagram of the self-timed I∆Σ modulator used in [1].

As was already pointed out in Chapter 1, the knowledge of the completion of the charge
transfer process is inherently available, in the operation of a ZCB integrator. Based on this
knowledge, an asynchronous controller can be built in order to control the sampling and
charge-transfer phases of the two cascaded half-delay integrators, i.e. generate the two non-
overlapping clock signals Φ1 and Φ2 (and the delayed versions of them), under the assumption
that the duration of the sampling phase is never exceeding the charge-transfer phase. In this
case, this event-based controller is a simple asynchronous state machine with two states (Φ1
and Φ2 ), which are triggered by each other by the completion signals of the charge transfer.
This process is illustrated in Figure 2-5.

Master of Science Thesis Georgios Karykis

14 System-level overview of Incremental ∆Σ ADC and description of previous prototype

Completion2

Φ2, Φ2d N cycles Φ1, Φ1d

State-A State-B
Done Completion1 Start

Figure 2-5: Asynchronous state machine for the generation of the self-timed clock signals
[25].

As a result, the timing of one conversion is as follows: Initially, the ADC is powered
down waiting for a startup control signal that triggers the conversion. Once the startup pulse
is present, reset of the two integration capacitors CI1 and CI2 is performed and after the reset
pulse the state machine gets in Φ1 state. In this state, the first integrator is sampling the
input signal and the second integrator is performing charge transfer. Once the charge transfer
of the second integrator is completed, the state machine is triggered by the completion signal
to Φ2 , when the first integrator is performing charge transfer and the second is sampling
the output of the first. When the first integrator is completing the charge transfer, Φ1 state
is triggered again and this process continues for a predefined number of cycles N of the
modulator. The completion of the conversion is detected by keeping track of the number of
performed cycles and comparing with N . Upon the completion of the conversion, the state
machine is generating a control signal (Done) and the modulator powers down.

2-3-2 ZCB SC integrator: Coarse-fine charge transfer mechanism

As briefly introduced in Chapter 1, the Zero-crossing based switched-capacitor integrator is

the most important building block of the self-timed ADC. Therefore, it is crucial to recognize
and mitigate the non-idealities of the integrator, in order to achieve the needed accuracy
of integration. The static accuracy of the ZCB integrator is dominated by the overshoot
at the virtual ground node VX , due to the finite response time of the ZCD. The constant
part of the overshoot results to offset, which is most often (to some extent) tolerable, while
the signal-dependent component creates non-linearity. Specifically, the overshoot at VX is
proportional to the delay time of the ZCD and the magnitude of the charging current source.
Moreover, if the integration is needed to be faster, the ramp-rate will be necessarily steeper,
leading to a larger error. It is, therefore, straightforward that a coarse-fine charging scheme
is necessary in order to decouple accuracy from speed and enhance the accuracy of ZCB
integrator. In principle, this coarse-fine scheme can take the form of either bi-directional [2]
or uni-directional charge transfer [7], as can be seen in Figure 2-6. In [1] the uni-directional
charge transfer scheme was implemented, because of its advantages over the bi-directional
scheme, that will become clear from the following analysis of the operation of both schemes.

The operation of both alternatives of ZCB SC integrators’ charge transfer (Φ2 ) begins
with a short preset phase (P ), when the output node is shorted to VDD . Thus, the initial

Georgios Karykis Master of Science Thesis

2-3 Description of the first prototype of self-timed I∆Σ ADC 15

Φ2 CI

Φ1d CS E2
P
Vin IF Φ2d
VX D
Vout
Φ2d Φ1 E1 VO CL
IC
Φ2
(a) ZCD integrator with bi-directional charge transfer scheme
Φ2 CI

Φ1d CS
P
Vin D Φ2d
VX Vout
Φ2d Φ1 De E1 E2 VO CL
IC IF
Φ2
(b) ZCD integrator with uni-directional charge transfer scheme
VO VO
VDD VDD
Settled
Settled
Output
Output

VSS VSS
t t
VX VX
VDD VDD
VX0 VX0 Final
Overshoot
Vearly
Final
VCM Overshoot
VCM
Coarse Phase Saved time
Overshoot
VSS VSS
t t
Φ1 Φ1
Φ2 Φ2
P P
E1 E1
E2 E2
D D
De
(c) Waveforms of bi-directional charge transfer (d) Waveforms of uni-directional charge transfer

Figure 2-6: Dual-rate ZCB integrator implementation alternatives.

Master of Science Thesis Georgios Karykis

16 System-level overview of Incremental ∆Σ ADC and description of previous prototype

condition of VX , due to charge conservation, is

(VDD − VIN )CS + ( 32 VDD − VO 0 )CI
VX0 = (2-11)
CS + CI
where (VIN − VCM ) · CS is the sampled input charge during the sampling phase (Φ1 ). The
preset level of VX depends on the sampled charge and the integrated charge of the previous
cycle (VO0 − VCM ) · CI , and, in order to ensure correct operation, VX0 needs to be higher
than VCM . This condition limits input and output swings, as the condition VX0 ≥ VCM is
VIN − VCM CI
equivalent to 0 > . Right after preset phase, the coarse charge transfer phase
VDD − VO CS
follows, while the nodes VO and VX ramp down rapidly, as can be seen in the waveforms of
Figure 2-6.
The difference between the two alternatives is the strategy for switching from coarse to
fine phase. For the bi-directional scheme, the coarse surrent source is active, until the ZCD
detects the virtual ground VX = VCM , when the coarse current source is switched-off. Since
the ZCD has a finite response time, there is coarse phase overshoot on VX , which is then
corrected by turning-on the fine current source IF , which has opposite polarity and much
lower magnitude than IC . During the fine charge transfer phase, the nodes VO and VX ramp
up, with relatively low ramp rate, until the ZCD detects again the virtual ground. Because,
IF  IC the final overshoot is relatively low.
In contrast, the uni-directional scheme is based on the concept of early-threshold detec-
tion, so is based on the assumption that the ZCD is capable of detecting also the crossing
of (another) slightly higher level than VCM , Vearly . Upon the level crossing of Vearly , the
transition from coarse to fine phase is triggered, by switching-off IC . During fine phase, IF
which has the same polarity with IC , ramps down VO and VX until the moment that the
virtual ground is detected. At the moment of the virtual ground detection, IF is switched-off
and the charge transfer is completed. In both cases, the coarse and fine phase duration are
signal dependent.
As a result, the uni-directional charge transfer scheme is inherently capable of achieving
similar virtual ground accuracy with the bi-directional scheme, while operating for shorter
time, because of the gradual reach of the virtual ground, instead of recovering from a po-
tentially large overshoot. Moreover, the energy consumption is lower, because the successive
charging and discharging of the capacitive network is avoided.

2-3-3 ZCB integrator: Correlated level shifting

So far, in the analysis of the ZCB integrator, we are dealing with ideal current sources and
ZCD and therefore, there is no mechanism that is creating a signal dependent component
on the overshoot of VX has been identified. In reality, for example, current sources have
finite output impedance, leading to variation of the ramp rate. Consequently, the fine phase
overshoot of the ZCB integrator will be signal dependent, due to the ramp-rate variation
of fine phase, even if ZCD has constant delay. Furthermore, the ZCD is a continuous time
comparator, whose response time is ramp rate dependent [2]. These two effects have been
recognized to limit the linearity of the ZCB integrator [25][8], leading to the conclusion that
in order to minimize the signal-dependent error the signal dependency of the current IF has
to be minimized and the delay of the ZCD has to be minimized and stabilized.

Georgios Karykis Master of Science Thesis

 2-3 Description of the first prototype of self-timed I∆Σ ADC 17

Φ2 CI VO

Φ1d CS
P P||E1
Vin D CCLS Φ2d
VX Vout
Vfine
Φ2d Φ1 De E1 E2 CL
IC IF
Φ2

(a) Uni-directional ZCB SC integrator with Correlated level shifting

VO / Vfine
VDD
Settled
Output

VSS
t
VX
VDD
VX0 Final
Overshoot
Vearly
VCM
Saved time

VSS
t
Φ1
Φ2
P
E1
E2
D
De
(b) Waveforms of uni-directional charge transfer with CLS

Figure 2-7: ZCB integrator employing Correlated level shifting.

Master of Science Thesis Georgios Karykis

18 System-level overview of Incremental ∆Σ ADC and description of previous prototype

The current source induced non-linearity of zero-crossing based circuits, can be effectively
reduced by utilizing the correlated level-shifting (CLS) technique, as introduced in [26]. The
essence of this technique is the removal of the dependence of the swing of the fine current
source from the output voltage of the integrator, by capacitively coupling the output of the
current source with VO , using a level-shifting capacitor CCLS , as shown in Figure 2-7. When
CLS is adopted in ZCB circuits, the operation is not altered and the operation of the ZCB
integrator with uni-directional charge transfer of Figure 2-6 is visualized in Figure 2-7. During
preset, both the output node VO and the fine current source output node Vf ine are pulled
to VDD . Next, during the coarse charge transfer phase (E1 ), VO is ramping down, while
Vf ine remains shorted with the supply until the beginning of the fine phase. During the fine
phase (E2 ), VO and Vf ine are slowly ramping down until the virtual ground is detected by
the ZCD. Because, the ramp rate during the fine phase is relatively low, the swing of the fine
current source is very small. Interestingly, Vf ine follows the same waveform in every cycle,
which is independent of the output voltage of the integrator. Moreover, the swing of Vf ine is
exactly the same (assuming constant ZCD delay), under the assumption that the coarse phase
overshoot is signal-independent. This leads to stabilization of fine charging current waveform
in every cycle (independent of VO ), which results to absolutely constant final overshoot at
VX . However, the exact swing of the fine current source is a function of the ZCD delay as
well, which is slightly ramp-rate dependent in practice. As a result, the delay of the ZCD
should be designed to be signal-independent and this is possible in practice by minimizing
the ramp-rate variation during the fine phase.
Furthermore, the limited swing of Vf ine which is always close to VDD is creating the
possibility to utilize well-known transistor-level design techniques that increase the output
impedance of a current source but need larger voltage headroom, for instance use a cascode
current source. The utilization of correlated level shifting in a ZCB SC integrator is greatly
beneficial and almost cost-free, as the only penalty that is is associated with it is the slightly
increased power consumption and timing overhead during the coarse charging phase due to
the increased load.This is happening because CCLS is appearing as extra load at the output
of the integrator during the coarse phase.

2-3-4 Circuit-level implementation details

In order to complete the overview of the first prototype of self-timed Incremental ∆Σ ADC
[1], a brief summary of the circuit level implementation of the critical blocks of the ZCB SC
integrator is presented. Here, the gated current sources and zero-crossing detector imple-
mentation are briefly discussed and their designed parameters are outlined. Also, the design
choices regarding the capacitors and sizing of the switches of the ZCD integrator are complet-
ing this overview. The effect of these design choices in the performance of ZCB integrator is
not tackled here, but will be made clear with the analysis that is following in Chapter 3.
First of all, the coarse current source is implemented with a single transistor, as can
be seen in Figure 2-8, biased with a simple current mirror. The unit element sizing was
1µm/10µm, biased to conduct approximately 100nA and the coarse current is programmable,
as k = {10, 20, 30, ...50} unit elements can operate in parallel. The coarse current varies thus
from IC = 1µA to IC = 5µA and its output impedance was simulated to be Rout,coarse =
800M Ω at low frequencies. The fine current source is implemented with a cascoded transis-
tor current source, sized as shown in Figure 2-8, biased as such to conduct approximately

Georgios Karykis Master of Science Thesis

2-3 Description of the first prototype of self-timed I∆Σ ADC 19

IF = 100nA. The output impedance of the fine current source was simulated to be ap-
proximately Rout,f ine = 38GΩ at low frequencies. The gating of both current sources was
implemented with a series switch, as this solution provides the fastest switching among all
alternatives [8].

VDD

VO
P||E1
CCLS E2

E1 VFB2 2/0.5

VCB 1/10 × k VFB1 1/10

Coarse CS Fine CS
Figure 2-8: Gated current sources implementation in [1].

Next, the Zero-crossing detector, being a continuous time comparator, was implemented
with a cascade of a low-noise autozeroed inverter-based preamplifier followed by a wideband
crossing detector, as visualized in Figure 2-9(a). Auto-zeroing was utilized primarily to control
the common mode voltage of the inverter preamp, but also because of the immunity to supply
noise that is provided and attenuation of the flicker noise. The preamplifier is autozeroed
during the sampling phase of the ZCB integrator, specifically during the fine charge transfer
phase of the other ZCB integrator. Furthermore, the early-threshold detection capability was
implemented, by level-shifting the output voltage of the preamplifier Vint , by means of a series
level-shifting capacitor Cof f , that is precharged accordingly (to Vof f ) during the preset phase
of the ZCB integrator, as can be seen in Figure 2-9(b). The generation of Vof f was done
on-chip using a simple diode voltage reference, but also can be provided off-chip. Finally, the
ZCD parts are powered down, using current starving switches, during the periods in time in
which they are not necessary, in order to save power.
The design parameters of the ZCD that are critical for the noise and linearity performance
are the maximum transconductance of the preamplifier (gm,tot ), preamp’s time constant (τ ),
the preamplifier’s response time during the fine phase (tI ) and the band-limiting capacitor of
the preamplifier, which is used to control its response time and time constant. Last but not
least, the current consumption of the preamplifier is of great interest. These parameters are
summarized for both integrators of the modulator in Table 2-1.
Finally, the capacitor values in the implementation of both ZCB integrators are summa-
rized in Table 2-2. Also, the switches were implemented by a single NMOS transistor, except
from the modulator’s PMOS feedback switches controlled by bs and the minimum length
(0.16µm) was used for all. The designed widths of all switches of both integrators was 0.8µm,
except from the modulator’s feedback switches and the switches close to virtual ground of the
integrators towards the integration capacitor. The latters’ width was 0.4µm, while the NMOS

Master of Science Thesis Georgios Karykis

20 System-level overview of Incremental ∆Σ ADC and description of previous prototype

ΦAZ

Wide-band
crossing detector
Φ2 19/0.5
Vramp CΑΖ Vint
D
VCM VX VG
ΦAZ 5/0.5 Clim
Φ2
EN

Auto-zeroed Inverter P

Preamplifier -
Voff
Coff
De
P

Φ2

(a) Schematic of the ZCD, employing AZ inverter-based preamp

Φ1
Φ2 P E1 E2
ΦAZ
EN
VDD

Vint VC

GND
(b) Waveforms of operation of AZ inverter preamplifier

Figure 2-9: Circuit diagram and operation of the ZCD in [1].

feedback switches were 1.2µm and PMOS feedback switches 2.4µm wide. The driving voltage
of switches (except from feedback switches) was boosted to around 1.85V (higher than supply
voltage VDD ), using clock boosters. The on-resistance of the 0.8µm switches was simulated
to be Ron = 1.2kΩ, the on-resistance of the 0.4µm switch was Ron = 2.1kΩ. For the feedback
switches, Ron,N M OS = 800Ω and Ron,P M OS = 890Ω.

Georgios Karykis Master of Science Thesis

2-4 Summary 21

Table 2-1: Design parameters of the inverter-based preamplifiers of the ZCDs in [1]

Parameters 1st Integrator 2nd Integrator

Peak bias current I0 9.03µA 2.75µA
Maximum transconductance gm,tot 135µA/V × 2 40µA/V × 2
Time constant τ 75ns 75ns
Response time tI 65ns 50ns
Band-limit capacitor Clim 200fF 55fF

Table 2-2: Capacitor values used in ZCB integrators in [1]

Capacitor 1st Integrator 2nd Integrator

Sampling capacitor CS 500fF 200fF
Integration capacitor CI 2pF 400fF
Correlated level shifting capacitor CCLS 400fF 400fF
Feedback capacitor CF B — 200fF
Feed-forward capacitor CF F — 200fF

2-4 Summary

This chapter started with a short presentation of the system-level considerations in the design
of an Incremental ADC, examining noise and linearity. Next, the design techniques that
were utilized in the previous design, such as the use of a uni-directional coarse-fine charge
transfer and correlated level-shifting and design choices, including the implementation of
current sources and ZCDs were briefly reviewed. The impact of all the aforementioned design
choices on the performance of the ZCB SC integrator will be examined in Chapter 3, where
all the performance trade-offs in the design of the ZCB integrator will be revealed.

Master of Science Thesis Georgios Karykis

22 System-level overview of Incremental ∆Σ ADC and description of previous prototype

Georgios Karykis Master of Science Thesis

 Chapter 3

Noise and linearity analysis of ZCB

SC integrator with CLS

The purpose of this chapter is the analysis of the noise and linearity of a ZCB SC integrator
with CLS. After an overview of the behavior of the ZCD with ramp inputs, the noise of the
ZCB integrator is presented, including all the apparent noise contributors, followed by an
estimation of the input-referred noise of the previous design [1] based on the developed noise
model. Next, the circuit-level non-idealities of the ZCB integrator that harm its linearity
performance are described, including an estimation of their contribution to the total input-
referred signal-dependent error of the ZCB integrator. The presented noise and linearity
analyses are similar to the analyses of a CBSC gain stage presented in [2] and [27] and is
expanding the analysis of the ZCB SC integrator described in [25], taking into account more
circuit-level non-idealities and phenomena.

3-1 Closer overview of ZCD response to ramp input

The first step of the analysis of the ZCB integrator is the description of the response of the
ZCD to ramp inputs and the recognition of the error sources of the charge transfer process.
For convenience, the schematic of the ZCB integrator with CLS of Figure 2-7 is repeated in
Figure 3-1 and the underlying signals in its ramp response are shown in Figure 3-3.
The ZCD of Figure 3-1 is a continuous time comparator, consisting of a cascade of a
low-noise autozeroed inverter preamplifier loaded by a bandlimiting capacitor Clim and a
wideband crossing detector stage, as noted in section 2-3-4. The inverter-based preamplifier
can be modeled by an ideal transconductance amplifier, as can be seen in Figure 3-2.
The output response of the preamp fed by a step ramp input with ramp-rate M
(VX = M · t · u(t)) is
 
Vint (t) = M · A0 t − τ 1 − e−t/τ


u(t) [2] (3-1)

Master of Science Thesis Georgios Karykis

 24 Noise and linearity analysis of ZCB SC integrator with CLS

Φ2 CI VO

Φ1d CS
P P||E1
Vin D CCLS Φ2d
VX Vout
Vfine
E1 E2 CL
Φ2d Φ1 De
IC IF
Φ2

Figure 3-1: ZCB integrator employing Correlated level shifting.

Vint

VIN gmnVIN gmpVIN ron rop Clim

Figure 3-2: AZ Inverter-based preamp small-signal model during charge transfer phase.

where A0 = (gmn + gmp ) · (ron k rop ) is DC gain of the preamplifier and τ is the preamp’s
output time constant τ = (ron k rop ) · Clim .
The response of the ZCD is visualized in Figure 3-3 for a uni-directional charge transfer
process.
Right after preset phase both coarse and fine current sources are turned on and VX is
ramping down with ramp-rate
CI IC + IF CI
MX,coarse = MO,coarse · = · . (3-2)
CS + CI CL + CCLS + CI k CS CS + CI
The crossing of the early threshold Vearly is detected by the ZCD after a small delay td,coarse
and the coarse current source is switched off. The coarse phase overshoot at VX (from Vearly )
equal to VX,OV,coarse = MX,coarse · td,coarse . Then, VX is continuing the ramp roll-off with
much lower rate
CI IF CI
MX,f ine = MO,f ine · = · . (3-3)
CS + CI CL + CI k CS CS + CI

and the preamplifier’s output Vint is rising according to (3-1), as shown in Figure 3-3. The
output of the preamplifier is reaching the inverter’s common mode voltage VC with delay ti ,
after VX crosses VCM , which is the moment when the input of the inverter VG is crossing
VC due to autozeroing. This time ti that the output of the preamplifier takes to reach the
threshold VC is defined as the preamplifier’s response time. Because the wideband crossing
detector is not responding instantaneously, there is a small delay tc (after ti ), until the de-
tection of the zero-crossing by the ZCD (rise of output D). With the rise of D, the fine
current source is switching off with delay td = ti + tc after the zero-crossing at VX , creating a

Georgios Karykis Master of Science Thesis

3-1 Closer overview of ZCD response to ramp input 25

Φ1
Φ2 P E1 E2
ΦAZ
EN
VDD
VX0

VX Vearly
VCM

GND
VDD

Vint VC

ti
GND

D
tc
De
td

Figure 3-3: Waveforms of ZCD during charge transfer phase.

fine-phase overshoot at VX equal to VX,OV,f ine = MX,f ine · td . In the previous, the most often
negligible delay of the digital control circuitry was not taken into consideration. The values
of gmn , gmp , ron and rop are varying with VX in the implementation with inverter preamp,
but even in case they were constant it is impossible to solve (3-1) analytically to obtain an
exact expression for the response delay ti . In [28] the limiting behavior was considered in two
extremes: when ti  τ , where the preamplifier is considered as an ideal gm C integrator and
when ti  τ , where the preamplifier is operating in steady state. The preamplifier’s response
time in these two extremes is
VC 1


 · , for ti  τ (3-4)
X,f ine · gm,tot ron k rop
 M

ti =
 2 · VC · Clim

 , for ti  τ (3-5)
MX,f ine · gm,tot


where gm,tot = gmn + gmp . The preamplifier’s response delay and output time constant are
key parameters for the noise design of the ZCD preamp as will be revealed in subsection 3-2-2.

Master of Science Thesis Georgios Karykis

26 Noise and linearity analysis of ZCB SC integrator with CLS

It is greatly important to note that since the modulator is operating on sampled data
of integrators, only the error of the integrated voltage at the end of the charge transfer is
important. Specifically, the noise power of the discrete-time integrated voltage at CI is of
interest, as far the noise performance is concerned. The input-referred noise power of the
integrator will then be the noise power across the sampling capacitor due to sampling process
(i.e. the well-understood kT /CS ) added to the to the noise power referred to the virtual
ground node VX at the end of the charge transfer. The latter component is equivalent to
noise power across the sampling capacitor CS at the end of the charge transfer phase [29].
As far as the static error is concerned, the input-referred error of the integrator is dominated
by the final overshoot at node VX , under the assumption that there is nothing adding error
charge to CI from the output side [2]. The overshoot at VX , can be seen as equivalent to
finite and non-linear open-loop gain of an OTA, in conventional OTA-based implementations
of switched-capacitor integrators [28].

3-2 Noise analysis of the ZCB integrator

3-2-1 Non steady-state noise analysis

Because of the transient nature of ZCB circuits, the conventional steady-state noise analysis
is not appropriate. For example, during the fine phase, variation of the charging current IF
due to noise, results in a random walk of the voltages across the capacitors of the feedback
network of ZCB integrator of Figure 3-1, leading to noise that is growing larger with time.
Also, the preamplifier of the ZCD does not necessarily reach steady-state (for ti  τ ), before
its output reaches the threshold VC . In other words, the statistical properties of the noise
are varying with time (non-stationary process) and the often-used noise analysis techniques
based on the root-mean-square (RMS) value of noise cannot be used to quantify the noise
behavior during an individual cycle.
However, the noise performance in this case can be analyzed in time-domain, as proposed
in [28], using the auto-correlation function between the underlying non-stationary random
processes to estimate their variance. It was also pointed out that even though the statistics
of the noise voltages and currents are non-stationary during each cycle, the same operation is
performed each clock cycle and the underlying signals are periodically sampled. As a result,
the sampled signals have the same statistics each clock cycle, forming a wide-sense stationary
(WSS) discrete time series. This property is called wide-sense cyclo-stationarity (WSCS)[30].
This observation led to the development of a periodic filtering frequency domain model in
[28] that facilitates the frequency domain analysis of ZCB circuits. Finally, it was also proven
and demonstrated in [28] that well-known noise aliasing techniques can be applied to obtain
a noise power spectral density (PSD) for the series of samples.
Based on the findings in [28] and [27], a design-oriented estimation of noise in the ZCB
integrator can be performed, following a similar approach with [29].

3-2-2 Apparent noise contributors

For the of estimation of the input-referred noise of the ZCB integrator, noise contributions
from both the sampling and charge transfer phases have to be added in power, as discussed

Georgios Karykis Master of Science Thesis

3-2 Noise analysis of the ZCB integrator 27

in section 3-1. The apparent noise contributors of the charge transfer process are the pream-
plifier’s thermal and flicker noise, thermal noise of the switches, thermal and flicker noise of
the fine current source and noise due to autozeroing. The total input-referred noise power of
the ZCB integrator will be
2
Vn,in,IN 2 2 2 2 2
T = Vn,CS ,sampling + Vn,in,ZCD + Vn,VX ,switches + Vn,VX ,IF + Vn,VX ,AZ (3-6)

2
where Vn,in,ZCD 2
is the total input-referred noise of the ZCD and Vn,V 2
and Vn,V are
X ,switches X ,IF
the noise powers of switches and IF referred to the virtual ground node VX . The estimation
of all these apparent noise contributors will be outlined, based on the methodology that was
introduced in [27], providing design guidelines for the suppression of all contributors and
the impact on power consumption. It is noteworthy that the proper balance of all these
contributors is of great importance in order to achieve low-noise operation under high power
efficiency.

Noise of the sampling phase

A fundamental limitation of noise performance of the integrator is the sampling noise during
the phase Φ1 , when the input of the integrator is sampled on CS . The noise behavior of
this sampling process is well-understood [31] and similar to OTA-based designs, the noise
2
power is Vn,C = kT /CS , where k is the Boltzmann’s constant and T is the absolute
S ,sampling
temperature. The only way to suppress this contributor is to use larger sampling capacitor
CS , an option that increases the power consumption of the integrator.

Input-referred noise of the ZCD

The noise contribution of the ZCD has been recognized as the most critical in the design of
ZCB circuits [2]. Noise at the output of the ZCD will influence the moment of virtual-ground
detection, which is equivalent to jitter on the ZCD delay. If the ZCD is modeled with an input-
referred noise voltage source, the threshold level is appearing noisy, resulting in variation of
the moment that the ZCD detects the threshold crossing. This is again equivalent to jitter
on the ZCD delay and input-referred noise power can be calculated based on the assumption
that the generated jitter power is exactly the same in both cases. This argument is visualized
in Figure 3-4.
Since the ZCD is composed of a cascade of a band-limiting preamplifier and a wide-band
crossing detector (as shown in Figure 2-9), the noise of second stage is suppressed by the gain
of the preamp and can be neglected. The thermal noise of the transconductance amplifier can
be modeled with an output current PSD of Sn,o = 4kT Gn , where Gn is the equivalent output
noise conductance. In case of the inverter-based preamp SI,o = 4kT γgm,tot and γ = 2/3, thus

8
SI,o = kT (gmn + gmp ). (3-7)
3
The variance of the output voltage of the preamplifier can be calculated according to [27] as
Z t
1
σV2n,V (t) = · SI,o · h(a)da (3-8)
int 2 0

Master of Science Thesis Georgios Karykis

28 Noise and linearity analysis of ZCB SC integrator with CLS

Jitter
VX
gm Clim D
VCM

(a) Noisy preamp results in ZCD jitter at output threshold crossing

Jitter
VX
gm Clim D

Vn,ZCD

VCM
(b) Noiseless preamp with input referred noise results in the same jitter at the input threshold crossing

Figure 3-4: ZCD noise modelling.

where SI,o is the preamplifier’s noise single-sided PSD and h(t) is the impulse response from
the noise source to the output of the preamp, which in case of the transconductance preamp
1 −t/τ
is h(t) = e . The resulting time-variant output noise power of the preamplifier is then
Clim
kT
σV2n,V (t) = Gn RO [1 − e−2t/τ ]u(t) (3-9)
int Clim
where RO is the output resistance of the preamp.
The conversion of noise voltages to timing jitter happens when a threshold detector is
sensing a noisy signal [30]. The output-referred noise voltage of the preamp results in jitter,
through the rate of change of Vint . The variance of threshold crossing time is then
−2
dVint (t)

σt2i = σV2n,V (ti ) · (3-10)
int dt Vint =VC

2
For the input-referred noise of the ZCD Vn,in,ZCD the equivalent jitter power is calculated as
−2
dVX (t)

σt2i = 2
Vn,in,ZCD · (3-11)
dt VX =VCM

Consequently, the equivalent input-referred noise, that is resulting to the same time jitter
power with the output-referred noise of the preamp is
σV2n,V (ti )
2
Vn,in,ZCD = int
(3-12)
2
AN (ti )

where AN is the noise gain which is a function of the response time ti of the preamp
! !
dVint (t) dVX (t)
AN (ti ) = (3-13)
dt t=ti dt t=ti

Georgios Karykis Master of Science Thesis

3-2 Noise analysis of the ZCB integrator 29

Taking into account when VX is a ramp with a ramp rate M , Vint is described by (3-1), the
noise gain can be calculated [27]

AN (ti ) = A0 1 − e−ti /τ u(ti )

(3-14)

According to (3-12), (3-9) and (3-14) the equivalent input-referred noise power the ZCD will
become
1 ti
 
2
Vn,in,ZCD = 4kT RN · coth u(ti ) (3-15)
4τ 2τ

where 4kT RN is the input-referred noise PSD of the preamplifier with RN = Gn /gm,tot2 the
input-referred noise resistance of the preamplifier. The second part of (3-15) is the non-
stationary effective noise bandwidth of the preamp N BW (ti , τ ). The function of effective
noise bandwidth is visualized for practical values of ti and τ in Figure 3-5. The noise power

100
ti = 40ns
ti = 55ns
ti = 70ns
ti = 85ns
steady-state NBW:1/4τ ti = 100ns
Effective NBW (MHz)

ti = 115ns
ti = 130ns
ti = 145ns
ti = 160ns
10 ti = 175ns

Integrator NBW: 1/2ti

1
0 20 40 60 80 100 120 140 160 180 200
Preamplifier output time constant (ns)

Figure 3-5: Effective noise bandwidth as function of ti and τ .

2
Vn,in,ZCD is representing broadband noise, but since we are dealing with a sampled-data
system, the noise contributor is subject to noise aliasing. Thus, the input-referred thermal
N BW (ti , τ )
noise PSD of the ZCD then needs to be scaled with [29], where fs is the average1
fs /2
sampling frequency of the SC integrator. However, the input-referred noise power of the ZCD
remains equal to (3-15).

It is interesting to observe the limiting behavior of equivalent noise bandwidth at the

1
The charge transfer duration of the integrators is signal dependent. For a first order estimation, the
average sampling frequency should be used, which is derived by transient simulation of the ZCB integrator.

Master of Science Thesis Georgios Karykis

30 Noise and linearity analysis of ZCB SC integrator with CLS

graphs of Figure 3-5:

1


 , for ti  2τ (3-16)
4τ

N BW (ti , τ ) = 1
, for ti  2τ (3-17)



2ti
where (3-16) is the noise bandwidth of the preamp that is operating in steady-state, while
(3-17) is the noise bandwidth of an ideal gmC integrator. Apart from the behavior at the
extremes, it is noteworthy to notice that allowing the preamplifier to operate with higher
response time ti , in order to have more time to do noise averaging, the NBW and the input-
referred noise of the ZCD are lower. The penalties that are associated with higher ti are
larger input-referred error of the ZCB integrator and higher power consumption.
In order to illustrate the power consumption trade-off, the current consumption and
the output Vint of the inverter preamplifier are plotted in Figure 3-6 along the entire charge
transfer. The inherent adaptive biasing of the inverter is clearly illustrated here, as the current
consumption is observed to be maximum around the threshold crossing instant, exactly when
the gm,tot is needed to be maximum. Also, during ti the inverter preamp is conducting
approximately its maximum current, which is determined by the designed transconductance
gm,tot and the gm /Id ratio of the transistors [32]. Since the input-referred noise of the ZCD
depends on N BW (ti , τ ) and gm,tot , these two parameters have to be designed properly so
2
that the target Vn,in,ZCD is met under the lowest power consumption. This means that first
of all the transconductance efficiency gm /Id of the transistors should be as high as possible
and that the combination of ti and gm,tot should be optimized.
Furthermore, the noise performance of the ZCD is typically suffering from 1/f (flicker)
noise [31] exhibited by the transistors of the preamp. The input-referred 1/f single-sided
K
PSD of a transistor is S1/f (f ) = [31], where K is a process-dependent parameter
COX W Lf
and COX is the oxide capacitance per unit area, leaving the area of the transistor W · L the
only design variable. Interestingly, in case of the autozeroed preamplifier, the 1/f noise is not
contributing to the input-referred noise of the ZCD, as autozeroing is acting as a high-pass
filter on 1/f noise, with cut-off frequency equal to the frequency at which autozeroing is
performed fAZ [33]. As a result, as far as 1/f corner frequency is lower than fAZ , the 1/f
noise contributor should be neglected.

Input-referred noise due to switches

During the charge-transfer phase, there are four switches along the feedback capacitive net-
work of the integrator that are conducting, exhibiting thermal noise, due to their finite on-
1
resistance Ron = ,where K 0 is a process-dependent parameter, W L is the designed
W
K 0 Vod
L
switch dimension and Vod is the transistor overdrive voltage. The equivalent circuit can be
seen in Figure 3-7. Thermal noise from these switches results in two noise contributors dur-
ing the charge transfer phase. The first one is noise at the virtual ground node during the
preamplifier’s response time, while the second is noise across the integration capacitor CI at
the sampling moment of the output of the integrator. These two noise contributors have the
same source, but are uncorrelated as they occur in different time instants.

Georgios Karykis Master of Science Thesis

3-2 Noise analysis of the ZCB integrator 31

VDD
VX0

VX Vearly
VCM

GND
VDD

Vint VC

ti
GND

Ipeak
Preamp Current

Preset Coarse Fine Idle Auto-

phase phase Zeroing

Figure 3-6: Current consumption and voltage response of inverter preamp during charge
transfer.

Ron2 CI

CS Ron3
D
VX
CL
Ron1 De
VCM Ron4

Vref
GCS with CLS

Figure 3-7: Noise due to switch on-resistance during charge transfer of ZCB integrator.

Examining the noise during the preamp’s response, the switch and capacitor network is
exhibiting an equivalent white noise PSD at the virtual ground node VX equal to

SR,n,eq = 4kT · Rn,eq , (3-18)

Master of Science Thesis Georgios Karykis

32 Noise and linearity analysis of ZCB SC integrator with CLS

with
2 2
CS CS + CI k CS
 
Rn,eq = Ron2 + Ron1 · + (Ron3 + Ron4 ) · (3-19)
CS + CI k CL CS + CI k CS + CL
The noise from switches at VX is filtered by the preamplifier in a similar manner with the
input-referred thermal noise of the preamp, resulting in jitter in ZCD decision with exactly
the same noise-bandwidth N BW (ti , τ ). Also, similar to the input-referred thermal noise of
the ZCD, the noise of switches during preamp’s response is subjet to noise aliasing and its
N BW (ti , τ )
broadband noise power spectral density has to be scaled with . As a result, the
fs /2
input-referred noise power due to switches during preamp’s response
2
Vn,in,switches−resp,sampl = 4kT · Rn,eq · N BW (ti , τ ) (3-20)
Also, this noise contributor is equivalent to the switch noise during the charge transfer of
conventional OTA-based SC integrators [29], where the OTA bandwidth is filtering the switch
noise. Ways to lower this contributor are to reduce the on-resistance of the switches, by using
wider devices in order to lower the noise resistance at VX , Rn,eq of (3-19) and also design for
lower the effective noise bandwidth N BW (ti , τ ). The strategy of lowering Rn,eq is effective,
especially establishing Rn,eq < Rn but it may degrade the linearity of the integrator if we
exaggerate, due to stronger charge injection and clock feed-through, as will explained in
subsection 3-3-1.
When the preamplifier’s output reaches VC , the wideband-crossing detector trips, with a
small delay tc , as shown in Figure 3-3. During tc , the preamp is not filtering the switch noise
anymore and the feedback switch capacitor network is open-loop. Thus, the switch noise
results in kT /C noise sampled onto the capacitors. We are primarily interested in the noise
across CI , as noise across CL is appearing as output-referred noise of the ZCB integrator,
that is heavily suppressed thanks to noise shaping of the modulator. Also, noise across CS
is not of interest, as it doesn’t contribute to the integrated noise voltage. The kT /C noise
across CI is the kT /C noise of Ceq = CS k CI k CL , through the capacitive divider from Ceq
to the integration capacitance CI . Therefore, the input-referred contributor will be

2  2
kT CS k CL CI

2
Vn,in,switches−sampl = · · (3-21)
Ceq CS k CL + CI CS
This contributor, along with the sampling phase kT /CS noise and thermal noise due to
fine current source (that will be quantified soon) is practically posing a limit on the mini-
mum capacitances that need to be used in ZCB integrator. The energy consumption asso-
ciated with the swing of the output voltage of the integrator VO after the preset phase is
Eswing = CT · (VDD − Vswing ), where CT = CL + CCLS + CI k CS is the output capacitance.
In the first prototype, CT = 1pF and the output swing is from 0.35V to 0.65V. An estimation
of the average energy consumption for an integrator can be made using the average output
voltage as Eswing = 1pF · 0.5V = 0.125pJ/cycle, and the energy per conversion for the 1st
integrator of [1] is 500 · Eswing = 60pJ/conv..
Finally, the total input referred noise contributor of switch noise during the charge trans-
fer of the ZCD integrator will be the sum of the two uncorrelated noise contributors
2
Vn,V 2
= Vn,in,switches−resp 2
+ Vn,in,switches−sampl (3-22)
X ,switches

Georgios Karykis Master of Science Thesis

3-2 Noise analysis of the ZCB integrator 33

Input-referred noise of fine current source

Another noise contributor of the charge transfer process is the noise of the fine current souce
IF , which is meaningful only after the preamplifier’s input threshold crossing instant. Noise
before this moment only affects the duration of the charge transfer, but does not result in
error on the integrated charge. The noise contribution of IF consists of the random walk on
integrator’s feedback capacitive network during two independent time intervals: the preamp’s
response time ti and during the threshold detection delay tc .
During preamp’s response time ti , the preamplifier is filtering the random walk on the
capacitive network, resulting in jitter in ZCD decision which is negatively correlated with the
jitter due to preamplifier’s output noise, as analyzed in [28]. Based on the analysis employing
the periodic filtering model in [27] which was directly applied also in [8], the input-referred
noise power during ti for white current source noise with power spectral density SIF (0) is
2
SIF (0) CI

2
Vn,in,I = · ti (3-23)
F /ti 2
Cout CS + CI
where Cout = CL + CS k CI . Similarly, the input-referred noise power during tc is
2
SIF (0) CI

2
Vn,in,I = · tc (3-24)
F /tc 2
Cout CS + CI
As a result, the total input-referred noise due to the fine current source will be the sum of
the previous two uncorrelated contributors, and thus
2
SIF (0) CI

2
Vn,in,I 2
= Vn,in,I 2
+ Vn,in,I = · (ti + tc ) (3-25)
F F /tc F /tc 2
Cout CS + CI
The above expressions are for a preamplifier that is operating as an ideal integrator (ti  τ ),
as in this case the noise power is maximized and the jitter correlation is minimum. This
was adopted because it provides a worst case estimate of the noise due to IF , as can be
understood from the analysis in [27]. The noise power from the current source is proportional
to ti , therefore low SIF (0) is required if ti is designed to be large. The thermal noise PSD
of IF , SIF (0), can be lowered by biasing the current source with lower gm , thus lowering the
charging current level. Also, for given ti and SIF (0), the noise due to IF can be effectively
decreased by increasing Cout . In order to keep the same speed of charge transfer, the required
fine current has to linearly increase with Cout , while the input-referred noise is dropping with
2 .
Cout

Input-referred noise due to auto-zeroing

Auto-zeroing is an effective way to attenuate the flicker noise of the preamplifier that is seen
in Figure 2-9, but sampling noise of this process is contributing to the overall input-referred
noise of the ZCB integrator. The sampled noise across the auto-zeroing capacitor CAZ can be
seen as noise of the threshold of the ZCD, which directly leads to noise across the sampling
capacitor CS at the end of the charge transfer process. This auto-zeroing noise is not filtered
by the preamplifier and the input-referred noise power is
2 kT
Vn,VX ,AZ
= (3-26)
CAZ + Clim

Master of Science Thesis Georgios Karykis

34 Noise and linearity analysis of ZCB SC integrator with CLS

As it is evident when inspecting (3-26), this contributor is depending only on the capaci-
tance levels of CAZ and Clim and doesn’t pose any significant restriction in terms of power
consumption.

3-2-3 Estimation of noise performance of the first prototype

Making use of the previous analysis of the apparent noise contributors, the total input-
referred noise powers of the first ZCB integrator, as well as, the ADC of [1] can be estimated.
Calculating the noise power of the individual contributors based on the design choices of [1]
the total input-referred noise voltage of the integrator is estimated to be vn,in,IN T 1 = 199.8µV
while the effective noise-bandwidth is N BW = 8.2M Hz. In this estimation, the thermal noise
due to switches during preamp’s response was found to be dominant, followed by the thermal
noise contributor of the ZCD preamp.
Using MATLAB simulation to estimate the quantization error of the modulator (Figure 2-
2) for N = 500, the quantization error range was found to be approximately Qr = 18µV .
The equivalent quantization noise standard deviation, assuming that the error is uniformly
Qr
distributed within its range will be σq = √ [16]. Since, this uniformity assumption is quite
12
far from reality and the quantization error appears busier close its the borders the σq is higher
and a 30-50% scaling should be adopted. Thus, taking 30% margin, the σq becomes

Qr
σq = √ · 1.3 = 5.196µV (3-27)
12

The estimation of the total input-referred RMS noise of the ADC, according to (2-10)
and (2-8) for k = 4/3, taking into account only the intrinsic noise of the first integrator, will
be s
2
4 vn,in,IN T1
vn,in,ADC = σq2 + · . (3-28)
3 N
This is resulting to vn,in,ADC = 12.33µV . This value is quite far from the input-referred noise
of the ADC reported in [1]. Possible reasons for this, besides the presence of an unmodelled
contributor, are an artifact of the measurement setup or the effect of supply noise.

3-3 Linearity analysis of the ZCB integrator with CLS

3-3-1 Non-linear error due to switches

Unlike OTA-based switched-capacitor circuits, which settle to steady-state during the charge-
transfer phase, current is still flowing through the switches of ZCB circuits at the instant the
output voltage is sampled. Output-dependent variations in the voltage drop across these
switches, whether from variations in switch on-resistance or current, lead to errors in the
integrated voltage of the ZCB integrator.
Referring to Figure 3-7, IR drop across the on-resistances Ron2 , Ron3 and Ron4 will
only create error on the sampled output voltage VO and not across the integration capacitor

Georgios Karykis Master of Science Thesis

3-3 Linearity analysis of the ZCB integrator with CLS 35

CI [34]. Because this error is not integrated each cycle, but appears only at the output of
the integrator, it is heavily suppressed by the noise-shaping of the modulator and hardly
contributes to the total input-referred error. In contrast, voltage drop across Ron1 is creating
CS CS k CI
error on the integrated voltage equal to − · Ron1 · IF . As a result, the
CI CL + CS k CI
input-referred error is
CS k CI
Vin,err−sw = −Ron1 · IF · (3-29)
CL + CS k CI
with its constant part leading to offset and its signal-dependent part creating non-linearity.
In context of the ∆Σ modulator, the switch with on-resistance Ron1 is representing the
feedback connection of the 1st integrator that is applied during the charge-transfer phase,
as shown in Figure 2-4. The feedback connection is implemented with the top-plate of CS
switched between the positive and the negative reference voltages, via an PMOS and a NMOS
unboosted switch respectively.

Ron,pmos Φ2 CI
- +
VREFP
CS Φ2d
Feedback D
VX
-
CL
+
VREFN De
Φ2
Ron,nmos VCM

GCS with CLS

Figure 3-8: Feedback switches on-resistance induced error.

Due to inherent systematic mismatch between NMOS and PMOS switches, a voltage
dependent error is created due to the IR drop across these switches, according to (3-29), with
Ron1 to take the value of Ron,nmos or Ron,pmos depending on the feedback signal, as shown
in Figure 3-8. Hopefully, if the variation of IF is assumed negligible, the mismatch between
Ron,nmos and Ron,pmos is leading to a slight (but constant) change of the reference voltages
from their ideal values, which leads to small system-level gain error of the ADC, which is
tolerable. Besides, for finite variation of IF , the variance of the voltage drops across the
feedback switches from the baseline value is creating non-linearity. The most effective way
to limit the non-linear error is to lower the on-resistance of these switches by increasing their
W
L and trying to achieve equal relatively voltage drop variances for the NMOS and PMOS
switches with respect to the whole output range of the ZCB integrator.
Other switch non-idealities that harm the accuracy of both the sampling phase and
introduce error on the integration capacitor CI at the end of the charge transfer phase are
clock feedthrough and charge injection. To be specific, the switches at the two ends of CI
introduce error charge on CI at the sampling instant. Also, the accuracy of sampled input
on CS is degraded, contributing to offset and non-linearity. Assuming a total switch gate
capacitance CG , the charge being fed through from the switch (distributed to source, drain

Master of Science Thesis Georgios Karykis

36 Noise and linearity analysis of ZCB SC integrator with CLS

and substrate) is given by

Qclkf eedthrough = CG · Vdrive (3-30)
where Vdrive is the gate driving voltage. The switch gate capacitance is proportional to oxide
capacitance per unit area (COX ) and the switch area W · L. Regarding charge injection, the
total charge in the channel of a switch that is conducting can be approximated as

Qchannel = COX · W L · (VGS − VT H ) = COX · W L · (Vdrive − VS − VT H ) (3-31)

A common approximation is that half of the charge is distributed to source and drain respec-
tively [35]. However, as the impedance on each side of the switch is different and the clock
fall time is finite, this is not entirely correct. Both equations above show that the switch area
must be minimized to reduce the non-idealities due to switching. In order to entirely remove
the signal dependent part of the charge injection, Vdrive − VS must not be dependent on the
source voltage of the switch, something which is achievable by switch bootstrapping [16] or
by introducing dummy switches [31]. The latter options that was not considered, as it turned
out that the errors caused by these two mechanisms were not very significant.

3-3-2 Non-linear error due to ramp-rate variation

The finite response time of the ZCD, in combination with the ramp-rate variation due to
signal dependency of IF create signal dependency of the overshoot voltage at VX from VCM .
This overshoot voltage is equal to the error voltage that is integrated on CI every cycle and
is not suppressed by the noise shaping of the modulator. If the time delay between the
zero-crossing instant and the turn-off moment of the fine current source is denoted as td , the
overshoot at VX can be expressed mathematically as
Z td Z td
IF (t) CI
VX,OV = MX,f ine (t) · dt = · · dt (3-32)
0 0 CL + CS k CI CS + CI
If IF (t) was constant, the overshoot would be constant and the integrator would be perfectly
linear, suffering only from finite offset equal to +VX,OV . In actual implementation, both
the charging current sources have finite output impedance due to channel-length modulation
effect of MOSFETs [31] and assuming Rout,f ine is the output impedance of IF the fine current
will be
Vf ine
 
IF = IF 0 · 1 + (3-33)
Rout,F
with IF 0 representing the baseline current and Vf ine the swing of the current source. Rout,f ine
is depending on the actual implementation and biasing of the current source, as well as, on
the level of the charging current. As the coefficient λ of channel length modulation slightly
varies with the VDS voltage of the transistor, Rout,f ine is expected to slightly vary with Vf ine .
Considering the ZCB integrator, without employing correlated level shifting, the swing of the
fine current source is identical with the output swing of the integrator and the possible ways to
enhance accuracy are to increase Rout,F or limit the swing of VO . However, increasing Rout,F is
tricky in this case because with supply voltage of around 1V , the biasing of a cascode current
source that can operate with Vmin = 0.35V is not a straightforward task, if not impossible.
Hopefully, when utilizing correlated level shifting, as described in subsection 2-3-3, the
swing of the fine current source is limited and in ideal case is independent of the swing of VO ,

Georgios Karykis Master of Science Thesis

3-3 Linearity analysis of the ZCB integrator with CLS 37

giving the opportunity to introduce a cascode fine current source. Thus, the overshoot VX,OV
is stabilized also, because of the identical trajectory of Vf ine in every integration cycle. This
stabilizes the waveform of IF in every cycle making it signal independent in ideal case with
constant coarse phase overshoot. The residue signal dependency of Vf ine and correspondingly
of IF will be due to the variance of the final point of Vf ine trajectory of Figure 2-7, caused
by the signal-dependent coarse phase overshoot on VO , due to finite coarse current source
output impedance. Based on the analysis of the ZCB integrator with CLS done in [34] and
[25], assuming a coarse current source with baseline current IC0 , output impedance Rout,C
and coarse phase ZCD delay of td,coarse , the fine current at the end of the charge transfer is

−1
td,coarse VO Rout,C · CCLS

IF = IF 0 − · IC0 − [25] (3-34)
Rout,F · CCLS Rout,F td,coarse
Under the assumption td,coarse is not signal dependent, the VO -dependent part of IF is
−1
VO Rout,C · CCLS

IF,var = [25] (3-35)
Rout,F td,coarse

and the effective output impedance of the fine current source with CLS has boosted now to

Rout,C · CCLS
 
Rout,F,eq = Rout,F [25] (3-36)
td,coarse

In order to estimate the non-linearity of the ADC caused by fine phase ramp-rate varia-
tion, the overshoot of (3-32) can be estimated, for a constant delay td = 75ns and assuming
IF to take its extreme values during the whole td , predicted by (3-34). This assumption is
corresponding to a worst-case scenario for the signal-dependency of IF . This procedure leads
to an estimated range of VX,OV (i.e. input-referred signal-dependent error range) for an out-
put swing from 0.35V to 0.65V of less than 2µV . This input-referred signal-dependent error
variance is rather small and in any case is not expected to be the dominant non-linear effect
of a ∆Σ modulator with INL at the level of 1LSB w.r.t. 14bit. The previous estimation was
done using the circuit-level parameters noted in subsection 2-3-4, under the worst-case as-
sumption that td,coarse is varying by ±20% from its baseline value of 10ns. Of course, td is by
any means constant, as it is modulated by the ramp-rate of VX , causing excess non-linearity
in the overshoot voltage. Furthermore, for a uni-directional charging scheme, regardless the
polarity of VO , both even and odd harmonics are expected to be present in VX,OV , even in
fully-differential realizations.

3-3-3 Non-linear error caused by turn-off transients of current sources

Besides switch and ramp-rate variation, the off-transients of both coarse and fine current
sources induce non-linear charge on CI at the end of the charge transfer. The coarse current
source current during its off-transient, contributes to the coarse phase overshoot on VO which
in turn, affects the swing of the fine current source creating variability on the fine current.
Regarding the fine current source, while it is turning off, it introduces error charge to the
feedback capacitive network, with the error charge across CI to be of importance. The
constant part of this error charge is leading to offset, but the signal-dependent part creates

Master of Science Thesis Georgios Karykis

38 Noise and linearity analysis of ZCB SC integrator with CLS

non-linearity that cannot be corrected. This error contributor is hard to analyze and the most
efficient design strategy is to quantify its importance using transient simulation. The output
current of the current sources can be monitored and ultimately, the integrated charge across
CI in each cycle (having a small constant input of the ZCB integrator) in order to observe
the overall signal dependency.

3-4 Summary

In this chapter, the noise and linearity analysis of a ZCB SC integrator with CLS have
been presented. After a short introduction on the behavior of the ZCD with ramp inputs, a
design-oriented estimation of input-referred noise of ZCB integrator was presented, including
all the apparent noise contributors, such as the thermal noise of switches, the fine current
source and ZCD thermal noise, which has been recognized as the most critical one. Based
on this analysis, the total noise of the first integrator of the first prototype was estimated.
Furthermore, apparent circuit non-idealities, like the finite on-resistance of switches, that lead
to linearity degradation of ZCB SC integrator were explored. The ramp-rate variation, which
is widely recognized as the dominant non-linear effect, turned out to be much less significant,
when correlated level-shifting is utilized, to effectively stabilize IF across the output swing of
the integrator.

Georgios Karykis Master of Science Thesis

 Chapter 4

Noise and linearity measurement

results of the first prototype

4-1 Existing Measurement setup

For the performance characterization of the first prototype self-timed ADC, a measurement
setup has been built [25], whose a block diagram can be seen in Figure 4-1. This setup was

VREFP
Regulator

VCM

ADC
On-board Analog Buffer under
VREFN
Reference Generation test

IIN
VIN
KEITHLEY
VIN
Input voltage generation
& measure-back
Phase Handshake

Bitstream & Clock

Configuration
GPIB

Digital Aquisition
& Control OSC

PC
USB
Matlab Labview DAQ FPGA

Figure 4-1: Block diagram of the measurement setup of the first prototype [25].

Master of Science Thesis Georgios Karykis

40 Noise and linearity measurement results of the first prototype

based on an NI M-series Data acquisition device (DAQ) and an Altera Cyclone-IV E-series
FPGA was used to implement the off-chip part of the control logic (cycle counting and Φ1 /Φ2
asynchronous generation). The performance critical parts of the setup are the input voltage
(VIN ) and ADC reference voltage (VREF P and VREF N ) generation. The input voltage was
generated using a precision Keithley-2400 current source meter [36], feeding a shunt on-board
resistor (' 120Ω). The reference was generated using an on-board LDO, the LP38511-ADJ
[37] from Texas Instruments.

4-2 Noise measurement

The noise characterization of the ADC involves the measurement of the sample-to-sample
standard deviation of the decimated output, δrms for a number of consecutive conversions
keeping the input voltage constant. The δrms represents the output-referred RMS noise of
the ADC and the resolution (ENOB) of the ADC can be derived by (2-7).
Inspecting the datasheet of LP38511-ADJ [37], it can be concluded that the noise PSD
of the reference is suffering from flicker noise at low-frequencies, that are in-band for the
measurement. Thus, even the input was completely noise-free, the measured noise of the
ADC would be degraded by the noise of the reference. When providing the input of the
ADC using a voltage divider between VREF P and VREF N , using the so-called ratiometric
measurement approach, the noise of input and reference are fully correlated and thus the
noise measurement gets more accurate. Following this approach, the resolution of the first
prototype was measured as a function of incremental cycles N , performing 100 conversions
at a single input point. The results of this measurement are shown in Figure 4-2.

17

16

15
ENOB (bit)

14

13

12

11

10
1 2 3 4
10 10 10 10
Number of cycles N

Figure 4-2: Measurement result of the first prototype for the resolution (ENOB) as a
function of N .

Specifically, for N = 500, the input-referred RMS noise was measured to be 14.3µV , that,
according to (2-7), is equivalent, to ENOB=15.4bits with respect to a stable input range of

Georgios Karykis Master of Science Thesis

4-3 Linearity measurement 41

0.7V . This measurement result is in quite close agreement with the analytical estimation of
the input-referred RMS noise of the ADC that was done based on the analysis of Chapter 3,
that resulted to an estimated input-referred noise of 12.33µV . This agreement is a sign of
validity of the noise analysis and the utilization of the developed noise model is expected to
be useful in the design of an improved self-timed ADC.

4-3 Linearity measurement

The measurement of linearity is involving DC sweep of the input voltage (provided by

Keithley-2400 source meter), measurement of the decimated output and plot the ADC trans-
fer function (decimated output versus the input voltage). After this, the integral non-linearity
(INL) of the ADC, can be obtained by calibrating out offset and gain error from this plot,
calculating the deviation of each point from the best-fitting straight line. In order to suppress
noise in the linearity measurement, the number of incremental cycles should be maximized
and multiple decimated output samples per input voltage are averaged. Furthermore, for
enhanced accuracy, the input DC voltage of the ADC is measured back by the source-meter
in a 4-wire configuration [36] for each input step (Figure 4-1).

Even when taking all these noise suppression measures, the INL results of the ADC were
not reproducible, which is a clear indication that the measurement setup is suffering from
noise. The possible noise sources are ground noise, noise from Keithley-2400 that affects the
input of the ADC or noise of the reference voltage VREF P that is generated from the reference
LDO. Using the voltage meter of Keithley-2400, it was possible to inspect the stability of input
voltage of the ADC and VREF P in order to trace the dominant noise source. It was observed
that Keithley-2400 is capable to provide a very precise and low-noise current, which generates
an accurate enough input voltage for the ADC. However, the VREF P was measured to be very
noisy with respect the accuracy that was targeted to measure.

Fortunately, in the existing measurement setup, there was a possibility of using an exter-
nal reference voltage. Also, a precision voltage source was available, the Yokogawa GS200 [38]
that was measured to be capable of generating a stable and accurate enough reference voltage.
Making use of this, an accurate linearity measurement was possible and the measured INL of
the ADC is plotted in Figure 4-3. The measured INL was within -0.7LSB to 0.6LSB, relative
to a 14-bit output code.

In order to show the repeatability of the linearity measurement, the INL plots of 5
consecutive measurements are plotted in Figure 4-4, along with the INL plot of Figure 4-3. It
was observed that the measurement was still not noise-free, but the fixes of the measurement
setup that were performed were enough in order to reveal the actual linearity pattern of the
previous design.

Finally, in order to illustrate the sample-to-sample variation of the linearity measurement,

the INL plots of 3 consecutive measurements of another sample (with larger steps of input
voltage) are shown in Figure 4-5, along with the INL plot of Figure 4-3. Interestingly, the
same pattern of INL is observed in this experiment as well.

Master of Science Thesis Georgios Karykis

42 Noise and linearity measurement results of the first prototype

0.6

0.4

0.2
INL (LSB wrt 14bit)

−0.2

−0.4

−0.6

−0.8
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Input voltage (V)

Figure 4-3: Measurement result of the INL of the first prototype [1].

0.6
0.2

0.4
0.1

0.68 0.69 0.7

0.2
INL (LSB wrt 14bit)

-0.2

-0.4

-0.6

-0.8
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Input voltage (V)

Figure 4-4: Measurement results of the INL of the first prototype of 6 consecutive runs.

4-4 Performance summary

The performance of the first prototype self-timed ∆Σ ADC is now summarized in Table 4-1.
In order to be able to compare with other ADCs and get a feeling of the energy-efficiency,
the two most-often used figures of merits (FOM) for the comparison of ADCs should be used.

Georgios Karykis Master of Science Thesis

4-4 Performance summary 43

0.8

0.6

0.4

0.2
INL (LSB wrt 14bit)

-0.2

-0.4

-0.6

-0.8
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Input voltage (V)

Figure 4-5: Measurement of the sample-to-sample variation of the INL of the first prototype
[1].

Table 4-1: Updated Performance Summary of the first prototype [1]

Specification Performance
Technology NXP 0.16µm 1P6M CMOS
Active Chip Area (mm2 ) 0.45
Supply Voltage (V) 1
Analog: 10
Supply Current (µA)
Digital: 9.8
Conversion Time (ms) < 0.75
Stable Input Range (V) 0.15 - 0.85
Input-Referred RMS Noise (µV) 14.3
SNR (dB) 84.76
†
INL (LSB) -0.7 - 0.6
FOMW (pJ/conversion-step) 1.05
FOMS (dB) 163.04
†
Relative to a 14-bit output code.

The first one is the Walden FOM,

P ower · Tconv
F OMW = [pJ/conversion − step] (4-1)
2(SN R−1.76)/6.02

Master of Science Thesis Georgios Karykis

44 Noise and linearity measurement results of the first prototype

where for the Incremental ADC the Nyquist-rate bandwidth is replaced by with the inverse
of the convesion time Tconv . In the previous expression, the signal-to-noise ratio SNR of the
ADC should be calculated as
Stable Input Range
SNR = 20 · log10 √ (4-2)
2 2 · Input Referred RMS Noise
√
In the expression for SNR, a crest-factor correction of 2 2 was included to take into account
the fact that the noise of the Incremental ADC is not characterized using an input full-scale
sinusoid. Besides, the second expression of FOM that is typically used in the comparison of
high resolution ADCs is the Schreier FOM [17]:
1 1
F OMS = SNR + 10 · log [dB] (4-3)
Power · Tconv
where again the Nyquist-rate bandwidth is replaced with the inverse of the conversion time
Tconv .

4-5 Summary

In this chapter, the measurement results for noise and linearity of the first prototype of self-
timed Incremental ∆Σ ADC have been presented. It was found that the noise performance
was superior, compared to the results reported in [1], which improves slightly the energy
efficiency of the previous design. On the other hand, the measured linearity was worse, but
in this case the measured INL plot was reproducible. Furthermore, the result of the noise
measurement is in close agreement with the estimation of noise performance that was done
in subsection 3-2-3, which proves the validity of the noise analysis presented before. This
agreement is extremely useful as a path is drawn for the improvement of the resolution of the
ADC in an energy-efficient way.
On the contrary, the linearity of the ADC was found to be slightly higher than 1 LSB with
respect to 14-bit codes, although it was expected to be much better according to the analysis of
the ramp-rate variation induced non-linearity. This means that the linearity analysis based on
the ramp-rate variation (ignoring the importance of the off-transients of the current sources)
fails to capture the dominant source of non-linearity, which poses difficulties in the design. It
apparent that another mechanism is creating non-linearity, with the off-transients of the fine
current source becoming a key suspect. Finally, the disagreement of the analytical estimation
with the measurement results suggests to follow a design procedure based on simulation of
the non-linearity, as the analytical estimation seems not very effective.

1
For thermal-noise dominated designs, DR ≈ SNR.

Georgios Karykis Master of Science Thesis

 Chapter 5

Design for improved self-timed ZCB

I∆Σ ADC

This chapter is primarily focusing on the design of the first integrator, as the most performance
critical component in the design of an improved self-timed I∆Σ ADC. Initially, the design
procedure of the entire ADC (focusing on the first integrator) is outlined. Then, the system-
level design considerations of the ADC are tackled, including modulator order and topology
and the architecture of the ZCB integrator that will be employed. Afterwards, the noise
and linearity design of the first integrator are described and finally, simulation results for
noise, linearity and power consumption of the first integrator that will be used to improve
the performance of the self-timed ADC are summarized.

5-1 Design procedure

Based on the knowledge that the noise and linearity performance of the entire I∆Σ ADC
vastly depend on the first integrator, the majority of the design efforts are focused on its
optimization. However, smart system-level design of the ADC and understanding of the
top-level trade-offs in the design will generate the opportunity of achieving the target specs
for improved noise and linearity with higher energy-efficiency. As a result, design-space
exploration is necessary in order to conclude on the modulator order, number of incremental
cycles N , noise allocation and architecture of the ZCB integrator. In this step, the noise
specification of the ZCB integrator is decided as well.
Following, the feasibility of use of a ZCB integrator topology starts with the estimation
of the achievable linearity. The best way to perform this is through simulation of the input-
referred error of the ZCB integrator. This is performed using transient simulation, where the
integrator is fed with a constant small input and is let to integrate for multiple cycles. The
integrated voltage across CI at the end of each cycle can be captured and after normalizing
the integration steps over their average value and scaling with the inverse of the integrator’s

Master of Science Thesis Georgios Karykis

46 Design for improved self-timed ZCB I∆Σ ADC

CI
constant the signal-dependent component of input-referred error of the integrator is then
CS
derived for the entire output swing. For instance, following this procedure, the integration
error of the first integrator of [1] was derived and visualized in Figure 5-1. In the same figure,
the simulation result for the INL of the previous design can also be seen. Using 8 input
voltage points, the INL was simulated to be approximately 0.8LSB with respect to 14bit.

0.5

Vin,err,norm (uV) 0.3

INL (LSB wrt 14bit)

22.85
0.1

0.35V -0.1
0.65V VO
-0.3
-22.85
-0.5
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Input voltage (V)
(a) (b)
Figure 5-1: Linearity simulation results for the first integrator in [1]: (a) Signal-dependent
component of input-referred error of the first integrator in [1], (b) Simulated INL of the first
prototype [1]

If we try to estimate the linearity of the ADC, based on the simulation of the input-
referred error of the first integrator (Figure 5-1(a)), following similar procedure with the
estimation of INL in OTA-based designs [12] we will end up with an estimation that is much
better compared to the simulated INL ((Figure 5-1(b)), because the non-linear component
of the error in Figure 5-1(a) is small compared to the error bounds. Interestingly, when an
approximation of this input-referred error pattern was used in a Matlab simulation of the
non-linearity, the resulting estimation of INL was around 0.3 LSB with respect to 14bit,
which is much better compared to the simulated INL (Figure 5-1(b)) and the measured INL
Figure 4-3 of the previous design [1]. Probably, this mismatch between the reality and the
estimation of the INL based on the simulated input-referred error of the integrator comes
from the inaccuracy of the simulated error. A possible reason for this is that in the context of
the modulator, the integrator is not working under the same conditions with the simulation
testbench, because is not operating with a small input voltage, but processes the entire input
range of the ADC. In this work, the simulated input-referred error was used as an indicator
of the linearity performance, based on the correspondence of the simulation results of the
previous design that are shown in Figure 5-1. All the design choices were judged based on
the behavior of the input-referred error and was concluded that the simulated input-referred
error needs to be suppressed in order to arrive to a design with better linearity.
Following this procedure for all the alternatives, the feasible options are short-listed and
the best candidate can be found. After this, if the linearity estimation of the examined
topology is close to the requirement, the integrator’s noise performance is tackled. First, the
target specification of the integrator’s input-referred noise should be estimated based on the
balance between q-noise and thermal noise and the number of incremental cycles N for a

Georgios Karykis Master of Science Thesis

5-2 System-level considerations 47

target noise performance of the ADC. Based on the analysis of section 3-2 the ZCB integrator
can be sized accordingly to meet the target specification taking a moderate design margin
into account. The noise design should be then verified through simulation with two feasible
simulation solutions for this task to be PSS/Pnoise simulation and transient noise simulation.
Then, the linearity design should be revisited again, taking the necessary measures to ensure
that the signal-dependent error is low enough to meet the linearity specification of the ADC.
The noise and linearity design are not independent of each other and typically iterations are
present in the design procedure.
After the design of the integrator is completed the ADC can be built and extensive
verification of the toplevel performance is mandatory. For the noise performance, a transient
noise simulation of multiple conversions using constant input voltage will give an estimation
of the ADC’s input-referred noise, calculating the point-to-point standard deviation of the
decimated outputs δrms . Regarding the linearity performance, an input sweep has to be
performed, using transient simulation. The INL of the ADC can then be estimated following
the same procedure with the linearity measurement of the ADC that described in section 4-3.

5-2 System-level considerations

5-2-1 Modulator order

The first step of the design process of an improved self-timed I∆Σ ADC is the decision of the
modulator order and architecture. Possible candidates for this implementation are a second-
order Boser-Wooley modulator with input feed-forward path (Figure 2-2) or an extension to a
third-order architecture (with both feed-forward (CIFF) and feed-back topologies (CIFB) [17]
to be considered). Between CIFF and CIFB, the CIFF architecture is in general preferred,
as the integrators of the loop-filter are processing only quantization noise, a fact that relaxes
the requirements from the first integrator [39] [40]. The final choice should be made with
respect to the optimization of the total energy consumption of the ZCD per conversion that
is needed in order to meet the target resolution (ENOB).
As presented in Chapter 1, the resolution specification for the improved self-timed ADC
is ENOB > 16.5bit. For the second-order modulator, with stable input range of A2 = 0.7V ,
according to (2-7), the input-referred RMS noise specification of the ADC that achieves
ENOB = 16.5bit is vn,in,ADC2 = 6.1µV . Similarly for a third-order modulator, assuming
operation under the maximum (theoretical) stable input range of A3 = 0.67V , the input-
referred RMS noise specification is vn,in,ADC3 = 5.85µV , according to (2-7). Furthermore,
from the analysis of subsection 2-2, the total input-referred noise of the ADC suffers from
quantization noise and intrinsic noise of the transistors, with the input-referred noise of the
first integrator to be assumed as the only intrinsic noise contributor for N  1, and thus
s
2
Vn,in,IN T1
vn,in,ADC = σq2 +k· (5-1)
N
with k = 4/3 for a second order modulator and k = 9/5 for a third order modulator. Following
the 40%:60% rule for the balance between quantization and thermal noise, we can estimate
σq for total input-referred noise of ADC of 6µV , resulting to σq = 3.8µV .

Master of Science Thesis Georgios Karykis

48 Design for improved self-timed ZCB I∆Σ ADC

Based on the previous calculation of σq , the number of incremental cycles N can be

estimated, making use of the EN OBq versus N plots of Figure 2-3, having as specification
ENOBq = 17.5bit which corresponds to the target value of σq = 3.8µV . The corresponding
approximate N was found to be N2 ' 1024 and N3 ' 256 for the 2nd and 3rd order modulators
respectively. For the two cases, the specification of the input-referred RMS noise of the first
ZCB integrator can be derived from
s
2

N
vn,in,IN T 1 = Vn,in,ADC − σq2 · (5-2)
k

and the calculated values are 128.8µV and 55.4µV respectively. These specifications compared
to the vn,in,IN T 1 ' 200µV of the first prototype that was operating for Ninit = 500, revealing
the need to suppress noise by a factor of 3.6 for a third-order design and a factor of 1.56 for
a second-order design.
In order to suppress the noise of the integrator, all the individual noise contributors should
be suppressed. To establish a first-order estimate of the power penalty we will round the noise
reduction factors to 4 and 2 respectively and consider only the noise of the preamplifier of the
ZCD, because it is the most critical block for the energy consumption of the ZCB integrator.
Also, if an inverter-based structure is employed to serve as a preamplifier, due to the inherent
dynamic biasing of the inverter, the ZCD power consumption is dominated by the current
that flows during the fine phase of the integrator and the current consumption of the preamp
during auto-zeroing. The fine phase current consumption and is consisting of

• Current consumption during the preamp’s response time ti (depending on the designed
gm
gm,tot and of the transistors and is proportional to ti )
Id
• Current consumption of the preamp before VX reaches virtual ground (depending on the
gm
designed gm,tot and of the transistors and the fine phase duration until VX reaches
Id
virtual ground).

Similarly, the current consumption during autozeroing is depending on the designed gm,tot
gm
and of the preamplifier’s transistors and is proportional to the autozeroing period.
Id
As analyzed in subsection 3-2-2, the input-referred noise of the ZCD can be lowered by
increasing gm or decreasing p
the effective N BW (ti , τ ). Specifically, the input-referred noise of
√
the ZCD is proportional to N BW (ti , τ ) and inversely-proportional to gm,tot . If we decide
not to alter N BW , gm,tot has to be scaled by 16× for the 3rd order modulator and 4× for
2nd order modulator to scale the noise contribution of ZCD to the desired levels. This means
that the energy consumption of a single cycle increases by 16× and 4× for the two cases, with
N3 N2
the overall energy consumption to scale with · 16× ' 8× and · 4× ' 8×. If we
Ninit Ninit
decide to keep gm the same and play only with N BW to meet the target noise specification
for the ZCB integrator, the N BW should be reduced by 16× and 4× for 3rd and 2nd order
case, respectively. For these requirements, according to (3-15), the designed ti and τ pairs
for the two cases should be ti = 1.04µs (16×) with τ > 1.06µs and ti = 260ns (4×) with
τ > 280ns. However, these options of ti = 260ns and ti = 1.04µs are not realistic, as they are

Georgios Karykis Master of Science Thesis

5-2 System-level considerations 49

associated with a large increase of duration of the charge transfer, degradation of the linearity
performance and probably unacceptable offset of the integrator. Besides, the increase of ti to
this level will make the noise design for the fine current source a hard task, posing the need
of use of a large CL which is not preferred.
On the other hand, a more realistic option is to operate with ti = 115ns (with τ > 130ns)
that leads to a decrease of the N BW by a factor of ' 2. In order to meet the noise specification
in the two cases, gm,tot is needed to be adjusted accordingly. This strategy will require 8×
increase in gm,tot for the 3rd order modulator and 2× increase for the 2nd order modulator.
Thus, considering the increase of energy consumption in one cycle, we should expect the
energy consumption of the fine phase before the virtual ground condition to increase by 8×,
while the energy consumption during preamp’s response increases by 16× and the energy
consumption of the autozeroing process increases by 8× for the case of 3rd order modulator.
Similarly, 2nd order modulator the single-cycle energy consumption scaling factors are 2×,
4× and 2× respectively. This will result to an increase of the overall energy consumption per
N3
conversion by slightly more than · 8× ' 4× for the 3rd order case and slightly more
Ninit
N2
than · 2× ' 4× for the 2nd order case.
Ninit
From this first-order estimation of the energy consumption scaling, we can conclude that
utilizing a higher-order modulator topology is not necessarily helpful in order to improve the
energy efficiency of a high resolution ZCB I∆Σ ADC. Of course, the noise allocation plays
very important role in the design, but the more relaxed vn,in,IN T 1 specification of the 2nd
order modulator, in combination with the way that the energy consumption scales make the
2nd order modulator more suitable candidate for improving the resolution and probably the
energy-efficiency of the self-timed ADC.
Furthermore, the argument of using a second order topology is reinforced further by
the presence of implementation difficulties in the design of a third-order modulator using
ZCB integrators. First of all, a feed-forward (CIFF) modulator topology seems the best
alternative, because of the lower sensitivity to integrators’ non-idealities and lower swing of
the first integrator. In a CIFF modulator, an analog adder is necessary before the quantizer,
which for for single-bit ∆Σ converters can be implemented passively using switched capacitors
[41]. In this case, a feed-through path is created between the first and third integrator outputs
because they are operating during the same clock phase. In OTA-based implementations, this
is not a problem as each OTA will force virtual ground at its input continuously. As the ZCB
integrators only detect when the virtual ground condition and then turn-off their current
source, it is evident that each integrator will turn-off at different times. As a result, while
one integrator gets in idle state after the completion of the charge transfer and the other is
still operating, the integrated voltage of the idle integrator will be corrupted by the other
integrator, harming the operation of the whole ADC. This issue is solvable in principle, but
proper operation dictates the use of more clock phases for the integrators with apparent
expenses in conversion time, digital circuit complexity and power consumption. On the other
hand, the feed-back (CIFB) topologies [17] do not suffer from this issue, as there is no feed-
forward path between the integrators, but the significantly larger output swing of the first
integrator [42] will make the linearity design of the first integrator tricky.
Consequently, because of the implementation difficulties of designing a 3rd order CIFF
modulator using ZCB integrators and the estimation that the utilization of a 3rd order modu-

Master of Science Thesis Georgios Karykis

50 Design for improved self-timed ZCB I∆Σ ADC

lator topology will not necessarily result to a more power efficient design of a higher resolution
self-timed ZCB ADC, a 2nd order ∆Σ modulator was decided to be used.

5-2-2 Matlab simulation of 2nd -order modulator with input-FF path

Once it is concluded that the extension to a third order modulator is hardly beneficial, the
reuse of the topology of Figure 2-1, that was used in [1], seems the most suitable option, mainly
because of the limited output swing of the first integrator. The second-order modulator with
input feed-forward path was simulated in Matlab, in order to obtain the output swings of the
two integrators and estimate the quantization noise for N = 1000. In Figure 5-2 the results
of this simulation are shown.

Quantization error vs. Input range

8
Quantization error(μV)

0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Input voltage (V)
Output swing of first integrator vs. Input range
1

0.8

0.6
W1 (V)
0.4

0.2

0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Input voltage (V)
Output swing of second integrator vs. Input range
1

0.8

0.6
W2 (V)
0.4

0.2

0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Input voltage (V)

Figure 5-2: Quantization noise and integrators’ swings for 2nd -order modulator with input
feed-forward path for N = 1000.

The swing of the first integrator was simulated to be limited to 300mV (from 0.35V to
0.65V), which will be really useful for the linearity design, because the simulated input-referred
error of the ZCB integrator was observed to increase rapidly as the output swing increases.
Also, an estimate of the quantization noise can be made, observing the quantization error
range, which was 4.4µV in worst case. If this quantization error was uniformly distributed
4.4µV
between its borders, the quantization noise standard deviation would be σq = √ =
12
1.27µV , but since it is observed busier close to the border, a margin around 30% should be
taken into account. Thus, the quantization noise standard deviation should be estimated

Georgios Karykis Master of Science Thesis

5-2 System-level considerations 51

after simulation as
4.4µV
σq = √ · 1.3 = 1.65µV (5-3)
12
This simulated value of σq is significantly lower than the theoretical value predicted by the
analysis in subsection 2-2. The reason for this is that the swing of w2 [N ] is much lower
than [−Vref , +Vref ] for the entire input range. This gives the opportunity to operate the
converter, with a balance between quantization and thermal noise higher than 60%:40%. By
allowing thermal noise to dominate, the specification of the input-referred noise of the first
integrator will be relaxed. For instance, in order to arrive to a design with ENOB = 16.8bit
(which corresponds to vn,in,ADC = 6.1µV ) with N = 1000, the specification of vn,in,IN T 1
becomes 160.8µV . This fact seems very beneficial and should be utilized in the design of a
higher-resolution self-timed ADC with improved energy-efficiency.

5-2-3 Design space exploration for the implementation of ZCB integrator

Fully-differential ZCB integrator

Until now, only the single-ended implementation of the ADC was taken into account. How-
ever, a fully differential implementation is generally preferred, because the signal range is
effectively√doubled with simultaneous increase of input-referred noise of an integrator by a
factor of 2. Thus, the SNR is inherently increased, creating the potential of reducing the
power consumption. Also, a fully-differential implementation is typically less susceptible to
power supply and ground noise and interference [31], while the effect of many non-idealities
during the charge-transfer of the ZCB integrator (e.g. switch IR drops and switching effects)
are in first-order cancelled by handling signals differentially.
Consequently, a fully-differential implementation of the ZCB integrator seemed very
promising and was realized, including all the performance-enhancement methods (correlated
level-shifting and uni-directional 2-phase charging scheme) that were used in [1]. Besides, a
Common-mode feedback (CMFB) mechanism is mandatory in this implementation and this
functionality was included. A circuit diagram of this integrator can be seen in Figure 5-3.
The operation of the fully-differential ZCB integrator is very similar with the single-
ended one with the difference that the signals in two brances are following complementary
trajectories. After preset, the positive output is ramping down, while the negative output is
ramping up, until the point that the early threshold condition is detected by the differential
ZCD, as visualized in Figure 5-4. Then, during the fine charging phase, the two branches
are settling with much lower ramp rates until the moment of virtual ground detection by the
ZCD.
In this implementation, two CMFB alternatives have been investigated: A conventional
switched-capacitor CMFB circuit [43] and a differential-difference amplifier (DDA) based
CMFB topology [44] (using a simple current-mirror OTA). In both cases, the CMFB signal is
controlling the gates of both coarse-fine charging NMOS current sources in order to stabilize
VDD
the output common-mode to . Both the alternatives were verified through simulation,
2
where it was observed that the the output common mode was effectively stabilized during the
coarse phase roll-off.

Master of Science Thesis Georgios Karykis

52 Design for improved self-timed ZCB I∆Σ ADC

PMOS coarse-fine current sources

E1 E2
IC CCLS IF
Vfinep
P P||E1

Φ1d CS VXp Φ2 CI Φ2d

Vinp Voutp
VOp
CL
Φ2d Φ1
D Φ2
VCMFB
CMFB
De
Φ2d Φ1
Φ1d CS Φ2 CI VOn Φ2d
Vinn Voutn
VXn
CL
P P||E1
CCLS Φ2
Vfinen
E1
IC IF E2

NMOS coarse-fine current sources

Figure 5-3: Circuit diagram of the fully-differential ZCB integrator with CMFB.

The first step towards the realization of a fully-differential ZCB integrator, before the
noise design, is the estimation of its non-linearity, following the procedure of simulation of the
signal-dependency of the input-referred error. In this step, it became clear that the realization
of the differential structure performing with linearity above 16bit is a hardly achievable task
within the timeframe of this project. The topology of Figure 5-3, was built using ideal
switches and capacitors and a Verilog-A [45] model for the ZCD (tunable delay). Operating
the ZCD without delay, the simulated range of the integration error across an output range
of [−0.3V, 0.3V ] was approximately 185µV which results to a signal-dependent input-referred
error range of 740µV , which has a significantly non-linear inverse-U shape. This is predicted
to lead to an achievable linearity for the ADC around the level of 11bit, which is far below
the target of this design.
A possible reason for the large signal-dependent error range that was observed in simula-
tion was the systematic mismatch between NMOS and PMOS current sources off-transients
at the end of fine phase. Although the output common-mode is effectively stabilized before
the turn-off of the coarse current sources, a large common-mode jump is observed at the
coarse current sources turn-off moment. This jump is heavily signal dependent and cannot
be corrected during the fine phase because of the small magnitude of fine currents. This
common-mode instability, however, is expected to be tolerable (and/or correctable) in the

Georgios Karykis Master of Science Thesis

5-2 System-level considerations 53

VO
VDD

Settled
output

VSS
VX t
VDD
VXn0 Final
Overshoot

VCM

VXp0
VSS
t
Φ1
Φ2
P
E1
E2
D
De

Figure 5-4: Signal waveforms of the fully-differential ZCB integrator during charge transfer.

context of a ∆Σ modulator, as it is expected to lead to common-mode error of the integra-

tor. In contrast, this heavily signal-dependent coarse phase overshoot at the output, that is
caused by the asymmetry off-transients of the NMOS-PMOS current sources is affecting the
swing of the fine current sources. This is expected to further contribute to the asymmetry
of the fine current sources off-transients. After this experiment, it was decided that a fully-
differential topology is hardly realizable within the timeframe of this project, because of the
high (simulated) signal-dependency of the input-referred error of the integrator.

Pseudo-differential ZCB integrator

Although, a fully-differential implementation seems not a realistic target for this project, a
pseudo-differential topology for the ZCB integrator is feasible, employing two single-ended
integrators for the two branches. A circuit diagram of the pseudo-differential alternative can
be seen in Figure 5-5. Since, there are only NMOS charging current sources, the non-linearity
issue of the differential integrator is not present anymore and the signal-dependent error of
the integrator can be brought to the desired level. The operation of the pseudo-differential
integrator is very similar to the single-ended one, as the two branches are operating indepen-

Master of Science Thesis Georgios Karykis

54 Design for improved self-timed ZCB I∆Σ ADC

Φ2 CI VOp

Φ1d CS
P P||E1
Vinp Dp CCLS Φ2d
VXp Voutp
Vfinep
CL
Φ2d Φ1 Dep E1p E2p
IC IF
Φ2

NMOS coarse-fine current sources

Φ2d Φ1
Φ1d CS
VXn P||E1 Φ2
Dn P
Vinn CCLS
Vfinen CL
Φ2d
Den E1n E2n
Voutn
IC IF

Φ2
CM
CI VOn
correction
Φ1 Φ2 VCM

Figure 5-5: Circuit diagram of the pseudo-differential ZCB integrator with CM correction.

dently and the only difference is that the output is sensed differentially. The underlying signals
during the charge-transfer phase are visualized in Figure 5-6. Also, in the pseudo-differential
topology there is no special need for common-mode control during the charge transfer phase,
as the mismatch between same type (NMOS) current sources is less severe compared to the
fully-differential integrator where different type of current sources (NMOS-PMOS) are used
in the two branches.
However, because of the fine phase overshoot at the end of the charge transfer, the
common-mode of VO and VX signals is gradually drifting downwards (common-mode error
accumulation) if we operate the integrator multiple times. This potentially harmful to the
correct operation in context of an incremental ADC and necessitates the use of a mechanism
that corrects the common-mode of the integrated voltage after the completion of the charge
transfer (i.e. during the next sampling phase of the integrator). This can be done using
small current sources that are pulling up the output nodes of both branches simultaneously
VDD
until the common-mode is reaching . This condition is sensed by an auxiliary low-
2
power comparator which is comparing the output common-mode (sensed using a capacitive
averaging) with the reference common-mode level VCM [8]. Because the magnitude of these
current sources is very small, the residual common-mode error is almost negligible. Following
this strategy, common-mode error accumulation is prevented, making the pseudo-differential
architecture a feasible alternative for the design of the self-timed I∆Σ ADC.
Considering the achievable performance using the pseudo-differential structure, the signal-
dependent integration error for output range between [-0.3V , 0.3V] is expected to be doubled
in worst case compared to the single-ended architecture, if we do not take into account the

Georgios Karykis Master of Science Thesis

5-2 System-level considerations 55

VOp VOn
VDD VDD

Settled
output

VSS VSS
VXp t VXn t
VDD VDD
VXp0 VXn0

VCM VCM

VSS VSS
t t
Φ1 Φ1
Φ2 Φ2
P P
E1p E1n
E2p E2n
Dp Dn
Dep Den

Figure 5-6: Signal waveforms of the pseudo-differential ZCB integrator during charge trans-
fer phase.

cancellation of second-order non-linearity. But, since the input signal range is doubled the
linearity of the ADC is not degraded even in this worst case estimation. This is making the
pseudo-differential alternative a competitive counterpart of the single-ended architecture, as
the potential of first-order cancellation of various non-idealities and elimination of second-
order non-linearity are present. √
Examining the noise behavior, the input-referred noise of the
pseudo-differential structure is 2× higher, thus the SN R is better. On the other hand, the
power consumption is effectively doubled, resulting to an energy-efficiency which is equal with
the single-ended implementation. Finally, because of great shortage in design time during this
project, it was decided not to implement the pseudo-differential ZCB integrator, although it
poses tangible benefits especially in the linearity behavior.

As a result, after examining all the possibilities related to the extension to a differential
implementation of the integrator, it was concluded that the most realistic alternative for this
project is to stay with the single-ended structure for the implementation of the ZCB integrator.
A fully-differential integrator turned out to be a not realizable target within this project, as
it was estimated that it cannot provide the accuracy that is required. Regarding the pseudo-
differential structure, it was adjourned, although it was recognized to pose certain benefits

Master of Science Thesis Georgios Karykis

56 Design for improved self-timed ZCB I∆Σ ADC

regarding its linearity behavior, without any degradation in energy efficiency (compared to
the single-ended structure), mainly because of great shortage in design time. As a result, in
this project the single-ended ZCB integrator was reused. Optimizing its performance towards
achieving the specifications set for this project could potentially lead to a design that has
superior energy-efficiency. This optimization for noise and linearity is following.

5-3 Noise and linearity design of the ZCB integrator

5-3-1 Noise design

Balance of the noise contributors and circuit-level design choices

The noise design is based on the analytical noise estimation of the ZCB integrator that
developed in section 3-2. Specifically, all the apparent noise contributors have to be suppressed
and balanced accordingly. According to prior analysis in this chapter, in order to achieve
ENOB=16.8 bit using the second-order modulator with N = 1000, the specification of total
input-referred noise of the first integrator is vn,in,IN T 1 = 160.8µV . In order to have proper
design margin, our design will over-suppress the noise of the integrator aggressively, setting
the target to vn,in,IN T 1 ' 100µV . Furthermore, in the new design, the total charge transfer
duration is decided to be approximately the same with the first prototype, in order to avoid
conversion time overhead. As a result, the specification of the charge-transfer duration is
Tcycle ' 500 − 550ns.
First of all, the capacitance levels have to be scaled up and CS is set to 1.2pF with
CI = 4.8pF in order to lower the sampling kT /CS contributor. The most important design
choice is, though, the effective noise-bandwidth, as it plays dominant role for the noise of the
ZCD and switches during the preamplifier’s response time. In order to lower N BW (ti , τ ), the
preamplifier’s response time ti has to increase while the energy consumption is also increasing.
Thus, it is not suggested to operate with ti > 120ns. However, we would like to N BW to
be around 2× lower compared to the designed value of the first prototype, thus the target
for NBW was set to ' 4.1M Hz. According to (3-15), for ti = 115ns and τ ' 140ns, the
effective noise-bandwidth becomes N BW < 4.6M Hz. Since it is not suggested to operate
with higher ti , it was decided to scale the gm of the preamp and apparently the equivalent
noise resistance of switches Req in order to achieve adequate values of the ZCD and switches
noise contributors.
For the noise of the ZCD, an increase of the gm is needed and a value of gm,tot = 450µA/V
was chosen. This increase of the gm was possible with a substantial increase of the power
consumption as will be explained later. Next, the switches noise during preamplifier’s response
time should by any means be dominant and this contributor can be further suppressed without
any significant power consumption penalty by reducing the equivalent noise resistance Req at
VX . Therefore, wider switches have to be used along the integrator’s feedback path and the
designed values for the on-resistances are: Ron2 = Ron3 = Ron4 ' 800Ω and Ron1 ' 600Ω.
The required width for for Ron2 , Ron3 and Ron4 is 1.2µm. Regarding the bitstream controlled
(unboosted) feedback NMOS and PMOS switches which correspond to Ron1 , the required
widths are 1.6µm for the NMOS switch and 4.2µm for the PMOS switch.

Georgios Karykis Master of Science Thesis

5-3 Noise and linearity design of the ZCB integrator 57

For the aforementioned design choices, the input-referred noise of the ZCB integrator
is estimated to be vn,in,IN T 1 = 94.8µV . In the new design, the sampling noise kT /CS is
dominating although this is not optimal in terms of energy-efficiency, as lowering the noise
of the preamplifier requires higher energy consumption than the suppression of the sampling
noise. However, during the design time of this project, the updated measurement results of
the first prototype, that presented in Chapter 4, were not available, so the validity of the
noise model was not proven. As a result, it was decided to suppress more aggressively the
contributors that are related with the charge transfer of the ZCB integrator, as an extra safety
measure to guarantee that the targets that were set for this project will be met in the end.

ZCD implementation

The architecture of the ZCD will be very similar with the ZCD of the first prototype, seen
in Figure 2-9, as again will be consisting of a transconductance preamplifier and a wide-band
crossing detector. The early-threshold generation mechanism is not subject to change, as this
is the common way to realize such functionality [4] and any problem was identified to be
associated with it. The wideband crossing detector is again a chain of two inverters, as this is
the most energy-efficient alternative, but they are slightly downsized in order to save power,
at the expense of a small increase of the signal-independent delay time tc .
For the realization of the preamplifier, an inverter-based structure is preferred, because of
the double transconductance gm,tot that is achievable for a given drain current and its inherent
dynamic biasing characteristic. Possible candidates for the inverter-based implementation of
the preamp are the class-AB inverter amplifier, the cascode-inverter amplifier and the current-
starved inverter amplifier, that are shown in Figure 5-7. The cascode-inverter amplifier is
superior to the simple inverter amplifier, by means of achieving much higher output resistance
and thus providing higher DC gain. In the design of the preamplifier, however, there is no
special need for very high output-resistance of the preamplifier, as the preamplifier’s time
constant τ is possible to be tuned via the band-limiting capacitor Clim . As a result, the
alternative of the cascode inverter was not utilized. On the other hand, the current-starved
inverter amplifier is employing a current source between the supply and the transistors of the
inverter that is providing a regulated supply VDD,inv to the inverter, improving significantly
the supply noise rejection of the structure. The disadvantage of the current starved inverter
amplifier is that VDD needs to be increased in order to maintain the inverter in its optimal
bias point.
Typically, the optimal bias point of a Class-AB inverter amplifier is at the boundary
between weak and strong inversion regions [14]. According to [25],[14] the optimal supply
voltage of a Class-AB inverter amplifier that is providing operation at the boundary between
weak and strong inversion is VDD,optimal = VT N + |VT P |, where VT N , VT P are the threshold
voltages of the NMOS and PMOS transistors. In the 0.16µm CMOS process [46], VT N +|VT P |
is slightly lower than 1V, so the VDD of the inverter is set to 1V, similar to the previous design
[1]. Taking this into account, in the current-starved inverter topology, since we want to bias
the inverter at its optimal bias point VDD,inv = VT N + |VT P | ' 1V , the supply voltage VDD
has to be increased, in order to leave voltage headroom for the current source to operate in
saturation. It is noteworthy that from the measurement results of the first prototype, the
supply noise disturbance does not seem to degrade significantly the performance of the ADC,

Master of Science Thesis Georgios Karykis

58 Design for improved self-timed ZCB I∆Σ ADC

VBP VBP

Vin Vout Vin Vout

VBN Vin Vout

EN

(a) (b) (c)

Figure 5-7: Alternatives for the inverter-based implementation of the preamplifier: (a)
class-AB inverter amplifier, (b) the cascode-inverter amplifier and (c) the current-starved
inverter amplifier.

thanks to the auto-zeroing of the ZCD, the noise shaping of the modulator and the correlated
level-shifting mechanism, as analyzed in [14] and [25]. As a result, utilizing the current-
starved inverter seems not necessary in this implementation and was decided to employ the
simple class-AB inverter amplifier, that was used also in the first prototype, keeping the
supply voltage at 1V. This topology was resized accordingly in order to fit in our needs and
optimized with respect to optimal power-efficiency.
The inverter structure, loaded by the band-limiting capacitor Clim , should be sized in
order to operate with a delay of ti = 115ns using IF ' 100nA, have a time constant τ ' 135ns,
providing gm,tot ' 450µA/V at the moment of input-threshold crossing. The sizing of the
preamplifier that is fulfilling these requirements is shown in Figure 5-8. The value of Clim
that is necessary is 0.6pF .

VDD

20/0.32
Vout
Vin

5/0.32 Clim=0.6pF

EN 1/0.16

Figure 5-8: Sizing of the inverter-based preamplifier for the first integrator.

In Figure 5-9, the operating point of the designed inverter is compared with the inverter

Georgios Karykis Master of Science Thesis

5-3 Noise and linearity design of the ZCB integrator 59

used in the first prototype. The transconductance efficiency was optimized by pushing the
operating point of the transistors closer to weak-inversion [32], achieving gm /Id ratio for both
the transistors of the new inverter larger than 18.25V −1 , while in the previous design the
transconductance efficiency was around 16.1V −1 .

(a) (b)

Figure 5-9: Comparison of the operating points of ZCD inverter-based preamplifiers: (a)
proposed design, (b) preamplifier used in [1].

In order to verify the argument of cancellation of the flicker noise by employing auto-
zeroing, the input-referred noise of the preamplifier was simulated. The input-referred noise
PSD was obtained and the 1/f noise corner frequency is well below the fAZ . Consequently,
the effect of 1/f noise of the transistors of the preamplifier, is not expected to contribute
significantly to the total input-referred noise of the integrator.
The noise design of the ZCB integrator should be, of course, verified with simulations
before proceeding with the design of the other building blocks of the ADC. The simulation
results for the input-referred noise of the integrator and the power consumption during the
charge-transfer phase are presented in section 5-4.

5-3-2 Linearity design

The linearity design of the ZCB integrator was based on the simulation of the signal-dependency
of the input-referred error, taking into account the design choices that are imperative for the
noise performance. The linearity optimization process of the integrator was involving Verilog-
A modeling of the current sources and use of ideal models for switches in order to examine
the importance of the various sources of non-linearity that described in section 3-3.
First of all, after up-sizing the capacitors and keeping the fine current source current
level to around 100nA, the signal dependent input-referred error was already improved and
its simulated range was [−9.155µV , 9.155µV ]. At this point, in order to bring this range well
below 10µV , which is expected to be enough to achieve INL for the ADC better than 1LSB
of 16bit, multiple experiments were done by replacing the actual implementation of various

Master of Science Thesis Georgios Karykis

60 Design for improved self-timed ZCB I∆Σ ADC

building blocks by ideal models in order to find out the dominant source of non-linearity. The
possible suspects were the switches and the current sources, with the ramp-rate non-linearity
and the off-transients to be considered.
When replacing the switches with ideal models having the proper values of on-resistance,
the simulated signal-dependent error did not change significantly and was concluded that
there is no severe problem coming from the switching effects. In contrast, when the current
sources were replaced with Verilog-A models having proper output resistances, the signal-
dependency of the error was drastically reduced. Also, when only the fine current source was
replaced by a Verilog-A model, the signal-dependency was also improved compared to the real
case, but was a bit worse than the previous test case with both the current sources replaced
by Verilog-A models. Interestingly, when the output resistances of the current sources used
in the Verilog-A model were scaled by a factor of 100, the signal-dependent error was not
observed to reach the level of the simulation with real current sources. From these series of
experiments, it was concluded that the ramp-rate induced non-linearity is not the dominant
non-linear mechanism of the charge-transfer process. However, the linearity degradation was
assumed to come from the off-transients of the fine current source, with the off-transients of
the coarse current source contributing marginally to the ramp-rate induced non-linearity.
After these experiments, the actual design of the current sources was revisited in order
to bring the signal-dependent error in spec. Because the off-transients of a cascode current
source are related with the area of the bottom transistor, this had to be downsized at the
possible expense of lowering the output-resistance. Furthermore, it turned out that the coarse
current source is not necessary to be downsized. Both the designed coarse and fine current
sources along with their biasing schemes are shown in Figure 5-10.

Vfine
100nA 200nA

E2
VO
0.6/30
100nA VFB2
E1 1/1
0.6/30
VCB VFB1
1/10 1/10 × k 1/5 1/5

Coarse CS Fine CS
(a) (b)

Figure 5-10: Sizing and biasing of charging current sources. (a) Coarse current source, (b)
Fine current source

The simulated output resistance of the coarse current source was Rout,coarse = 840M Ω,
while the output resistance of the fine current source is higher than 26.8GΩ and varies around
2% with its output voltage Vf ine , as Vf ine is swept from 720mV to 960mV.
With these design choices and adjustments, the input-referred signal-dependent error of
the ZCB integrator was simulated and is visualized in Figure 5-11. The signal-dependent error
range, after downsizing the fine current source and using CCLS = 0.2pF , was only 5.2µV ,

Georgios Karykis Master of Science Thesis

5-4 Simulation results of the ZCB integrator 61

which is expected to be enough to improve the INL of the ADC and push it lower than 1LSB
of 16bit. The simulated average charge-transfer duration of the ZCD was Tcycle = 535ns,
with the fine phase was lasting approximately Tf ine = 320ns on average.

Vin,err,norm(uV)

2.6

0.35V
0.65V VO

-2.6

Figure 5-11: Normalized input-referred error of the ZCB integrator.

5-4 Simulation results of the ZCB integrator

The design of the ZCB integrator should be extensively verified by simulation and the sim-
ulation results for noise and linearity performance, as well as the power consumption are
presented here.

5-4-1 Input-referred noise

The verification of the noise design can be done by means of transient noise simulation or
PSS/Pnoise simulation using SpectreRF [47], because we are dealing with a sampled data
system which is subject to noise aliasing [48].

The testbench for the PSS/Pnoise simulation of the input-referred noise is shown in
Figure 5-12 where the ZCB integrator is used in unity-feedback configuration with the use of
two ideal sample-and-hold circuits (implemented in Verilog-A), according to the guidelines in
[49] and [47]. This configuration is ensuring the convergence for the PSS/Pnoise simulation
and is typically used for such purpose.

The outcome of this simulation was that the input-referred noise of the integrator is
vn,in,IN T 1 = 122.5µV . For the sake of comparison, the first integrator of [1] was simulated
using the same testbench, resulting in vn,in,IN T 1 = 189.22µV .

Performing a transient noise simulation of the ZCB integrator keeping the input voltage
fixed to Vin = 0.5V and capturing the integrated voltage in the end of each cycle, we can
calculate the standard-deviation of the integrated voltage. Using 15 cycles for the transient-
noise simulation we get δVI = 30.075µV . Scaling with the inverse of the integrator’s constant
CI
, we obtain the input-referred RMS noise of the integrator. The result of this was an
CS
input-referred noise of vn,in,IN T 1 = 120.3µV .

Master of Science Thesis Georgios Karykis

62 Design for improved self-timed ZCB I∆Σ ADC

Φ1 Φ2

S/H S/H
Φ2
Φ2 CI VO

Φ1d CS
P P||E1
Vin D CCLS Φ2d
VX Vout
Vfine
E1 E2 CL
Φ1 De
IC IF
Φ2

ZCB integrator under test

Figure 5-12: Simulation testbench for the input-referred noise of ZCB integrator.

5-4-2 Input-referred error over process corners

The first step in the linearity verification of the ZCB integrator over process corners is to
ensure that the current source is functional over all the corners achieving, preferably, output
impedance higher than 20GΩ. The simulation result of the output-resistance over the 5
corners is summarized in Table 5-1.
Table 5-1: Simulated fine current source output impedance over process corners.

Process corner Fine current source output resistance

nominal 27.5 GΩ
snsp 29.9 GΩ
fnfp 24.7 GΩ
snfp 35.6 GΩ
fnsp 19.1 GΩ

As a next step, the linearity of the ZCB integrator is simulated over corners, demand-
ing the signal-dependent error to remain in spec under process variations. Unfortunately, it
was observed that the integration error behavior is very sensitive to process variations with
the integrator operation collapsing in different corners. The main reason of this problematic
behavior was found to be the transition from coarse to fine charging phase. For example, in
the slow corner, the transition was happening too late, after the virtual ground was reached,
making the integration error dominated by the non-linear coarse phase overshoot. In fast
corner, the transition was happening too early, increasing very much the swing of the fine
current source which was collapsing (Vf ine < Vmin ) before the virtual ground condition es-
tablishment. The latter made the signal dependency of the integration error dominated by
the ramp-rate variation, as the output resistance of IF much lower than its designed value.
Fortunately, the offset voltage of the early-threshold generation mechanism Vof f can act as a
trimming node and the proper operation of the ZCB integrator can restored over all process

Georgios Karykis Master of Science Thesis

5-4 Simulation results of the ZCB integrator 63

corners. After extensive simulation, the optimal values of Vof f that is needed to achieve this
were found and the input-referred error was brought in spec. The results of this procedure,
including the preamp’s response time in every process corner are summarized in Table 5-2.

Table 5-2: Input-referred error of ZCB integrator over corners

Process corner Input-referred error range ti average Tcycle Voff

nominal 5.2µV 115ns 535ns 446mV
snsp 10.82µV 224ns 805.2ns 492mV
fnfp 22.04µV 57ns 540ns 395mV
snfp 8.46µV 109.7ns 573.3ns 500mV
fnsp 9.15µV 86.5ns 572ns 393mV

5-4-3 Power consumption

The current consumption of the designed ZCB integrator during charge-transfer phase can
be monitored using transient simulation, capturing the currents flowing to ground node. The
result of this simulation is shown in Figure 5-13. In this figure, the current of the analog part
of the ZCD (inverter preamp) is colored red, the current of the digital part of the ZCD (WCD)
is colored green and the current of the rest analog circuitry of the integrator (including the
current sources and the current reference) is colored blue.

Figure 5-13: Simulation of current consumption of ZCB integrator during charge transfer.

The maximum analog current level is increased by approximately 25%, compared to the
first prototype, while the total energy consumption during the charge transfer is expected to
increase by a factor of 2×. However, the total energy consumption is not necessarily scaling

Master of Science Thesis Georgios Karykis

64 Design for improved self-timed ZCB I∆Σ ADC

by 2×, as a big proportion of energy is consumed during the autozeroing process of the ZCD,
which can be optimized by reducing the autozeroing duration which is happening during
the fine phase of the second integrator. This will be discussed in the design of the second
integrator in section 6-1.

5-5 Summary

In this chapter, the design of the first ZCB integrator for the improved self-timed I∆Σ ADC
was treated, after exploring the various system-level modifications that were in principle
possible. After realizing that a fully-differential implementation is not possible because of
its bad linearity and the shortage of design time that did not permit the realization of the
pseudo-differential topology, the new design was decided to be single-ended. Regarding the
modulator’s topology and order, it was concluded that a higher-order topology would not
necessarily lead to improved energy-efficiency so the new design will be based on the same
topology as the first prototype.
The improvement in resolution, linearity and energy-efficiency will come, primarily, from
the smart design of the first integrator and proper noise allocation. In this chapter, the ZCB
integrator was sized in order to achieve input-referred noise and input-referred error that
is expected to lead to resolution and linearity better than 16bit, with the lowest possible
overhead in power consumption. Generous design margin was taken into account in all design
choices in order to ensure the validity of the design, and all the choices were extensively
verified by simulations.

Georgios Karykis Master of Science Thesis

 Chapter 6

Final Realization

This chapter describes the implementation details of the new prototype self-timed ZCB I∆Σ
ADC, except for the design of the first integrator that was treated in the previous chapter.
The discussion starts with the design of the second ZCB integrator of the ADC and continues
with a short presentation of the auxiliary circuits, such as the clock boosters, the bitstream
quantizer and the current reference that are to great extent reused from the previous design
[1], as their proper functionality is proven. After that, the layout of the new test-chip is
given and then the pre-layout and post-layout simulation results of the new design, including
resolution, linearity, conversion time and power consumption are presented. Finally, the
performance summary of the new design and comparison with the state-of-the-art designs of
CBSC/ZCB ∆Σ ADCs and OTA-based ∆Σ targeted for sensor interfacing are given.

6-1 Design of the second ZCB integrator

The requirements of the second integrator of the modulator is significantly relaxed compared
to the first integrator in terms of noise and linearity. As a result, the second integrator should
be a scaled version of the first integrator in order to minimize its power consumption.
In this design, the capacitor levels of the second ZCB integrator were scaled with a factor
of 2, thus CS2 = CL1 = 0.6pF and CI2 = 1.2pF , CAZ2 = 1.2pF and the load capacitor of
the integrator was chosen to be CL2 = 0.2pF . Also, the preamplifier of the ZCD, which is
the most current-consuming element of the integrator was scaled with a factor of 4. The
sizing of the second preamplifier is shown in Figure 6-1. This sizing resulted to scaling of the
maximum current of the preamp by a factor of 4, being Ipreamp2,max = 3.37µA, achieving total
transconductance of gm,tot2 ' 120µA/V as can be seen in Figure 6-1, where the operating
point of the second preamplifier is attached.
Furthermore, when the second integrator is employed in the context of a self-timed ∆Σ
modulator, the timing of the two integrators can be asymmetrical and the charge transfer
can be designed to be faster in order to obtain savings in conversion time of the ADC. More
importantly, since the auto-zeroing of the preamplifier of the first integrator is performed

Master of Science Thesis Georgios Karykis

66 Final Realization

VDD

5/0.32
Vout
Vin

1.25/0.32 Clim=0.2pF

EN 1/0.16

Figure 6-1: Sizing and operating point of the inverter-based preamplifier of the second
integrator.

during the fine phase of the second integrator, the fine charge transfer duration is a critical
parameter for the energy consumption of the first integrator. The reason for this is that during
auto-zeroing the maximum current is flowing through the inverter amplifier. The minimum
duration of the auto-zeroing is dictated by the auto-zeroing time constant

CAZ + Clim
τAZ = (6-1)
gm,tot

Taking a conservative estimation, the minimum time required for the auto-zeroing operation
to be 10× the auto-zeroing time constant. Thus, for the first ZCB integrator with gm,tot =
450µA/V , CAZ = 3.6pF and Clim = 0.6pF , the minimum auto-zeroing time is

CAZ1 + Clim1
TAZ1,min = 10 · τAZ1 = 10 · = 93.3ns (6-2)
gm,tot1

Consequently, in order to avoid unnecessary static power consumption due to auto-zeroing

of the first preamplifier, we have to design the second integrator to have fine-phase duration
around Tf ine2 ' 100ns or apply smart control of the auto-zeroing process introducing extra
complexity in the digital circuitry. The first solution was preferred and accomplished by
adjusting the magnitude of the fine current source. Setting If ine2 ' 180nA and Clim2 =
0.2pF , the preamplifier’s response time ti2 and time constant τ2 were 95.6ns and 120ns
respectively. For these design choices and setting Vof f 2 = 448mV , it was manageable to limit
the fine charge transfer duration to Tf ine2 = 112.5ns and total charge-transfer duration to
Tcharge−transf er2 = 290.5ns on average.
The design choices for the preamplifier of the second integrator are summarized in Ta-
ble 6-1, along with the design choices of the preamplifier of the first integrator for comparison.
The design of the second integrator was verified through simulations following the same pro-
cedure with the design of the first integrator. The signal-dependent input-referred error range

Georgios Karykis Master of Science Thesis

6-2 Further energy consumption reduction measures 67

Table 6-1: Design parameters of the inverter-based preamplifiers in the ZCDs

Parameters 1st Int. preamp 2nd Int. preamp

Maximum transconductance gm,tot 450µA/V 120µA/V
Maximum bias current Imax 12.25µA 3.37µA
Response time ti 115ns 95.6ns
Time constant τ 132ns 154ns
Bandlimiting capacitor Clim 0.6pF 0.2pF

was simulated to be 65µV , using CCLS2 = 0.1pF and the input-referred RMS noise was sim-
ulated using transient noise simulation to be vn,in,IN T 2 = 635µV . These values for noise and
signal-dependent error are expected not to harm the performance of the entire ADC.

6-2 Further energy consumption reduction measures

In the design of both ZCB integrators, it has been recognized the the energy consumption is
dominated by the current that the preamplifiers consume during fine charge transfer phase
and during their auto-zeroing operation. The energy consumption of the preamp during the
fine phase can be tuned by lowering the fine charge transfer duration, i.e setting the early
threshold of the ZCD closer to VCM adjusting Vof f accordingly. Also, the energy consumption
during the auto-zeroing of one ZCD is proportional to the fine charge transfer duration of the
other ZCB integrator. These two factors were taken into account in the design of both ZCB
integrators.
Taking a step further, if it was possible to eliminate the need of auto-zeroing in each
cycle, apparent energy savings will be present. During the design of the ZCB integrators, it
was observed that the charge across the auto-zeroing capacitor is not changing substantially
among successive integration cycles, because CAZ is much higher than the input capacitance
of the ZCD preamp. Consequently, the opportunity of skipping auto-zeroing cycles is indeed
present, having although impact to linearity of the integrators as the threshold of each ZCD
will slightly vary from cycle to cycle for the cycles when AZ is not performed. Another
disadvantage lies in the suppression of the 1/f noise of the ZCD preamplifiers as the cut-off
frequency of the 1/f noise will be lower. In order to investigate this opportunity, the AZ
signal of the ZCDs can be gated using an universal AZ control signal that is controlling in
which cycle the auto-zeroing will be performed. This was implemented in a configurable way
using an external control signal to control the auto-zeroing processes. The generation of AZ
control signal can be done by the state-machine for the generation of the self-timed clocks
of the ADC. In this configuration, the duration of auto-zeroing can be optimized as well
implementing the necessary logic off-chip in order to limit the AZ duration to approximately
10×τAZ of each ZCD.
Another opportunity for energy savings comes from the observation that the swing of
the first integrator is limited to [0.35V, 0.65V ]. So, since the output is preset in every cycle
to 1V , unnecessary expenses in conversion time and energy consumption are present due to
the roll-off of VO1 from VDD to the actual swing of the integrator. By presetting to a lower

Master of Science Thesis Georgios Karykis

68 Final Realization

voltage than VDD the majority of these expenses are prevented. This is implemented in the
new design, using an external Vpreset1 connection of the chip.

6-3 Implementation of the other sub-blocks of the ADC

In order to implement the ADC, besides the two ZCB integrators, auxiliary circuitry needs
to be realized, such as digital logic for the control of the charge-transfer phases of the two
ZCB integrators, clock-boosters in order to drive the switches, a bit-stream comparator and
a current reference. Also, the generation of the Vof f voltages that are necessary in the early-
threshold generation mechanism of the ZCDs is required. These sub-blocks were present
in the first prototype of the self-timed ADC and the proper functionality of the designed
blocks in [1] is verified. The requirements from these sub-blocks remain the same in the new
design, so these sub-blocks are reused with small modifications. This section is presenting the
implementation details of these sub-blocks, including short discussion on the requirements
from them.

6-3-1 Generation of Vof f

As described before, the early-threshold of the ZCDs is implemented using capacitive level-
shifting of the preamplifier’s output of the ZCD. The level-shifting capacitor Cof f is needed
to be precharged before the beginning of the charge-transfer to a suitable voltage Vof f . The
precharging of Cof f is done during the preset phase of the ZCB integrator and the Vof f
voltages that are reqired for the two integrators are Vof f 1 = 446mV and Vof f 2 = 451mV .
These voltages can be generated on-chip by means of a diode voltage reference as can be seen
in Figure 6-2.

100nA

Voff
W/L

Figure 6-2: Schematic of a diode voltage reference for the generation of Vof f inside the
ZCDs.

The designed dimensions for the two diodes are W1 /L1 = 1/16.3 and W2 /L2 = 1/16.85.
Although this method has been proven functional, it is beneficial to include the possibility
of external generation of the Vof f voltages, although it is consuming two I/O pins of the chip.
By doing so, the possibility of trimming the switching point from coarse to fine charging phase
remains in order to avoid linearity problems coming from process variations. The configuration

Georgios Karykis Master of Science Thesis

6-3 Implementation of the other sub-blocks of the ADC 69

of on-chip or off-chip Vof f generation is provided using one bit of the configuration shift
register of the chip.

6-3-2 Digital control of the charge-transfer

The digital control logic that was designed in [1] is completely matching the requirements
of this design, so it was reused, including the layout, with minor modifications. The digital
circuitry is generating the preset P and control signals of the current sources E1 , E2 for
both integrators, as well as the auto-zeroing signals AZ1 , AZ2 , based on Φ1 , Φ2 and the ZCD
outputs D, De of the ZCB integrators. The control logic has been designed using standard
cells available in the design libraries of NXP C14 technology [46] and for the new realization a
few blocks were downsized in order to save power, at the expense of the slight increase of the
delay time tc . Implementation details of the self-timed control circuitry can be found in [25].
For the generation of the preset signal, a low-power tunable delay element was utilized [50].
The tuning of the delay is possible via a current starving current source, which is configurable
in this implementation, using two bits of the configuration shift register of the chip for each
integrator.

6-3-3 Clock boosters

In order to ensure low on-resistance of NMOS switches with low supply voltage, the driving
voltage of the switches has to be boosted above VDD . This typically realized using the clock-
boosting technique [16] [51] and implementations of a single-output and a double-output clock
booster that were used in [1] are shown in Figure 6-3. The double-output clock booster is
functional if the inputs are complementary and is used for example to boost the Φ1,d − Φ2,d
and AZ1 − AZ2 signals. The single-output clock booster is used to boost Φ1 and RSTn .
Regarding a clock-booster’s input-output behavior, when the input voltage of a is a
square-wave between GN D and VDD the clock-booster is generating a square-wave with
identical timing and ideally doubled amplitude (between GN D and 2 · VDD ). In practice, the
voltage-boost ratio is lower than 2, because of the finite parasitic capacitance Cp at the clock-
booster’s output due to gate capacitance of the driven switches and parasitic capacitance of
the wiring [51]. In order to ensure that the driving voltage will be 1.85V in worst case, the
capacitors Cb1 , Cb2 of the clock booster have to be adjusted carefully, using the results of
post-layout simulation of the ADC.

6-3-4 Bitstream comparator

The accuracy requirements from a bitstream comparator that is used in the context of a ∆Σ
ADC are very relaxed, as the error of the comparator due to offset or kick-back noise is highly
suppressed by the aggressive noise shaping of the loop-filter. For this reason and high power
efficiency due to their negligible static power consumption, the use of a dynamic comparator
was chosen in the first prototype. The implemented comparator in [1], which is reused in
the new design is shown in Figure 6-4. This comparator is consisting of an input pair with a
regenerative latch followed by an SR latch.

Master of Science Thesis Georgios Karykis

70 Final Realization

VDD

M1 M2

M3
VH OUT

Cb1 Cb2 Cp
MSW
M4
GND

IN
GND
(a)

VDD

OUT1

Cb1 Cb2 Cp
MSW

GND
IN1
GND
OUT2

IN2
Cp
MSW

GND

(b) GND

Figure 6-3: Schematics of (a) a single-output clock-booster and (b) a double-output clock
booster [25].

The operation of the dynamic comparator is based on the Latch input control signal.
When Latch is low the regenerative latch is reset and is isolated from the input and the
SR latch is keeping the reuslt of the previous comparison. With the rise of Latch, a new
comparison is triggered, with the input voltage altering the equilibrium of the regenerative
latch, until it is settling to its new state. The new state of the latch is then latched in the
SR latch, providing the new comparison result. In the context of the self-timed ADC, the
Latch signal of the comparator is the inverse of the fine phase control signal of the second
ZCB integrator E2n .

6-3-5 Current reference

For biasing purposes of the gated current sources, diode voltage-references and the delay ele-
ments that are present in the digital control circuit of the modulator, a conventional constant-
gm current reference [31], that is insensitive to supply voltage variations was designed in the

Georgios Karykis Master of Science Thesis

6-3 Implementation of the other sub-blocks of the ADC 71

VDD

Latch M5 M6

OUT+
OUT-

M3 M4

Vin M1 M2 VCM

Input Pair + Regenerative Latch GND S-R Latch

Figure 6-4: Schematic of the dynamic bitstream comparator [25].

prototype chip of [1]. This current reference is matching perfectly the requirements of the
new design, thus the design and layout are completely reused in the new chip. The schematic
of this current reference, that is including a low-voltage startup circuit is shown in Figure 6-5.
According to [31], the output current of this reference is
2
1 2 1

Iout = 2 · 1− √ , (6-3)
Rbias µn COX (W/L)1 k

where k is the aspect ratio of the NMOS transistors of the current reference. Using Rbias =
620kΩ and k = 10 the output current of the current reference is ' 100nA

VDD

1:1
M6
M4 M3 1µm/400µm

M5
Mirrored 1µm/20µm
CM
current
50fF
M2 M1 M7
1:k 6µm/0.25µm

Rbias

GND Start-up Circuit

Figure 6-5: Schematic of the current reference, including the start-up circuit [25].

Master of Science Thesis Georgios Karykis

72 Final Realization

In the previous implementation, the possibility of off-chip generation of the bias current
was included, for safety reasons in case of failure of the start-up circuit. This option was
remained in the new chip and the selection between on-chip or off-chip reference current
generation is done using two bits of the configuration shift register of the chip.

6-4 Configurability and testing features of the chip

The designed test chip should be able to operate in different modes in order to ensure its proper
operation and also enhance the possibility of drawing useful conclusions on the operation of
ZCB circuits. Thus, many configuration options are available in the designed chip, which are
now summarized:

• On-chip / off-chip Vof f generation (1 bit in shift register for both integrators)
• Control of magnitude of coarse current sources with 5 steps (3 bits in shift-register for
each integrator)
• Control of the correlated level-shifting capacitances with 2 steps: 0.2pF or 0.4pF for
the first integrator and 0.1pF or 0.2pF for the second integrator (1 bit in shift register
for each integrator)
• Control of the magnitude of the fine current source of the second integrator with 2 steps:
90nA or 180nA (1 bit in shift register)
• Control of the preset duration of the integrators with 3 steps (2 bits in shift register for
each integrator)

The first, second and fifth configuration options of the chip were present in the previous design
[1], but the third and fourth are introduced in the new prototype. Furthermore, in order to
make the chip testing friendly, internal probing of the crucial signals of the operation is
mandatory. For this reason, in the previous design an analog multiplexer/buffer and a digital
multiplexer have been employed in order to facilitate the monitoring of the ouput signals of
the two integrators VO and the two preamplifiers of the ZCDs Vint , as well as, the digital
control signals of preset P and control of the current sources E1 and E2 . The implementation
details of these circuits can be found in [25]. This functionality was maintained in the new
chip and the required circuitry is reused, as its proper functionality has been proven.

6-5 Layout

The layout of the chip was designed in NXP CMOS14 [46] 0.16µm 1P5M standard CMOS
technology and can be seen in Figure 6-6, where the building blocks of the chip are highlighted.
The chip dimensions are 0.785mm×0.85mm and 30 I/O pads are required with 14 I/Os being
analog, 14 I/Os being digital and 2 I/Os do not have ESD protection and are used as outputs
of the analog buffer. During the layout design of the chip special care was taken to ensure
proper voltage levels at the outputs of the clock boosters and tried to minimize the parasitic
capacitance at the input of the first ZCD preamp, as both phenomena have been recognized
as limiting factors of the achievable linearity of the converter [25].

Georgios Karykis Master of Science Thesis

6-5 Layout 73

0.785mm

G O
H
B
D
I
0.85mm A
C
F

M E N

L J K
P
Q

A: Capacitors of 1st integrator B: Preamplifier of ZCD of 1st integrator C: Capacitors of 2nd integrator
D: Preamplifier of ZCD of 2nd integrator E: Switches F: Fine current sources G: Coarse current sources
H: Current reference I: Voff generation and offchip control K: Control logic of 1st integrator
L: Control logic of 2nd integrator M: Bitstream comparator and WCD of 2nd integrator
N: WCD of 1st integrator O: Analog output buffer P: Digital output buffer Q: Shift register

Figure 6-6: Layout of the ADC in 0.16µm 1P5M CMOS.

Master of Science Thesis Georgios Karykis
74 Final Realization

6-6 Simulation results

After the ADC is built, extensive performance characterization is necessary, performing pre-
layout and post-layout simulations. The simulation results of the ADC are following, concern-
ing all the common specifications of Incremental ∆Σ ADCs, such as resolution, conversion
time, linearity, as well as power consumption. In the end, a performance summary of the
designed ADC is presented and the obtained performance is compared with other state-of-
the-art ADCs, tailored for I&M applications.

6-6-1 Pre-layout simulation results

Functional verification

The first step of the characterization procedure of an ADC is its functional verification. This
is checked, ultimately, by performing a single conversion, by means of a transient simulation.
In this case, the designed ADC performed a conversion with Vin = 0.5000033V and the
decimated output voltage that obtained was Vdec,out = 0.49709436V and the conversion time
that was needed was Tconv = 0.9670ms, taking into account the time that is needed for the
configuration of chip and reset of the ADC. Furthermore, in this step, the simulation of the
average power consumption of the ADC can be performed, capturing the analog and digital
supply currents and extracting their average values during the conversion time interval. The
resulting average analog supply current is IVDDA = 15.89µA, while the average digital supply
current is IVDDD = 9.67µA.

Input-referred noise

Then, the resolution of the ADC was treated and the input-referred noise was simulated,
by performing a transient noise simulation for the entire conversion. The decimated output
voltages were captured for the 16 points of the simulation and the point-to-point standard
deviation of the decimated outputs was calculated to be δrms = 5.155µV 1 . As a result, the
input-referred RMS noise of the ADC is vn,in,ADC,prelayout = δrms = 5.155µV . This noise
value is fairly close to the expectation vn,in,ADC
\ that can be made based on the simulation
of the input-referred noise of the first ZCB integrator [subsection 5-4], where the value of
vn,in,IN T 1 = 120.3µV was found and the estimated quantization noise standard deviation for
N = 1000, which is σq = 1.65µV [subsection 5-2-2]. Taking these into account, the estimated
input-referred noise of the ADC is
s
2
4 vn,in,IN T1
vn,in,ADC
\ = σq2 + · = 4.7µV. (6-4)
3 1000

Moreover, the simulated input-referred noise of the ADC is corresponding to a resolution

of
0.7
 
ENOB(bits) = 20 · log10 − 1.76 6.02 = 16.76bit (6-5)
vn,in,ADC,prelayout
1
For the noise simulation, the input voltage source was slightly noisy (Vn,in,pk−pk = 50nV ) in order to
trigger quantization noise.

Georgios Karykis Master of Science Thesis

6-6 Simulation results 75

The SNR of the converter can be calculated from the simulated input-referred noise to be

0.7
SNR = 20 · log10 √ = 93.63dB 2 (6-6)
2· 2 · vn,in,ADC,prelayout

Linearity (INL) and conversion time

Finally, the linearity of the converter has to be simulated, requiring an input sweep and
transient simulation for the whole conversion for each input voltage point. In this case, the
input was swept and the results for the decimated output and conversion time for the 15-point
input sweep are shown in Table A-1.

Using the input-decimated output pairs of Table A-1, the INL of the ADC can be es-
timated, by normalizing across the best-fitting straight line. The INL of the ADC, as esti-
mated with this pre-layout simulation is shown in Figure 6-7. The simulated offset of the
ADC was found to be VOS,prelayout = 3.6557mV , while the gain error was 1.1%. More-
over, the conversion time is visualized in Figure 6-8, with the maximum conversion time
being Tconv,max = 1.0016ms. The offset voltage of the ADC in this test was found to be
VOS,pre−layout = 3.265mV with the gain error being 2.1%. The offset and gain error were
not optimized in this design, as it is possible to be calibrated out in the digital domain in a
practical application. If this is not enough for a particular application, system-level chopping
[24] can be applied to effectively minimize offset and gain error of the ADC.

0.5

0.4

0.3

0.2
INL (LSB wrt 16bit)

0.1

−0.1

−0.2

−0.3

−0.4

−0.5
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Input Voltage (V)

Figure 6-7: Pre-layout simulated INL of the ADC.

2
√
A crest-factor 2 · 2 was included to take into account that the ADC is simulated with a constant input
and not with a full-scale sinusoid that is a common practice in performance characterization of general-purpose
ADCs.

Master of Science Thesis Georgios Karykis

76 Final Realization

0.99

0.98
Conversion time (ms)

0.97

0.96

0.95

0.94

0.93

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

Input Voltage (V)

Figure 6-8: Pre-layout simulated conversion time of the ADC as function of input voltage.

6-6-2 Post-layout simulation results

Functional verification

Similarly with the pre-layout verification procedure, the first step of the post-layout verifi-
cation is to confirm that the functionality of the ADC is correct. Again, a single conversion
with Vin = 0.5000033V was simulated and the decimated output voltage that obtained was
Vdec,out = 0.49561133V and the conversion time that was needed was Tconv = 0.9732ms,
taking into account the time that is needed for the configuration of chip and reset of the
ADC.

Input-referred noise

The next step, was to simulate the input-referred noise of the ADC with extracted layout. In
this case, the whole analog part was extracted, but the digital control of the two integrators
was simulated in schematic level, because of the limitation in simulation time. Using 8 points
for the transient noise simulation the point-to-point standard deviation of the decimated
outputs was δrms = vn,in,ADC,postlayout = 5.565µV . The calculated SN R in this case was
92.96dB and the resolution of the ADC was EN OBpost−layout = 16.67bit.

Linearity (INL) and conversion time

The linearity performance was simulated after layout extraction (again the digital control of
the integrators remained in schematic level), performing an 8-point input sweep. The results
for the decimated output and conversion time can be inspected in Table A-2. The INL of the
ADC was extracted from these results and is visualized in Figure 6-9. The conversion time

Georgios Karykis Master of Science Thesis

6-7 Performance summary 77

for this input sweep is plotted as well in Figure 6-10. Finally, the offset voltage in this test
was observed to be 3.976mV and the gain error was 3.45%.

0.5

0.4

0.3

0.2
INL (LSB wrt 16bit)

0.1

−0.1

−0.2

−0.3

−0.4

−0.5
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Input Voltage (V)

Figure 6-9: Post-layout simulated INL of the ADC.

0.99
Conversion time (ms)

0.98

0.97

0.96

0.95

0.94
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Input Voltage (V)

Figure 6-10: Post-layout simulated conversion time of the ADC as function of input voltage.

6-7 Performance summary

The simulated performance of the designed ADC is now summarized in Table 6-2. In order to
facilitate comparison with other designed ADCs and quantify the energy efficiency, the two
most-used figures of merit (FOM) that were briefly described in section 4-4 are calculated.

Master of Science Thesis Georgios Karykis

78 Final Realization

Table 6-2: Performance Summary

Specification Simulated Performance

Technology NXP 0.16µm 1P5M CMOS
Active Chip Area 0.6675 mm2
Supply Voltage 1V
Analog: 15.89µA
Supply Current
Digital: 9.67µA
Conversion Time < 1.01 ms
Stable Input Range 0.15V - 0.85V
Input-Referred RMS Noise 5.155µV
(pre-layout)
Input-Referred RMS Noise 5.565µV
(post-layout)
SNR (post-layout) 92.96dB
Resolution (EN OBpost−layout ) 16.67bit
†
INL -0.255 - 0.27 (LSB)
††
FOMW 0.71 pJ/conversion-step
†††
FOMS 168.8dB
† †† P ower · Tconv
Relative to a 16-bit output code. F OMW = (SN R−1.76)/6.02 .
2
††† 1
F OMS = SNR + 10 · log .
Power · Tconv

As can be seen in Table 6-2, the designed second-order I∆Σ ADC achieves (post-layout
simulated) resolution of approximately 17-bit and linearity of approximately 1 LSB with
respect to 17-bit, operating at 1000 incremental cycles. This performance is the best reported
among all the CBSC/ZCB ∆Σ ADCs, as can be seen in Table 6-3, in terms of achievable
resolution and linearity. Furthermore, the designed ADC consumes in total 25.56µA from 1V
supply, having conversion time of 1.01 ms in worst case. This leads to an improved energy
efficiency of the ADC which has Schreier FOM of 168.8dB, which is the highest compared to
all the prior CBSC/ZCB reported designs. Actually, the new design is improving the energy-
efficiency of the first prototype self-timed ADC[1]3 by 5.76 dB. Furthermore, the achieved
energy efficiency is very close to the state-of-the-art energy-efficiency of the OTA-based ∆Σ
ADC, with exception the design of [11] which is by far superior among all.

6-8 Improved measurement setup proposal

During the characterization time of the first prototype, a few options towards realizing a more
robust measurement setup came up. First of all the LDO that was used for the generation
of the reference voltage of the ADC was noisy, so a solution of a precision voltage reference
should be seeked. Perfect candidates for this are the ADR4520 [52], available from Analog
Devices or the LTC6655 [53], available from Linear Technology. Both these alternatives are
3
referred to its updated performance that is summarized in Table 4-1

Georgios Karykis Master of Science Thesis

 6-9 Summary 79

Table 6-3: Performance comparison with Prior CBSC/ZCB ∆Σ ADCs

[6] [7] [8] [9] [1] This work

Architecture ∆Σ2 - FD ∆Σ2 - FD ∆Σ4 - PD ∆Σ2 - SE IADC2 - SE IADC2 - SE
Process 0.18µm 45nmLP 90nm 3µmT F T 0.16µm 0.16µm
Area (mm2 ) 0.21 0.0448 0.33 26 0.45 0.6675
VDD (V ) 1.8 1.1 1 11.2 1 1
Sampling frequency 2.56 MHz 50 MHz 96 MHz 400 kHz 750 kHz 990 kHz
OSR 64 30 48 128 500 1000
Bandwidth (Hz) 20 kHz 833 kHz 1 MHz 1.56 kHz 667 Hz 495 Hz
Dynamic Range (dB) 71 54.3 70 69 81.9 92.96
Peak SNR (dB) 65.3 47.7 66 65.6 81.9 92.96
Power 0.42mW 630µW 5.94mW 63.3mW 20µW 25.56µW
FOMW (pJ/step) 6.98 1.91 1.82 13.03 1.46 0.71
FOMS (dB) 147.8 145.5 152.3 112.9 157.1 168.8
†
The reported performance of this work is based on simulation results.

generating higher voltage than 1V, so a resistive divider at the output of the voltage reference
is needed. Both these two alternatives are expected to facilitate the measurement of the new
ADC, as they are capable of achieving proper level of accuracy for our task.
The second consideration towards the enhancement of the robustness of the measurement
setup is based on tailoring it to the exact requirements of measurement. A measurement
setup that is based on an Alterra Cyclone II FPGA [54], and a 20-bit DAC, for instance
AD5791 [55] available from Analog Devices, for the generation of the input voltage of the
ADC is expected to be realizable. In this setup, the use of Labview can be avoided and
the control of the measurement procedure and data post-processing can be performed using
Matlab. For the measurement data transfer, the solution of using an RS-232 link is possible.
In that way, timing overhead of the measurement procedure can be avoided, thus reducing
the measurement time, making the setup immune to environmental noise and low-frequency
noise and interference.

6-9 Summary

In this chapter, the implementation details of the new prototype, except for the design of
the first integrator, were described. Finally, the top-level simulation results of the ADC were
presented, achieving 16.7-bit resolution in the post-layout simulation, INL of 0.5LSB with
respect to 16-bit, consuming 25.56µA from a 1V supply and operating for 1.01ms in worst
case.

Master of Science Thesis Georgios Karykis

80 Final Realization

Georgios Karykis Master of Science Thesis

 Chapter 7

Conclusions

This final chapter summarizes the work that has been done during this thesis project. It also
provides suggestions for future work on the self-timed ZCB I∆Σ ADC.

7-1 Thesis summary

The initial objective of this thesis was to develop an improved prototype of self-timed ZCB
I∆Σ ADC, achieving resolution and linearity above 16-bit, while improving (if possible) its
energy-efficiency. In order to fulfill this task, the new design is based on the first prototype
self-timed I∆Σ ADC [1], making use of all the performance enhancing techniques that have
been used before in the design of ZCB circuits, such as inverter-based implementation of
the preamplifier of the ZCD, correlated level-shifting and uni-directional coarse-fine charge
transfer scheme. Moreover, the options of extension to a differential structure and/or higher
order modulator have been examined.
This project is mainly focused on the optimization of the first ZCB integrator of the
loop-filter, as it is recognized as the most performance critical block of the ADC. For this
purpose the noise and linearity of the ZCB integrator have been analyzed and presented
in this thesis. The developed noise model was fairly accurate and has been verified by the
updated noise measurement results of the previous design [1], that were obtained during this
project. Main motivation for revisiting the measurement of the previous design was, however,
the observation that the measurement result of the INL was not reproducible. Also, the
knowledge of the actual linearity of the previous design was expected to verify to some extent
the linearity analysis of the ZCB integrator and help in the design of the new prototype.
The actual linearity of the previous design has been measured successfully, but the result is
not close to the expectation that was done based on the linearity analysis, because of the
significance of the off-transients of the gated current sources. As a result, in the development
of the improved prototype, a simulation-intensive linearity design procedure was found to be
the most suitable.

Master of Science Thesis Georgios Karykis

82 Conclusions

Next, the actual design of the improved ADC was tackled, starting with the possibilities
of extension to a third-order modulator and realization of a differential structure for the
ZCB integrators. Based on the developed noise model, it has been concluded that utilizing
a third-order modulator is not necessarily beneficial. Also, the presence of an issue in the
implementation of a 3rd -order CIFF modulator using ZCB integrators was discouraging and
the reuse of the 2nd -order modulator topology with input feed-forward path, that was used
in [1] was decided. Next, the option of a fully-differential implementation was examined, but
because of its large (simulated) signal-dependent input-referred error, probably due to the
mismatch of off-transients between NMOS and PMOS current sources turned out to be a
non-realistic target of this project. However, a pseudo-differential topology was found to be
suitable, but time limitations during this project did not permit its realization. As a result,
single-ended ZCB integrators were optimized in order to realize an ADC that meets the target
specifications of this project.
Based on the developed noise model, the first ZCB integrator was resized and following a
simulation-intensive linearity design procedure, the necessary measures were taken in order to
reduce the signal-dependency of the input-referred error of the ZCB integrator. After verifying
the design of the first integrator, the second ZCB integrator was designed as a scaled version
of the first one. In the end, the design of the ADC was completed, the layout was designed
and verified extensively using pre-layout and post-layout simulations.
Based on pre-layout and post-layout simulations, the designed second-order I∆Σ ADC
achieves (post-layout simulated) resolution of approximately 16.7-bit and INL equal to 1LSB
w.r.t. 17-bit. To achieve this, the modulator operates for 1000 incremental cycles, having con-
version time less than 1.01ms, while consuming less than 26µA from 1V supply. As a result, an
anticipated energy-efficiency in terms of F OMS = 168.8dB and F OMW = 0.71 pJ/conv.step
was found, which is improvement compared to the state-of-the-art of CBSC/ZCB ∆Σ ADCs
and quite close to the state-of-the-art designs of OTA-based ∆Σ ADCs.

7-2 Suggestions for future work

The correct operation of the designed ADC has been verified using simulations and its layout
has been designed and verified as well. But, since the new prototype has not been fabricated, it
can be readily included in an MPW run. This will enable the experimental characterization of
the improved self-timed ZCB I∆Σ ADC, leading to improved understanding of its performance
limiting factors. Also, there are some potential improvements and direct extensions of this
work that are summarized below.

• Based on the designed single-ended ZCB I∆Σ ADC, an extension to the pseudo-differential
topology that was proposed in this thesis but was not implemented due to design time
restrictions is possible. A pseudo-differential implementation is expected to demon-
strate superior resolution and linearity at comparable energy-efficiency with the pro-
posed single-ended ZCB I∆Σ ADC.

• The noise balance of the individual contributors can be revisited in order to achieve
higher energy efficiency. As mentioned previously, in this design the noise contributors
of the charge-transfer phase of the ZCB integrator, including ZCD preamp noise, were

Georgios Karykis Master of Science Thesis

7-2 Suggestions for future work 83

suppressed more aggressively compared to kT /CS . This was done to provide extra de-
sign margin, because during the design time of this project the validity of the developed
noise model was not proven, as the updated measurement results of the first prototype
were not available. Thus, another iteration of the noise design is suggested, in which
the noise of the ZCD preamp should dominate the total input-referred noise of the ZCB
integrator. In this case, the current consumption of the preamplifier is expected to be
lower, improving further the energy-efficiency of the ADC.

• Since it turned out that the major limiting factor of the linearity performance of the
ADC is the off-transient behavior of the fine charging current source, an alternative
implementation of the fine current source should be found. Possible candidates could
be a source degenerated current source or a switched-resistor current source similar
to [7]. The latter solution is expected to drastically reduce the off-transients at the
expense of increased die area. Also, implementing the current source using switched
resistors could potentially remove the off-transients mismatch problem and make the
fully-differential implementation of the ZCB integrator possible.

• Finally, the designed ADC can be readily applied to the implementation of integrated
sensor readout circuits of low-frequency signals, such as environmental signals.

Master of Science Thesis Georgios Karykis

84 Conclusions

Georgios Karykis Master of Science Thesis

 Appendix A

Results of pre-layout and

post-layout input sweeps

In this appendix, the results of the pre-layout and post-layout input sweeps of the designed
ADC are attached. These results have been used to extract the INL of the ADC which is
plotted in Figure 6-7 and Figure 6-9 respectively. Also, based on these findings the conversion
time of the ADC was plotted in Figure 6-8 and Figure 6-10 respectively.

Table A-1: Simulation results of pre-layout input sweep

Input voltage (Vin ) Decimated output (Vdec,out ) Conversion time (Tconv )

0.1500033 V 0.14603355 V 1.0016 ms
0.2000033 V 0.19592756 V 0.9989 ms
0.2500033 V 0.24582146 V 0.9914 ms
0.3000033 V 0.29574511 V 0.9867 ms
0.3500033 V 0.34560931 V 0.9804 ms
0.4000033 V 0.39550321 V 0.9765 ms
0.4500033 V 0.44539742 V 0.9706 ms
0.5000033 V 0.49529133 V 0.9670 ms
0.5500033 V 0.54519136 V 0.9628 ms
0.6000033 V 0.59508607 V 0.9574 ms
0.6500033 V 0.69487378 V 0.9513 ms
0.7000033 V 0.69687377 V 0.9454 ms
0.7500033 V 0.74476780 V 0.9435 ms
0.8000033 V 0.79466139 V 0.9390 ms
0.8500033 V 0.84455542 V 0.9321 ms

Master of Science Thesis Georgios Karykis

86 Results of pre-layout and post-layout input sweeps

Table A-2: Simulation results of post-layout input sweep

Input voltage (Vin ) Decimated output (Vdec,out ) Conversion time (Tconv )

0.2000033 V 0.19533799 V 1.0017 ms
0.3000033 V 0.29502029 V 0.9921 ms
0.4000033 V 0.39464400 V 0.9827 ms
0.5000033 V 0.49429681 V 0.9732 ms
0.6000033 V 0.59395695 V 0.9655 ms
0.7000033 V 0.69360929 V 0.9555 ms
0.8000033 V 0.79326194 V 0.9454 ms

Georgios Karykis Master of Science Thesis

 Bibliography

[1] C. Chen, Z. Tan, M.A.P. Pertijs, “A 1V 14b self-timed Zero-crossing-based Incremental

∆Σ ADC,” in 2013 IEEE International Solid-State Circuits Conference (ISSCC) Digest
of technical papers, San Francisco, CA, USA, pp. 274 – 275, February, 2013.

[2] J. K. Fiorenza, T. Sepke, P. Holloway, C. G. Sodini, and H.-S. Lee, “Comparator-Based

Switched-Capacitor Circuits for Scaled CMOS Technologies,” IEEE Journal of Solid-
State Circuits, vol. 41, pp. 2658 – 2668 , December 2006.

[3] L. Brooks and H.-S. Lee, “A 12b, 50MS/s, Fully Differential Zero-Crossing Based
Pipelined ADC,” IEEE Journal of Solid-State Circuits, vol. 44, pp. 3329 – 3343 , De-
cember 2009.

[4] S. Lee, A. Chandrakasan, and H.-S. Lee, “A 12b 5-to-50MS/s 0.5-to-1V Voltage Scal-
able Zero-Crossing Based Pipelined ADC,” in Proceedings of the ESSCIRC (ESSCIRC),
pp. 355 – 358 , 2011.

[5] T. Sepke, J. K.Fiorenza, C. G.Sodini, P. Holloway, and H.-S. Lee, “Comparator-Based

Switced-Capacitor Circuits For Scaled CMOS Technologies,” in IEEE Internationl Solid-
State Circuits Conference (ISSCC), pp. 812 – 821 , 2006.

[6] M.-C. Huang and S.-I. Liu, “A Fully Differential Comparator-Based Switched-Capacitor
Delta-Sigma Modulator,” IEEE Transactions on Circuits and Systems-II:Express Briefs,
vol. 56, pp. 369 – 373 , May 2009.

[7] T. Musah, S. Kwon, H. Lakdawala, K. Soumyanath, and U.-K. Moon, “A 630µW

zero-crossing-based Delta-Sigma ADC using switched-resistor current sources in 45nm
CMOS,” in IEEE Custom Integrated Circuits Conference (CICC), pp. 1 – 4 , 2009.

[8] K.Cornelissens and M.Steyaert, “Comparator-Based Switched-Capacitor Delta-Sigma

A/D Converters,” Advanced Analog Circuit Design (AACD), pp. 155 – 175 , September
2010.

Master of Science Thesis Georgios Karykis

88 Bibliography

[9] W.-M. Lin, C.-F. Lin, and S.-I. Liu, “A CBSC second-order sigma-delta modulator in
3µm LTPS-TFT technology,” in IEEE Asian Solid-State Circuits Conference (A-SSCC),
pp. 133 – 136 , November 2009.

[10] S. Ha, J. Park, Y. M. Chi, J. Viventi, J. Rogers, and G. Cauwenberghs, “85 dB dy-
namic range 1.2 mW 156 kS/s biopotential recording IC for high-density ECoG flexible
active electrode array,” in IEEE European Solid State Circuits Conference. (ESSCIRC),
pp. 141–144, 2013.

[11] Y. Chae, K. Souri, and K. A. Makinwa, “A 6.3 µW 20 bit incremental zoom-ADC with 6
ppm INL and 1 µV offset,” IEEE Journal of Solid-State Circuits, vol. 45, pp. 1099–1110,
June 2010.

[12] A. Agah, K. Vleugels, P. B. Griffin, M. Ronaghi, J. D. Plummer, B. A. Wooley, “A High-

Resolution Low-Power Incremental ADC With Extended Range for Biosensor Arrays,”
IEEE Journal of Solid-State Circuits, vol. 45, pp. 1099–1110, June 2010.

[13] C.-H. Chen, Y. Zhang, T. He, P. Chiang, and G. C. Temes, “A 11 µW 250 Hz BW

two-step incremental ADC with 100 dB DR and 91 dB SNDR for integrated sensor
interfaces,” in IEEE Custom Integrated Circuits Conference (CICC), pp. 1–4 , 2014.

[14] Y. Chae and G. Han, “Low Votlage, Low Power, Inverter-Based Switched-Capacitor
Delta-Sigma Modulator,” IEEE Journal of Solid-State Circuits, vol. 44, pp. 458 – 472 ,
February 2009.

[15] T. Christen, “A 15-bit 140µW scalable-bandwidth inverter-based modulator for a MEMS

microphone with digital output,” IEEE Journal of Solid-State Circuits, vol. 48, pp. 1–11
, July 2013.

[16] M. J. M. Pelgrom, Analog-to-Digital Conversion. Dordrecht, The Netherlands: Springer,

2010.

[17] R. Schreier and G. C. Temes, Understanding Delta-Sigma Data Converters. Wiley-IEEE

Press, November 2004.

[18] S. R. Norsworthy, R. Schreier, and G. C. Temes, Delta-Sigma Data Converters: Theory,

Design, and Simulation. New York: IEEE Press, 1996.

[19] J. Márkus, P. Deval, V. Quiquempoix, J. Silva, and G. C. Temes, “Incremental Delta-

Sigma Structures for DC Measurement: an Overview (Invited Paper),” in IEEE Custom
Integrated Circuits Conference (CICC), pp. 411–418 , 2006.

[20] J. Márkus, J. Silva, and G. C. Temes, “Theory and Application of Incremental ∆Σ

Converters,” IEEE Transactions on Circuits and Systems-I: Regular Papers, vol. 51,
pp. 678–690 , April 2004.

[21] V. Quiquempoix, P. Deval, A. Barreto, G. Bellini, J. Márkus, J. Silva, and G. C. Temes,

“A Low-Power 22-bit Incremental ADC,” IEEE Journal of Solid-State Circuits, vol. 41,
pp. 1562 – 1571 , November 2006.

Georgios Karykis Master of Science Thesis

 89

[22] A. Agah, K. Vleugels, P. B. Griffin, M. Ronaghi, J. D. Plummer, and B. A. Wooley, “A

High-Resolution Low-Power Incremental Σ∆ ADC With Extended Range for Biosensor
Arrays,” IEEE Journal of Solid-State Circuits, vol. 45, pp. 1099–1110 , June 2010.

[23] J. Márkus, Higher-order Incremental Delta-Sigma Analog-to-Digital Converters. Ph.D.

Thesis, Budapest University of Technology and Economics, Budapest, Hungrary, 2005.

[24] M. A. P. Pertijs and J. H. Huijsing, Precision Temperature Sensors in CMOS Technology.

Dordrecht, The Netherlands: Springer, 2006.

[25] C. Chen, Energy-Efficient Self-Timed Zero-Crossing-Based Incremental Delta-Sigma

ADC. MSc. Thesis, Delft, The Netherlands, 2012.

[26] H.Venkatram, B.Hershberg, and U-K.Moon, “Asynchronous CLS for Zero Crossing
Based Circuits,” in IEEE International Conference on Electronics, Circirts and Systems
(ICECS), pp. 1025 – 1028 , 2010.

[27] T. Sepke, P. Holloway, C. G. Sodini, and H.-S. Lee, “Noise Analysis for Comparator-
Based Circuits,” IEEE Transactions on Circuits and Systems-I: Regular Papers, vol. 56,
pp. 541 – 533 , March 2009.

[28] T. Sepke, Comparator Design and Analysis for Comparator-Based Switched-Capacitor

Circuits. Ph.D Thesis, Massachusetts Institute of Technology, Cambridge, MA, United
States, September 2006.

[29] R. Schreier, J. Silva, J. Steensgaard, and G. C. Temes, “Design-Oriented Estimation

of Thermal Noise in Switched-Capacitor Circuits,” IEEE Transactions on Circuits and
Systems-I: Regular Papers, vol. 52, pp. 2358 – 2368 , November 2005.

[30] J. Phillips and K. Kundert, “Noise in Mixers, Oscillators, Samplers, and Logic. An
Introduction to Cyclostationary Noise,” The Designer’s Guide Community, May 2000.

[31] B. Razavi, Design of Analog CMOS Integrated Circuits . Boston: McGraw-Hill, 2001.

[32] W. M. C. Sansen, Analog Design Essentials. Dordrecht, The Netherlands: Springer,

2006.

[33] C. C. Enz and G. C. Temes, “Circuit Techniques for Reducing the Effects of Op-Amp
Imperfections: Autozeroing, Correlated Double Sampling, and Chopper Stabilization,”
Proceedings of the IEEE, vol. 84, pp. 1584 – 1614 , November 1996.

[34] M. C. Guyton, A Low-Voltage Zero-Crossing-Based Delta-Sigma Analog-to-Digital Con-

verter. Ph.D Thesis, Massachusetts Institute of Technology, Cambridge, MA, United
States, July 2010.

[35] D. A. Johns and K. Martin, Analog Integrated Circuit Design . New Jersey: Wiley, 1996.

[36] Manual of Keithley SourceMeter SMU Instruments: Series 2400.

[37] Datasheet of TI LP38511-ADJ: 800mA Fast-Transient Response Adjustable Low-Dropout

Linear Voltage Regulator . Analog Devices, 2012.

Master of Science Thesis Georgios Karykis

90 Bibliography

[38] Manual of Yokogawa GS200 Precision DC Voltage/Current Source.

[39] J. Silva, U. Moon, J. Steengard, and G. Temes, “Wideband low distortion delta-sigma
ADC topology,” IEEE Electronics letters, vol. 37, pp. 737–738, June 2001.

[40] H. Park, K. Nam, D. K. Su, K. Vleugels, and B. A. Wooley, “A 0.7-V 870-µW Digital-
Audio CMOS Sigma-Delta Modulator,” IEEE Journal of Solid-State Circuits, vol. 44,
April 2009.

[41] Libin Yao, Michiel Steyaert, Willy Sansen, Low-Power Low-Voltage Sigma-Delta Modu-
lators in Nanometer CMOS. New York: Springer-Verlag, 2006.

[42] L. Yao, M. Steyaert, W. Sansen, “A 1-V 140-µW 88-dB audio sigma-delta modulator
in 90-nm CMOS,” IEEE Journal of Solid-State Circuits, vol. 39, pp. 1809 – 1818 ,
November 2004.

[43] O. Choksi, L.R. Carley, “Analysis of switched-capacitor common-mode feedback circuit,”

Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on,
vol. 50, pp. 906 – 917 , December 2004.

[44] L. Lah, J. Choma, J. Draper, “A continuous-time common-mode feedback circuit

(CMFB) for high-impedance current-mode applications,” Circuits and Systems II: Ana-
log and Digital Signal Processing, IEEE Transactions on, vol. 47, pp. 1057–7130 , August
2002.

[45] Ken Kundert, Olaf Zinke, The Designer’s Guide to Verilog-AMS. Springer, 2004.

[46] CMOS14 Design Manual, version 4.05. NXP Semiconductors (Confidential), December
2010.

[47] K. Kundert, “Simulating Switched-Capacitor Filters with SpectreRF,” The Designer’s

Guide Community, July 2006.

[48] B. Murmann, “Thermal Noise in Track-and-Hold Circuits: Analysis and simulation tech-
niques.,” IEEE Solid State Circuits magazine , pp. 46–54 , Spring 2012.

[49] Manolis Terrovitis, Ken Kundert, “Device Noise Simulation of ∆Σ Modulators,” The
Designer’s Guide Community, August 1999.

[50] B. Schell and Y. Tsividis, “A Low Power Tunable Delay Element Suitable for Asyn-
chronous Delays of Burst Information,” IEEE Journal of Solid-State Circuits, vol. 43,
May 2008.

[51] T. B. Cho and P. R. Gray, “A 10 b, 20 Msample/s, 35 mW Pipeline A/D Converter,”

IEEE Journal of Solid-State Circuits, vol. 30, March 1995.

[52] Datasheet of ADR4520/ADR4525/ADR4530/ADR4533/ADR4540/ADR4550: Ultralow

Noise, High Accuracy Voltage References . Analog Devices, 2012.

[53] Datasheet of LTC6655: 0.25ppm Noise, Low Drift Precision References . Linear Tech-
nology, 2012.

Georgios Karykis Master of Science Thesis

 91

[54] Cyclone II Device Handbook (Volume 1). Altera Corporation, February 2008.

[55] Datasheet of AD5791: 1 ppm 20-Bit 1 LSB INL Voltage Output DAC . Analog Devices,
2013.

Master of Science Thesis Georgios Karykis

92 Bibliography

Georgios Karykis Master of Science Thesis