Assignment No 4
Name : Muhammad Saqib
Degree: M.Sc. Electrical Eng.
Subject : MEMS
Department : Electrical Eng.
Reg. No : 2022-MS-EE-18
Date : / / 2023
Question:
Design CMOS in MOCROWIND Software.
CMOS
The term “CMOS” stands for “complementary-symmetry
metal–oxide–semiconductor,” which is pronounced as
“see mos.” CMOS is a type of MOSFET where its
fabrication process uses complementary & symmetrical P-
type & N-type MOSFET pairs for logic functions. The
main CMOS device characteristics are consumption of
low static power & high noise immunity. The inverter is
accepted universally as the basic logic gate while
performing a Boolean operation on a single i/p variable. A
basic inverter circuit is used to accomplish a logic
variable by complementing from A to A’. So, a CMOS
inverter is a very simple circuit designed with two
opposite-polarity MOSFETs in a complementary way.
This article discusses an overview of the CMOS inverter
and its working with applications.
CMOS inverter definition is a device that is used to
generate logic functions known as CMOS inverter and is
an essential component in all integrated circuits. A CMOS
inverter is a FET (field effect transistor) composed of a
metal gate that lies on top of oxygen’s insulating layer on
top of a semiconductor. These inverters are used in most
electronic devices accountable for generating data n small
circuits.
CMOS Inverter Symbol & Truth Table
The working of a CMOS inverter is the same as other
types of FETs, except it depends on an oxygen layer to
divide electrons within the gate & semiconductor. They
are designed with a power supply, input voltage terminal,
output voltage, gate, drain, and PMOS & NMOS
transistors connected to the gate & drain terminals.
When the low input voltage is given to the CMOS
inverter, then the PMOS transistor is switched ON
whereas the NMOS transistor will switch OFF by
allowing the flow of electrons throughout the gate
terminal & generating high logic output voltage.
Similarly, when the high input voltage is given to the
CMOS inverter, then the PMOS transistor is switched
OFF, whereas the NMOS transistor will be switched ON,
preventing as many electrons from attaining the output
voltage & generating low logic output voltage.
CMOS Simulation step by step
Select the PMOS
Select the N-MOS
Fig. of P&N- MOS
Connect the gate of P&N-MOS
Apply the voltages at the Vg, Vdd, and Vss.
OUTPUT Signal
