DATA SHEET

MOS INTEGRATED CIRCUIT

µPD784035(A), 784036(A)
16/8-BIT SINGLE-CHIP MICROCONTROLLER

The µPD784036(A) is a product of the µPD784038 sub-series in the 78K/IV series. A stricter quality assurance
program applies to the µPD784036(A) than the µPD784036 (standard product). In terms of the NEC quality, the
µPD784036(A) is classified as the special grade.
The µPD784036(A) contains various peripheral hardware such as ROM, RAM, I/O ports, 8-bit resolution A/D and
D/A converters, timers, serial interface, and interrupt functions, as well as a high-speed, high-performance CPU.
In addition, the µPD78P4038(A) (one-time PROM or EPROM product), which can be operated within the same
power supply voltage ranges as masked-ROM products, and development tools are supported.

For specific functions and other detailed information, consult the following user’s manual.
This manual is required reading for design work.
µPD784038, 784038Y Sub-Series User’s Manual, Hardware : U11316E
78K/IV Series User’s Manual, Instruction : U10905E

FEATURES
• Higher reliability than the µPD784036 (Refer to Qual- • PWM outputs: 2
ity Grade on NEC Semiconductor Devices (Document • Serial interface: 3 channels
number C11531E).) UART/IOE (3-wire serial I/O): 2 channels
• Minimum instruction execution time: 125 ns CSI (3-wire serial I/O, 2-wire serial I/O): 1 channel
(at 32 MHz) • Clock frequency division function
• Number of I/O ports: 64 • Watchdog timer: 1 channel
• Timer/counters • Clock output function
16-bit timer/counter × 3 units Selected from fCLK, fCLK/2, fCLK/4, fCLK/8, or fCLK/16
16-bit timer × 1 unit • Power supply voltage: VDD = 2.7 to 5.5 V
• A/D converter: 8-bit resolution × 8 channels
• D/A converter: 8-bit resolution × 2 channels
• Standby function
HALT/STOP/IDLE mode

APPLICATIONS
Controllers for automobile electronic control systems, gas detector circuit-breakers, various types of safety
equipment, etc.

This manual describes the µPD784036(A) unless otherwise specified.

The information in this document is subject to change without notice.

Document No. U13010EJ1V0DS00 (1st edition)

Date Published December 1997 J
Printed in Japan
© 1997
 µPD784035(A), 784036(A)

ORDERING INFORMATION
Part number Package Internal ROM Internal RAM
(bytes) (bytes)
µPD784035GC(A)-×××-3B9 80-pin plastic QFP (14 × 14 mm) 48K 2 048
µPD784036GC(A)-×××-3B9 80-pin plastic QFP (14 × 14 mm) 64K 2 048

Remark ××× is a ROM code suffix.

QUALITY GRADE

Part number Package Quality grade

µPD784035GC(A)-×××-3B9 80-pin plastic QFP (14 × 14 mm) Special
µPD784036GC(A)-×××-3B9 80-pin plastic QFP (14 × 14 mm) Special

Remark ××× is a ROM code suffix.

Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by
NEC Corporation to know the specification of quality grade on the devices and its recommended applications.

2
 µPD784035(A), 784036(A)

78K/IV SERIES PRODUCT DEVELOPMENT DIAGRAM

: Under mass production

: Under development

I2C bus supported Multimaster I2C bus supported

µPD784038Y µPD784225Y
Standard models µPD784038 µPD784225
Enhanced internal memory capacity, 80 pins,
µPD784026 pin compatible with the µPD784026 added ROM correction

Enhanced A/D, Multimaster I2C bus supported Multimaster I2C bus supported
16-bit timer,
and power µPD784216Y µPD784218Y
management
µPD784216 µPD784218
100 pins, Enhanced internal memory capacity,
enhanced I/O and added ROM correction
internal memory capacity

µPD784054

µPD784046
ASSP models Equipped with 10-bit A/D

µ PD784955
For DC inverter control

µ PD784908
Equipped with IEBusTM
controller

µPD784943 Multimaster I2C bus supported

For CD-ROM µ PD784928Y
µ PD784928

µPD784915 Enhanced function of the µPD784915

For software servo control,

equipped with analog circuit
for VCR,
enhanced timer

3
 µPD784035(A), 784036(A)

FUNCTIONS
Product
Item µPD784035(A) µPD784036(A)

Number of basic instructions 113

(mnemonics)
General-purpose register 8 bits × 16 registers × 8 banks, or 16 bits × 8 registers × 8 banks (memory mapping)
Minimum instruction execution 125 ns/250 ns/500 ns/1 000 ns (at 32 MHz)
time
Internal ROM 48K bytes 64K bytes
memory RAM 2 048 bytes
Memory space Program and data: 1M byte
I/O ports Total 64
Input 8
Input/output 56
Additional Pins with pull- 54
function up resistor
pinsNote 24
LED direct
drive outputs
Transistor 8
direct drive
Real-time output ports 4 bits × 2, or 8 bits × 1
Timer/counter Timer/counter 0: Timer register × 1 Pulse output capability
(16 bits) Capture register × 1 • Toggle output
Compare register × 2 • PWM/PPG output
• One-shot pulse output
Timer/counter 1: Timer register × 1 Pulse output capability
(8/16 bits) Capture register × 1 • Real-time output (4 bits × 2)
Capture/compare register × 1
Compare register × 1
Timer/counter 2: Timer register × 1 Pulse output capability
(8/16 bits) Capture register × 1 • Toggle output
Capture/compare register × 1 • PWM/PPG output
Compare register × 1
Timer 3 : Timer register × 1
(8/16 bits) Compare register × 1
PWM outputs 12-bit resolution × 2 channels
Serial interface UART/IOE (3-wire serial I/O) : 2 channels (incorporating baud rate generator)
CSI (3-wire serial I/O, 2-wire serial I/O): 1 channel
A/D converter 8-bit resolution × 8 channels
D/A converter 8-bit resolution × 2 channels
Clock output Selected from fCLK, fCLK/2, fCLK/4, fCLK/8, fCLK/16 (can be used as a 1-bit output port)
Watchdog timer 1 channel
Standby HALT/STOP/IDLE mode
Interrupt Hardware source 23 (16 internal, 7 external (sampling clock variable input: 1))
Software source BRK instruction, BRKCS instruction, operand error
Nonmaskable 1 internal, 1 external
Maskable 15 internal, 6 external
• 4-level programmable priority
• 3 operation statuses: vectored interrupt, macro service, context switching
Supply voltage VDD = 2.7 to 5.5 V
Package 80-pin plastic QFP (14 × 14 mm)

Note Additional function pins are included in the I/O pins.

4
 µPD784035(A), 784036(A)

CONTENTS

1. DIFFERENCES BETWEEN µPD784038 SUB-SERIES SPECIAL PRODUCTS .................... 7

2. DIFFERENCES BETWEEN STANDARD AND SPECIAL PRODUCTS .................................. 7

3. PIN CONFIGURATION (TOP VIEW) ......................................................................................... 8

4. BLOCK DIAGRAM ..................................................................................................................... 10

5. LIST OF PIN FUNCTIONS ......................................................................................................... 11

5.1 Port Pins ............................................................................................................................................ 11
5.2 Non-Port Pins ................................................................................................................................... 13
5.3 I/O Circuits for Pins and Handling of Unused Pins .................................................................... 15

6. CPU ARCHITECTURE ............................................................................................................... 18

6.1 Memory Space .................................................................................................................................. 18
6.2 CPU Registers .................................................................................................................................. 21
6.2.1 General-purpose registers ................................................................................................ 21
6.2.2 Control registers ................................................................................................................ 22
6.2.3 Special function registers (SFRs) .................................................................................... 23

7. PERIPHERAL HARDWARE FUNCTIONS ................................................................................ 28

7.1 Ports ................................................................................................................................................... 28
7.2 Clock Generator ............................................................................................................................... 29
7.3 Real-Time Output Port ..................................................................................................................... 31
7.4 Timers/Counters ............................................................................................................................... 32
7.5 PWM Output (PWM0, PWM1) .......................................................................................................... 34
7.6 A/D Converter ................................................................................................................................... 35
7.7 D/A Converter ................................................................................................................................... 36
7.8 Serial Interface ................................................................................................................................. 37
7.8.1 Asynchronous serial interface/three-wire serial I/O (UART/IOE) ................................ 38
7.8.2 Synchronous serial interface (CSI) .................................................................................. 40
7.9 Clock Output Function .................................................................................................................... 41
7.10 Edge Detection Function ................................................................................................................ 42
7.11 Watchdog Timer ............................................................................................................................... 42

8. INTERRUPT FUNCTION ............................................................................................................ 43

8.1 Interrupt Source ............................................................................................................................... 43
8.2 Vectored Interrupt ............................................................................................................................ 45
8.3 Context Switching ............................................................................................................................ 46
8.4 Macro Service ................................................................................................................................... 46
8.5 Examples of Macro Service Applications ..................................................................................... 47

5
 µPD784035(A), 784036(A)

9. LOCAL BUS INTERFACE ......................................................................................................... 49

9.1 Memory Expansion .......................................................................................................................... 49
9.2 Memory Space .................................................................................................................................. 50
9.3 Programmable Wait ......................................................................................................................... 51
9.4 Pseudo-Static RAM Refresh Function .......................................................................................... 51
9.5 Bus Hold Function ........................................................................................................................... 51

10. STANDBY FUNCTION ............................................................................................................... 52

11. RESET FUNCTION ..................................................................................................................... 53

12. INSTRUCTION SET .................................................................................................................... 54

13. ELECTRICAL CHARACTERISTICS ......................................................................................... 59

14. PACKAGE DRAWINGS ............................................................................................................. 80

15. RECOMMENDED SOLDERING CONDITIONS ........................................................................ 81

APPENDIX A DEVELOPMENT TOOLS .......................................................................................... 82

APPENDIX B RELATED DOCUMENTS ......................................................................................... 85

6
 µPD784035(A), 784036(A)

1. DIFFERENCES BETWEEN µPD784038 SUB-SERIES SPECIAL PRODUCTS

The only difference between the µPD784031(A), µPD784035(A), and µPD784036(A) is their capacity of internal
memory.
The µPD78P4038(A) is produced by replacing the masked ROM in the µPD784031(A), µPD784035(A), or
µPD784036(A) with 128K-byte one-time PROM or EPROM. Table 1-1 shows the differences between these products.

Table 1-1. Differences between the µPD784038 Sub-Series Special Products

Product µPD784031(A) µPD784035(A) µPD784036(A) µPD78P4038(A)

Item (under develoment)
Internal ROM None 48K bytes 64K bytes 128K bytes
(masked ROM) (masked ROM) (one-time PROM or
EPROM)
Internal RAM 2 048 bytes 4 352 bytes

2. DIFFERENCES BETWEEN STANDARD AND SPECIAL PRODUCTS

Table 2-1 shows the differences between standard and special products.

Table 2-1. Differences between Standard and Special Products

Product
µPD784035(A), µPD784036(A) µPD784035, µPD784036, µPD784037, µPD784038
Item
Quality grade Special Standard

Package 80-pin plastic QFP (14 × 14 × 2.7 mm) 80-pin plastic QFP (14 × 14 × 2.7 mm)
80-pin plastic QFP (14 × 14 × 1.4 mm)
80-pin plastic TQFP (fine pitch, 12 × 12 mm)

7
 µPD784035(A), 784036(A)

3. PIN CONFIGURATION (TOP VIEW)

• 80-pin plastic QFP (14 × 14 mm)

µPD784031GC(A)-×××-3B9, µPD784036GC(A)-×××-3B9

P25/INTP4/ASCK/SCK1
P31/ TxD/SO1

P23/INTP2/CI
P30/RxD/SI1

P22/INTP1
P24/INTP3
P26/INTP5

P21/INTP0

P77/ANI7
P76/ANI6
P75/ANI5
P20/NMI
P27/SI0

AVREF3
AVREF2

AVREF1
ANO1
ANO0

AVDD
AVSS
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
P32/SCK0/SCL 1 60 P74/ANI4
P33/SO0/SDA 2 59 P73/ANI3
P34/ TO0 3 58 P72/ANI2
P35/ TO1 4 57 P71/ANI1
P36/ TO2 5 56 P70/ANI0
P37/ TO3 6 55 VDD0
RESET 7 54 P17
VDD1 8 53 P16
X2 9 52 P15
X1 10 51 P14/TXD2/SO2
VSS1 11 50 P13/RXD2/SI2
P00 12 49 P12/ASCK2/SCK2
P01 13 48 P11/PWM1
P02 14 47 P10/PWM0
P03 15 46 TESTNote
P04 16 45 VSS0
P05 17 44 ASTB/CLKOUT
P06 18 43 P40/AD0
P07 19 42 P41/AD1
P67/REFRQ/HLDAK 20 41 P42/AD2
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
P66/ WAIT/HLDRQ
P65/WR
P64/RD
P63/A19
P62/A18
P61/A17
P60/A16
P57/A15
P56/A14
P55/A13
P54/A12
P53/A11
P52/A10
P51/A9
P50/A8
P47/AD7
P46/AD6
P45/AD5
P44/AD4
P43/AD3

Note Connect the TEST pin to VSS0 directly.

8
 µPD784035(A), 784036(A)

A8-A19 : Address bus P60-P67 : Port 6

AD0-AD7 : Address/data bus P70-P77 : Port 7
ANI0-ANI7 : Analog input PWM0, PWM1 : Pulse width modulation output
ANO0, ANO1 : Analog output RD : Read strobe
ASCK, ASCK2 : Asynchronous serial clock REFRQ : Refresh request
ASTB : Address strobe RESET : Reset
AVDD : Analog power supply RxD, RxD2 : Receive data
AVREF1-AVREF3 : Reference voltage SCK0-SCK2 : Serial clock
AVSS : Analog ground SCL : Serial clock
CI : Clock input SDA : Serial data
CLKOUT : Clock output SI0-SI2 : Serial input
HLDAK : Hold acknowledge SO0-SO2 : Serial output
HLDRQ : Hold request TEST : Test
INTP0-INTP5 : Interrupt from peripherals TO0-TO3 : Timer output
NMI : Non-maskable interrupt TxD, TxD2 : Transmit data
P00-P07 : Port 0 VDD0, VDD1 : Power supply
P10-P17 : Port 1 VSS0, VSS1 : Ground
P20-P27 : Port 2 WAIT : Wait
P30-P37 : Port 3 WR : Write strobe
P40-P47 : Port 4 X1, X2 : Crystal
P50-P57 : Port 5

9
 µPD784035(A), 784036(A)

4. BLOCK DIAGRAM

RxD/SI1
UART/IOE2
TxD/SO1
NMI Baud-rate
Programmable ASCK/SCK1
interrupt controller generator
INTP0-INTP5
RxD2/SI2
UART/IOE1
TxD2/SO2
INTP3
Timer/counter 0 Baud-rate
TO0 ASCK2/SCK2
(16 bits) generator
TO1
SCK0/SCL
Clocked serial
INTP0 Timer/counter 1 SO0/SDA
interface
(16 bits)
SI0
78K /IV ASTB/CLKOUT
INTP1 ROM Clock output
CPU core AD0-AD7
INTP2/CI Timer/counter 2
TO2 (16 bits) A8-A15
TO3 A16-A19
Bus interface
RD
Timer 3 WR
(16 bits) WAIT/HLDRQ
REFRQ/HLDAK
P00-P03 Port 0 P00-P07
Real-time output
port
P04-P07
RAM Port 1 P10-P17

PWM0
PWM Port 2 P20-P27
PWM1

Port 3 P30-P37
ANO0
ANO1
D/A converter Port 4 P40-P47
AVREF2
AVREF3
Port 5 P50-P57

ANI0-ANI7 Port 6 P60-P67

AVDD
AVREF1 A/D converter Port 7 P70-P77
AVSS
RESET
INTP5 Watchdog timer TEST
System control X1
X2
VDD0, VDD1
VSS0, VSS1

Remark The internal ROM capacity differs for each product.

10
 µPD784035(A), 784036(A)

5. LIST OF PIN FUNCTIONS

5.1 Port Pins (1/2)

Pin I/O Dual-function Function

P00-P07 I/O - Port 0 (P0):
• 8-bit I/O port.
• Functions as a real-time output port (4 bits × 2).
• Inputs and outputs can be specified bit by bit.
• The use of the pull-up resistors can be specified by software for the pins
in input mode together.
• Can drive a transistor.

P10 I/O PWM0 Port 1 (P1):

P11 PWM1 • 8-bit I/O port.

P12 ASCK2/SCK2 • Inputs and outputs can be specified bit by bit.

P13 RxD2/SI2 • The use of the pull-up resistors can be specified by software for the pins
in input mode together.
P14 TxD2/SO2
• Can drive LED.
P15-P17 -

P20 Input NMI Port 2 (P2):

P21 INTP0 • 8-bit input-only port.

P22 INTP1 • P20 does not function as a general-purpose port (nonmaskable

interrupt). However, the input level can be checked by an interrupt
P23 INTP2/CI
service routine.
P24 INTP3
• The use of the pull-up resistors can be specified by software for pins
P25 INTP4/ASCK/SCK1 P22 to P27 (in units of 6 bits).
P26 INTP5 • The P25/INTP4/ASCK/SCK1 pin functions as the SCK1 output pin by
P27 SI0 CSIM1.

P30 I/O RxD/SI1 Port 3 (P3):

P31 TxD/SO1 • 8-bit I/O port.

P32 SCK0/SCL • Inputs and outputs can be specified bit by bit.

P33 SO0/SDA • The use of the pull-up resistors can be specified by software for the pins
in input mode together.
P34-P37 TO0-TO3

P40-P47 I/O AD0-AD7 Port 4 (P4):

• 8-bit I/O port.
• Inputs and outputs can be specified bit by bit.
• The use of the pull-up resistors can be specified by software for the pins
in the input mode together.
• Can drive LED.

P50-P57 I/O A8-A15 Port 5 (P5):

• 8-bit I/O port.
• Inputs and outputs can be specified bit by bit.
• The use of the pull-up resistors can be specified by software for the pins
in the input mode together.
• Can drive LED.

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 µPD784035(A), 784036(A)

5.1 Port Pins (2/2)

Pin I/O Dual-function Function

P60-P63 I/O A16-A19 Port 6 (P6):

P64 RD • 8-bit I/O port.

P65 WR • Inputs and outputs can be specified bit by bit.

P66 WAIT/HLDRQ • The use of the pull-up resistors can be specified by software for the pins
in the input mode together.
P67 REFRQ/HLDAK
P70-P77 I/O ANI0-ANI7 Port 7 (P7):
• 8-bit I/O port.
• Inputs and outputs can be specified bit by bit.

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 µPD784035(A), 784036(A)

5.2 Non-Port Pins (1/2)

Pin I/O Dual-function Function

TO0-TO3 Output P34-P37 Timer output
CI Input P23/INTP2 Input of a count clock for timer/counter 2
R XD Input P30/SI1 Serial data input (UART0)
RXD2 P13/SI2 Serial data input (UART2)
T XD Output P31/SO1 Serial data output (UART0)
TXD2 P14/SO2 Serial data output (UART2)
ASCK Input P25/INTP4/SCK1 Baud rate clock input (UART0)
ASCK2 P12/SCK2 Baud rate clock input (UART2)
SDA I/O P33/SO0 Serial data I/O (2-wire serial I/O)
SI0 Input P27 Serial data input (3-wire serial I/O0)
SI1 P30/RXD Serial data input (3-wire serial I/O1)
SI2 P13/RXD2 Serial data input (3-wire serial I/O2)
SO0 Output P33/SDA Serial data output (3-wire serial I/O0)
SO1 P31/TXD Serial data output (3-wire serial I/O1)
SO2 P14/TXD2 Serial data output (3-wire serial I/O2)
SCK0 I/O P32/SCL Serial clock I/O (3-wire serial I/O0)
SCK1 P25/INTP4/ASCK Serial clock I/O (3-wire serial I/O1)
SCK2 P12/ASCK2 Serial clock I/O (3-wire serial I/O2)
SCL P32/SCK0 Serial clock I/O (2-wire serial I/O)
NMI Input P20 External interrupt -
INTP0 P21 reguest • Input of a count clock for timer/counter 1
• Capture/trigger signal for CR11 or CR12
INTP1 P22 • Input of a count clock for timer/counter 2
• Capture/trigger signal for CR22
INTP2 P23/CI • Input of a count clock for timer/counter 2
• Capture/trigger signal for CR21
INTP3 P24 • Input of a count clock for timer/counter 0
• Capture/trigger signal for CR02
INTP4 P25/ASCK/SCK1 -
INTP5 P26 Input of a conversion start trigger for A/D converter
AD0-AD7 I/O P40-P47 Time multiplexing address/data bus (for connecting external memory)
A8-A15 Output P50-P57 High-order address bus (for connecting external memory)
A16-A19 Output P60-P63 High-order address bus during address expansion (for connecting external memory)
RD Output P64 Strobe signal output for reading the contents of external memory
WR Output P65 Strobe signal output for writing on external memory
WAIT Input P66/HLDRQ Wait signal insertion
REFRQ Output P67/HLDAK Refresh pulse output to external pseudo static memory
HLDRQ Input P66/WAIT Input of bus hold request
HLDAK Output P67/REFRQ Output of bus hold response
ASTB Output CLKOUT Latch timing output of time multiplexing address (A0-A7) (for
connecting external memory)
CLKOUT Output ASTB Clock output

13
 µPD784035(A), 784036(A)

5.2 Non-Port Pins (2/2)

Pin I/O Dual-function Function

RESET Input - Chip reset
X1 Input - Crystal input for system clock oscillation (A clock pulse can also be input
X2 - to the X1 pin.)

ANI0-ANI7 Input P70-P77 Analog voltage inputs for the A/D converter

ANO0, ANO1 Output - Analog voltage outputs for the D/A converter

AVREF1 - - Application of A/D converter reference voltage

AVREF2, AVREF3 Application of D/A converter reference voltage

AVDD Positive power supply for the A/D converter

AVSS Ground for the A/D converter

VDD0Note 1 Positive power supply of the port part

VDD1Note 1 Positive power supply except for the port part

VSS0Note 2 Ground of the port part

VSS1Note 2 Ground except for the port part

TEST Directly connect to VSS0. (The TEST pin is for the IC test.)

Notes 1. The potential of the VDD0 pin must be equal to that of the VDD1 pin.
2. The potential of the VSS0 pin must be equal to that of the VSS1 pin.

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 µPD784035(A), 784036(A)

5.3 I/O Circuits for Pins and Handling of Unused Pins

Table 5-1 describes the types of I/O circuits for pins and the handling of unused pins.
See Figure 5-1 for the configuration of these various types of I/O circuits.

Table 5-1. Types of I/O Circuits for Pins and Handling of Unused Pins (1/2)

Pin I/O circuit type I/O Recommended connection method for unused pins

P00-P07 5-H I/O Input state : Connect these pins to VDD0.

P10/PWM0 Output state: Leave open.

P11/PWM1

P12/ASCK2/SCK2 8-C

P13/RxD2/SI2 5-H

P14/TxD2/SO2

P15-P17

P20/NMI 2 Input Connect these pins to VDD0 or VSS0.

P21/INTP0

P22/INTP1 2-C Connect these pins to VDD0.

P23/INTP2/CI

P24/INTP3

P25/INTP4/ASCK/SCK1 8-C I/O Input state : Connect these pins to VDD0.

Output state: Leave open.

P26/INTP5 2-C Input Connect these pins to VDD0.

P27/SI0

P30/RxD/SI1 5-H I/O Input state : Connect these pins to VDD0.

P31/TxD/SO1 Output state: Leave open.

P32/SCK0/SCL 10-B

P33/SO0/SDA

P34/TO0-P37/TO3 5-H

P40/AD0-P47/AD7

P50/A8-P57/A15

P60/A16-P63/A19

P64/RD

P65/WR

P66/WAIT/HLDRQ

P67/REFRQ/HLDAK

P70/ANI0-P77/ANI7 20-A I/O Input state : Connect these pins to VDD0 or VSS0.
Output state: Leave open.

ANO0, ANO1 12 Output Leave open.

ASTB/CLKOUT 4-B

15
 µPD784035(A), 784036(A)

Table 5-1. Types of I/O Circuits for Pins and Handling of Unused Pins (2/2)

Pin I/O circuit type I/O Recommended connection method for unused pins

RESET 2 Input -

TEST 1-A Connect this pin to VSS0 directly.

AVREF1-AVREF3 - Connect these pins to VSS0.

AVSS

AVDD Connect this pin to VDD0.

Caution When I/O mode of an I/O dual-function pin is unpredictable, connect the pin to VDD0 through a
resistor of 10 to 100 kilohms (particularly when the voltage of the reset input pin becomes higher
than that of the low level input at power-on or when I/O is switched by software).

Remark Since type numbers are consistent in the 78K series, those numbers are not always serial in each product.
(Some circuits are not included.)

16
 µPD784035(A), 784036(A)

Figure 5-1. I/O Circuits for Pins

Type 1-A VDD0 Type 2-C

VDD0
P

IN Pull-up
P enable
N

VSS0 IN
Type 2

Schmitt trigger input with hysteresis characteristics

IN
Type 5-H
VDD0
Schmitt trigger input with hysteresis characteristics
Type 4-B VDD0
Pull-up
enable P
VDD0
Data P Data P
OUT IN/OUT
Output N Output N
disable disable
VSS0
VSS0
Input
Push-pull output which can output high impedance enable
(both the positive and negative channels are off.)
Type 8-C Type 12
VDD0

Pull-up
enable P
VDD0
Data P P
Analog output
IN/OUT voltage OUT
Output N
N
disable
VSS0

Type 10-B Type 20-A

VDD0
VDD0
Data P
Pull-up IN/OUT
enable P

VDD0 Output N
disable
Data P VSS0
Open IN/OUT Comparator
drain P
N +
Output – N
disable VSS0
AVREF AVSS
(Threshold voltage)

Input
enable

17
 µPD784035(A), 784036(A)

6. CPU ARCHITECTURE

6.1 Memory Space

A 1M-byte memory space can be accessed. By using a LOCATION instruction, mode for mapping internal data
areas (special function registers and internal RAM) can be selected. A LOCATION instruction must always be
executed after a reset, and can be used only once.

(1) When the LOCATION 0 instruction is executed

• Internal memory
The table below indicates the internal data areas and internal ROM areas of each product.

Product name Internal data area Internal ROM area

µPD784035(A) 0F700H-0FFFFH 00000H-0BFFFH

µPD784036(A) 00000H-0F6FFH

Caution The following internal ROM areas, existing at the same addresses as the internal data areas,
cannot be used when the LOCATION 0 instruction is executed:

Product name Unusable area

µPD784035(A) -

µPD784036(A) 0F700H-0FFFFH (2 304 bytes)

• External memory
External memory is accessed in external memory expansion mode.

(2) When the LOCATION 0FH instruction is executed

• Internal memory
The table below lists the internal data areas and internal ROM areas for each product.

Product name Internal data area Internal ROM area

µPD784035(A) FF700H-FFFFFH 00000H-0BFFFH

µPD784036(A) 00000H-0FFFFH

• External memory
External memory is accessed in external memory expansion mode.

18
 Figure 6-1. µPD784035(A) Memory Map

When the LOCATION 0

When the LOCATION
instruction is executed
0FH instruction is executed
FF F FF H FFF F F H Special function registers (SFRs)
FFF DFH
FFF D 0 H Note 1
FFF 0 0H (256 bytes)
0 FE FFH FFE FFH FFE FFH
General-purpose Internal RAM
External memory registers (128 bytes) (2 048 bytes)
(960K bytes)Note 1
0 FE 8 0H FFE 8 0H FF7 0 0H
0 FE 7FH FFE 7FH FF6 FFH

10 0 00H 0 FE 2FH Macro service control FFE 2FH

0 F F FF H Special function registers (SFRs)
0 F F DF H Note 1
0 FE 0 6H word area (42 bytes) FFE 0 6H
0 F F D0 H (256 bytes)
0FF 0 0H Data area (512 bytes)
0 F E FF H 0 FD 0 0H FFD 0 0H
Internal RAM 0 FC FFH FFC FFH
(2 048 bytes) Program/data area External memory
(1 536 bytes) (997 120 bytes)Note 1
0F 7 0 0H 0 F 7 0 0H FF7 0 0H
0 F 6 FF H
0B F FFH
Program/data area
(48K bytes)
External memory Note 2

µPD784035(A), 784036(A)
(14 080 bytes)Note 1 0 1 0 0 0H
0 0 F FFH 1 00 0 0H
CALLF entry area 0FF FFH
(2K bytes) Note 2
0C 0 0 0 H 0 0 8 0 0H 0C0 0 0H
0B F FF H 0 0 7 FFH 0BF FFH
0 0 0 8 0H
Internal ROM 0 0 0 7FH CALLT table area
Internal ROM
(48K bytes) 0 0 0 4 0H (64 bytes) (48K bytes)
0 0 0 3FH Vector table area

00 0 00H 0 0 0 0 0H (64 bytes) 0 00 0 0H

Notes 1. Accessed in external memory expansion mode.

19

2. Base area, or entry area based on a reset or interrupt. Internal RAM is excluded in the case of a reset.
20

Figure 6-2. µPD784036(A) Memory Map

When the LOCATION 0 When the LOCATION 0FH

instruction is executed instruction is executed
F FFF FH F F FFF H Special function registers (SFRs)
F F FDF H
F F FD0 H Note 1
F F F0 0 H (256 bytes)
0 FEF FH F FEF FH F FEF FH
General-purpose Internal RAM
External memory (2 048 bytes)
registers (128 bytes)
(960K bytes)Note 1
0 FE8 0 H F FE8 0 H F F70 0H
0 FE7 FH F FE7 FH F F 6 F FH

1 000 0H 0 FE2 FH Macro service control F FE2 FH

0 FFF FH Special function registers (SFRs)
0 FFDFH Note 1
0 FE0 6 H word area (42 bytes) F FE0 6 H
0 FFD0 H (256 bytes)
0 FF 0 0 H Data area (512 bytes)
0 FEF FH 0 FD0 0 H F FD0 0 H
Internal RAM 0 FCF FH F FCF FH
Program/data area
(2 048 bytes) External memory
(1 536 bytes)
0 F70 0H 0 F70 0H F F70 0H (980 736 bytes)Note 1
0 F 6 F FH
Note 2 0 FFF FH
0 F 6 F FH
Program/data areaNote 3
0 100 0H
0 0 FF FH
Internal ROM CALLF entry
(63 232 bytes) Note 4 area (2K bytes)
0 080 0H 1 000 0H
0 0 7 F FH 0 FFF FH

µPD784035(A), 784036(A)
0 008 0H
0 0 0 7 FH CALLT table area
Internal ROM
0 0 0 4 0 H (64 bytes)
Note 4
(64K bytes)
0 0 0 3 FH Vector table area

0 000 0H 0 0 0 0 0 H (64 bytes) 0 000 0H

Notes 1. Accessed in external memory expansion mode.

2. This 2304-byte area can be used as an internal ROM area only when the LOCATION 0FH instruction is executed.
3. When the LOCATION 0 instruction is executed : 63 232 bytes
When the LOCATION 0FH instruction is executed: 65 536 bytes
4. Base area, or entry area based on a reset or interrupt. Internal RAM is excluded in the case of a reset.
 µPD784035(A), 784036(A)

6.2 CPU Registers

6.2.1 General-purpose registers

A set of general-purpose registers consists of sixteen general-purpose 8-bit registers. Two 8-bit general-purpose
registers can be combined to form a 16-bit general-purpose register. Moreover, four 16-bit general-purpose registers,
when combined with an 8-bit register for address extension, can be used as 24-bit address specification registers.
Eight banks of this register set are provided. The user can switch between banks by software or the context
switching function.
General-purpose registers other than the V, U, T, and W registers used for address extension are mapped onto
internal RAM.

Figure 6-3. General-Purpose Register Format

A (R1) X (R0)
AX (RP0)
B (R3) C (R2)
BC (RP1)
R5 R4
RP2
R7 R6
RP3
V R9 R8
VVP (RG4) VP (RP4)
U R11 R10
UUP (RG5) UP (RP5)
T D (R13) E (R12)
TDE (RG6) DE (RP6)
W H (R15) L (R14)
WHL (RG7) HL (RP7) 8 banks

The character strings enclosed in

parentheses represent absolute names.

Caution By setting the RSS bit of PSW to 1, R4, R5, R6, R7, RP2, and RP3 can be used as the X, A, C, B,
AX, and BC registers, respectively. However, this function must be used only when using
programs for the 78K/III series.

21
 µPD784035(A), 784036(A)

6.2.2 Control registers

(1) Program counter (PC)

This register is a 20-bit program counter. The program counter is automatically updated by program execution.

Figure 6-4. Format of Program Counter (PC)

19 0
PC

(2) Program status word (PSW)

This register holds the CPU state. The program status word is automatically updated by program execution.

Figure 6-5. Format of Program Status Word (PSW)

15 14 13 12 11 10 9 8

PSWH UF RBS2 RBS1 RBS0

PSW
7 6 5 4 3 2 1 0

PSWL S Z RSSNote AC IE P/V 0 CY

Note This flag is used to maintain compatibility with the 78K/III series. This flag must be set to 0 when programs
for the 78K/III series are being used.

(3) Stack pointer (SP)

This register is a 24-bit pointer for holding the start address of the stack. The high-order 4 bits must be set
to 0.

Figure 6-6. Format of Stack Pointer (SP)

23 20 0
SP 0 0 0 0

22
 µPD784035(A), 784036(A)

6.2.3 Special function registers (SFRs)

The special function registers are registers with special functions such as mode registers and control registers
for built-in peripheral hardware. The special function registers are mapped onto the 256-byte space between 0FF00H
and 0FFFFHNote.

Note Applicable when the LOCATION 0 instruction is executed. FFF00H-FFFFFH when the LOCATION 0FH
instruction is executed.

Caution Never attempt to access addresses in this area where no SFR is allocated. Otherwise, the
µPD784036(A) may be placed in the deadlock state. The deadlock state can be cleared only by
a reset.

Table 6-1 lists the special function registers (SFRs). The titles of the table columns are explained below.

• Abbreviation ................... Symbol used to represent a built-in SFR. The abbreviations listed in the table are
reserved words for the NEC assembler (RA78K4). The C compiler (CC78K4) allows
the abbreviations to be used as sfr variables with the #pragma sfr command.
• R/W ................................. Indicates whether each SFR allows read and/or write operations.
R/W : Allows both read and write operations.
R : Allows read operations only.
W : Allows write operations only.
• Manipulatable bits .......... Indicates the maximum number of bits that can be manipulated whenever an SFR is
manipulated. An SFR that supports 16-bit manipulation can be described in the sfrp
operand. For address specification, an even-numbered address must be speci-
fied.
An SFR that supports 1-bit manipulation can be described in a bit manipulation
instruction.
• When reset ..................... Indicates the state of each register when RESET is applied.

23
 µPD784035(A), 784036(A)

Table 6-1. Special Function Registers (SFRs) (1/4)

Manipulatable bits
AddressNote Special function register (SFR) name Abbreviation R/W When reset
1 bit 8 bits 16 bits

0FF00H Port 0 P0 R/W - Undefined

0FF01H Port 1 P1 -

0FF02H Port 2 P2 R -

0FF03H Port 3 P3 R/W -

0FF04H Port 4 P4 -

0FF05H Port 5 P5 -

0FF06H Port 6 P6 - 00H

0FF07H Port 7 P7 - Undefined

0FF0EH Port 0 buffer register L P0L -

0FF0FH Port 0 buffer register H P0H -

0FF10H Compare register (timer/counter 0) CR00 - -

0FF12H Capture/compare register (timer/counter 0) CR01 - -

0FF14H Compare register L (timer/counter 1) CR10 CR10W -

0FF15H Compare register H (timer/counter 1) - - -

0FF16H Capture/compare register L (timer/counter 1) CR11 CR11W -

0FF17H Capture/compare register H (timer/counter 1) - - -

0FF18H Compare register L (timer/counter 2) CR20 CR20W -

0FF19H Compare register H (timer/counter 2) - - -

0FF1AH Capture/compare register L (timer/counter 2) CR21 CR21W -

0FF1BH Capture/compare register H (timer/counter 2) - - -

0FF1CH Compare register L (timer 3) CR30 CR30W -

0FF1DH Compare register H (timer 3) - - -

0FF20H Port 0 mode register PM0 - FFH

0FF21H Port 1 mode register PM1 -

0FF23H Port 3 mode register PM3 -

0FF24H Port 4 mode register PM4 -

0FF25H Port 5 mode register PM5 -

0FF26H Port 6 mode register PM6 -

0FF27H Port 7 mode register PM7 -

0FF2EH Real-time output port control register RTPC - 00H

0FF30H Capture/compare control register 0 CRC0 - - 10H

0FF31H Timer output control register TOC - 00H

0FF32H Capture/compare control register 1 CRC1 - -

0FF33H Capture/compare control register 2 CRC2 - - 10H

Note Applicable when the LOCATION 0 instruction is executed. When the LOCATION 0FH instruction is
executed, F0000H is added to each address.

24
 µPD784035(A), 784036(A)

Table 6-1. Special Function Registers (SFRs) (2/4)

Manipulatable bits
AddressNote 1 Special function register (SFR) name Abbreviation R/W When reset
1 bit 8 bits 16 bits

0FF36H Capture register (timer/counter 0) CR02 R - - 0000H

0FF38H Capture register L (timer/counter 1) CR12 CR12W -

0FF39H Capture register H (timer/counter 1) - - -

0FF3AH Capture register L (timer/counter 2) CR22 CR22W -

0FF3BH Capture register H (timer/counter 2) - - -

0FF41H Port 1 mode control register PMC1 R/W - 00H

0FF43H Port 3 mode control register PMC3 -

0FF4EH Register for optional pull-up resistor PUO -

0FF50H Timer register 0 TM0 RNote 2 - - 0000H

0FF51H - -

0FF52H Timer register 1 TM1 TM1W -

0FF53H - - -

0FF54H Timer register 2 TM2 TM2W -

0FF55H - - -

0FF56H Timer register 3 TM3 TM3W -

0FF57H - - -

0FF5CH Prescaler mode register 0 PRM0 R/W - - 11H

0FF5DH Timer control register 0 TMC0 - 00H

0FF5EH Prescaler mode register 1 PRM1 - - 11H

0FF5FH Timer control register 1 TMC1 - 00H

0FF60H D/A conversion value setting register 0 DACS0 - -

0FF61H D/A conversion value setting register 1 DACS1 - -

0FF62H D/A converter mode register DAM - 03H

0FF68H A/D converter mode register ADM - 00H

0FF6AH A/D conversion result register ADCR R - - Undefined

0FF70H PWM control register PWMC R/W - 05H

0FF71H PWM prescaler register PWPR - - 00H

0FF72H PWM modulo register 0 PWM0 - - Undefined

0FF74H PWM modulo register 1 PWM1 - -

0FF7DH One-shot pulse output control register OSPC - 00H

0FF80H I2C bus control register IICC -

0FF81H Prescaler mode register for serial clock SPRM - - 04H

0FF82H Synchronous serial interface mode register CSIM - 00H

Notes 1. Applicable when the LOCATION 0 instruction is executed. When the LOCATION 0FH instruction is
executed, F0000H is added to each address.
2. Some registers cannot read. Refer to the µPD78038, µPD784038Y Sub-Series User’s Manual,
Hardware for details.

25
 µPD784035(A), 784036(A)

Table 6-1. Special Function Registers (SFRs) (3/4)

Manipulatable bits
AddressNote 1 Special function register (SFR) name Abbreviation R/W When reset
1 bit 8 bits 16 bits

0FF84H Synchronous serial interface mode register 1 CSIM1 R/W - 00H

0FF85H Synchronous serial interface mode register 2 CSIM2 -

0FF86H Serial shift register SIO - -

0FF88H Asynchronous serial interface mode register ASIM -

0FF89H Asynchronous serial interface mode register 2 ASIM2 -

0FF8AH Asynchronous serial interface status register ASIS R -

0FF8BH Asynchronous serial interface status register 2 ASIS2 -

0FF8CH Serial receive buffer: UART0 RXB - - Undefined

Serial transmission shift register: UART0 TXS W - -

Serial shift register: IOE1 SIO1 R/W - -

0FF8DH Serial receive buffer: UART2 RXB2 R - -

Serial transmission shift register: UART2 TXS2 W - -

Serial shift register: IOE2 SIO2 R/W - -

0FF90H Baud rate generator control register BRGC - - 00H

0FF91H Baud rate generator control register 2 BRGC2 - -

0FFA0H External interrupt mode register 0 INTM0 -

0FFA1H External interrupt mode register 1 INTM1 -

0FFA4H Sampling clock selection register SCS0 - -

0FFA8H In-service priority register ISPR R -

0FFAAH Interrupt mode control register IMC R/W - 80H

0FFACH Interrupt mask register 0L MK0L MK0 FFFFH

0FFADH Interrupt mask register 0H MK0H

0FFAEH Interrupt mask register 1L MK1L - FFH

0FFC0H Standby control register STBC - Note 2 - 30H

0FFC2H Watchdog timer mode register WDM - Note 2 - 00H

0FFC4H Memory expansion mode register MM - 20H

0FFC5H Hold mode register HLDM - 00H

0FFC6H Clock output mode register CLOM -

0FFC7H Programmable wait control register 1 PWC1 - - AAH

0FFC8H Programmable wait control register 2 PWC2 - - AAAAH

Notes 1. Applicable when the LOCATION 0 instruction is executed. When the LOCATION 0FH instruction is
executed, F0000H is added to each address.
2. A write operation can be performed only with special instructions MOV STBC, #byte and MOV
WDM,#byte. Other instructions cannot perform a write operation.

26
 µPD784035(A), 784036(A)

Table 6-1. Special Function Registers (SFRs) (4/4)

Manipulatable bits
AddressNote Special function register (SFR) name Abbreviation R/W When reset
1 bit 8 bits 16 bits

0FFCCH Refresh mode register RFM R/W - 00H

0FFCDH Refresh area specification register RFA -

0FFCFH Oscillation settling time specification register OSTS - -

0FFD0H- External SFR area - - -

0FFDFH

0FFE0H Interrupt control register (INTP0) PIC0 - 43H

0FFE1H Interrupt control register (INTP1) PIC1 -

0FFE2H Interrupt control register (INTP2) PIC2 -

0FFE3H Interrupt control register (INTP3) PIC3 -

0FFE4H Interrupt control register (INTC00) CIC00 -

0FFE5H Interrupt control register (INTC01) CIC01 -

0FFE6H Interrupt control register (INTC10) CIC10 -

0FFE7H Interrupt control register (INTC11) CIC11 -

0FFE8H Interrupt control register (INTC20) CIC20 -

0FFE9H Interrupt control register (INTC21) CIC21 -

0FFEAH Interrupt control register (INTC30) CIC30 -

0FFEBH Interrupt control register (INTP4) PIC4 -

0FFECH Interrupt control register (INTP5) PIC5 -

0FFEDH Interrupt control register (INTAD) ADIC -

0FFEEH Interrupt control register (INTSER) SERIC -

0FFEFH Interrupt control register (INTSR) SRIC -

Interrupt control register (INTCSI1) CSIIC1 -

0FFF0H Interrupt control register (INTST) STIC -

0FFF1H Interrupt control register (INTCSI) CSIIC -

0FFF2H Interrupt control register (INTSER2) SERIC2 -

0FFF3H Interrupt control register (INTSR2) SRIC2 -

Interrupt control register (INTCSI2) CSIIC2 -

0FFF4H Interrupt control register (INTST2) STIC2 -

Note Applicable when the LOCATION 0 instruction is executed. When the LOCATION 0FH instruction is
executed, F0000H is added to each address.

27
 µPD784035(A), 784036(A)

7. PERIPHERAL HARDWARE FUNCTIONS

7.1 Ports
The ports shown in Figure 7-1 are provided to enable the application of wide-ranging control. Table 7-1 lists the
functions of the ports. For the inputs to port 0 to port 6, a built-in pull-up resistor can be specified by software.

Figure 7-1. Port Configuration

P00

Port 0

P07
P10

Port 1

P17

P20-P27 8 Port 2

P30

Port 3

P37
P40

Port 4

P47
P50

Port 5

P57
P60

Port 6

P67
P70

Port 7

P77

28
 µPD784035(A), 784036(A)

Table 7-1. Port Functions

Port name Pin Function Pull-up specification by software

Port 0 P00-P07 • Bit-by-bit input/output setting supported Specified as a batch for all pins placed in
• Operable as 4-bit real-time outputs input mode.
(P00-P03, P04-P07)
• Capable of driving transistors

Port 1 P10-P17 • Bit-by-bit input/output setting supported Specified as a batch for all pins placed in
• Capable of driving LEDs input mode.

Port 2 P20-P27 • Input port Specified for the 6 bits (P22-P27) as a batch.

Port 3 P30-P37 • Bit-by-bit input/output setting supported Specified as a batch for all pins placed in
input mode.

Port 4 P40-P47 • Bit-by-bit input/output setting supported Specified as a batch for all pins placed in
• Capable of driving LEDs input mode.

Port 5 P50-P57 • Bit-by-bit input/output setting supported Specified as a batch for all pins placed in
• Capable of driving LEDs input mode.

Port 6 P60-P67 • Bit-by-bit input/output setting supported Specified as a batch for all pins placed in
input mode.

Port 7 P70-P77 • Bit-by-bit input/output setting supported -

7.2 Clock Generator

A circuit for generating the clock signal required for operation is provided. The clock generator includes a frequency
divider; low current consumption can be achieved by operating at a lower internal frequency when high-speed
operation is not necessary.

Figure 7-2. Block Diagram of Clock Generator

X1
fXX
Oscillator 1/2 1/2 1/2 1/2
Selector

X2 fCLK
CPU
Peripheral circuits

fXX/2

UART/IOE
INTP0 noise eliminator
Oscillation settling timer

Remark fXX : Oscillator frequency or external clock input

fCLK : Internal operating frequency

29
 µPD784035(A), 784036(A)

Figure 7-3. Examples of Using Oscillator

(1) Crystal/ceramic oscillation

µ PD784036(A)

VSS1
X1

X2

(2) External clock

• When EXTC bit of OSTS = 1 • When EXTC bit of OSTS = 0

µ PD784036(A) µ PD784036(A)
X1 X1

X2 Open X2
µ PD74HC04, etc.

Caution When using the clock generator, to avoid problems caused by influences such as stray
capacitance, run all wiring within the area indicated by the dotted lines according to the following
rules:

• Minimize the wiring length.

• Wires must never cross other signal lines.
• Wires must never run near a line carrying a large varying current.
• The grounding point of the capacitor of the oscillator must always be at the same potential as
VSS1. Never connect the capacitor to a ground pattern carrying a large current.
• Never extract a signal from the oscillator.

30
 µPD784035(A), 784036(A)

7.3 Real-Time Output Port

The real-time output port outputs data stored in the buffer, synchronized with a timer/counter 1 match interrupt
or external interrupt. Thus, pulse output that is free of jitter can be obtained.
Therefore, the real-time output port is best suited to applications (such as open-loop control over stepping motors)
where an arbitrary pattern is output at arbitrary intervals.
As shown in Figure 7-4, the real-time output port is built around port 0 and the port 0 buffer register (P0H, P0L).

Figure 7-4. Block Diagram of Real-Time Output Port

Internal bus

8 4 4

Real-time output port Buffer register

control register 8
(RTPC) P0H P0L

INTP0 (externally) 4 4
INTC10 (from timer/counter 1) Output trigger
control circuit
INTC11 (from timer/counter 1)

Output latch (P0)

P07 P00

31
 µPD784035(A), 784036(A)

7.4 Timers/Counters
Three timer/counter units and one timer unit are incorporated.
Moreover, seven interrupt requests are supported, allowing these units to function as seven timer/counter units.

Table 7-2. Timer/Counter Operation

Name
Timer/counter 0 Timer/counter 1 Timer/counter 2 Timer 3
Item

Count pulse width 8 bits -

16 bits

Operating mode Interval timer 2ch 2ch 2ch 1ch

External event counter -

One-shot timer - - -

Function Timer output 2ch - 2ch -

Toggle output - -

PWM/PPG output - -

One-shot pulse outputNote - - -

Real-time output - - -

Pulse width measurement 1 input 1 input 2 inputs -

Number of interrupt requests 2 2 2 1

Note The one-shot pulse output function makes the level of a pulse output active by software, and makes the
level of a pulse output inactive by hardware (interrupt request signal).
Note that this function differs from the one-shot timer function of timer/counter 2.

32
 µPD784035(A), 784036(A)

Figure 7-5. Timer/Counter Block Diagram

Timer/counter 0
Clear information Software trigger

Selector
Timer register 0
fxx/8 Prescaler (TM0) OVF

Match

Pulse output control

Compare register
(CR00) TO0

Compare register
Match
(CR01)
TO1

INTP3 Edge Capture register

detection (CR02)
INTC00
INTP3 INTC01

Timer/counter 1

Clear information
Selector

Timer register 1
fxx/8 Prescaler (TM1/TM1W) OVF

Event input Compare register Match

(CR10/CR10W) INTC10
To real-time
output port
Edge Capture/compare register Match
INTP0 INTC11
detection (CR11/CR11W)
INTP0
Capture register
(CR12/CR12W)

Timer/counter 2

Clear information
Selector

Timer register 2
fxx/8 Prescaler (TM2/TM2W) OVF

Match
Pulse output control

Compare register
INTP2/CI Edge (CR20/CR20W) TO2
detection

INTP2 Match
Capture/compare register
(CR21/CR21W)
TO3

INTP1 Edge Capture register

detection (CR22/CR22W)
INTC20
INTP1 INTC21

Timer 3

Timer register 3 Clear

fxx/8 Prescaler (TM3/TM3W)

Match CSI
Compare register
(CR30/CR30W)
INTC30

Remark OVF: Overflow flag

33
 µPD784035(A), 784036(A)

7.5 PWM Output (PWM0, PWM1)

Two channels of PWM (pulse width modulation) output circuitry with a resolution of 12 bits and a repetition
frequency of 62.5 kHz (fCLK = 16 MHz) are incorporated. Low or high active level can be selected for the PWM output
channels, independently of each other. This output is best suited to DC motor speed control.

Figure 7-6. Block Diagram of PWM Output Unit

Internal bus

16 8
PWM modulo register

8 7 4 3 PWM control register

PWMn 15 0 (PWMC)

8 4
Reload
control

8-bit Pulse control Output

fCLK Prescaler circuit PWMn (output pin)
down-counter control

4-bit counter
1/256

Remark n = 0, 1

34
 µPD784035(A), 784036(A)

7.6 A/D Converter

An analog/digital (A/D) converter having 8 multiplexed analog inputs (ANI0-ANI7) is incorporated.
The successive approximation system is used for conversion. The result of conversion is held in the 8-bit A/D
conversion result register (ADCR). Thus, speedy high-precision conversion can be achieved. (The conversion time
is about 7.5 µs at fCLK = 16 MHz.)
A/D conversion can be started in any of the following modes:

• Hardware start : Conversion is started by means of trigger input (INTP5).

• Software start : Conversion is started by means of bit setting the A/D converter mode register (ADM).

After conversion has started, one of the following modes can be selected:

• Scan mode : Multiple analog inputs are selected sequentially to obtain conversion data from all pins.
• Select mode: A single analog input is selected at all times to enable conversion data to be obtained
continuously.

ADM is used to specify the above modes, as well as the termination of conversion.
When the result of conversion is transferred to ADCR, an interrupt request (INTAD) is generated. Using this feature,
the results of conversion can be continuously transferred to memory by the macro service.

Figure 7-7. Block Diagram of A/D Converter

ANI0
ANI1 Sample-and-hold circuit Series resistor string
Input selector

ANI2 AVREF1
ANI3
ANI4 R/2
Voltage comparator
ANI5
ANI6 R
ANI7 Tap selector
Successive conver-
sion register (SAR)

Conversion
INTP5 Edge trigger Control INTAD
detector circuit R/2
AVSS

Trigger enable
8

A/ D converter mode A/ D conversion

register (ADM) result register (ADCR)

8 8

Internal bus

35
 µPD784035(A), 784036(A)

7.7 D/A Converter

Two digital/analog (D/A) converter channels of voltage output type, having a resolution of 8 bits, are incorporated.
An R-2R resistor ladder system is used for conversion. By writing the value to be subject to D/A conversion in
the 8-bit D/A conversion value setting register (DACSn: n = 0, 1), the resulting analog value is output on ANOn
(n = 0, 1). The range of the output voltages is determined by the voltages applied to the AVREF2 and AVREF3 pins.
Because of its high output impedance, no current can be obtained from an output pin. When the load impedance
is low, insert a buffer amplifier between the load and the converter.
The impedance of the ANOn pin goes high while the RESET signal is low. DACSn is set to 0 after a reset
is released.

Figure 7-8. Block Diagram of D/A Converter

ANOn
2R
AVREF2 R

2R

Selector

2R
AVREF3
R

2R

DACSn DACEn

Internal bus

Remark n = 0, 1

36
 µPD784035(A), 784036(A)

7.8 Serial Interface

Three independent serial interface channels are incorporated.

• Asynchronous serial interface (UART)/three-wire serial I/O (IOE) × 2

• Synchronous serial interface (CSI) × 1
• Three-wire serial I/O (IOE)
• Two-wire serial I/O (IOE)

So, communication with points external to the system and local communication within the system can be performed
at the same time. (See Figure 7-9.)

Figure 7-9. Example Serial Interfaces

UART + Three-wire serial I/O + Two-wire serial I/O

µ PD784036(A)
Master Slave
[Three-wire serial I/O]
SO1 SI
[UART] SI1 SO
RxD
SCK1 SCK
RS-232-C TxD Note
INTPm Port
driver/receiver
Port Port INT
VDD VDD
Slave
SDA SB0
SCL SCK0
Note
INTPn Port

Port INT
[Two-wire serial I/O]

Note Handshake line

37
 µPD784035(A), 784036(A)

7.8.1 Asynchronous serial interface/three-wire serial I/O (UART/IOE)

Two serial interface channels are available; for each channel, asynchronous serial interface mode or three-wire
serial I/O mode can be selected.

(1) Asynchronous serial interface mode

In this mode, 1-byte data is transferred after a start bit.
A baud rate generator is incorporated to enable communication at a wide range of baud rates.
Moreover, the frequency of a clock signal applied to the ASCK pin can be divided to define a baud rate.
With the baud rate generator, the baud rate conforming to the MIDI standard (31.25 kbps) can be obtained.

Figure 7-10. Block Diagram of Asynchronous Serial Interface Mode

Internal bus

Receive buffer RXB, RXB2

RxD, RxD2 Receive Transmission TXS, TXS2

shift register shift register

TxD, TxD2

INTSR,
Reception INTSR2 Transmission
control parity control parity INTST, INTST2
INTSER,
check bit addition
INTSER2

Baud rate generator

1/2m
Selector

fXX/2
1/2n+1
ASCK, ASCK2
1/2m

Remark fXX: Oscillator frequency or external clock input

n = 0 to 11
m = 16 to 30

38
 µPD784035(A), 784036(A)

(2) Three-wire serial I/O mode

In this mode, the master device makes the serial clock active to start transmission, then transfers 1-byte data
in phase with the clock.
This mode is designed for communication with a device incorporating a conventional synchronous serial interface.
Basically, three lines are used for communication: the serial clock line (SCK) and the two serial data lines (SI
and SO).
In general, a handshake line is required to check the state of communication.

Figure 7-11. Block Diagram of Three-Wire Serial I/O Mode

Internal bus

Direction control
circuit

SIO1, SIO2

SI1, SI2 Shift register Output latch

SO1, SO2

Interrupt signal INTCSI1,

SCK1, SCK2 Serial clock counter generator INTCSI2

1/m 1/2n+1 fXX/2

Selector

Serial clock
control circuit

Remark fXX: Oscillator frequency or external clock input

n = 0 to 11
m = 1, 16 to 30

39
 µPD784035(A), 784036(A)

7.8.2 Synchronous serial interface (CSI)

With this interface, the master device makes the serial clock active to start transmission, then transfers 1-byte data
in phase with the clock.

Figure 7-12. Block Diagram of Synchronous Serial Interface

Internal bus

Direction
control circuit

Set Reset
SI0
Selector

Shift register Output latch

SO0/SDA

N-ch open-drain
output enabled
(when two-wire
mode is used)

Serial clock Interrupt signal

SCK0/SCL counter generator INTCSI

Serial clock Timer 3 output

Selector

N-ch open-drain control circuit

output enabled fXX/16
(when two-wire
mode is used) Prescaler
Selector

CLS0
CLS1 fXX/2

Remark fXX: Oscillator frequency or external clock input

40
 µPD784035(A), 784036(A)

(1) Three-wire serial I/O mode

This mode is designed for communication with a device incorporating a conventional synchronous serial interface.
Basically, three lines are used for communication: the serial clock line (SCK0) and serial data lines (SI0 and SO0).
In general, a handshake line is required to check the state of communication.

(2) Two-wire serial I/O mode

In this mode, 8-bit data is transferred using two lines: the serial clock line (SCL) and serial data bus (SDA).
In general, a handshake line is required to check the communication state.

7.9 Clock Output Function

The frequency of the CPU clock signal can be divided for output to a point external to the system. Moreover, the
port can be used as a 1-bit port.
The ASTB pin is also used for the CLKOUT pin, so that when this function is used, the local bus interface cannot
be used.

Figure 7-13. Block Diagram of Clock Output Function

fCLK

fCLK/2
Selector

fCLK/4 Output control CLKOUT

fCLK/8

fCLK/16

Enable output Output level

41
 µPD784035(A), 784036(A)

7.10 Edge Detection Function

The interrupt input pins (NMI, INTP0-INTP5) are used to apply not only interrupt requests but also trigger signals
for the built-in circuits. As these pins are triggered by an edge (rising or falling) of an input signal, a function for edge
detection is incorporated. Moreover, a noise suppression function is provided to prevent erroneous edge detection
caused by noise.

Table 7-3. Noise Suppression Method for Interrupt Input Pins

Pin Detectable edge Noise suppression method

NMI Rising edge or falling edge Analog delay

INTP0-INTP3 Rising edge or falling edge, or both edges Clock samplingNote

INTP4, INTP5 Analog delay

Note INTP0 is used for sampling clock selection.

7.11 Watchdog Timer

A watchdog timer is incorporated for CPU runaway detection. The watchdog timer, if not cleared by software within
a specified interval, generates a nonmaskable interrupt. Furthermore, once watchdog timer operation is enabled, it
cannot be disabled by software. The user can specify whether priority is placed on an interrupt based on the watchdog
timer or on an interrupt based on the NMI pin.

Figure 7-14. Block Diagram of Watchdog Timer

fCLK Timer

fCLK/221

fCLK/220
Selector

INTWDT
fCLK/219

fCLK/217

Clear signal

42
 µPD784035(A), 784036(A)

8. INTERRUPT FUNCTION

Table 8-1 lists the interrupt request handling modes. These modes are selected by software.

Table 8-1. Interrupt Request Handling Modes

Handling mode Handled by Handling PC and PSW contents

Vectored interrupt Software Branches to a handling routine for execution The PC and PSW contents are pushed
(arbitrary handling). to and popped from the stack.

Context switching Automatically selects a register bank, and The PC and PSW contents are saved to
branches to a handling routine for execution and read from a fixed area in the
(arbitrary handling). register bank.

Macro service Firmware Performs operations such as memory-to-I/O- Maintained

device data transfer (fixed handling).

8.1 Interrupt Source

An interrupt can be issued from any one of the interrupt sources listed in Table 8-2: execution of BRK and BRKCS
instructions, an operand error, or any of the 23 other interrupt sources.
Four levels of interrupt handling priority can be set. Priority levels can be set to nest control during interrupt handling
or to concurrently generate interrupt requests. Nested macro services, however, are performed without suspension.
When interrupt requests having the same priority level are generated, they are handled according to the default
priority (fixed). (See Table 8-2.)

43
 µPD784035(A), 784036(A)

Table 8-2. Interrupt Sources

Default Source Internal/ Macro

Type
priority Name Trigger external service

Software - BRK instruction Instruction execution - -

BRKCS instruction

Operand error When the MOV STBC,#byte, MOV WDM,#byte, or LOCATION

instruction is executed, exclusive OR of the byte operand and
byte does not produce FFH.

Nonmaskable - NMI Detection of edge input on the pin External -

WDT Watchdog timer overflow Internal

Maskable 0 (highest) INTP0 Detection of edge input on the pin (TM1/TM1W capture trigger, External Enabled
TM1/TM1W event counter input)

1 INTP1 Detection of edge input on the pin (TM2/TM2W capture trigger,

TM2/TM2W event counter input)

2 INTP2 Detection of edge input on the pin (TM2/TM2W capture trigger, Internal Enabled
TM2/TM2W event counter input)

3 INTP3 Detection of edge input on the pin (TM0 capture trigger, TM0
event counter input)

4 INTC00 TM0-CR00 match signal issued

5 INTC01 TM0-CR01 match signal issued

6 INTC10 TM1-CR10 match signal issued (in 8-bit operation mode)

TM1W-CR10W match signal issued (in 16-bit operation mode)

7 INTC11 TM1-CR11 match signal issued (in 8-bit operation mode)

TM1W-CR11W match signal issued (in 16-bit operation mode)

8 INTC20 TM2-CR20 match signal issued (in 8-bit operation mode)

TM2W-CR20W match signal issued (in 16-bit operation mode)

9 INTC21 TM2-CR21 match signal issued (in 8-bit operation mode)

TM2W-CR21W match signal issued (in 16-bit operation mode)

10 INTC30 TM3-CR30 match signal issued (in 8-bit operation mode)

TM3W-CR30W match signal issued (in 16-bit operation mode)

11 INTP4 Detection of edge input on the pin External Enabled

12 INTP5 Detection of edge input on the pin

13 INTAD A/D converter processing completed (ADCR transfer) Internal Enabled

14 INTSER ASI0 reception error -

15 INTSR ASI0 reception completed or CSI1 transfer completed Enabled

INTCSI1

16 INTST ASI0 transmission completed

17 INTCSI CSI0 transfer completed

18 INTSER2 ASI2 reception error -

19 INTSR2 ASI2 reception completed or CSI2 transfer completed Enabled

INTCSI2

20 (lowest) INTST2 ASI2 transmission completed

Remark ASI: Asynchronous serial interface

CSI: Synchronous serial interface

44
 µPD784035(A), 784036(A)

8.2 Vectored Interrupt

When a branch to an interrupt handling routine occurs, the vector table address corresponding to the interrupt
source is used as the branch address.
Interrupt handling by the CPU consists of the following operations:

• When a branch occurs : Push the CPU status (PC and PSW contents) to the stack.
• When control is returned : Pop the CPU status (PC and PSW contents) from the stack.

To return control from the handling routine to the main routine, use the RETI instruction. The branch destination
addresses must be within the range of 0 to FFFFH.

Table 8-3. Vector Table Address

Interrupt source Vector table address

BRK instruction 003EH

Operand error 003CH

NMI 0002H

WDT 0004H

INTP0 0006H

INTP1 0008H

INTP2 000AH

INTP3 000CH

INTC00 000EH

INTC01 0010H

INTC10 0012H

INTC11 0014H

INTC20 0016H

INTC21 0018H

INTC30 001AH

INTP4 001CH

INTP5 001EH

INTAD 0020H

INTSER 0022H

INTSR 0024H

INTCSI1

INTST 0026H

INTCSI 0028H

INTSER2 002AH

INTSR2 002CH

INTCSI2

INTST2 002EH

45
 µPD784035(A), 784036(A)

8.3 Context Switching

When an interrupt request is generated, or when the BRKCS instruction is executed, an appropriate register bank
is selected by the hardware. Then, a branch to a vector address stored in that register bank occurs. At the same
time, the contents of the current program counter (PC) and program status word (PSW) are stacked in the register
bank.
The branch address must be within the range of 0 to FFFFH.

Figure 8-1. Context Switching Caused by an Interrupt Request

0000B
<7> Transfer Register bank (0-7)
Register bank n (n = 0-7)
PC19-16 PC15-0 A X
B C
<2> Save <6> Exchange R5 R4
(Bits 8 to 11 of R7 R6
temporary register)
<5> Save V VP
U UP <3> Switching between register banks
Temporary register (RBS0-RBS2 ← n)
T D E
<4> RSS ← 0
W H L IE ← 0
<1> Save

PSW

8.4 Macro Service

The macro service function enables data transfer between memory and special function registers (SFRs) without
requiring the intervention of the CPU. The macro service controller accesses both memory and SFRs within the same
transfer cycle to directly transfer data without having to perform data fetch.
Since the CPU status is neither saved nor restored, nor is data fetch performed, high-speed data transfer is
possible.

Figure 8-2. Macro Service

Read Write
Macro service
CPU Memory SFR
Write controller Read

Internal bus

46
 µPD784035(A), 784036(A)

8.5 Examples of Macro Service Applications

(1) Serial interface transmission

Transmission data storage buffer (memory)

Data n
Data n - 1

Data 2
Data 1

Internal bus

Transmission TXS (SFR)

TxD shift register

Transmission control INTST

Each time a macro service request (INTST) is generated, the next transmission data is transferred from memory
to TXS. When data n (last byte) has been transferred to TXS (that is, once the transmission data storage buffer
becomes empty), a vectored interrupt request (INTST) is generated.

(2) Serial interface reception

Reception data storage buffer (memory)

Data n
Data n - 1

Data 2
Data 1

Internal bus

Reception buffer RXB (SFR)

Reception
RxD shift register

Reception control INTSR

Each time a macro service request (INTSR) is generated, reception data is transferred from RXB to memory.
When data n (last byte) has been transferred to memory (that is, once the reception data storage buffer becomes
full), a vectored interrupt request (INTSR) is generated.

47
 µPD784035(A), 784036(A)

(3) Real-time output port

INTC10 and INTC11 function as the output triggers for the real-time output ports. For these triggers, the macro
service can simultaneously set the next output pattern and interval. Therefore, INTC10 and INTC11 can be used
to independently control two stepping motors. They can also be applied to PWM and DC motor control.

Output pattern profile (memory) Output timing profile (memory)

Pn Tn
Pn–1 Tn–1

P2 T2
P1 T1

Internal bus Internal bus

Match
(SFR) P0L CR10 (SFR)

INTC10
Output latch TM1

P00-P03

Each time a macro service request (INTC10) is generated, a pattern and timing data are transferred to the buffer
register (P0L) and compare register (CR10), respectively. When the contents of timer register 1 (TM1) and CR10
match, another INTC10 is generated, and the P0L contents are transferred to the output latch. When Tn (last
byte) is transferred to CR10, a vectored interrupt request (INTC10) is generated.
For INTC11, the same operation as that performed for INTC10 is performed.

48
 µPD784035(A), 784036(A)

9. LOCAL BUS INTERFACE

The local bus interface enables the connection of external memory and I/O devices (memory-mapped I/O). It
supports a 1M-byte memory space. (See Figure 9-1.)

Figure 9-1. Example of Local Bus Interface

µ PD784036(A)

Decoder
A16-A19

RD
PROM Kanji character
WR Pseudo SRAM generator
µ PD27C1001A
REFRQ µPD24C1000

AD0-AD7 Data bus

Data bus

ASTB Latch

Address bus
A8-A15

Gate array for I/O

expansion including
Centronics interface
circuit, etc.

9.1 Memory Expansion

By adding external memory, program memory or data memory can be expanded to one of seven sizes between
256 bytes and approximately 1M byte.

49
 µPD784035(A), 784036(A)

9.2 Memory Space

The 1M-byte memory space is divided into eight spaces, each having a logical address. Each of these spaces
can be controlled using the programmable wait and pseudo-static RAM refresh functions.

Figure 9-2. Memory Space

FFFFFH

512K bytes

80000H
7FFFFH

256K bytes

40000H
3FFFFH

128K bytes
20000H
1FFFFH

64K bytes
10000H
0FFFFH

16K bytes

0C000H
0BFFFH

16K bytes
08000H
07FFFH

16K bytes
04000H
03FFFH

16K bytes

00000H

50
 µPD784035(A), 784036(A)

9.3 Programmable Wait

When the memory space is divided into eight spaces, a wait state can be separately inserted for each memory
space while the RD or WR signal is active. This prevents the overall system efficiency from being degraded even
when memory devices having different access times are connected.
In addition, an address wait function that extends the ASTB signal active period is provided to assure a longer
address decode time. (This function is set for the entire space.)

9.4 Pseudo-Static RAM Refresh Function

Refresh is performed as follows:

• Pulse refresh
A bus cycle is inserted where a refresh pulse is output on the REFRQ pin at regular intervals. When the memory
space is divided into eight, and a specified area is being accessed, refresh pulses can also be output on
the REFRQ pin as the memory is being accessed. This can prevent the refresh cycle from suspending normal
memory access.
• Power-down self-refresh
In standby mode, a low-level signal is output on the REFRQ pin to maintain the contents of pseudo-static RAM.

9.5 Bus Hold Function

A bus hold function is provided to facilitate connection to devices such as a DMA controller. Suppose that a bus
hold request signal (HLDRQ) is received from an external bus master. In this case, upon the completion of the bus
cycle being performed at the reception, the address bus, address/data bus, ASTB, RD, and WR pins are placed in
the high-impedance state, and the bus hold acknowledge signal (HLDAK) is made active to release the bus for the
external bus master.
While the bus hold function is being used, the external wait and pseudo-static RAM refresh functions are disabled.

51
 µPD784035(A), 784036(A)

10. STANDBY FUNCTION

The standby function allows the power consumption of the chip to be reduced. The following standby modes are
supported:

• HALT mode : The CPU operation clock is stopped. By occasionally inserting the HALT mode during normal
operation, the overall average power consumption can be reduced.
• IDLE mode : The entire system is stopped, with the exception of the oscillator. This mode consumes only
very little more power than STOP mode, but normal program operation can be restored in almost
as little time as that required to restore normal program operation from HALT mode.
• STOP mode : The oscillator is stopped. All operations in the chip stop, such that only leakage current flows.

These modes can be selected by software.

A macro service can be initiated in HALT mode.

Figure 10-1. Standby Mode Status Transition

Macro service request

ttling
tion se
Oscilla ses Program End of one operation Macro
Wait for p
time ela operation End of macro service service
oscillation
settling
Int
1

er
1
e

at st
ot

te

e
ru
RE Set
ut N

ut No

ion
op qu
pt
SE HA

e
inp

re

on ce r
inp

er
OP t
T LT
TP t

qu t
TP T E
5

IN pu

ST inpu
IN ESE IDL

inp
TP

i
5

rv
es
4, in

e
Se ET

se
IN

u
tN
R et

ot

S
ro
S
4,

e2

RE
of
ac
TP

d
M
IN

En
I,
NM

I,
NM

STOP IDLE HALT

(standby) (standby) (standby)
Request for masked interrupt

Notes 1. INTP4 and INTP5 are applied when not masked.

2. Only when the interrupt request is not masked

Remark NMI is enabled only by external input. The watchdog timer cannot be used to release one of the standby
modes (STOP, HALT, or IDLE mode).

52
 µPD784035(A), 784036(A)

11. RESET FUNCTION

Applying a low-level signal to the RESET pin initializes the internal hardware (reset status).
When the RESET input makes a low-to-high transition, the following data is loaded into the program counter (PC):

• Eight low-order bits of the PC : Contents of location at address 0000H

• Intermediate eight bits of the PC : Contents of location at address 0001H
• Four high-order bits of the PC : 0

The PC contents are used as a branch destination address. Program execution starts from that address. Therefore,
a reset start can be performed from an arbitrary address.
The contents of each register can be set by software, as required.
The RESET input circuit contains a noise eliminator to prevent malfunctions caused by noise. This noise eliminator
is an analog delay sampling circuit.

Figure 11-1. Accepting a Reset

Execute instruction
Delay Delay Delay Initialize PC at reset start address

RESET
(input)

Internal reset signal

Start reset End reset

For power-on reset, the RESET signal must be held active until the oscillation settling time (approximately 40 ms)
has elapsed.

Figure 11-2. Power-On Reset

Execute instruction at
Oscillation settling time Delay Initialize PC reset start address

VDD

RESET
(input)

Internal reset signal

End reset

53
 µPD784035(A), 784036(A)

12. INSTRUCTION SET

(1) 8-bit instructions (The instructions enclosed in parentheses are implemented by a combination of
operands, where A is described as r.)
MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC,
ROLC, SHR, SHL, ROR4, ROL4, DBNZ, PUSH, POP, MOVM, XCHM, CMPME, CMPMNE, CMPMNC, CMPMC,
MOVBK, XCHBK, CMPBKE, CMPBKNE, CMPBKNC, CMPBKC, CHKL, CHKLA

Table 12-1. Instructions Implemented by 8-Bit Addressing

2nd operand #byte A r saddr sfr !addr16 mem r3 [WHL+] n NoneNote 2

r' saddr' !!addr24 [saddrp] PSWL [WHL-]
1st operand [%saddrg] PSWH

A (MOV) (MOV) MOV (MOV)Note 6 MOV (MOV) MOV MOV (MOV)

ADDNote 1 (XCH) XCH (XCH)Note 6 (XCH) (XCH) XCH (XCH)
(ADD)Note 1 (ADD)Note 1 (ADD)Notes 1, 6 (ADD)Note 1 ADDNote 1 ADDNote 1 (ADD)Note 1

r MOV (MOV) MOV MOV MOV MOV RORNote 3 MULU

ADDNote 1 (XCH) XCH XCH XCH XCH DIVUW
(ADD)Note 1 ADDNote 1 ADDNote 1 ADDNote 1 INC
DEC

saddr MOV (MOV)Note 6 MOV MOV INC

ADDNote 1 (ADD)Note 1 ADDNote 1 XCH DEC
ADDNote 1 DBNZ

sfr MOV MOV MOV PUSH

ADDNote 1 (ADD)Note 1 ADDNote 1 POP
CHKL
CHKLA

!addr16 MOV (MOV) MOV

!!addr24 ADDNote 1

mem MOV
[saddrp] ADDNote 1
[%saddrg]

mem3 ROR4
ROL4

r3 MOV MOV
PSWL
PSWH

B, C DBNZ

STBC, WDM MOV

[TDE+] (MOV) MOVBKNote 5

[TDE–] (ADD)Note 1
MOVMNote 4

Notes 1. ADDC, SUB, SUBC, AND, OR, XOR, and CMP are the same as ADD.
2. There is no second operand, or the second operand is not an operand address.
3. ROL, RORC, ROLC, SHR, and SHL are the same as ROR.
4. XCHM, CMPME, CMPMNE, CMPMNC, and CMPMC are the same as MOVM.
5. XCHBK, CMPBKE, CMPBKNE, CMPBKNC, and CMPBKC are the same as MOVBK.
6. When saddr is saddr2 with this combination, an instruction with a short code exists.

54
 µPD784035(A), 784036(A)

(2) 16-bit instructions (The instructions enclosed in parentheses are implemented by a combination of
operands, where AX is described as rp.)
MOVW, XCHW, ADDW, SUBW, CMPW, MULUW, MULW, DIVUX, INCW, DECW, SHRW, SHLW, PUSH, POP,
ADDWG, SUBWG, PUSHU, POPU, MOVTBLW, MACW, MACSW, SACW

Table 12-2. Instructions Implemented by 16-Bit Addressing

2nd operand #word AX rp saddrp strp !addr16 mem [WHL+] byte n NoneNote 2
rp' saddrp' !!addr24 [saddrp]
1st operand [%saddrg]

AX (MOVW) (MOVW) (MOVW) (MOVW)Note 3 MOVW (MOVW) MOVW (MOVW)

ADDWNote 1 (XCHW) (XCHW) (XCHW)Note 3 (XCHW) XCHW XCHW (XCHW)
(ADD)Note 1 (ADDW)Note 1 (ADDW)Notes 1,3 (ADDW)Note 1

rp MOVW (MOVW) MOVW MOVW MOVW MOVW SHRW MULWNote 4

ADDWNote 1 (XCHW) XCHW XCHW XCHW SHLW INCW
(ADDW)Note 1 ADDWNote 1 ADDWNote 1 ADDWNote 1 DECW

saddrp MOVW (MOVW)Note 3 MOVW MOVW INCW

ADDWNote 1 (ADDW)Note 1 ADDWNote 1 XCHW DECW
ADDWNote 1

sfrp MOVW MOVW MOVW PUSH

ADDWNote 1 (ADDW)Note 1 ADDWNote 1 POP

!addr16 MOVW (MOVW) MOVW MOVTBLW

!!addr24

mem MOVW
[saddrp]
[%saddrg]

PSW PUSH
POP

SP ADDWG
SUBWG

post PUSH
POP
PUSHU
POPU

[TDE+] (MOVW) SACW

byte MACW
MACSW

Notes 1. SUBW and CMPW are the same as ADDW.

2. There is no second operand, or the second operand is not an operand address.
3. When saddrp is saddrp2 with this combination, an instruction with a short code exists.
4. MULUW and DIVUX are the same as MULW.

55
 µPD784035(A), 784036(A)

(3) 24-bit instructions (The instructions enclosed in parentheses are implemented by a combination of
operands, where WHL is described as rg.)
MOVG, ADDG, SUBG, INCG, DECG, PUSH, POP

Table 12-3. Instructions Implemented by 24-Bit Addressing

2nd operand #imm24 WHL rg saddrg !!addr24 mem1 [%saddrg] SP NoneNote

1st operand rg'

WHL (MOVG) (MOVG) (MOVG) (MOVG) (MOVG) MOVG MOVG MOVG

(ADDG) (ADDG) (ADDG) ADDG
(SUBG) (SUBG) (SUBG) SUBG

rg MOVG (MOVG) MOVG MOVG MOVG INCG

ADDG (ADDG) ADDG DECG
SUBG (SUBG) SUBG PUSH
POP

saddrg (MOVG) MOVG

!!addr24 (MOVG) MOVG

mem1 MOVG

[%saddrg] MOVG

SP MOVG MOVG INCG

DECG

Note There is no second operand, or the second operand is not an operand address.

56
 µPD784035(A), 784036(A)

(4) Bit manipulation instructions

MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR, BFSET

Table 12-4. Bit Manipulation Instructions Implemented by Addressing

2nd operand CY saddr.bit sfr.bit /saddr.bit /sfr.bit NoneNote

A.bit X.bit /A.bit /X.bit
PSWL.bit PSWH.bit /PSWL.bit /PSWH.bit
mem2.bit /mem2.bit
1st operand !addr16.bit !!addr24.bit /!addr16.bit /!!addr24.bit

CY MOV1 AND1 NOT1

AND1 OR1 SET1
OR1 CLR1
XOR1

saddr.bit MOV1 NOT1

sfr.bit SET1
A.bit CLR1
X.bit BF
PSWL.bit BT
PSWH.bit BTCLR
mem2.bit BFSET
!addr16.bit
!!addr24.bit

Note There is no second operand, or the second operand is not an operand address.

57
 µPD784035(A), 784036(A)

(5) Call/return instructions and branch instructions

CALL, CALLF, CALLT, BRK, RET, RETI, RETB, RETCS, RETCSB, BRKCS, BR, BNZ, BNE, BZ, BE, BNC, BNL,
BC, BL, BNV, BPO, BV, BPE, BP, BN, BLT, BGE, BLE, BGT, BNH, BH, BF, BT, BTCLR, BFSET, DBNZ

Table 12-5. Call/Return and Branch Instructions Implemented by Addressing

Instruction $addr20 $!addr20 !addr16 !!addr20 rp rg [rp] [rg] !addr11 [addr5] RBn None
address
operand

Basic BCNote CALL CALL CALL CALL CALL CALL CALL CALLF CALLF BRKCS BRK
instruction BR BR BR BR BR BR BR BR RET
RETCS RETI
RETCSB RETB

Composite BF
instruction BT
BTCLR
BFSET
DBNZ

Note BNZ, BNE, BZ, BE, BNC, BNL, BL, BNV, BPO, BV, BPE, BP, BN, BLT, BGE, BLE, BGT, BNH, and BH
are the same as BC.

(6) Other instructions

ADJBA, ADJBS, CVTBW, LOCATION, SEL, NOT EI, DI, SWRS

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 µPD784035(A), 784036(A)

13. ELECTRICAL CHARACTERISTICS

ABSOLUTE MAXIMUM RATINGS (TA = 25 °C)

Parameter Symbol Conditions Rating Unit

Supply voltage VDD -0.5 to +7.0 V
AVDD AVSS to VDD + 0.5 V
AVSS -0.5 to +0.5 V
Input voltage VI -0.5 to VDD + 0.5 V
Output voltage VO -0.5 to VDD + 0.5 V
Output low current IOL At one pin 15 mA
Total of all output pins 100 mA
Output high current IOH At one pin -10 mA
Total of all output pins -100 mA
A/D converter reference input AVREF1 -0.5 to VDD + 0.3 V
voltage
D/A converter reference input AVREF2 -0.5 to VDD + 0.3 V
voltage
AVREF3 -0.5 to VDD + 0.3 V
Operating ambient temperature TA -40 to +85 °C
Storage temperature Tstg -65 to +150 °C

Caution Absolute maximum ratings are rated values beyond which physical damage will be caused to the
product; if the rated value of any of the parameters in the above table is exceeded, even
momentarily, the quality of the product may deteriorate. Always use the product within its rated
values.

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 µPD784035(A), 784036(A)

OPERATING CONDITIONS
• Operating ambient temperature (TA) : -40 to +85 °C
• Rise time and fall time (tr, tf) (at pins which are not specified) : 0 to 200 µs
• Power supply voltage and clock cycle time : See Figure 13-1.

Figure 13-1. Power Supply Voltage and Clock Cycle Time

10 000

4 000
Clock cycle time tCYK [ns]

1 000
Guaranteed
operating
range

125
100
62.5

10
0 1 2 3 4 5 6 7
Power supply voltage [V]

CAPACITANCE (TA = 25 °C, VDD = VSS = 0 V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Input capacitance CI f = 1 MHz 10 pF

Output capacitance CO 0 V on pins other than measured pins 10 pF

I/O capacitance CIO 10 pF

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 µPD784035(A), 784036(A)

OSCILLATOR CHARACTERISTICS (TA = -40 to +85 °C, VDD = +4.5 to 5.5 V, VSS = 0 V)

Resonator Recommended circuit Parameter MIN. MAX. Unit

Ceramic resonator Oscillator frequency (fXX) 4 32 MHz
or crystal

VSS1 X1 X2

C1 C2

External clock X1 input frequency (fX) 4 32 MHz

X1 X2 X1 input rise and fall times 0 10 ns

(tXR, tXF)

X1 input high-level and low- 10 125 ns

HCMOS level widths (tWXH, tWXL)
inverter

Caution When using the system clock generator, run wires in the portion surrounded by broken lines
according to the following rules to avoid effects such as stray capacitance:

• Minimize the wiring.

• Never cause the wires to cross other signal lines.
• Never cause the wires to run near a line carrying a large varying current.
• Cause the grounding point of the capacitor of the oscillator to have the same potential as VSS1.
Never connect the capacitor to a ground pattern carrying a large current.
• Never extract a signal from the oscillator.

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 µPD784035(A), 784036(A)

OSCILLATOR CHARACTERISTICS (TA = -40 to +85 °C, VDD = +2.7 to 5.5 V, VSS = 0 V)

Resonator Recommended circuit Parameter MIN. MAX. Unit

Ceramic resonator Oscillator frequency (fXX) 4 16 MHz
or crystal

VSS1 X1 X2

C1 C2

External clock X1 input frequency (fX) 4 16 MHz

X1 X2 X1 input rise and fall times 0 10 ns

(tXR, tXF)

X1 input high-level and low- 10 125 ns

HCMOS level widths (tWXH, tWXL)
inverter

Caution When using the system clock generator, run wires in the portion surrounded by broken lines
according to the following rules to avoid effects such as stray capacitance:

• Minimize the wiring.

• Never cause the wires to cross other signal lines.
• Never cause the wires to run near a line carrying a large varying current.
• Cause the grounding point of the capacitor of the oscillator to have the same potential as VSS1.
Never connect the capacitor to a ground pattern carrying a large current.
• Never extract a signal from the oscillator.

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 µPD784035(A), 784036(A)

DC CHARACTERISTICS (TA = -40 to +85 °C, VDD = AVDD = +2.7 to 5.5 V, VSS = AVSS = 0 V) (1/2)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Input low voltage VIL1 For pins other than those described in -0.3 0.3VDD V
Notes 1, 2, 3, and 4
VIL2 For pins described in Notes 1, 2, 3, and -0.3 0.2VDD V
4
VIL3 VDD = +5.0 V ± 10 % -0.3 +0.8 V
For pins described in Notes 2, 3, and 4

Input high voltage VIH1 For pins other than those described in 0.7VDD VDD + 0.3 V
Note 1
VIH2 For pins described in Note 1 0.8VDD VDD + 0.3 V
VIH3 VDD = +5.0 V ± 10 % 2.2 VDD + 0.3 V
For pins described in Notes 2, 3, and 4

Output low voltage VOL1 IOL = 2 mA 0.4 V

VOL2 VDD = +5.0 V ± 10 % 1.0 V
IOL = 8 mA
For pins described in Notes 2 and 5
Output high voltage VOH1 IOH = -2 mA VDD - 1.0 V
VOH2 VDD = +5.0 V ± 10 % VDD - 1.4 V
IOH = -5 mA
For pins described in Note 4
X1 input low current IIL EXTC = 0 -30 µA
0 V ≤ VI ≤ VIL2

X1 input high current IIH EXTC = 0 +30 µA

VIH2 ≤ VI ≤ VDD

Notes 1. X1, X2, RESET, P12/ASCK2/SCK2, P20/NMI, P21/INTP0, P22/INTP1, P23/INTP2/CI, P24/INTP3,
P25/INTP4/ASCK/SCK1, P26/INTP5, P27/SI0, P32/SCK0/SCL, P33/SO0/SDA, TEST
2. P40/AD0-P47/AD7, P50/A8-P57/A15
3. P60/A16-P63/A19, P64/RD, P65/WR, P66/WAIT/HLDRQ, P67/REFRQ/HLDAK
4. P00-P07
5. P10-P17

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 µPD784035(A), 784036(A)

DC CHARACTERISTICS (TA = -40 to +85 °C, VDD = AVDD = +2.7 to 5.5 V, VSS = AVSS = 0 V) (2/2)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Input leakage current ILI 0 V ≤ VI ≤ VDD ±10 µA

For pins other than X1 when EXTC = 0

Output leakage current ILO 0 V ≤ VO ≤ VDD ±10 µA

VDD supply current IDD1 Operation mode fXX = 32 MHz 25 45 mA
VDD = +5.0 V ± 10 %
fXX = 16 MHz 12 25 mA
VDD = +2.7 to 3.3 V
IDD2 HALT mode fXX = 32 MHz 13 26 mA
VDD = +5.0 V ± 10 %
fXX = 16 MHz 8 12 mA
VDD = +2.7 to 3.3 V
IDD3 IDLE mode fXX = 32 MHz 12 mA
(EXTC = 0) VDD = +5.0 V ± 10 %
fXX = 16 MHz 8 mA
VDD = +2.7 to 3.3 V
Pull-up resistor RL VI = 0 V 15 80 kΩ

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 µPD784035(A), 784036(A)

AC CHARACTERISTICS (TA = -40 to +85 °C, VDD = AVDD = +2.7 to 5.5 V, VSS = AVSS = 0 V)

(1) Read/write operation (1/2)

Parameter Symbol Conditions MIN. MAX. Unit

Address setup time tSAST VDD = +5.0 V ± 10 % (0.5 + a) T - 15 ns

(0.5 + a) T - 31 ns

ASTB high-level width tWSTH VDD = +5.0 V ± 10 % (0.5 + a) T - 17 ns

(0.5 + a) T - 40 ns

Address hold time (to ASTB↓) tHSTLA VDD = +5.0 V ± 10 % 0.5T - 24 ns

0.5T - 34 ns

Address hold time (to RD↑) tHRA 0.5T - 14 ns

Delay from address to RD↓ tDAR VDD = +5.0 V ± 10 % (1 + a) T - 9 ns

(1 + a) T - 15 ns

Address float time (to RD↓) tFRA 0 ns

Delay from address to data input tDAID VDD = +5.0 V ± 10 % (2.5 + a + n) T - 37 ns

(2.5 + a + n) T - 52 ns

Delay from ASTB↓ to data input tDSTID VDD = +5.0 V ± 10 % (2 + n) T - 40 ns

(2 + n) T - 60 ns

Delay from RD↓ to data input tDRID VDD = +5.0 V ± 10 % (1.5 + n) T - 50 ns

(1.5 + n) T - 70 ns

Delay from ASTB↓ to RD↓ tDSTR 0.5T - 9 ns

Data hold time (to RD↑) tHRID 0 ns

Delay from RD↑ to address active tDRA After program VDD = +5.0 V ± 10 % 0.5T - 8 ns
is read
0.5T - 12 ns
After data is VDD = +5.0 V ± 10 % 1.5T - 8 ns
read
1.5T - 12 ns

Delay from RD↑ to ASTB↑ tDRST 0.5T - 17 ns

RD low-level width tWRL VDD = +5.0 V ± 10 % (1.5 + n) T - 30 ns

(1.5 + n) T - 40 ns

Address hold time (to WR↑) tHWA 0.5T - 14 ns

Delay from address to WR↓ tDAW VDD = +5.0 V ± 10 % (1 + a) T - 5 ns

(1 + a) T - 15 ns

Delay from ASTB↓ to data output tDSTOD VDD = +5.0 V ± 10 % 0.5T + 19 ns

0.5T + 35 ns

Delay from WR↓ to data output tDWOD 0.5T - 11 ns

Delay from ASTB↓ to WR↓ tDSTW 0.5T - 9 ns

Remarks T: TCYK (system clock cycle time)

a: 1 (during address wait), otherwise, 0
n: Number of wait states (n ≥ 0)

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 µPD784035(A), 784036(A)

(1) Read/write operation (2/2)

Parameter Symbol Conditions MIN. MAX. Unit

Data setup time (to WR↑) tSODW VDD = +5.0 V ± 10 % (1.5 + n) T - 30 ns

(1.5 + n) T - 40 ns

Data hold time (to WR↑)Note tHWOD VDD = +5.0 V ± 10 % 0.5T - 5 ns

0.5T - 25 ns

Delay from WR↑ to ASTB↑ tDWST 0.5T - 12 ns

WR low-level width tWWL VDD = +5.0 V ± 10 % (1.5 + n) T - 30 ns

(1.5 + n) T - 40 ns

Note The hold time includes the time during which VOH1 and VOL1 are held under the load conditions of
CL = 50 pF and RL = 4.7 kΩ.

Remarks T: TCYK (system clock cycle time)

n: Number of wait states (n ≥ 0)

(2) Bus hold timing

Parameter Symbol Conditions MIN. MAX. Unit

Delay from HLDRQ↑ to float tFHQC (6 + a + n) T + 50 ns

Delay from HLDRQ↑ to HLDAK↑ tDHQHHAH VDD = +5.0 V ± 10 % (7 + a + n) T + 30 ns

(7 + a + n) T + 40 ns

Delay from float to HLDAK↑ tDCFHA 1T + 30 ns

Delay from HLDRQ↓ to HLDAK↓ tDHQLHAL VDD = +5.0 V ± 10 % 2T + 40 ns

2T + 60 ns

Delay from HLDAK↓ to active tDHAC VDD = +5.0 V ± 10 % 1T - 20 ns

1T - 30 ns

Remarks T: TCYK (system clock cycle time)

a: 1 (during address wait), otherwise, 0
n: Number of wait states (n ≥ 0)

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 µPD784035(A), 784036(A)

(3) External wait timing

Parameter Symbol Conditions MIN. MAX. Unit

Delay from address to WAIT↓ input tDAWT VDD = +5.0 V ± 10 % (2 + a) T - 40 ns

(2 + a) T - 60 ns

Delay from ASTB↓ to WAIT↓ input tDSTWT VDD = +5.0 V ± 10 % 1.5T - 40 ns

1.5T - 60 ns

Hold time from ASTB↓ to WAIT tHSTWTH VDD = +5.0 V ± 10 % (0.5 + n) T + 5 ns

(0.5 + n) T +10 ns

Delay from ASTB↓ to WAIT↑ tDSTWTH VDD = +5.0 V ± 10 % (1.5 + n) T - 40 ns

(1.5 + n) T - 60 ns

Delay from RD↓ to WAIT↓ input tDRWTL VDD = +5.0 V ± 10 % T - 50 ns

T - 70 ns

Hold time from RD↓ to WAIT↓ tHRWT VDD = +5.0 V ± 10 % nT + 5 ns

nT + 10 ns

Delay from RD↓ to WAIT↑ tDRWTH VDD = +5.0 V ± 10 % (1 + n) T - 40 ns

(1 + n) T - 60 ns

Delay from WAIT↑ to data input tDWTID VDD = +5.0 V ± 10 % 0.5T - 5 ns

0.5T - 10 ns

Delay from WAIT↑ to WR↑ tDWTW 0.5T ns

Delay from WAIT↑ to RD↑ tDWTR 0.5T ns

Delay from WR↓ to WAIT↓ input tDWWTL VDD = +5.0 V ± 10 % T - 50 ns

T - 75 ns

Hold time from WR↓ to WAIT tHWWT VDD = +5.0 V ± 10 % nT + 5 ns

nT + 10 ns

Delay from WR↓ to WAIT↑ tDWWTH VDD = +5.0 V ± 10 % (1 + n) T - 40 ns

(1 + n) T - 70 ns

Remarks T: TCYK (system clock cycle time)

a: 1 (during address wait), otherwise, 0
n: Number of wait states (n ≥ 0)

(4) Refresh timing

Parameter Symbol Conditions MIN. MAX. Unit

Random read/write cycle time tRC 3T ns

REFRQ low-level pulse width tWRFQL VDD = +5.0 V ± 10 % 1.5T - 25 ns

1.5T - 30 ns

Delay from ASTB↓ to REFRQ tDSTRFQ 0.5T - 9 ns

Delay from RD↑ to REFRQ tDRRFQ 1.5T - 9 ns

Delay from WR↑ to REFRQ tDWRFQ 1.5T - 9 ns

Delay from REFRQ↑ to ASTB tDRFQST 0.5T - 15 ns

REFRQ high-level pulse width tWRFQH VDD = +5.0 V ± 10 % 1.5T - 25 ns

1.5T - 30 ns

Remark T: TCYK (system clock cycle time)

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 µPD784035(A), 784036(A)

SERIAL OPERATION (TA = -40 to +85 °C, VDD = +2.7 to 5.5 V, AVSS = VSS = 0 V)

(1) CSI

Parameter Symbol Conditions MIN. MAX. Unit

Serial clock cycle time (SCK0) tCYSK0 Input External clock 10/fXX + 380 ns
When SCK0 and SO0 are CMOS I/O
Output T µs
Serial clock low-level width tWSKL0 Input External clock 5/fXX + 150 ns
(SCK0) When SCK0 and SO0 are CMOS I/O
Output 0.5T - 40 µs
Serial clock high-level width tWSKH0 Input External clock 5/fXX + 150 ns
(SCK0) When SCK0 and SO0 are CMOS I/O
Output 0.5T - 40 µs
SI0 setup time (to SCK0↑) tSSSK0 40 ns

SI0 hold time (to SCK0↑) tHSSK0 5/fXX + 40 ns

SO0 output delay time tDSBSK1 CMOS push-pull output 0 5/f XX + 150 ns
(to SCK0↓) (3-wire serial I/O mode)
tDSBSK2 Open-drain output 0 5/f XX + 400 ns
(2-wire serial I/O mode), RL = 1 kΩ

Remarks 1. The values in this table are those when CL is 100 pF.
2. T : Serial clock cycle set by software. The minimum value is 16/fXX.
3. fXX : Oscillator frequency

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 µPD784035(A), 784036(A)

(2) IOE1, IOE2

Parameter Symbol Conditions MIN. MAX. Unit

Serial clock cycle time tCYSK1 Input VDD = +5.0 V ± 10 % 250 ns

(SCK1, SCK2) ns
500
Output Internal, divided by 16 T ns

Serial clock low-level width tWSKL1 Input VDD = +5.0 V ± 10 % 85 ns

(SCK1, SCK2) ns
210
Output Internal, divided by 16 0.5T - 40 ns

Serial clock high-level width tWSKH1 Input VDD = +5.0 V ± 10 % 85 ns

(SCK1, SCK2) 210 ns

Output Internal, divided by 16 0.5T - 40 ns

Setup time for SI1 and SI2 tSSSK1 40 ns

(to SCK1, SCK2↑)
Hold time for SI1 and SI2 tHSSK1 40 ns
(to SCK1, SCK2↑)
Output delay time for SO1 and tDSOSK 0 50 ns
SO2 (to SCK1, SCK2↓)
Output hold time for SO1 and tHSOSK When data is transferred 0.5tCYSK1 - 40 ns
SO2 (to SCK1, SCK2↑)

Remarks 1. The values in this table are those when CL is 100 pF.
2. T: Serial clock cycle set by software. The minimum value is 16/fXX.

(3) UART, UART2

Parameter Symbol Conditions MIN. MAX. Unit

ASCK clock input cycle time tCYASK VDD = +5.0 V ± 10 % 125 ns

250 ns

ASCK clock low-level width tWASKL VDD = +5.0 V ± 10 % 52.5 ns

85 ns

ASCK clock high-level width tWASKH VDD = +5.0 V ± 10 % 52.5 ns

85 ns

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 µPD784035(A), 784036(A)

CLOCK OUTPUT OPERATION

Parameter Symbol Conditions MIN. MAX. Unit

CLKOUT cycle time tCYCL nT ns

CLKOUT low-level width tCLL VDD = +5.0 V ± 10 % 0.5tCYCL - 10 ns

0.5tCYCL - 20 ns

CLKOUT high-level width tCLH VDD = +5.0 V ± 10 % 0.5tCYCL - 10 ns

0.5tCYCL - 20 ns

CLKOUT rise time tCLR VDD = +5.0 V ± 10 % 10 ns

20 ns

CLKOUT fall time tCLF VDD = +5.0 V ± 10 % 10 ns

20 ns

Remarks n: Divided frequency ratio set by software in the CPU (n = 1, 2, 4, 8, 16)

T: tCYK (system clock cycle time)

OTHER OPERATIONS

Parameter Symbol Conditions MIN. MAX. Unit

NMI low-level width tWNIL 10 µs

NMI high-level width tWNIH 10 µs
INTP0 low-level width tWIT0L 4tCYSMP ns

INTP0 high-level width tWIT0H 4tCYSMP ns

Low-level width for INTP1- tWIT1L 4tCYCPU ns

INTP3 and CI
High-level width for INTP1- tWIT1H 4tCYCPU ns
INTP3 and CI
Low-level width for INTP4 and tWIT2L 10 µs
INTP5
High-level width for INTP4 and tWIT2H 10 µs
INTP5
RESET low-level width tWRSL 10 µs
RESET high-level width tWRSH 10 µs

Remarks tCYSMP: Sampling clock set by software

tCYCPU: CPU operation clock set by software in the CPU

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 µPD784035(A), 784036(A)

A/D CONVERTER CHARACTERISTICS

(TA = -40 to +85 °C, VDD = AV DD = AVREF1 = +2.7 to 5.5 V, VSS = AVSS = 0 V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Resolution 8 bit

Total errorNote 1.0 %

Linearity calibrationNote 0.8 %

Quantization error ±1/2 LSB

Conversion time tCONV FR = 1 120 tCYK

FR = 0 180 tCYK

Sampling time tSAMP FR = 1 24 tCYK

FR = 0 36 tCYK

Analog input voltage VIAN -0.3 AVREF1 + 0.3 V

Analog input impedance RAN 1 000 MΩ

AVREF1 current AIREF1 0.5 1.5 mA

AVDD supply current AIDD1 fXX = 32 MHz, CS = 1 2.0 5.0 mA

AIDD2 STOP mode, CS = 0 1.0 20 µA

Note Quantization error is not included. This parameter is indicated as the ratio to the full-scale value.

Remark tCYK: System clock cycle time

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 µPD784035(A), 784036(A)

D/A CONVERTER CHARACTERISTICS (TA = -40 to +85 °C, VDD = AVDD = +2.7 to 5.5 V, VSS = AVSS = 0 V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Resolution 8 bit

Total error Load conditions: VDD = AVDD = AVREF2 0.6 %

4 MΩ, 30 pF = +2.7 to 5.5 V
AVREF3 = 0 V
VDD = AVDD = +2.7 to 5.5 V 0.8 %
AVREF2 = 0.75VDD
AVREF3 = 0.25VDD
Load conditions: VDD = AVDD = AVREF2 0.8 %
2 MΩ, 30 pF = +2.7 to 5.5 V
AVREF3 = 0 V
VDD = AVDD = +2.7 to 5.5 V 1.0 %
AVREF2 = 0.75VDD
AVREF3 = 0.25VDD

Settling time Load conditions: 2 MΩ, 30 pF 10 µs

Output resistance RO DACS0, 1 = 55 H 10 kΩ
Analog reference voltage AVREF2 0.75VDD VDD V
AVREF3 0 0.25VDD V

Resistance of AVREF2 and RAIREF DACS0, 1 = 55 H 4 8 kΩ

AVREF3
Reference power supply AIREF2 0 5 mA
input current AIREF3 -5 0 mA

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 µPD784035(A), 784036(A)

DATA RETENTION CHARACTERISTICS (TA = -40 to +85 °C)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Data retention voltage VDDDR STOP mode 2.5 5.5 V

Data retention current IDDDR VDDDR = +2.7 to 5.5 V 10 50 µA

VDDDR = +2.5 V 2 10 µA
VDD rise time tRVD 200 µs
VDD fall time tFVD 200 µs
VDD hold time tHVD 0 ms
(to STOP mode setting)
STOP clear signal input time tDREL 0 ms
Oscillation settling time tWAIT Crystal 30 ms
Ceramic resonator 5 ms
Input low voltage VIL Specific pinsNote 0 0.1VDDDR V

Input high voltage VIH 0.9VDDDR VDDDR V

Note RESET, P20/NMI, P21/INTP0, P22/INTP1, P23/INTP2/CI, P24/INTP3, P25/INTP4/ASCK/SCK1,

P26/INTP5, P27/SI0, P32/SCK0/SCL, and P33/SO0/SDA pins

AC TIMING TEST POINTS

VDD - 1 V
0.8VDD or 2.2 V 0.8VDD or 2.2 V
Test points
0.8 V 0.8 V
0.45 V

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 µPD784035(A), 784036(A)

TIMING WAVEFORM

(1) Read operation

tWSTH

ASTB

tSAST tDRST
tDSTID
tHSTLA

A8-A19

tDAID tHRA

AD0-AD7

tDSTR tFRA tHRID

tDAR tDRID tDRA

RD

tWRL

(2) Write operation

tWSTH

ASTB

tSAST tDWST
tDSTOD
tHSTLA

A8-A19

tHWA

AD0-AD7

tDSTW tHWOD
tDAW tDWOD tSODW

WR

tWWL

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 µPD784035(A), 784036(A)

HOLD TIMING

ADTB, A8-A19,
AD0-AD7, RD, WR
tFHQC
tDCFHA tDHAC

HLDRQ

tDHQLHAL
tDHQHHAH

HLDAK

EXTERNAL WAIT SIGNAL INPUT TIMING

(1) Read operation

ASTB

tDSTWTH
tHSTWTH
tDSTWT

A8-A19

AD0-AD7

tDAWT tDWTID

RD

tDRWTL tDWTR

WAIT

tHRWT
tDRWTH

(2) Write operation

ASTB

tDSTWTH
tHSTWTH
tDSTWT

A8-A19

AD0-AD7

tDAWT

WR

tDWWTL tDWTW

WAIT

tHWWT
tDWWTH

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 µPD784035(A), 784036(A)

REFRESH TIMING WAVEFORM

(1) Random read/write cycle

tRC
ASTB

WR

tRC tRC tRC tRC

RD

(2) When refresh memory is accessed for a read and write at the same time

ASTB

RD, WR

tDSTRFQ tDRFQST
tWRFQH

REFRQ

tWRFQL

(3) Refresh after a read

ASTB

tDRFQST

RD

tDRRFQ

REFRQ

tWRFQL

(4) Refresh after a write

ASTB

tDRFQST

WR

tDWRFQ

REFRQ

tWRFQL

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 µPD784035(A), 784036(A)

SERIAL OPERATION

(1) CSI

tWSKL0 tWSKH0

SCK

tSSSK0 tHSSK0
tCYSK0

SI Input data

tDSBSK1 tHSBSK1

SO Output data

(2) IOE1, IOE2

tWSKL1 tWSKH1

SCK

tSSSK1 tHSSK1
tCYSK1

SI Input data

tDSOSK tHSOSK

SO Output data

(3) UART, UART2

tWASKH tWASKL

ASCK,
ASCK2

tCYASK

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 µPD784035(A), 784036(A)

CLOCK OUTPUT TIMING

tCLH tCLL

CLKOUT

tCLR tCLF

tCYCL

INTERRUPT REQUEST INPUT TIMING

tWNIH tWNIL

NMI

tWIT0H tWIT0L

INTP0

tWIT1H tWIT1L

CI,
INTP1-INTP3

tWIT2H tWIT2L

INTP4, INTP5

RESET INPUT TIMING

tWRSH tWRSL

RESET

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 µPD784035(A), 784036(A)

EXTERNAL CLOCK TIMING

tWXH tWXL

X1

tXR tXF

tCYX

DATA RETENTION CHARACTERISTICS

STOP mode setting

VDD
VDDDR
tDREL
tHVD tFVD tRVD tWAIT

RESET

NMI
(Clearing by falling edge)

NMI
(Clearing by rising edge)

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 µPD784035(A), 784036(A)

14. PACKAGE DRAWINGS

80 PIN PLASTIC QFP (14x14)

A
B

60 41
61 40

detail of lead end

C D S

Q R

80 21
1 20
F

G J
H I M

K
P
M

N
L
NOTE ITEM MILLIMETERS INCHES
Each lead centerline is located within 0.13 mm (0.005 inch) of A 17.2±0.4 0.677±0.016
its true position (T.P.) at maximum material condition.
B 14.0±0.2 0.551 +0.009
–0.008

C 14.0±0.2 0.551 +0.009

–0.008
D 17.2±0.4 0.677±0.016
F 0.825 0.032
G 0.825 0.032
H 0.30±0.10 0.012 +0.004
–0.005
I 0.13 0.005
J 0.65 (T.P.) 0.026 (T.P.)
K 1.6±0.2 0.063±0.008
L 0.8±0.2 0.031 +0.009
–0.008
M 0.15 +0.10 +0.004
0.006 –0.003
–0.05
N 0.10 0.004
P 2.7±0.1 0.106 +0.005
–0.004
Q 0.1±0.1 0.004±0.004
R 5°±5° 5°±5°
S 3.0 MAX. 0.119 MAX.
S80GC-65-3B9-5

Remark The shape and material of the ES version are the same as those of the corresponding mass-produced
product.

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 µPD784035(A), 784036(A)

15. RECOMMENDED SOLDERING CONDITIONS

The conditions listed below shall be met when soldering the µPD784035(A) and µPD784036(A).
For details of the recommended soldering conditions, refer to our document Semiconductor Device Mounting
Technology Manual (C10535E).
Please consult with our sales offices in case any other soldering process is used, or in case soldering is done under
different conditions.

Table 15-1. Soldering Conditions for Surface-Mount Devices

µPD784035GC(A)-×××-3B9: 80-pin plastic QFP (14 × 14 mm)

µPD784036GC(A)-×××-3B9: 80-pin plastic QFP (14 × 14 mm)

Soldering process Soldering conditions Symbol

Infrared ray reflow Peak package's surface temperature: 235 °C IR35-00-3

Reflow time: 30 seconds or less (210 °C or more)
Maximum allowable number of reflow processes: 3

VPS Peak package's surface temperature: 215 °C VP15-00-3

Reflow time: 40 seconds or less (200 °C or more)
Maximum allowable number of reflow processes: 3

Wave soldering Solder temperature: 260 °C or less WS60-00-1

Flow time: 10 seconds or less
Number of flow processes: 1
Preheating temperature : 120 °C max. (measured on the package surface)

Partial heating method Terminal temperature: 300 °C or less -

Heat time: 3 seconds or less (for one side of a device)

Caution Do not apply two or more different soldering methods to one chip (except for partial heating
method for terminal sections).

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 µPD784035(A), 784036(A)

APPENDIX A DEVELOPMENT TOOLS

The following development tools are available for system development using the µPD784036(A).
See also (5).

(1) Language processing software

RA78K4 Assembler package for all 78K/IV series models

CC78K4 C compiler package for all 78K/IV series models

DF784038 Device file for µPD784038 sub-series models

CC78K4-L C compiler library source file for all 78K/IV series models

(2) PROM write tools

PG-1500 PROM programmer

PA-78P4026GC Programmer adaptor, connects to PG-1500

PG-1500 controller Control program for PG-1500

(3) Debugging tools

• When using the in-circuit emulator IE-78K4-NS

IE-78K4-NSNote In-circuit emulator for all 78K/IV series models

IE-70000-MC-PS-B Power supply unit for IE-78K4-NS

IE-70000-98-IF-CNote Interface adapter when the PC-9800 series computer (other than a notebook)
is used as the host machine

IE-70000-CD-IFNote PC card and interface cable when a PC-9800 series notebook is used as the
host machine

IE-70000-PC-IF-CNote Interface adapter when the IBM PC/ATTM or compatible is used as the host
machine

IE-784038-NS-EM1Note Emulation board for evaluating µPD784038 sub-series models

NP-80GC Emulation probe for 80-pin plastic QFP (GC-3B9 type)

EV-9200GC-80 Socket for mounting on target system board made for 80-pin plastic QFP
(GC-3B9 type)

ID78K4-NSNote Integrated debugger for IE-78K4-NS

SM78K4-NS System simulator for all 78K/IV series models

DF784038 Device file for µPD784038 sub-series models

Note Under development

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 µPD784035(A), 784036(A)

• When using the in-circuit emulator IE-784000-R

IE-784000-R In-circuit emulator for all 78K/IV series models

IE-70000-98-IF-B Interface adapter when the PC-9800 series computer (other than a notebook)
IE-70000-98-IF-CNote is used as the host machine

IE-70000-98N-IF-B Interface adapter and cable when a PC-9800 series notebook is used as the
host machine

IE-70000-PC-IF-B Interface adapter when the IBM PC/AT or compatible is used as the host
IE-70000-PC-IF-CNote machine

IE-78000-R-SV3 Interface adapter and cable when the EWS is used as the host machine

IE-784038-NS-EM1Note Emulation board for evaluating µPD784038 sub-series models

IE-784038-R-EM1Note

IE-78400-R-EM Emulation board for all 78K/IV series models

IE-78K4-R-EX2Note Conversion board for 80 pins to use the IE-784038-NS-EM1 on the

IE-784000-R. The board is not needed when the conventional product
IE-784038-R-EM1 is used.

EP-78230GC-R Emulation probe for 80-pin plastic QFP (GC-3B9 type)

EV-9200GC-80 Socket for mounting on target system board made for 80-pin plastic QFP
(GC-3B9 type)

ID78K4 Integrated debugger for IE-784000-R

SM78K4 System simulator for all 78K/IV series models

DF784038 Device file for µPD784038 sub-series models

Note Under development

(4) Real-time OS

RX78K/IV Real-time OS for 78K/IV series models

MX78K4 OS for 78K/IV series models

83
 µPD784035(A), 784036(A)

(5) Notes when using development tools

• The ID78K-NS, ID78K4, and SM78K4 can be used in combination with the DF784038.
• The CC78K and RX78K/IV can be used in combination with the RA78K4 and DF784038.

• The NP-80GC is a product from Naito Densei Machida Seisakusho Co., Ltd. (044-822-3813). Consult the NEC
sales representative for purchasing.

• The host machines and operating systems corresponding to each software are shown below.

Host machine PC EWS

[OS] PC-9800 Series [WindowsTM] HP9000 Series 700TM [HP-UXTM]
IBM PC/AT and compatibles [Windows] SPARCstationTM [SunOSTM]
NEWSTM (RISC) [NEWS-OSTM]
Software
RA78K4 Note

CC78K4 Note

PG-1500 controller Note -

ID78K4-NS -
ID78K4
SM78K4 -
RX78K/IV Note

MX78K4 Note

Note Software under MS-DOS

84
 µPD784035(A), 784036(A)

APPENDIX B RELATED DOCUMENTS

Documents Related to Devices

Document No.
Document name
Japanese English

µPD784035(A), 784036(A) Data Sheet U13010J This manual

µPD784031(A) Data Sheet U13009J Under creation

µPD78P4038(A) Data Sheet To be created To be created

µPD784038, 784038Y Sub-Series User's Manual, Hardware U11316J U11316E

µPD784038 Sub-Series Special Function Registers U11090J -

78K/IV Series User's Manual, Instruction U10905J U10905E

78K/IV Series Instruction Summary Sheet U10594J -

78K/IV Series Instruction Set U10595J -

78K/IV Series Application Note, Software Basic U10095J -

Documents Related to Development Tools (User’s Manual)

Document No.
Document name
Japanese English

RA78K4 Assembler Package Operation U11334J U11334E

Language U11162J U11162E

RA78K Series Structured Assembler Preprocessor U11743J U11743E

CC78K4 C Compiler Operation U11572J U11572E

Language U11571J U11571E

CC78K Series Library Source File U12322J U12322E

PG-1500 PROM Programmer U11940J U11940E

PG-1500 Controller PC-9800 Series (MS-DOSTM) Base EEU-704 EEU-1291

PG-1500 Controller IBM PC Series (PC DOSTM) Base EEU-5008 U10540E

IE-78K4-NS Under creation To be created

IE-784000-R U12903J EEU-1534

IE-784038-NS-EM1 To be created To be created

IE-784038-R-EM1 U11383J U11383E

EP-78230 EEU-985 EEU-1515

SM78K4 System Simulator Windows Base Reference U10093J U10093E

SM78K Series System Simulator External Parts User Open U10092J U10092E
Interface Specifications

ID78K4 Integrated Debugger Reference U12796J U12796E

ID78K4 Integrated Debugger Windows Base Reference U10440J U10440E

ID78K4 Integrated Debugger HP-UX, SunOS, NEW-OS Base Reference U11960J U11960E

Caution The above documents may be revised without notice. Use the latest versions when you design
application systems.

85
 µPD784035(A), 784036(A)

Documents Related to Software to Be Incorporated into the Product (User’s Manual)

Document No.
Document name
Japanese English

78K/IV Series Real-Time OS Basic U10603J U10603E

Installation U10604J U10604E

Debugger U10364J -

OS for 78K/IV Series MX78K4 Basic U11779J -

Other Documents

Document No.
Document name
Japanese English

IC PACKAGE MANUAL C10943X

Semiconductor Mount Technology Manual C10535J C10535E

Quality Grades on NEC Semiconductor Device C11531J C11531E

NEC Semiconductor Device Reliability/Quality Control System C10983J C10983E

Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) U11892J E11892E

Semiconductor Device Quality Control/Reliability Handbook C12769J -

Guide for Products Related to Micro-Computer: Other Companies C11416J -

Caution The above documents may be revised without notice. Use the latest versions when you design
application systems.

86
 µPD784035(A), 784036(A)

NOTES FOR CMOS DEVICES

1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note: Strong electric field, when exposed to a MOS device, can cause destruction
of the gate oxide and ultimately degrade the device operation. Steps must
be taken to stop generation of static electricity as much as possible, and
quickly dissipate it once, when it has occurred. Environmental control must
be adequate. When it is dry, humidifier should be used. It is recommended
to avoid using insulators that easily build static electricity. Semiconductor
devices must be stored and transported in an anti-static container, static
shielding bag or conductive material. All test and measurement tools
including work bench and floor should be grounded. The operator should
be grounded using wrist strap. Semiconductor devices must not be touched
with bare hands. Similar precautions need to be taken for PW boards with
semiconductor devices on it.

2 HANDLING OF UNUSED INPUT PINS FOR CMOS

Note: No connection for CMOS device inputs can be cause of malfunction. If no

connection is provided to the input pins, it is possible that an internal input
level may be generated due to noise, etc., hence causing malfunction. CMOS
device behave differently than Bipolar or NMOS devices. Input levels of
CMOS devices must be fixed high or low by using a pull-up or pull-down
circuitry. Each unused pin should be connected to VDD or GND with a
resistor, if it is considered to have a possibility of being an output pin. All
handling related to the unused pins must be judged device by device and
related specifications governing the devices.

3 STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note: Power-on does not necessarily define initial status of MOS device. Produc-
tion process of MOS does not define the initial operation status of the device.
Immediately after the power source is turned ON, the devices with reset
function have not yet been initialized. Hence, power-on does not guarantee
out-pin levels, I/O settings or contents of registers. Device is not initialized
until the reset signal is received. Reset operation must be executed imme-
diately after power-on for devices having reset function.

87
 µPD784035(A), 784036(A)

IEBus is a trademark of NEC Corporation.

MS-DOS and Windows are registered trademarks or trademarks of Microsoft Corporation in the United States
and/or other countries.
PC/AT, and PC DOS are trademarks of IBM Corporation.
HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
SunOS is a trademark of Sun Microsystems, Inc.
NEWS and NEWS-OS are trademarks of SONY Corporation.

88
 µPD784035(A), 784036(A)

Regional Information

Some information contained in this document may vary from country to country. Before using any NEC
product in your application, pIease contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:

• Device availability

• Ordering information

• Product release schedule

• Availability of related technical literature

• Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)

• Network requirements

In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.

NEC Electronics Inc. (U.S.) NEC Electronics (Germany) GmbH NEC Electronics Hong Kong Ltd.
Santa Clara, California Benelux Office Hong Kong
Tel: 408-588-6000 Eindhoven, The Netherlands Tel: 2886-9318
800-366-9782 Tel: 040-2445845 Fax: 2886-9022/9044
Fax: 408-588-6130 Fax: 040-2444580
800-729-9288 NEC Electronics Hong Kong Ltd.
NEC Electronics (France) S.A. Seoul Branch
NEC Electronics (Germany) GmbH Velizy-Villacoublay, France Seoul, Korea
Duesseldorf, Germany Tel: 01-30-67 58 00 Tel: 02-528-0303
Tel: 0211-65 03 02 Fax: 01-30-67 58 99 Fax: 02-528-4411
Fax: 0211-65 03 490
NEC Electronics (France) S.A. NEC Electronics Singapore Pte. Ltd.
NEC Electronics (UK) Ltd. Spain Office United Square, Singapore 1130
Milton Keynes, UK Madrid, Spain Tel: 253-8311
Tel: 01908-691-133 Tel: 01-504-2787 Fax: 250-3583
Fax: 01908-670-290 Fax: 01-504-2860
NEC Electronics Taiwan Ltd.
NEC Electronics Italiana s.r.1. NEC Electronics (Germany) GmbH Taipei, Taiwan
Milano, Italy Scandinavia Office Tel: 02-719-2377
Tel: 02-66 75 41 Taeby, Sweden Fax: 02-719-5951
Fax: 02-66 75 42 99 Tel: 08-63 80 820
Fax: 08-63 80 388 NEC do Brasil S.A.
Cumbica-Guarulhos-SP, Brasil
Tel: 011-6465-6810
Fax: 011-6465-6829

J97. 8

89
 µPD784035(A), 784036(A)

Some related documents may be preliminary versions. Note that, however, what documents are preliminary is not indicated
in this document.

The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited
without governmental license, the need for which must be judged by the customer. The export or re-export of this product
from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.

No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this
document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from use of a device described herein or any other liability arising
from use of such device. No license, either express, implied or otherwise, is granted under any patents,
copyrights or other intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on
a customer designated "quality assurance program" for a specific application. The recommended applications
of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each
device before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.

M4 96. 5