Anupam Jena (21HCS4119)

Skand Singh Chauhan (21HCS4182)

Shauryaditya Gauniyal (21HCS4179)
Tanushree (21HCS4186)
Yashika Yadav (21HCS4195)
CLOCK GENERATOR (8284A)

ANUPAM
 CONTENTS

01 02 03 04
Basic Functions PIN Diagram Logic Diagram Interfacing
• 8824 clock generator is an IC developed by Intel.

• Generates system clock signal for 8086/8088 microprocessor

and peripherals.

• Without clock generator, it requires many additional circuits to

generate the clock in an 8086/8088-based system.

• 8284A basic functions or signals:

clock generation, RESET synchronization, READY synchronization,

and a TTL level peripheral clock signal which are very important
essential signal to microprocessors.
• It provides a stable clock to the processors and peripherals.

• Along with the clock signal it also generates ready and reset signal
8086,8088 processor.

• Available in the 18 pin (DIP) package.

• Operates on a signal +5v supply.

• It can use either a crystal or a TTL external signal as frequency

source.

• It is Capable of clock synchronization with other 8284 chip.

PIN DIAGRAM OF 8284A
PIN FUNCTIONS

Vcc We connect +5V power supply here with 10% tolerance

which is used to operate 8284 clock generator

X1 Used as input pins in internal crystal oscillator. We

connect external crystal with these pins. The external
crystal work as operating frequency source

X2
Ready Synchronization Select Pin: It defines synchronization mode of READY signal. If

ASYNC’ the pin is low then 2 stage ready synchronization is provided and if the pin is high then
single stage READY synchronization is provided in the 8284 clock generator

EFI External Frequency Input Pin: It also works as frequency source for 8284 clock generator

Frequency/Crystal Select Pin: This pin is used to select clocking source of 8284 clock generator. If

F/C’ this pin is high then EFI signals are sent in 8284 clock generator as a frequency source and if this
pin is low then the internal crystal oscillator provides the timing signal
OSC Oscillator Pin: This is an output pin. It is the oscillator output which the 8284 clock generator
generates which is directly sent to 8086 microprocessor

RES’ RESET Input Pin: This is an active low pin. This pin is used to reset the 8284 clock generator

RESET It is an output pin. This output is generated by 8284 clock

generator which is sent to 8086/8088 RESET input pin

GND Ground: This pin is used for Ground Connection

CLK Clock: This is an output pin. The clock signal which is generated by 8284 is used as
input signal for 8086/8088 based systems

AEN’1 These are input pins. These pins are used simultaneously to provide READY signal to
the microprocessor as a result the microprocessor generates a WAIT signal to the CPU
for R/W cycle

RDY1
RDY2 These pins are also used simultaneously to provide READY signal to the microprocessor
as a result the microprocessor generates a WAIT signal to the CPU for R/W cycle

AEN’2
READY It is an output pin. The READY signal which is generated by 8284 is directly sent to 8086/8088
READY input pin and it is synchronized with RDY1 and RDY2 inputs

PCLK
Peripheral Clock Output pin: Through this pin ,peripheral clock signals which is
generated by 8284, is sent to those devices which have requirement of low frequency
like 8254 because PCLK signals’ frequency is 1/6th of external crystals’ frequenecy

CSYNC Clock Synchronization pin: This is an input pin. This pin allows several 8284 chips to
simultaneously connect to each other and synchronize
LOGIC DIAGRAM OF 8284 CLOCK GENERATOR
WORKING OF 8284 CLOCK GENERATOR

8284 clock generator generates some important signals like RESET signal,
Oscillator signal, Peripheral clock signal, clock signal and READY signal for
8086/8088 microprocessor or other peripheral devices
• RESET Section

Reset section basically composes of 2 components: Schmitt Trigger & D type

flip flop

• D type flip flop ensures the timing requirement of 8086 RESET

The RESET section produces RESET output which is applied to the

microprocessor on -ve edge of each clock cycle and 8086 microprocessor
samples this RESET signal at each +ve edge of the clock cycle
• Clock Section
Clock section produces 3 output signals: Oscillator output signal, Peripheral
clock signal, clock signal

It consists of components: External Crystal Oscillator, 2:1 Multiplexer, div by 3

counter, div by 2 counter & the inverting buffer

The crystal oscillator generates a square wave signal at its output when the
crystal is attached between the 2 input pins X1 & X2.

From X1 & X2 we connect the external 15 Mhz crystal so that the crystal
oscillator produce a square wave whose frequency is equal to the frequency of
the external crystal.
This square wave output signal is simultaneously feed into the inverter and to
the AND gate of the 2:1 multiplexer.

This inverter produces oscillator signals at its output. This oscillator signal is
sometimes used as the EFI signal to other 8284 clock generator in a system
The output of the oscillator is sent to the AND gate of the 2:1 multiplexer or
EFI is sent to the div by 3 counter if select by the F/C’ input pin.

The function of F/C’ pin is to choose a frequency source for 8284 clock
generator.

If F/C’ pin is high then it is logical 1 and EFI signal is sent to the div by 3 counter,
and if the pin is low then it is logical 0, and the square wave produced by
Crystal Oscillator is sent to the div by 3 counter.

Now the output of the div by 3 counter is sent to the D type flip flop of ready
segment that provides timing for READY synchronization.
The output of the div by 3 counter is also sent to the div by 2 counter that
generates PCLK-Peripheral Clock Signal as its output which sent to peripheral
devices having low frequency requirement and the output of div by 3 counter
is sent as clock signal to the 8086 microprocessor.
 Interfacing of 8284 with 8086
• The clock signal generated by 8284 is sent to the 8086 microprocessor i.e.
5MHz.
• RESET signal is directly sent to 8086 microprocessor.
• PCLK is sent to those devices having low frequency requirement.
• X1,X2 are input pins for internal crystal oscillator which is conncted to an
external 15 MHz crystal.
• F/C’ or clock synchronization pin are Grounded to select external crystal
THANK YOU
Demultiplexing address and
data buses
 Multiplexing
• A Multiplexer is a system of multiple inputs and just one output to
receive signals coming from multiple acquisition networks. The
device transfers all input signals to a microprocessor, which
receives and processes the data, transmits it to the output devices,
and controls the system as a whole.

• The main reason of multiplexing address and data bus is to reduce

the number of pins for address and data and dedicate those pins
for other several functions of microprocessor. These multiplexed
set of lines used to carry the lower order 8 bit address as well as
data bus.
 Need for Demultiplexing
Multiplexing burdens the hardware designer with the
task of extracting or demultiplexing information from
these multiplexed pins.
Memory and I/O require that the address remains valid
and stable throughout a read or write cycle. If the buses
are multiplexed, the address changes at the memory
and I/O, which causes them to read or write data in the
wrong locations
 Demultiplexing 8086 & 8088
microprocessors
All the computer system includes 3 buses:
1. an address bus that provides the memory and I/O with
the memory address or the I/O port number.
2. A data bus that transfers data between the
microprocessor and the memory and I/O in the system
3. a control bus that provides control signals to the
memory and I/O.
These buses must be present in order to interface to
memory and I/O
Demultiplexing 8088 microprocessors
• In the 8088 microprocessor, the multiplexed address are
the address and bus data connections, that is, A19/S6–
A16/S3 and AD7–AD0. Now, these are demultiplexed
with two 74LS373 or 74LS573 transparent latches.
• These transparent latches, which are like wires
whenever the address latch enable pin (ALE) becomes a
logic 1, pass the inputs to the outputs. After a short
time, ALE returns to its logic 0 condition, which causes
the latches to remember the inputs at the time of the
change to a logic 0.
 Demultiplexing 8088
microprocessors
• In this case, A7–A0 are stored in the bottom latch and
A19–A16 are stored in the top latch. This yields a
separate address bus with connections A19–A0. These
address connections allow the 8088 to address 1M byte
of memory space. The fact that the data bus is separate
allows it to be connected to any 8-bit peripheral device
or memory component.
 Demultiplexing 8086
microprocessors
Like the 8088, the 8086 system requires separate address,
data, and control buses. It differs primarily in the number of
multiplexed pins. In the 8088, only AD7–AD0 and A19/S6–
A16/S3 are multiplexed. In the 8086, the multiplexed pins
include AD15–AD0 A19/S6–A16/S3, and /S7. All of these
signals must be demultiplexed.
Demultiplexing 8086 microprocessors
The circuit shown is almost identical to the one pictured in
8088 microprocessor, except that an additional 74LS373
latch has been added to demultiplex the address/data bus
pins AD15–AD8 and a /S7 input has been added to the top
74LS373 to select the high-order memory bank in the l6-bit
memory system of the 8086. Here, the memory and I/O
system see the 8086 as a device with a 20-bit address bus
(A19–A0), a l6-bit data bus (D15–D0), and a three-line
control bus.
THE BUFFERED SYSTEM

SKAND
• It is a temporary holding area for data while it's waiting to be
transferred to another location.

• The concept of the buffer was developed in order to prevent

data congestion from an incoming to an outgoing port of
transfer.

• If more than 10 unit loads are attached to any bus pin, the
entire 8086 or 8088 system must be buffered.

• The demultiplexed pins are already buffered by the 74LS373 or

74LS573 latches.

• It have been designed to drive the high-capacitance buses

encountered in microcomputer system.
• The buffer’s output currents have been increased so that more TTL unit
loads may be driven:
1. A logic 0 output provides up to 32 mA of sink current.
2. A logic 1 output provides up to 5.2 mA of source current .

• A fully buffered signal will introduce a timing delay to the system.

• Both 74LS373 or 74LS573 are octal D-type latch, which are commonly
used component in digital electronics and microprocessor-based
systems.

• It can use either a crystal or a TTL external signal as frequency

source.

• It is Capable of clock synchronization with other 8284 chip.

THE FULLY BUFFERED 8088

SKAND
FULLY BUFFERED 8088
• Notice
1. The remaining eight address pins, A15–A8, use a 74LS244
octal buffer.
2. The eight data bus pins, D7–D0, use a 74LS245 octal
bidirectional bus buffer.
3. The control bus signals, M/IO’, RD’ and WR’, use a
74LS244 buffer.

• A fully buffered 8088 system requires two 74LS244s, one

74LS245, and two 74LS373s.

• The direction of the 74LS245 is controlled by the DT/R’ signal

and is enabled and disabled by the DEN’ signal.
THE FULLY BUFFERED 8086

SKAND
FULLY BUFFERED 8086
• Notice
1. . Its address pins are already buffered by the 74LS373
address latches.
2. Its data bus employs two 74LS245 octal bidirectional
bus buffers.
3. The control bus signals, M/IO’ ,RD’ , and WR’ use a
74LS244 buffer.

• A fully buffered 8086 system requires one 74LS244, two

74LS245s, and three 74LS373s.

• The 8086 requires one more buffer than the 8088 because of
the extra eight data bus connections, D15–D8.

• It also has a BHE’ signal that is buffered for memory-bank

selection.