Board Design

A HDMI design guide for successful

high-speed PCB design
By Thomas Kugelstadt, impedance for transmis-
Senior Systems Engineer, sion line interconnects and
Texas Instruments Inc. provides an excellent low-in-
ductance path for the return
Introduction current flow.
This article presents design • Placing the power plane next
guidelines for helping users of to the ground plane creates
HDMI mux-repeaters to maximise additional high-frequency
the device’s full performance bypass capacitance.
through careful printed circuit • Routing the slower speed con-
board (PCB) design. We’ll explain trol signals on the bottom layer
important concepts of some allows for greater flexibility as
main aspects of high-speed PCB these signal links usually have
design with recommendations. margin to tolerate discontinui-
This discussion will cover layer ties such as vias.
stack, differential traces, con-
Figure 1: The device pin-out is tailored for HDTV receiver applications
trolled impedance transmission If an additional supply voltage
lines, discontinuities, routing plane or signal layer is needed,
guidelines, reference planes, vias add a second power / ground
and decoupling capacitors. plane system to the stack to
keep it symmetrical. This makes
Layer stack the stack mechanically stable
The pin-out of a HDMI mux-re- and prevents it from warping.
peater is tailored for the design in Also the power and ground
HDTV receiver circuits (see Figure plane of each power system can
1). Each side of the package pro- be placed closer together, thus
vides a HDMI port, featuring four increasing the high-frequency
differential TMDS signal pairs, bypass capacitance significantly.
Figure 2: Recommended 4- or 6- layer stack for a receiver PCB design
thus resulting in three input and
one output port. The remaining Differential Traces
signals comprise the supply rails, HDMI uses transition minimised
Vcc and ground, and lower speed differential signalling (TMDS) for
signals such as the I2C interface, transmitting high-speed serial
Hotplug-detect and the mux-se- data. Differential signalling offers
lector pins. significant benefits over single- Figure 3: TEM wave radiation from the large fringing fields around a single
A minimum of four layers are ended signalling. conductor and the small fringing fields outside the closely coupled conduc-
required to accomplish a low EMI In single-ended systems, cur- tor loop of a differential signal pair.
PCB design (see Figure 2). Layer rent flows from the source to
stacking should be in the follow- the load through one conductor
ing order (top-to-bottom): TMDS and returns via a ground plane
signal layer, ground plane, power or wire. The transversal electro-
plane and control signal layer. magnetic wave (TEM), created by
• Routing the high-speed the current flow, can freely radi-
Figure 4: Traces of different electrical length cause phase shifts between
TMDS traces on the top layer ate to the outside environment
signal, generating difference signals that cause serious EMI problems.
avoids the use of vias (and causing severe electromagnetic
the introduction of their interference (EMI) (Figure 3). closely coupled, the currents in radiate, thus yielding significant-
inductances) and allows for Also noise from external sources the two conductors are of equal ly lower EMI (see Figure 3).
clean interconnects from induced into the conductor is amplitude but opposite polarity Another benefit of close
the HDMI connectors to the unavoidably amplified by the and their magnetic fields cancel. electric coupling is that external
repeater inputs, and from the receiver, thus compromising The TEM waves of the two con- noise induced into both con-
repeater output to the sub- signal integrity. ductors, now being robbed of ductors equally appears as com-
sequent receiver circuit. Differential signalling instead their magnetic fields, cannot ra- mon-mode noise at the receiver
• Placing a solid ground plane uses two conductors, one for the diate into the environment. Only input. Receivers with differential
next to the high-speed signal forward, the other one for the re- the far smaller fringing fields inputs are sensitive to signal
layer establishes controlled turn current to flow. Thus, when outside the conductor loop can differences only, but immune

EE Times-India | eetindia.com 
to common-mode signals. The frequency. This time difference,
receiver, therefore, rejects com- also known as intra-pair skew, is
mon-mode noise and signal specified by HDMI for a receiver
integrity is maintained. with 0.4 TBIT for a TMDS clock
To make differential signal- rate of 225 MHz, which trans-
Figure 5: Physical geometries of differential traces
ling work on a PCB, the spacing lates to 178 ps maximum. For an
of the two traces of a differential HDMI transmitter the specifica-
signal pair must be kept the tion calls for 0.15 TBIT for a TMDS
same across the entire length of clock rate of 225 MHz, which
the trace. Otherwise, variations in translates to 66 ps maximum.
the spacing cause imbalances in Because pixel generation
the field coupling, thus, reducing requires the synchronous trans-
the cancellation of the magnetic mission of four differential TMDS
fields “ leading to increased EMI. signal pairs, (3 data + 1 clock), it
In addition to larger EMI, must reach the receiver at the
changes in conductor spacing same time. Ideally, all four signal
cause the differential impedance pairs should be of equal electrical
of the signal pair to change, thus length to ensure zero time dif-
creating discontinuities in an ference. HDMI, however, allows
impedance-controlled trans- for a maximum inter-pair skew,
mission system, which leads to the time difference between
signal reflections compromising signal pairs, for a receiver of 0.2
signal integrity. TCHARACTER + 1.78 ns, yielding a to-
Besides consistent spacing, tal of 2.67 ns for a TMDS clock of
both conductors must be of 225 MHz. For an HDMI transmit-
Figure 6: TDR display revealing the locations of discontinuities
equal electrical length to ensure ter, the specification calls for 0.2
their signals reach the receiver TCHARACTER resulting in 888ps.
inputs at the same time. Figure 4
shows the “+” and the “”” signals Controlled Impedance
of a differential pair during logic Transmission Lines
state changes for traces of equal Controlled impedance traces are
and different length. used to match the differential
For traces of equal length impedance of the transmission
both signals are equal and op- medium, e.g., cables, and the
posite. Therefore, their sum must termination resistors. Differential
add to zero. If the traces differ impedance is determined by the
in electrical length, the signal physical geometries of the signal Figure 7: Skew reduction via meandering using chamfered corners
on the shorter trace changes its pair traces, their relation to the
state earlier than the one on the adjacent ground plane and the
longer trace. During that time PCB dielectric. These geometries
both traces drive currents into must be maintained across the
the same direction. Because the entire trace length.
longer trace, which is supposed Figure 5 depicts the param-
to act as return path, continues to eters relevant for impedance
drive current, the current of the calculation for both, Microstrip Figure 8:Routing around an object
“early” driving, shorter trace must traces (outer layer traces), and
find its return path via a reference stripline traces (traces within the 1. For loosely coupled strip- the adjacent “+” and “”” conduc-
plane (power or ground). layer stack, typically sandwiched lines, s > 12 mils, the number tors. X can be a trace of another
When adding both signals by two ground planes). 0.748 might be replaced with signal pair, a ground shield trace
the sum signal diverts from the To calculate the trace geom- 0.374 or a TTL/CMOS trace.
zero level during the transi- etries in Figure 5 for a 100 differ- 2. For W < 2h the maximum er- For adjacent signal pairs and
tion phase. At high frequency ential impedance TMDS signal ror is 3% shield traces, make distance d
these different signals appear as pair, the closed-form equations 3. For best accuracy keep b “ t > 3 s. Running the shield trace
sharp transients of considerable 1 “ 6 can be applied. 2W and b > 4t, where b is the (preferably ground) on one side
magnitude, showing up on the dielectric thickness between potentially creates an imbalance
ground plane, causing serious ground planes that can increase EMI. Ground
EMI problems. trace shields should have a scat-
Note that the width of the With regards to the distance tering of vias to the underlying
“noise” pulses is equal to the between a different signal pair ground plane.
phase shift between the two and its environment, Figure 5 Note: At first glance the
signals, and can be translated shows a trace X that is not as- equations above represent an
into a time difference for a given sociated with the current flow in inexpensive way to attain the

 eetindia.com | EE Times-India
 differential impedance. Some create an echo that is reflected
field solvers can also calculate back to the reflectometer (hence
the current distributions inside the name). Increases in the im-
conductors. The advantage a pedance create an echo that re-
2D field solver wields over an inforces the original pulse while
approximation is the flexibility decreases in the impedance
Figure 9: Lumping discontinuities
to consider almost any arbitrary create an echo that opposes the
cross-section geometry. In addi- original pulse.
tion to the first-order terms such The resulting reflected pulse
as line width, dielectric thickness that is measured at the output/
and dielectric constant, sec- input to the TDR is displayed
ond-order terms such as trace or plotted as a function of time
thickness, solder mask and trace and, because the speed of signal
Figure 10: Avoiding via clearance sections etch back can be considered. propagation is relatively con-
stant for a given transmission
Discontinuities medium, can be read as a func-
Discontinuities are locations in tion of trace length.
the signal path where the differ- The goal in PCB design must
ential trace impedance deviates be to minimise discontinuities
from its specified value (of 100 15 wherever possible, thus elimi-
per cent for HDMI), and assumes nating reflections and maintain-
either higher or lower impedance ing signal integrity. Following a
values. Discontinuities cause sig- minimum set of routing guide-
nal reflections due to impedance lines helps avoiding unneces-
Figure 11: Keeping planes out of the area between edge-fingers mismatch compromising signal sary discontinuities. The remain-
integrity. These are primarily the ing, unavoidable discontinuities
result of changes in the effective should be lumped, that is their
trace width or in the line-to-line areas should be kept small and
spacing caused either by un- placed together as close as pos-
avoidable transitions in the trace sible. The idea is to concentrate
geometries along the signal path, the points of reflection to a
or by poor routing of the signal certain area rather than having
traces. them distributed across the en-
Potential locations for discon- tire signal path.
tinuities are: The magnitude of the dis-
• where the solder pads of the continuities seen using a TDR
HDMI connector meet the are directly effected by the edge
signal traces rate of the pulse used by the
• where signal traces meet vias, TDR. The faster the TDR edge the
component pads of resistors, more discontinuities will show
or IC-pins up, and the larger the imped-
• 90o bends in signal traces ance spike will appear. With the
Figure 12: Field coupling within a microstrip structure • where a signal pair is split to HDMI specification they have
route around an object defined the edge rate that is to
be used to be 200ps. Figure 6
Discontinuities are detected illustrates this point. The lower
during differential impedance, line on the graph was taken us-
TDR, tests. A TDR, (time-domain ing a 30ps edge rate and the up-
reflectometer), is an electronic per line was taken with a 200pf
instrument used to characterise filter. The discontinuities created
Figure 13: Return current paths in solid versus slotted ground planes and locate faults in metallic con- by the SMA launch onto the
ductors. TPA board that show up on the
trace geometries. However, is to use a 2D or better field A TDR transmits a fast rise time low line are completely invisible
these functions are based on solver. This is a software tool pulse along the conductor. If the when the 200ps edge rate filter
empirical data and represent that solves Maxwell’s Equations conductor is of uniform imped- is applied.
good approximations at best. and calculates the electric and ance and properly terminated,
The actual accuracy might vary magnetic fields for an arbitrary the entire transmitted pulse will Routing Guidelines
significantly and various sources cross-section transmission line. be absorbed in the far-end ter- Guidelines for routing PCB traces
even cite possible errors of up to From these, it also calculates the mination and no signal will be are necessary when trying to
10 per cent. electrical performance terms, reflected back to the TDR. But maintain signal integrity and
A more accurate, and in the such as characteristic imped- where impedance discontinui- lower EMI. Although there seems
long term cheaper approach, ance, signal speed, crosstalk and ties exist, each discontinuity will to be an endless number of pre-

EE Times-India | eetindia.com 
 changes the differential trace length between the HDMI
impedance creating a small connector and the device as
discontinuity. A 45o bends short as possible to minimise
is seen as an even smaller attenuation.
discontinuity. 12. Use good HDMI connectors
4. When routing around an whose impedances meet the
object, route both trace of a specifications.
pair in parallel. Splitting the 13. Place bulk capacitors, (i.e., 10
traces changes the line-to- ¼F), close to power sources,
Figure 14: Return current paths for a single and a multiple layer change
line spacing, thus causing such as voltage regulators or
the differential impedance to where the power is supplied
change and discontinuities to the PCB.
to occur. 14. Place smaller 0.1 ¼F or 0.01
5. Place passive components ¼F capacitors at the device.
within the signal path, such
as source-matching resistors Reference Planes
or ac-coupling capacitors, The power and ground planes of
next to each other. Routing a high-speed PCB design usually
as in case a) does create wid- must satisfy a variety of require-
er trace spacing than in b); ments. At DC and low frequen-
however, the resulting dis- cies they must deliver stable ref-
continuity is limited to a far erence voltages, such as Vcc and
narrower electrical length. ground, to the supply terminals
6. When routing traces next to of integrated circuits and termi-
a via or between an array of nation resistors.
vias, make sure that the via At high frequencies refer-
clearance section does not ence planes, and in particular
interrupt the path of the re- ground planes, serve numer-
Figure 15: Return current paths for a single- and a multiple layer change
turn current on the ground ous purposes. For the design of
plane below. controlled impedance transmis-
7. Avoid metal layers and traces sion systems, the ground plane
underneath or between the should provide strong electric
pads of the HDMI connec- coupling with the differential
tors for better impedance traces of an adjacent signal layer.
matching. Otherwise they As mentioned earlier, close cou-
may cause the differential pling causes the magnetic fields
Figure 16: Capacitor losses modelled by a series resonance circuit
impedance to drop below to cancel, thus minimising EMI
75 and fail your board during through reduced TEM wave
TDR testing. radiation of the remaining fring-
8. Use the smallest size possible ing fields. To accomplish close
for signal trace vias and HDMI coupling, place the ground
connector pads as they have plane next to a high-speed sig-
less impact on the 100 dif- nal layer.
ferential impedance. Large Although differential signal-
vias and pads can cause the ling ideally does not require sep-
impedance to drop below arate current return paths, there
85. always will be some form of
9. Use solid power and ground common-mode noise currents
planes for 100 impedance capacitively coupling into the
Figure 17: Capacitor impedance versus frequency
control and minimum power closest reference plane, (which
cautions to be taken, this section correction along the signal noise. ideally is a ground plane).
provides only a few main recom- path. Use chamfered corners 10. For 100 differential imped- Providing a continuous, low-
mendations as layout guidance. with a length-to-trace width ance use the smallest trace impedance return path for these
1. Reduce intra-pair skew in a ratio of 3 to 5. The distance spacing possible, which usu- current requires the reference
differential trace by intro- between bends should be at ally is specified by your PCB planes to be of solid copper
ducing small meandering least 8 to 10 times the trace vendor. Make sure that the sheets, free from voids and crev-
corrections at the point of width. geometries in Figure 5 are: ices.
mismatch. 3. Use 45o bends (chamfered s < h, s < W, W < 2h, and d > Layer stacks with multiple
2. Reduce inter-pair skew, corners), instead of right- 2s. Even better, use a 2D field power systems can benefit from
caused by component place- angle (90o) bends. Right- solver to determine the trace reference planes that are stitched
ment and IC pinouts, by angle bends increase the geometries more accurately. with vias. Here ground planes of
making larger meandering effective trace width, which 11. Keep the trace electrical different layers are connected

 eetindia.com | EE Times-India
through a number of vias placed by heavy capacitive loading. The return current flow begins at (CD). RS depicts the resistance
at regular intervals across the When connecting decoupling the bottom of the power plane, in the leads and the plates of
board. Similar is valid for the capacitors to a ground plane, or where it is closest to the signal the capacitor. The three resis-
stitching of like power planes. interconnecting ground planes, current. It then flows through the tive losses are combined into
For stitched reference planes, the via inductance becomes power via, across the decoupling one equivalent series resistance
it is important that the via clear- more important than its capaci- capacitor into the ground via, (ESR). As in the ESR case, the
ance section (or anti pads in the tance. The magnitude of this and returns on top of the ground equivalent series inductance
case of ground vias) does not inductance is approximately: plane. (ESL) combines the inductance
interfere with the path of the Current return paths com- of the capacitor plates and the
return current. In the case of an prising multiple vias and decou- internal leads.
obstacle the return current will pling capacitors possess high Note that the capacitor con-
find its way around it. However, inductance, thus compromising necting vias, although low in
by doing so, the current’s elec- signal integrity and increasing impedance, contribute a sig-
tromagnetic fields will most likely EMI. If possible, avoid changing nificant amount to the series
interfere with the fields of other Because this equation involves layers during high-speed trace inductance. Therefore, reduce
signal traces introducing cross- a logarithm, changing the via di- routing, as it usually worsens via inductance by using two
talk. Moreover, this obstacle will ameter does little to influence the board performance, compli- vias per capacitor terminal.
adversely affect the impedance inductance. A big change may cates design and increases Figure 17 shows the progres-
of the traces passing over it. be effected by changing the via manufacturing cost. sion of capacitor impedance (Z)
length or by using multiple vias versus frequency for a 10 nF ca-
Vias in parallel. Therefore, connect de- Decoupling Capacitors pacitor. At frequencies far below
The term via commonly refers to coupling capacitors to ground by Decoupling capacitors provide the self resonance frequency
a plated hole in a printed circuit using two paralleled vias per de- a local source of charge for ICs (SRF), the capacitive reactance is
board. While some applications vice terminal. For low inductance requiring a significant amount dominant. Closer to SRF the in-
require through-hole vias to be connections between ground of supply current in response to ductive reactance gains influence
wide enough to accommodate planes, use multiple vias in regu- internal switching. Insufficient trying to neutralise the capacitive
the leads of through-hole compo- lar intervals across the board. decoupling causes a lack of sup- component. At SRF the capaci-
nents, high-speed board designs Although it is highly recom- ply current required, which may tive and inductive reactance can-
mainly use them as trace routing mended not to change layers of prevent the IC from working cel and only the ESR is effective.
vias when changing signal layers, high-speed traces, if the neces- properly resulting in signal in- Note that the ESR is frequency
or as connecting vias to connect sity still occurs ensures a continu- tegrity data errors to occur. This dependent, and in contrast to
SMT components to the required ous return current path. Figure 14 requires them to provide low popular believe, does not reach
reference plane and also to con- on the left shows the flow of the impedance across the frequency its minimum at SRF. The imped-
nect reference planes of the same return current for a single layer range of interest. To accomplish ance Z however does.
potential to each other (recall the change and on the right for a that, a common approach is to The reason why the parallel-
via stitched ground plane of the multiple layer change. distribute an array of decoupling ing of capacitors in a distributed
previous section). The ability for the current flow capacitors evenly across the decoupling network works is
Layers connecting to a via to change from the bottom to board. In addition to maintain- because the total capacitance
do so by making direct contact the top of the ground plane is ing signal integrity, decoupling increases to , where n is the
with a pad surrounding the via provided by a metallic laminate capacitors serve as EMC filters number of decoupling capaci-
(the via pad). Layers that must of the inner clearance ring. Thus, preventing high-frequency tors used. And with , the capaci-
not connect are separated from when a signal passes through RF signals from propagating tor impedance is reduced to for
the via by a clearance ring. Every a via and continues on the op- throughout the PCB. frequencies below SRF. Similar
via has capacitance to ground, posite side of the same plane, a When connecting a ca- holds true for the inductance.
which can be approximated us- return current discontinuity does pacitor between the power Here and because the imped-
ing the following equation: not exist. and ground planes we are actu- ance decreases to for frequen-
Changing a signal trace from ally loading the power supply cies above SRF.
one layer to another by crossing with a series resonant circuit, Designing a solid decoupling
multiple reference planes com- whose frequency dependent network must include lower
plicates the design of the return R-L-C components represent frequencies down to DC, which
current path. In the case of two the equivalent circuit of a real requires the implementation of
ground planes, a ground-to- capacitor. Figure 16 shows the large capacitors. Therefore, to
ground via must be placed near parasitic components of an ini- provide sufficient low imped-
the signal via to ensure a continu- tial equivalent circuit and their ance at low frequencies, place
ous return current path, (right conversion into a series reso- 1 ¼F to 10 ¼F tantalums at the
diagram in Figure 14). If the refer- nant circuit. output of voltage regulators and
ence planes are of different volt- The leakage resistance RL at the point where power is sup-
Because the capacitance in- age potentials, such as the power represents the loss through leak- plied to the PCB. For the higher
creases proportional with size, and ground planes in Figure 15, age current at low frequencies. frequency range place several
trace vias in high-speed designs the design of the return path be- RD and CD indicate the losses 0.1 ¼F or 0.01 ¼F ceramics next
should be as small as possible to comes messy as it requires a third due to molecular polarisation, to every high speed switching IC.
avoid signal degradation caused via and a decoupling capacitor. (RD), and dielectric absorption,

EE Times-India | eetindia.com 
Summary PCB design. Despite the enormous tent is to provide PCB designers with presented will help accomplishing
Without claiming to be complete, amount of technical literature, semi- design guidelines in a very compre- an EMC-compliant board design in
the objective of this paper is to cover nars, newsletters and internet forums hensive way. the shortest time possible.
the main aspects of high-speed on the subject, this document’s in- Followingtherecommendations

 eetindia.com | EE Times-India