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org (E-ISSN 2348-1269, P- ISSN 2349-5138)

Implementation and Optimization of Low Power

CMOS 6T SRAM cell using Leakage Reduction
Technique
Sajal Agrawal Ashish Dubey
Department- electronics and communication Assistant professor
Shri Ram group of college Branch - vlsi
Bamore (MP) Shriram College of Engineering & Management
Bamor (MP)
Abstract- 6T SRAM cell using Double Gate FINFET & are sensed by the sensor circuits, and then discharged to
Power Gating (PG) are applied on the optimized 6T SRAM complete the reading procedure. [4-5].
cache memory Cell and it is establish to be most efficient in SRAM is a kind of RAM. It's a kind of semiconductor
terms of voltage drop & power loss & develop speed of memory which stores information in the form of electronic
circuit. In this paper voltage drop & power loss of switches. SRAM is quicker and uses less power than DRAM
conventional 6T cell at90nm technology has been estimated since it does not need to be refreshed to maintain data. [6].
and circuit techniques to decrease Leakage in deep Since SRAM can be read and written quickly, it is often
submicron technology, Double Gate FINFET & Power employed for caching data in computers. It is also
Gating has converse & functional on conventional 6T implemented in microcontrollers and networking hardware.
SRAM cell. We looked at the power use, average write [7-9] Every SRAM chip's memory cell retains a binary digit
delay, and write power product delay of low power SRAM as long as power is supplied to the device. A bit stored in a
cell layouts. Energy consumption in the SRAM cell has flip-flop will remain in that state until the opposite state is
been minimised by using DG FINFET methods. According maintained. SRAM, despite its little size, boasts lightning-
to the findings, the DG FINFET-based SRAM cell is the fast data access. On-chip memory options include SRAM as
most efficient. We examine utilization of DGF system gives well. [10][17]. Both SRAM and DRAM have their uses. But
low leakage & high presentation function by using SRAM often outperforms DRAM, and its access times may
maximum speed & low thresh hold voltage transistors for be as low as ten nanoseconds. SRAM also doesn't need to be
logic cell. refreshed as often as dynamic random-access memory
(DRAM). SRAM operates on a low, continuous current and
consumes less power than DRAM. [11][21]. SRAM has the
Key Words: Cadence, Low Power, CMOS, Average write
drawbacks of being more expensive and taking up more
delay, 6T SRAM cell, write power product delay.
space on the chip in general. Each chip has less storage
space, and manufacturing them is more labour intensive.
I. INTRODUCTION
Since SRAM's power consumption is proportional to the
The SRAM cell is a common component of many frequency with which it is accessed, it consumes almost little
modern electronic devices. It outperforms conventional power while it is not being actively used. SRAM still
memory cells in speed and energy efficiency. [1-2]. It doesn't consumes the same amount of power as DRAM at greater
need to be refreshed on a regular basis. This is why SRAM speeds. [12][19]. DRAM, or dynamic random-access
has become the go-to memory cell for VLSI architects. As a memory, is a storage technology that operates on
result, SRAM cells are always evolving to improve their semiconductors. DRAM is often used to store the code
functionality. Because of this, a wide variety of SRAM cell required by the CPU to run the operating system of a
types, such as the 6T SRAM, 7T SRAM, 8T SRAM, 9T computer. DRAM, however, is not limited to only desktop
SRAM, etc., may be found in published works. In digital PCs and servers. RAM allows the central processing unit of a
systems, the 6T SRAM is the standard. This cell has a computer to bypass the need to go through memory
capacity of 1 bit. As long as the battery is charged, the bit sequentially and access data immediately. Data stored in
will stay put in the cell. This study evaluates a 6T SRAM RAM may be accessed much more quickly than data stored
cell's architecture and operation. In order to analyse on a hard drive. RAM is often quicker since it is closer to the
performance in 180nm CMOS technology, Cadence Virtuoso heart of the machine. [13][22].
is employed. A 6T SRAM typically consists of 2 inverters
connected in series. The basic components of a 6T SRAM
memory cell are shown in Figure 1. [3]. These 2 inverters are
where the necessary information is locked for safekeeping.
Data storage is referred to as a "Write operation," whereas
data retrieval is called a "Read operation." The contents of an
SRAM cell are uploaded using the Write operation, and
retrieved by the Read operation. The BL & BLB data lines
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II. IMPLEMENTATION MEMORY SRAM CELL & ITS
OPERATION
 MEMORY CELL DESIGN
In diagram1, we can see the components of a common 6T
SRAM cell, which include 2 CCI & 2 AT. For as long as the
power is on, the inverters act as the cell's "memory,"
ensuring the integrity of each data bit.
Transistors PM1 and PM2 are PMOS devices, whereas
NM1, NM2, NM3, and NM4 are NMOS. Cell NM3 & NM4
are connected to Bit Lines through an AT connection. Below,
we'll go through the many states that an SRAM cell may be
in.

Figure.2 Write Waveform of 6T SRAM Cell

 Read Operation
A high enough cell beta ratio (CBR) ensures a consistent
and reliable read operation. However, a high beta ratio has
the downside of poor efficiency. The CBR may be measured
as the percentage of the pull-down transistor's driving current
to the power-driving transistor's current. Precharging BL (BL
& BLB) to VDD, logic 1, is standard practise before reading
the cell's displayed data bit. This is demonstrated in
diagram.3. logic '1' activates the WL, or Word Line. The
amount of discharge that occurs along a BL through an
access transistor & pull down transistor is proportional to the
value of the data bit stored in the cell, leading to a differential
voltage (DV) drop along the BLs and BLBs. In a memory
Figure.1 A 6T SRAM Cell Schematic cell, the value of a single bit is determined by the Sense
Amplifier's reading of the differential voltage between BL
 Standby/Hold Mode and BLB. Large capacitive charges may be charged and
The cell's link to Bit Lines BL & BLB is severed by discharged by SA. For rapid RO sensitivity of SA is
access transistors NM3 & NM4 when the Word Line is in the maximum. Thus, DV may not be too huge as it could flip
logical 0 state. If the power is on, the cell's two CCN will situation of CCI. Read waveform of 6T SRAM Cell is
keep reinforcing the data bit being shown. presented in Fig.4.

 Write Operation
A high enough cell gamma ratio (CGR) is required for a
write operation to succeed. Calculating CGR is as simple as
comparing the driving current of the PT (AT) to the current
drawn by the pull up transistor. The BL functionality is
dependent on the pace of writing into the cell. To lessen the
charging burden on each access transistor, complementary
Bit Lines are employed on opposite sides of the cell. Since
there isn't a single huge access transistor needed, we may
instead employ several smaller ones. The cell is made
accessible to the outside world when the WL is set to logic 1,
activating access transistors N3 & N4. Then, AT is used to
send the BL data (BL and BLB) to the receiving cell.
Following a winning WO, the logical zero is grouped to the
WL. The primary BL group is logic "0," which is used to
write into a cell, and the primary BLB group is logic "1,"
Figure.3 Schematic of 6T SRAM Cell with SA Circuit
which is used to write into a cell. The AT may therefore
bypass the logic rate through the BL and BLB in the cell, as
the WL has been grouped to logic 1. When the data bit is
successfully written into the cell, the connection between the
cell and the outside world is severed by setting the WL to
logic 0. See figure for illustration of waveform.2.

Figure.4 Read Waveform of 6T SRAM Cell

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 Noise-Response (NR) of 6T SRAM
The inverter latch is fed two different DC voltages to
generate noise [16]. It determines the maximum noise
voltage an inverter latch may endure before inverting the
output or cell data. The NR of 6T SRAM cell has been
presented in Fig.5.

Figure.7 Transient Response of 6T SRAM Cell using DG

FINFET Technique

 Noise-Response (NR) of 6T SRAM using DG FINFET

.
The inverter latch is modified by introducing two
Figure.5 SRAM Cell with an NR of 6T independently variable DC voltages, which combine to create
noise. Each inverter's input must be supplied with DC
III. 6T SRAM CELL USING DG FINFET TECHNIQUE voltages, and the polarity of these voltages must be
(DGFT) monitored using the DG FINFET approach. The NR of 6T
SRAM cell utilizing DGFT has been presented in Fig.8.
The acronym FINFET refers to a transistor with a fin-
shaped channel. The high computational density of Silicon
Architecture is made possible by the use of FINFETs, which
are Non Planar Dual Gate Transistors. FINFETs get their
name from the thin silicon "fin" that covers the conduct
channel. The fin's depth ensures that the equipment's channel
length is optimal.
The 6T SRAM cell supports DGFT functionality. The
front and rear gates of a DGF may be controlled
autonomously (SD) to expand performance and cut down on
energy consumption. Mutually parallel transistors may be
connected using SD gate control on non-critical channels.
Two transistors with its source and drain terminals connected
form a PT pair. In DGF, the second gate is the polar opposite
of the first gate, which is often used to better regulate LC and Figure.8 The DGF-based NR of a 6T SRAM cell
short channel effect (SCE). LP and OP modes, in which the
back gate is connected to reverse-bias voltage to decrease IV. POWER GATING TECHNIQUE
leakage power, are possible FINFET operating modes, as are
hybrid modes, which leverage agreement of LP and SD gate Caching using Power Gating allows unused portions of
modes. Key issues are caused by CMOS's fundamental the cache to effectively "switch off" the supply voltage,
substance, which prevents it from scaling down in bulk preventing energy loss due to leakage. The idea behind this is
(SOB) without interruption. SCE, optimal current, gate- to turn on an additional transistor in the cache's SRAM cells
dielectric leakage, and equipment to equipment variation are through the highest VT in the VDD or ground path, while the
the primary obstacles to SOB CMOS nano-meter gate VT of the other transistors in the cell is rather low.
lengths. A functional diagram of a DG FINFET on a 6T
SRAM cell is shown. After applying DGFT to a 6T SRAM
Cell, the resulting waveform is seen in diagram (7).

Figure 9: SRAM cell with an NMOS Power Gating

The supplementary transistor is activated during

operation and deactivated during non-operation. There is a
"gate" in the cell's voltage supply. Power Gating sustain
Figure.6 A DGFT-based schematic of a 6T SRAM cell presentation benefits of lower supply & Vt when dropping
leakage & leakage energy dissipation.

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The layout of the Power Gating 6T SRAM Cell is seen in VI. CONCLUSION
Fig. 10. Its system have two Back to Back CMOS inverters, The effects of external noise and power supply variations
2 access transistor, linking access transistor to BL & BLB & on the 6T SRAM cell were manipulated to conduct a
NMOS transistor in ground direction of 2 Back to Back comparative analysis of its Low power, Average power,
CMOS inverters. Average write Delay, and write power product Delay. The
Noise Response was found to be reduced even more in both
cases when 0.7V was used as the power source. We evaluate
and contrast the energy use, typical write latency, and write
power product delay of several low-power SRAM cell
designs. The SRAM cell's energy consumption was cut down
to the bare minimum with the use of DG FINFET methods.
According to the findings, a DG FINFET-based SRAM cell
performs well. Similar results were seen when comparing the
average write delay & write power product Delay of a 6T
SRAM cell with and without the DG FINFET in power
supply 0.7V to those of a cell only subject to externally
produced noise. Conventional 6T SRAM cells have had
leakage power and leakage current reduced by using circuit
approaches to decrease leakage in deep sub-micron, like
transistor sizing and power gating, and have been compared
Figure 10: Schematic of Power Gating 6T with Optimized 6T SRAM cache memory cells, whose
SRAM Cell circuit speed has been increased. Optimised Power Gating
has been determined to be the most effective method for
reducing leakage, beating all the other methods listed here.
The most significant reduction in power loss & voltage drop
has been found to be attained in traditional 6T SRAM cells
by using a circuit method to decrease leakage in deep sub-
micron. The Power Gating SRAM Cell Optimal Cache
Memory Circuit Via Permitting for Different Parameters
leakage reduction method exhibits significant decrease.
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