Binary Logic

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 Readings and Exercises
• P & H: Section 2.6
• ARMv8 Instruction Set Overview:
▪ Section 5.4, subsections 2, 5, 7, 8
▪ Section 5.5, subsections 3, 4

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 Objectives
At the end of this section, you will be able to
1. Work with binary logic instructions in ARMv8
2. Use shifting instructions in ARMv8
3. Use sign extension and bitfield operations in
ARMv8

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 Bitwise Logical Instructions
• Manipulate one or more bits in a register
• AND
▪ Truth table:
a b a AND b
0 0 0
0 1 0
1 0 0
1 1 1

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Bitwise Logical Instructions (cont’d)
▪ Form (64-bit): and Xd, Xn, Xm
• Eg: mov x19, 0xAA // 1010 1010
mov x20, 0xF0 // 1111 0000
and x21, x19, x20 // 1010 0000
• Note that 0xF0 forms a bitmask
▪ It “masks out” all bits except bits 4-7
▪ 32-bit and immediate forms also exist
• Eg: mov w19, 0x55 // 0101 0101
and w19, w19, 0xF // 0000 1111
// 0000 0101

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Bitwise Logical Instructions (cont’d)
▪ ands sets or clears N and Z flags according to the
result (V and C always cleared)
• Eg: test if bit 3 is set in x20
. . .
ands x19, x20, 0x8
b.eq bitclear
bitset: . . .
bitclear: . . .

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Bitwise Logical Instructions (cont’d)
▪ tst is an alias for ands
• Form (64-bit): tst Xn, Xm
• Alias for: ands xzr, Xn, Xm
• Eg:
. . .
tst x20, 0x8
b.eq bitclear
bitset: . . .
bitclear: . . .

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Bitwise Logical Instructions (cont’d)
• Inclusive OR
▪ Truth table:
a b a OR b
0 0 0
0 1 1
1 0 1
1 1 1

▪ Form (64-bit): orr Xd, Xn, Xm

• 32-bit and immediate forms also exist

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Bitwise Logical Instructions (cont’d)
▪ Eg: set bits 4 and 5 in x19
mov x19, 0xAA // 1010 1010
mov x20, 0x30 // 0011 0000
orr x19, x19, x20 // 1011 1010

▪ mov is an alias of orr

• Form: mov Xd, Xm
• Alias for: orr Xd, xzr, Xm

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Bitwise Logical Instructions (cont’d)
• Exclusive OR
▪ Truth table:
a b a EOR b
0 0 0
0 1 1
1 0 1
1 1 0

▪ Form (64-bit): eor Xd, Xn, Xm

• 32-bit and immediate forms also exist

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Bitwise Logical Instructions (cont’d)
▪ Eg: toggle bits 0-3 in w20
mov w20, 0x55 // 0101 0101
eor w20, w20, 0x0F // 0000 1111
// 0101 1010

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Bitwise Logical Instructions (cont’d)
• Bit Clear
▪ Is actually AND NOT
▪ Truth table:
a b a AND NOT b
0 0 0
0 1 0
1 0 1
1 1 0

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Bitwise Logical Instructions (cont’d)
▪ Form (64-bit): bic Xd, Xn, Xm
• 32-bit form also exists (but no immediate)
▪ Eg: clear bits 2-5
mov x20, 0xFF // 1111 1111
mov x21, 0x3C // 0011 1100
bic x19, x20, x21 // 1100 0011

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Bitwise Logical Instructions (cont’d)
• OR NOT
▪ Truth table:
a b a OR NOT b
0 0 1
0 1 0
1 0 1
1 1 1

▪ Form (64-bit): orn Xd, Xn, Xm

• 32-bit form also exists (but no immediate)

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Bitwise Logical Instructions (cont’d)
• NOT
▪ Truth table:
a NOT a
0 1
1 0

▪ Implemented using mvn (move NOT)

▪ Form (64-bit): mvn Xd, Xm
• Alias for: orn Xd, xzr, Xm
• 32-bit form also exists (but no immediate)

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Bitwise Logical Instructions (cont’d)
• EOR NOT
▪ Truth table:
a b a EOR NOT b
0 0 1
0 1 0
1 0 0
1 1 1

▪ Form (64-bit): eon Xd, Xn, Xm

• 32-bit form also exists (but no immediate)

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 Bitwise Shift Instructions
• Logical Shift Left
▪ Form (64-bit): lsl Xd, Xn, Xm
• Xn: bit pattern to be shifted
• Xm: shift count
▪ 0 is shifted into rightmost bit
▪ Shifted out bits are lost

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Bitwise Shift Instructions (cont’d)
▪ LSL is a quick way to do multiplication by a power of
two
• i.e. by 2n, where n is the shift count
• Eg: 5 x 8
mov x20, 5 // 0000 0101
mov x21, 3 // 23 = 8
lsl x19, x20, x21 // 0010 1000

▪ 32-bit and immediate forms exist

• Eg:
mov w20, 5 // 0000 0101
lsl w19, w20, 3 // 0010 1000

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 Bitwise Shift Instructions (cont’d)
• Logical Shift Right
▪ Form (64-bit): lsr Xd, Xn, Xm
• Xn: bit pattern to be shifted
• Xm: shift count
▪ 0 is shifted into leftmost bit
▪ Shifted out bits are lost

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Bitwise Shift Instructions (cont’d)
▪ LSR is a way to do division by a power of two
• Any remainder is lost
• Eg: 15 / 4 = 3
mov x20, 15 // 0000 1111
mov x21, 2 // 22 = 4
lsr x19, x20, x21 // 0000 0011

• Does not work for negative signed integers

▪ Use ASR to preserve the sign bit
▪ 32-bit and immediate forms exist
• 0 is inserted at bit 31 when using W operands

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 Bitwise Shift Instructions (cont’d)
• Arithmetic Shift Right
▪ Form (64-bit): asr Xd, Xn, Xm
• Xn: bit pattern to be shifted
• Xm: shift count
▪ Sign bit is duplicated when shifting
• Called sign extension

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Bitwise Shift Instructions (cont’d)
▪ ASR preserves the sign when dividing by a power of
two
• Eg: -8 / 2 = -4
mov x20, -8 // 1111 … 1111 1000
mov x21, 1 // 21 = 2
asr x19, x20, x21 // 1111 … 1111 1100

▪ 32-bit and immediate forms exist

• Bit 31 is the sign bit when using W operands

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 Bitwise Shift Instructions (cont’d)
• Rotate Right
▪ Form (64-bit): ror Xd, Xn, Xm
• Xn: bit pattern to be rotated
• Xm: shift count
▪ Bits shifted out on the right are inserted on the left

▪ 32-bit form uses bits 0-31 only

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 Sign/Zero Extend Operations
• Signed Extend Byte
▪ Form (32-bit): sxtb Wd, Wn
▪ Sign-extends bit 7 in Wn to bits 8-31
▪ Eg: sign bit

mov w20, 0xFF // 0000 … 0000 1111 1111

sxtb w19, w20 // 1111 … 1111 1111 1111

▪ Eg: sign bit

mov w20, 0x7F // 0000 … 0000 0111 1111

sxtb w19, w20 // 0000 … 0000 0111 1111

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Sign/Zero Extend Operations (cont’d)
• Signed Extend Halfword
▪ Form (32-bit): sxth Wd, Wn
▪ Sign-extends bit 15 in Wn to bits 16-31
• 64-bit forms exist for sxtb and sxth
▪ Eg: sxth x19, w20
• Signed Extend Word
▪ Form (64-bit only): sxtw Xd, Wn
▪ Sign-extends bit 31 to bits 32-63
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Sign/Zero Extend Operations (cont’d)
• Unsigned Extend Byte
▪ Form (32-bit only): uxtb Wd, Wn
▪ Zero-extends bits 8-31
▪ Eg:
mov w20, 0xFF // 0000 … 0000 1111 1111
uxtb w19, w20 // 0000 … 0000 1111 1111

• Unsigned Extend Halfword

▪ Form (32-bit only): uxth Wd, Wn
▪ Zero-extends bits 16-31
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 Bitfield Operations
• Bitfield Insert
▪ Form (32-bit): bfi Wd, Wn, #lsb, #width
• Wn: source bit pattern
• #lsb: insertion position
• #width: number of bits in the bitfield
▪ Source bitfield occupies bits 0 to (width-1) in Wn
▪ Bits lsb to (lsb + width – 1) in Wd are replaced by the
source bitfield
• All other bits in Wd are unchanged

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 Bitfield Operations (cont’d)
▪ Eg:
mov w20, 0xAA // 0000 … 0000 1010 1010
mov w19, 0xFFFFFFFF // 1111 … 1111 1111 1111
bfi w19, w20, 4, 5 // 1111 … 1110 1010 1111

▪ Unsigned Bitfield Insert in Zero (ubfiz)

• Similar to bfi, except that Wd is zeroed first
▪ Signed Bitfield Insert in Zero (sbfiz)
• Similar to ubfiz, except that bits on left are sign extended

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 Bitfield Operations (cont’d)
• Bitfield Extract and Insert Low
▪ Form (32-bit): bfxil Wd, Wn, #lsb, #width
• Wn: source bit pattern
• #lsb: extraction position
• #width: number of bits in the bitfield
▪ Source bitfield is bits lsb to (lsb + width – 1) in Wn
▪ Bits 0 to (width - 1) in Wd are replaced by the source
bitfield
• All other bits in Wd are unchanged

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 Bitfield Operations (cont’d)
▪ Eg:
mov w20, 0xAA // 0000 … 0000 1010 1010
mov w19, 0xFFFFFFFF // 1111 … 1111 1111 1111
bfxil w19, w20, 6, 3 // 1111 … 1111 1111 1010

▪ Unsigned Bitfield Extract (ubfx)

• Similar to bfxil, except that bits on left are zero extended
▪ Signed Bitfield Extract (sbfx)
• Similar to bfxil, except that bits on left are sign extended

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