Unit 2

Central Processing Unit

General Register Organization, Stack
organization, Addressing modes,
Instruction Classification,
Program control.
 Introduction to CPU
• What is CPU?
• The part of the computer that performs bulk of data processing
operations is called CPU
• The major components of CPU are :
1. ALU
• Made up of circuits
• Does all the A & L operations
• Performs the required microoperations for executing the instructions
• Has no internal storage
2. CU
• Direction & coordination of operations
• Generation of timing & control signals
• Supervises the transfer of information among the registers and instructs
the ALU as to which operation to perform
3. Registers
• They are the high speed temporary data storage area within the
processor to support execution activities
• Stores intermediate data used during the execution of the
instructions
• Both instructions and data can be stored
• Number of registers varies depends on the processor
 General Register Organization
• In programming, memory locations are needed for storing pointers,
temporary result and so on..
• Memory access is the most time consuming process in a computer
• Then it is more convenient & more efficient to store these
intermediate values in processor registers , which are connected
through the common bus system
 23
X24
92 CARRY 1, 2X4=8, 8+1=9
46 NEXT LINE SKIPPING 1 POSITION
552 PERFORM ADDITION
• EX: R1<-R2-R3
• R2 for A input of ALU, R3 for B input of ALU, R1 for destination
register and ALU operation to subtract A-B
• Field : SELA SELB SELD OPR
• Symbol : R2 R3 R1 SUB
• Control word : 010 011 001 00101
 Stack Organization
• A stack is a storage segment that follows LIFO principle
• A stack in a digital computer is a memory unit with an address register
names SP that counts only after an initial value is loaded into the stack
• SP value always points to the top item in the stack
• The two operations in stack are Insertion (PUSH) & Deletion (POP) of data
• These operations are done by incrementing or decrementing the SP
• A stack can be organized as a finite number of memory words or registers,
i.e, stack is of two types ;
1. Register Stack &
2. Memory Stack
1. Register stack
• In a 64 bit stack, SP contains 6 bits because, 2^6=64
• There are two other 1 bit registers in the stack named FULL & EMTY
• FULL is set to 1 when STACK is full
• Likewise EMTY is set to 1 , if STACK is empty
• DR holds the binary data to be written into or read out of the stack
 Operations on register stack
1. PUSH operation
SP <- SP + 1 // increment stack
M[SP] <- DR // write into stack
IF [SP = 0] then (FULL = 1) // check if stack is FULL
EMTY <- 0 // mark the stack not empty
2. POP operation
DR <- M[ SP ] // read item from the stack
SP <- SP – 1 // decrement SP
IF (SP = 0) then (EMTY = 1) // check if stack is empty
FULL <- 0// mark the stack not full
2. Memory stack
• A stack can be implemented in a random access memory (RAM)
attached to a CPU.
• The implementation of a stack in the CPU is done by assigning a
portion of memory to a stack operation and using a processor register
as a stack pointer.
• The starting memory location of the stack is specified by the
processor register as stack pointer.
• Here the stack limits can be checked by using 2 processor registers
• One to hold the upper limit (3000 in this example) another to hold
the lower limit (4001 here)
• SP is compared with the upper limit after each PUSH operation
• Likewise compared with the lower limit after each POP operation
• If the stack is full with elements , that condition is called STACK
OVERFLOW
• If the stack has no elements , that condition is called STACK
UNDERFLOW
1. PUSH operation
SP <- SP – 1
M[ SP ] <- DR
2. POP operation
M[ SP ] <- DR
SP <- SP + 1
Applications of stack
• 3 types of expressions
Infix a+b
Prefix +ab
Postfix (reverse polish notation) ab+
Applications
1. Converting infix to postfix
(a+b)*(c+d)=ab+cd+*
2. Evaluate postfix expression
ab+cd-*
 Instruction Formats
• Computer perform task on the basis of instruction provided. An instruction
in computer comprises of groups called fields.
• These field contains different information as for computers every thing is in
0 and 1 so each field has different significance on the basis of which a CPU
decide what to perform.
• The most common fields are:
1. Operation field which specifies the operation to be performed like
addition.
2. Address field which contain the location of operand, i.e., register or
memory location.
3. Mode field which specifies how operand is to be founded.
Address fields
• The no.of address fields depends on internal organization of registers
• Mainly there are three types of organizations
1. Single accumulator organization-CLA,CMA,ADD X (IMPLICIT)
2. General register organization-ADD R1,R2,R3 (R1 act as both source
and destination)
3. Stack organization –PUSH AND POP
• On the basis of number of address, instruction formats are of 4 types:
1. Zero Address Instructions
2. One Address Instructions
3. Two Address Instructions
4. Three Address Instructions
5. RISC Instructions
• To illustrate the influence of the number of addresses on computer
programs, we will evaluate the arithmetic statement
X = (A + B) ∗ (C + D)
• Using zero, one, two, three or RISC address instruction.
• We will use the symbols ADD, SUB, MUL, and DIV for the four
arithmetic operations;
• MOV for the transfer-type operation; and LOAD and STORE for
transfers to and from memory and AC register.
• We will assume that the operands are in memory addresses A, B, C,
and D, and the result must be stored in memory at address X.
1. THREE-ADDRESS INSTRUCTIONS
Computers with three-address instruction formats can use each
address field to specify either a processor register or a memory
operand.
The program in assembly language that evaluates X = (A + B) ∗ (C + D) is
shown below, together with comments that explain the register
transfer operation of each instruction
• ADD R1, A, B // R1 ← M [A] + M [B]
• ADD R2, C, D //R2 ← M [C] + M [D]
• MUL X, R1, R2 //M [X] ← R1 ∗ R2

• Advanatage :- Results in short program when evaluating arithmetic

expression
• Disadvantage:- Binary coded instruction requires too many bits to
specify 3 addresses
• Commercial computer Cyber 170 uses this type of format
2. TWO-ADDRESS INSTRUCTIONS
Two address instructions are the most common in commercial
computers. Here again each address field can specify either a processor
register or a memory word.
The program to evaluate X = (A + B) ∗ (C + D) is as follows:
• MOV R1, A //R1 ← M [A]
• ADD R1, B //R1 ← R1 + M [B]
• MOV R2, C //R2 ← M [C]
• ADD R2, D //R2 ← R2 + M [D]
• MUL R1, R2 //R1 ← R1∗R2
• MOV X, R1 //M [X] ← R1
3. ONE-ADDRESS INSTRUCTIONS
One-address instructions use an implied accumulator (AC) register for
all data manipulation.
For multiplication and division there is a need for a second register.
However, here we will neglect the second and assume that the AC
contains the result of all operations.
The program to evaluate X = (A + B) ∗ (C + D) is
• LOAD A AC ← M [A]
• ADD B AC ← AC+ M [B]
• STORE T M [T] ← AC
• LOAD C AC ← M [C]
• ADD D AC ← AC + M [D]
• MUL T AC ← AC ∗ M [T]
• STORE X M [X] ← AC
4. ZERO-ADDRESS INSTRUCTIONS
A stack-organized computer does not use an address field for the
instructions ADD and MUL.
The PUSH and POP instructions, however, need an address field to
specify the operand that communicates with the stack.
The following program shows how X = (A + B) ∗ (C + D) will be written
for a stack organized computer.
• PUSH A TOS ← A
• PUSH B TOS ← B
• ADD TOS ← (A + B)
• PUSH C TOS ← C
• PUSH D TOS ← D
• ADD TOS ← (C + D)
• MUL TOS ← (C + D) ∗ (A + B)
• POP X M [X] ← TOS
RISC Instruction
• Reduced instruction set computer
• Use only load and store instruction when communicating between memory
and CPU
LOAD R1,A R1<-M[A]
LOAD R2,B R2<-M[B]
LOAD R3,C R3<-M[C]
LOAD R4,D R4<-M[D]
ADD R1,R2 R1<-R1+R2
ADD R3,R4 R3<-R3+R4
MUL R1,R2 R1<-R1*R3
STORE X,R1 M[X]<-R1
 Addressing modes
• The operation field of an instruction specifies the operation to be
performed.
• This operation must be executed on some data stored in computer
registers or memory words.
• The way the operands are chosen during program execution is
dependent on the addressing mode of the instruction.
• The addressing mode specifies a rule for interpreting or modifying the
address field of the instruction before the operand is actually
referenced.
1. Implied Mode
• In this mode the operands are specified implicitly in the definition of
the instruction.
• For example, the instruction “complement accumulator” is an
implied- mode instruction
• Zero address instructions in stack organized computers are implied
mode
2. Immediate mode
• Operand is specified in the instruction
• It contains an operand field rather than address field
• The operand field contains the actual operand to be used in the
operation specified in the instruction
• They are useful for initializing registers to a constant value
3. Register mode
• In this mode the operands are in registers that reside within the CPU
• The particular register is selected from a register field in the
instruction
4. Register indirect mode
• Instruction specifies register in CPU whose contents give the address
of the operand in the memory
• The selected register contains the address of the operand rather than
the operand itself
• Advantage is that address field of instruction uses fewer bits to select
a register
5. Auto increment/decrement mode
• Similar to register indirect mode except that the register is
incremented or decremented after its value is used to access the
memory
• When the address stored in the register refers to a table of data in
memory, it is necessary to increment or decrement the register after
every access to the table
• This can be achieved by using the increment or decrement instruction
6. Direct address mode
• Effective address is equal to address part of the instruction
• Operand resides in memory and its address given directly by address
field
• In branch type instruction, address field specifies actual branch
address
7. Indirect addressing mode
In this mode, the address field of the instruction gives the address
where the effective address is stored in the memory
Control fetches the instruction from memory and uses its address part
to access memory again to read the effective address
8. Relative addressing mode
• Content of PC is added to the address part of the instruction to obtain
the effective address
• Often used by branch type instructions
• To clarify with an example, assume that PC contains the number 825
and address part of the instruction contains the number 24
• The location at 825 is read from memory during the fetch phase and
the program counter is then incremented by 1 to 826
• The effective address computation for the relative address mode is
826+ 24=850
9. Indexed addressing mode
• Content of the index register is added to Address part of the
instruction to obtain the effective address
• Index register is a special CPU register that contains index values and
usually used with arrays
• Address field of the instruction defines beginning address of a data
array in the memory
• The distance between beginning address and address of operand is in
the index value stored in the index register
10. Base register addressing mode
• In this mode, content of base register is added to the address part of
the instruction to obtain the effective address
• Base register holds a base address and the address field of the
instruction gives displacement relative to the base address
• The difference between indexing and base addressing modes are in
the way they are used rather than in the way that they are computed
• This method is used to facilitate the relocation of programs in
memory
Computer instructions
• Data transfer instruction- data from one location to another without
change
• Data Manipulation instruction- arithmetic,logic and shift
• Program control instructions- decision making and change path
Data transfer instruction
• LOAD- memory to register(accumulator)
• STORE- register to memory
• MOVE- one register to another
• EXCHANGE- swap info b/w registers or b/w register and memory
• INPUT/OUTPUT- register to i/o terminals
• PUSH/POP- data b/w register and stack
Data Manipulation instruction
• Arithmetic Instruction
• Logical and Bit Manipulation Instruction
• Shift Instruction
Arithmetic Instruction
Logical and Bit Manipulation Instruction
Shift Instruction
• SHL
1001 = 0010 (0 APPENDED ON THE RIGHT)
• SHR
1001= 0100 (0 APPENDED ON THE LEFT)
• SHLA
1001= 0010 =0100 (2=4) (*2)
• SHRA
1001= 0100 =0010 (4=2) (/2)
• ROR
1001= 1100 (1 APPENDED TO THE LEFT)
• ROL
1001= 0011 (1 APPENDED TO THE RIGHT)
• RORC (THROUGH CARRY)
• ROLC(THROUGH CARRY)
Program Control Instructions
 Program control
1. Status Bit Conditions
2. Conditional branch instructions
3. Subroutine call & return
4. Program interrupts
Status Bit Conditions
• Most CPU architectures maintain a number of status bits that indicate
the results from the most recent ALU operation.
• These bits are usually stored in a status register, which is not directly
accessible as an argument in machine instructions.
• The bits are set automatically by many instructions, and used by
conditional branch instructions that follow.
V (overflow) indicates overflow in 2's complement.(-ve numbers)
C (carry) set to 1 if C8 is 1.
S (sign) set to 1 if F7 is 1.
Z (zero) set to 1 if output 0. ( all bits are 0 )
2. Conditional branch instructions
3. Subroutine call & return
• A subroutine is a self-contained sequence of instructions that
performs a given computational task.
• The instruction is executed by performing two operations:
1. The address of the next instruction available in the program counter
(the return address) is Stored in a temporary location so the
subroutine knows where to return
2. Control is transferred to the beginning of the subroutine.
4. Program interrupts
• Program interrupt refers to the transfer of program control from a
currently running program to another service
• program as a result of an external or internal generated request. Control
returns to the original program after the service program is executed.
• The interrupt procedure is, in principle, quite similar to a subroutine call
except for three Variations:
1. The interrupt is usually initiated by an internal or external signal rather
than from the Execution of an instruction
2. The address of the interrupt service program is determined by the
hardware rather than from the address field of an instruction.
Types of interrupts
• There are three major types of interrupts that cause a break in the
normal execution of a Program.
• They can be classified as:
1. External interrupts
2. Internal interrupts
3. Software interrupts
• External interrupts come from input-output (I/O) devices, from a
timing device, from a circuit monitoring the power supply, or from
any other external source.
• Internal interrupts arise from illegal use of an instruction or data.
• Internal interrupts are also called traps.
• Examples of interrupts caused by internal error conditions are register
overflow, attempt to divide by zero, an invalid operation code, stack
overflow.
• A software interrupt is initiated by executing an instruction.
• Software interrupt is a special call instruction that behaves like an
interrupt rather than a subroutine call.
• It can be used by the programmer to initiate an interrupt procedure
at any desired point in the program.
Difference between CISC and RISC
S.No. RISC CISC
1. RISC is a reduced instruction CISC is a complex instruction
set. set.
2. The number of instructions The number of instructions
is less as compared to CISC. is more as compared to RISC.

3. The addressing modes are The addressing modes are

less. more.
4. It works in a fixed instruction It works in a variable
format. instruction format.
5. The RISC consumes low The CISC consumes high
power. power.
6. The RISC processors are The CISC processors are less
highly pipelined. pipelined.
7. It optimizes the performance It optimizes the performance
by focusing on software. by focusing on hardware.
8. Requires more RAM. Requires less RAM.