energies

Article
Full-Bridge Active-Clamp Forward-Flyback Converter
with an Integrated Transformer for High-Performance
and Low Cost Low-Voltage DC Converter of
Vehicle Applications
Jaeil Baek 1 and Han-Shin Youn 2, *
1 Department of Electrical Engineering, Princeton University, Princeton, NJ 08540, USA;
jaeil.baek@princeton.edu
2 Department of Electrical Engineering, Incheon National University, 119, Academy-ro, Yeonsu-gu,
Incheon 406840, Korea
* Correspondence: hsyoun@inu.ac.kr




Received: 14 January 2020; Accepted: 12 February 2020; Published: 16 February 2020


Abstract: This paper presents a full-bridge active-clamp forward-flyback (FBACFF) converter

with an integrated transformer sharing a single primary winding. Compared to the conventional
active-clamp-forward (ACF) converter, the proposed converter has low voltage stress on the primary
switches due to its full-bridge active-clamp structure, which can leverage high performance Silicon-
metal–oxide–semiconductor field-effect transistor (Si-MOSFET) of low voltage rating and low channel
resistance. Integrating forward and flyback operations allows the proposed converter to have much
lower primary root mean square (RMS) current than the conventional phase-shifted-full-bridge (PSFB)
converter, while covering wide input/output voltage range with duty ratio over 0.5. The proposed
integrated transformer reduces the transformer conduction loss and simplify the secondary structure
of the proposed converter. As a result, the proposed converter has several advantages: (1) high heavy
load efficiency, (2) wide input voltage range operation, (3) high power density with the integrated
transformer, and (4) low cost. The proposed converter is a very promising candidate for applications
with wide input voltage range and high power, such as the low-voltage DC (LDC) converter for
eco-friendly vehicles.

Keywords: active-clamp converter; DC-DC converter; eco-friendly vehicle; forward-flyback converter;

high efficiency; high power density; integrated transformer; low-voltage DC converter; soft-switching

1. Introduction
Nowadays, eco-friendly vehicles such as hybrid electric vehicle and electric vehicle have been
researched and developed to satisfy the strengthened CO2 emission regulations as well as to increase
fuel economy [1–3]. A lot of power conversion systems have been studied for eco-friendly vehicles.
These power conversion systems require not only a high efficiency to improve the fuel economy but also
a high power density because those are installed in the engine and trunk rooms of eco-friendly vehicles.
Moreover, the price of eco-friendly vehicles is much higher than that of the traditional vehicles due to
additional power conversion systems, i.e., drive motor, inverter, converters, and battery. Therefore,
reducing the production cost is also one of the most important design considerations for eco-friendly
vehicles. Furthermore, the power consumption caused by electronic devices of vehicles has been
rapidly increased due to the remarkable improvement of information technology and development of
electronic system such as advanced driver assistance system (ADAS), motor drive steering system
(MDPS), traction control system (TCS), information devices, etc. [4].

Energies 2020, 13, 863; doi:10.3390/en13040863 www.mdpi.com/journal/energies

 Energies 2019, 12, x FOR PEER REVIEW 2 of 17
Energies 2020, 13, 863 2 of 17
Energies 2019, 12, x FOR PEER REVIEW 2 of 17
To supply power to electronic devices of vehicles, a LDC converter that charges low voltage (LV)
battery
To (e.g., 13.6 V) to with the energy storedvehicles,
in high voltage (HV) batterycharges (e.g. 300 V) is commonly
To supply
supply powerpower to electronic
electronic devices
devices of of vehicles,aaLDC LDCconverter
converterthat that chargeslow lowvoltage
voltage(LV) (LV)
used in eco-friendly
battery vehicles. The LV battery is usually controlled to maintain its nominal voltage.
battery (e.g., 13.6 V)
(e.g., 13.6 V)with
with theenergy
the energy stored
stored in in high
high voltage
voltage (HV) (HV) battery
battery (e.g.,(e.g.
300 300
V) isV) is commonly
commonly used
Namely,
used the LDC converter
in eco-friendly vehicles. should
The LVbebattery
designed to cover
is usually wide input
controlled to voltage
maintain range of the HV battery.
its nominal
in eco-friendly vehicles. The LV battery is usually controlled to maintain its nominal voltage. voltage.
Namely,
Due to the increased
Namely, power consumption of high-performance electronic devices (ADAS, MDPS, and
the LDC the LDC converter
converter should beshould designed be designed
to cover wide to cover
input wide input
voltage voltage
range of therange
HV of the HV
battery. Duebattery.
to the
so on)
Due to in increased
the vehicles, power
the discharging
consumption current
of of the LV battery
high-performance has been
electronic increased.
devices (ADAS, Accordingly,
MDPS, and to
increased power consumption of high-performance electronic devices (ADAS, MDPS, and so on) in
somaintain
on) in the the LV
vehicles, battery in
the discharging normal range,
current the nominal
of thehas LVbeenbatteryoutput current
has been of the LDC
increased.toAccordingly,converter, toi.e.,
vehicles, discharging current of the LV battery increased. Accordingly, maintain the LV
chargingthe
maintain current
LV of the in
battery LVnormal
battery,range,has been the also continuously
nominal output increased.
current of the AsLDCa result, it is getting
converter, i.e.,
battery in normal range, the nominal output current of the LDC converter, i.e., charging current of
important
charging for theofLDC
current the LV converter tohas
achieve higher heavy loadincreased.
efficiency.As Currently,
a result, plug-in hybrid
the LV battery, has been alsobattery,
continuously been also continuously
increased. As a result, it is getting important it
foristhe
getting
LDC
electric vehicles
important
converter to the (PHEVs)
forachieve LDC usually
converter
higher
adopt
heavytoload achieve a HV battery
higher
efficiency. heavy with
Currently, load240–413 V (nominal
efficiency.
plug-in hybridCurrently,
360 plug-in
V), and
electric vehicles
HEVs do
hybrid
(PHEVs)
a HV
electric battery with 200–310 V operating range (nominal 270
usually adopt a HV battery with 240–413 V (nominal 360 V), and HEVs do a HV battery with 200–310do
vehicles (PHEVs) usually adopt a HV battery with 240–413V). Both
V uses
(nominal approximated
360 V), and 13.6
HEVs VVLV
battery.
aoperating
HV battery Inrange
addition,
with the LDC
200–310
(nominal converter
V operating
270 V). Both uses is designed
range (nominal
approximatedup 270to 2kW meaning
V). Both
13.6 V LVuses very high
approximated
battery. In output
addition, 13.6current
the LV of
VLDC
140–160
battery. InA.addition, the LDC converter is designed
converter is designed up to 2 kW meaning very high output current of 140–160 A. up to 2kW meaning very high output current of
140–160 In order
A. to achieve high efficiency and high power density
In order to achieve high efficiency and high power density under wide input voltage range and under wide input voltage range and
highIn
high ordercurrent
output
output to achieve
current high efficiency
specifications,
specifications, and high power
theconventional
the conventional LDCLDC density under
converter
converter wide
adopts
adopts input voltage full-bridge
a phase-shifted
a phase-shifted range and
full-bridge
high output
(PSFB) current
converter specifications,
as shown in the
Figure conventional
1 due to theLDC converter
zero-voltage
(PSFB) converter as shown in Figure 1 due to the zero-voltage switching (ZVS) characteristic and twice adopts
switchinga phase-shifted
(ZVS) full-bridge
characteristic and
(PSFB)
powering converter
twice poweringoperation as in
shown
operation in Figure
one switching 1 dueoftoperiod
one switching
period thePSFB
the zero-voltage
the PSFBswitching
of converter converter
[5–9]. (ZVS)
However, characteristic
[5–9].since
However, andthe
since
the operating
twice powering
operating duty operation
ratio at the in one
nominal switching
input period
voltage of
is the
far PSFB
small, converter
the
duty ratio at the nominal input voltage is far small, the PSFB converter has large circulating current PSFB [5–9].
converter However,
has large since the
circulating
operating duty
currentfreewheeling
during ratio at
during freewheeling the nominal
periods periods input
as shown asinvoltage
shown
Figure is far
in1b, small,
Figure
which the
1b,causes PSFB converter
which significant has
causes significant large circulating
high conduction
high conduction loss
current during freewheeling periods as shown in Figure 1b, which
at heavy load condition. Furthermore, the PSFB converter has large system volume because of two of
loss at heavy load condition. Furthermore, the PSFB converter causes
has significant
large system high
volume conduction
because
loss
twoatmagnetic
magnetic heavy load
components condition.
components Furthermore,
(transformer
(transformer and output the PSFB
and output
inductorconverter
shownhas
inductor shown
in largein
Figure system
Figure
2b), volume
which 2b),must because
which must
be firmlyof be
two
fixedmagnetic
firmly byfixed
usingby components
using additional
additional (transformer
bulky and
bulky devices, and
devices, output
largeand inductor
sizelarge shown
size ofcircuits
of snubber snubberin Figure
tocircuits 2b),
constraint which
to constraint must be
voltage
voltage stresses
firmly fixed by using additional bulky devices, and large size of snubber
on the secondary diodes. As a result, the conventional PSFB converter makes difficult to minimize the to
stresses on the secondary diodes. As a result, the conventional PSFB circuits
converterto constraint
makes voltage
difficult
stresses
minimize
size of theon power
the size
the secondary
of theunit
control diodes.
power (PCU) Asshown
control a result,
unit the conventional
in(PCU)
Figure shown
2a which PSFB converter
in includes
Figure 2aanwhich
inverter,makes LDCdifficult
includes to
an inverter,
converter,
minimize
LDCcontrol
and theboard.
converter, sizeandof the power
control control unit (PCU) shown in Figure 2a which includes an inverter,
board.
LDC converter, and control board.

(a) (b)
(a) (b)
Figure 1. Conventional phase-shifted full-bridge (PSFB) converter. (a) Circuit diagram. (b) Primary
Figure 1.
Figure Conventional phase-shifted
1. Conventional phase-shifted full-bridge
full-bridge(PSFB)
(PSFB) converter.
converter. (a)
(a) Circuit
Circuit diagram.
diagram. (b)
(b) Primary
Primary
current waveform.
current waveform.
current waveform.

(a)
(a) (b)(b)
Figure 2.2.Pictures
Figure2. ofofpower
Picturesof control
powercontrol
controlunit
unit (PCU) and
(PCU) LDC
and converter
LDC converterfor vehicle applications. (a) PCU.
Figure Pictures power unit (PCU) and LDC converter forfor vehicle
vehicle applications.
applications. (a) (a)
PCU.PCU.
(b)
(b)LDC.
LDC.
(b) LDC.
 Energies 2020, 13, 863 3 of 17

Many DC/DC topologies with low circulating current have been developed to reduce the
conduction loss of the conventional PSFB converter [5–11]. The converter presented in [7] reduces the
circulating current of the PSFB converter by using large resonant inductance. However, it has serious
disadvantages of two additional switches and large volume of auxiliary inductor, which results in
increasing the volume and cost of the LDC converter. The converters shown in [8,11] can obtain small
circulating current by using an additional capacitor in the primary side or a coupled inductor in the
secondary side. However, an additional capacitor in [8] cannot be small to handle high voltage stress
and high current stress. A coupled inductor in [11] requires larger core size compared to a discrete
output inductor to keep the same power loss. Moreover, these converters should have two separate
magnetic components. Therefore, these converters are still limited in improving power density of the
LDC converter.
To complement large circulating current of the conventional PSFB converter, many
active-clamp-forward (ACF) converters have been studied [12–19]. These ACF converters have
advantages of the zero circulating current and low number of switches, which results in lower
conduction loss compared to the conventional PSFB converter. However, despite of low conduction
loss, these converters suffer from high voltage stress on the primary switches, which becomes far worse
taking into account wide input voltage range. As a result, the ACF converters in [12–19] should use low
performance of Si-MOSFETs increasing conduction loss and switching loss. In order to improve this
drawback and achieve high efficiency, the ACF converters can adopt silicon-carbide (SiC) MOSFETs
which has high voltage rating, small on-resistance, and small parasitic capacitance. However, using
SiC-MOSFETs significantly increases the cost of LDC converter. Moreover, the ACF converters still
use two magnetic components increasing the volume of converter. To relieve the voltages stress
on the primary switches of the ACF converters, three-switch ACF converters were researched and
developed [14,15]. However, one of three switches still suffer from high voltage stress. Moreover, the
converters in [14,15] should use complex driving circuits and two magnetic components. To reduce the
number of the magnetic components, ACF converters with an integrated magnetic were represented
as shown in Figure 3 [16,17]. Although these converters utilize only one integrated magnetic, the
primary and secondary windings are wound the outside of the core shown in Figure 3, which requires
additional shield and structure causing the extra cost and volume to minimize the adverse effect
of electromagnetic interference (EMI). As a result, the conventional and previously studied ACF
Energies 2019, 12, x FOR PEER REVIEW 4 of 17
converters have limitations in commercialization especially for vehicle applications.

C1 D1
Np NL CO RO
CO NP1 NS1
Cc RO Q1
NS

D1 Lr
VS
VS
QA NP2 NS2
Q2
QM D2
D2 C2

(a) (b)

Figure
Figure 3. 3. Conventional
Conventional active-clamp-forward
active-clamp-forward (ACF)(ACF) converters
converters with integrated
with integrated magnetics.
magnetics. (a)
(a) Integration
Integration of a transformer
of a transformer and anand an output
output inductor
inductor [16].
[16]. (b) (b) Integration
Integration of twooftransformers
two transformers
[17]. [17].

In this paper, the full-bridge active-clamp-forward-flyback (FBACFF) converter adopting an

2. Operational Principle
integrated transformer sharing single primary winding is proposed for the LDC converter of vehicle
Figures 4 and
applications. 5 show the
The proposed circuit
FACFF diagram
converter hasand
the operational key waveforms
following advantages compared of the proposed
to conventional
converter,
topologies: respectively. In the proposed
(1) active-clamp structure of converter, the primary
the proposed switches
converter Q1 and
minimizes theQ 4 are turned
circulating on at of
current
thethesame time to transfer the power from the input to the output through the forward
conventional PSFB converter, which results in higher efficiency; (2) full-bridge structure of thetransformer
(Tfor ). Meanwhile,
proposed the switches
converter relieves Q 2 and
high Q3 are stress
voltage drivenon complementarily with Qof
the primary switches 1 and
the Q 4 to reset Tfor ACF
conventional as
well as to deliver
converter the energy
and thus stored in
the proposed the flyback
converter cantransformer (Tfly) into theSi-MOSFETs
adopt cost-competitive output. For the andsake of
achieve
analysis, several assumptions are made as follows:
high efficiency without high-cost SiC-MOSFETs; (3) it can have lower diode voltage stress than the
1) all parasitic components except for those specified in Figure 4 are ignored;
2) a clamp capacitor (CC) is large enough to be considered as a constant voltage source (VCc );
3) the output voltage (VO) is constant;
4) the transformer turns ratio (n) of the forward and flyback transformers (Tfor and Tfly) is N/1, where
N is the number of the primary winding.
Energies 2019, 12, x FOR PEER REVIEW 4 of 17

Energies 2020, 13, 863 4 of 17

C1 D1
Np NL CO RO
CO NP1 NS1
PSFBCconverter, which
c
N enables the proposed converter
S
R to useQ high-current rating diodes; and (4) a
O
1

proposed single integrated transformerDreduces volume and cost of the

1
L LDC converter. The primary r
V S
V
and secondary windings of the proposed integrated transformer are wound inside
S
Q A
Q N Nof the transformer P2 S2
2

core, which enables

Q the proposed converter not only to minimize theCadverse effect of EMI D but also 2
M D 2 2

to eliminate additional snubber circuits due to small leakage inductance. As a result, the proposed
converter can achieve high efficiency, high power density, and low cost compared to the conventional
(a) (b)
topologies. In order to verify the validity of the proposed converter, a prototype with 200–310 V input
and 1.8 kW
Figure (13.6 V/130 A)active-clamp-forward
3. Conventional output was built and the experimental
(ACF) convertersresults
with are presentedmagnetics.
integrated compared (a)
with
the conventional PSFB converter which is the most widely used in the commercialized LDC
Integration of a transformer and an output inductor [16]. (b) Integration of two transformers [17]. converter.

2. Operational Principle
2. Operational Principle
Figures 4 and 5 show the circuit diagram and operational key waveforms of the proposed converter,
Figures 4 and
respectively. 5 proposed
In the show theconverter,
circuit diagram and
the primary operational
switches Q1 and key
Q4 arewaveforms
turned on atofthe the proposed
same time
converter, respectively.
to transfer the power In thethe
from proposed converter,
input to the the primary
output through switches
the forward Q1 and Q
transformer (T4forare turned on at
). Meanwhile,
the same time toQtransfer
the switches 2 and Q3the
are power from the input to
driven complementarily theQoutput
with 1 and Qthrough
4 to reset the forward
Tfor as well as transformer
to deliver
(Tfor).the
Meanwhile, the in
energy stored switches Q2 and
the flyback Q3 are driven
transformer complementarily
(Tfly ) into the output. Forwith Q1 and
the sake Q4 to reset
of analysis, Tfor as
several
well assumptions
as to deliverarethemade
energy stored in the flyback transformer (Tfly) into the output. For the sake of
as follows:
analysis, several assumptions are made as follows:
(1) all parasitic components except for those specified in Figure 4 are ignored;
1) all(2)
parasitic components
a clamp capacitor (Cexcept for those
C ) is large enough specified in Figure
to be considered as4aare ignored;
constant voltage source (VCc );
2) a clamp
(3) the capacitor (CC) is (V
output voltage large
O ) enough
is constant;to be considered as a constant voltage source (VCc );
3) the(4)output voltage (VOturns
the transformer ) is constant;
ratio (n) of the forward and flyback transformers (Tfor and Tfly ) is N/1, where
N is the number
4) the transformer of the(n)
turns ratio primary
of thewinding.
forward and flyback transformers (Tfor and Tfly) is N/1, where
N is the number of the primary winding.

iO

Q1 vds1 Tfor Tfly Q3 vds3

n:1 n:1

VCc VO
iD1 iD2
iLlkgLlkg Lm,for Lm,fly Cc CO RO
VS Tint, n:1
vD1 vD2
Q2 vds2 Q4 vds4
D1 D2

(a)

Tfor D1
Q1 Q3

Cc CO
VS RO

Q2 Q4
Tfly D2
Tint, n:1

(b)

Figure
Figure 4. Proposed
4. Proposed converter.
converter. (a) Circuit
(a) Circuit diagram.diagram. (b)diagram
(b) Circuit Circuit diagram with a proposed
with a proposed integrated
integrated
transformer. transformer.
 Energies
Energies 2019, 12, x2020,
FOR 13,PEER
863 REVIEW 5 of 17 5 of 17

DTs
DeffTs D＇
eff Ts

Q2 Q1,Q4 Q2,Q3 Q1,Q4

VS
VS-nVO nVO
vLlkg
nVO
vLm,fly
VCc-nVO
vLm,for
VCc

iLm,fly
iLlkg
iLm,for
vds1
VS
vds2
vds4
VCc
vds3
IO
iD2

iD1
vD1
(VCc)/n
VS/n
vD2
t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t0'

Figure 5. Key operational waveforms of the proposed converter.

Figure 5. Key operational waveforms of the proposed converter.
The proposed converter shows 10 operational modes during one switching period and each mode
The proposed with
is explained its topological
converter showsstate 10 asoperational
shown in Figure modes6. during one switching period and each
Mode 1 [t0 –t1 , Figure 6a]: At time t0 , after the commutation of the secondary diodes (D1 and D2 )
mode is explained with its topological state as shown in Figure 6.
ends and the leakage inductor current (iLlkg ) reaches to the magnetizing current of Tfly (iLm,fly ), nVO ,
Mode and1V[t 0–t1, Figure 6a]: At time t0, after the commutation of the secondary diodes (D1 and D2)
S –nV O are applied to the magnetizing inductance of Tfor (Lm,for ) and the magnetizing inductance
ends andofthe Tflyleakage inductor current
(Lm,fly ), respectively. As a result, (iLlkg)iLm,for
reaches
, iLm,flyto the imagnetizing
, and Llkg are linearlycurrent
increased.of The
Tfly (iLm,fly),is
power nVO, and
VS–nVO are transferred
appliedtotothe theoutput through Qinductance
magnetizing 1 , Q4 , integrated
of Tfor transformer,
(Lm,for) andand theDmagnetizing
1 at this mode.inductance
From the of Tfly
voltage across transformers,
(Lm,fly), respectively. As a result, iLm,for i , i
, iLm,fly
Lm,for Lm,fly , and current of
, and iLlkg are linearlyD (i ) are expressed as follows:
1 D1 increased. The power is transferred to

the output through Q1, Q4, integrated transformer, and nVD O

1 at this mode. From the voltage across
iLm, f or (t) = iLm, f or (t0 ) + ( t − t0 ) , (1)
transformers, iLm,for, iLm,fly, and current of D1 (iD1) are expressed L m, f or as follows:

nV
= i(Lm
iLm, f ilyLm(t, )for=(ti)Llkg for (
t) , = t0 ) + (t ) O+ V
iLm, (tS−−t0nV ) ,O (t − t ), (2) (1)
f ly L0 0
m , for Lm, f ly
i S −f or
(t) −ViLm, nV(t)O
iLm , fly (t ) = iLlkgiD1(t()t)==iLmLm,
, fly (t0 ) +
f ly
. (t − t0 ) , (3) (2)
n Lm , fly

iLm, fly (t ) − iLm, for (t )

iD1 (t ) =
. (3)
n
Mode 2 [t1–t2, Figure 6b]: After t1, Q1 and Q4 are turned off, and mode 2 begins. iLm,fly is the same
as the reflected load current (IO/n) charges Coss1 and Coss4 and discharges Coss2 and Coss3. Thus, the
voltages across Q1 and Q4 (vds1 and vds4) simultaneously increase to VS/2, and the voltages across Q2
and Q3 (vds2 and vds3) decrease to VS/2 and VCc–VS/2, respectively. Thus, the voltage across Lm,fly (vLm,fly)
is decreased from VS–nVO to –nVO so that the sum of the voltages across Lm,fly and Lm,for is zero at the
end of this mode.
 2
Llkg iLlkg (t2 ) ≥ Coss VCc + S  , (4)
2  2  2
where Coss = Coss1 = Coss2 = Coss3 = Coss4.
Mode 5 [t4–t5, Figure 6e]: At time t4, vds2 and vds3 are 0V, and iLkkg flows through body diodes of Q2
Energies3.2020,
and Q As a13,result,
863 Q2 and Q3 can achieve the ZVS operation. Moreover, since the sum of vLm.for6 of
and
17
vLm.fly is zero, –VCc is applied to Llkg. Thus, iLlkg is linearly decreased to iLm.for with the commutation
between D1 and D2. iLlkg at this mode is:
iO
iO Tfor Tfly Q3
Q1
Q1 Tfor Tfly Q3 n:1 n:1
n:1 n:1
VLlkg
VLlkg VCc iD1 iD2 VO
VCc iD1 iD2 VO iLlkgLlkg Lm,for Lm,fly Cc CO RO
VS VLm,for VLm,fly
iLlkgLlkg Lm,for Lm,fly Cc CO RO
VS VLm,for VLm,fly
Tint, n:1
Q2 Q4
Tint, n:1
Q2 Q4 D1 D2
D1 D2

(b)
(a)
iO iO

Q1 Tfor Tfly Q3 Q1 Tfor Tfly Q3

n:1 n:1 n:1 n:1
VLlkg VLlkg
VCc iD1 iD2 VO VCc iD1 iD2 VO
iLlkgLlkg Lm,for Lm,fly Cc CO RO iLlkgLlkg Lm,for Lm,fly Cc CO RO
VS VLm,for VLm,fly VS VLm,for VLm,fly
Tint, n:1 Tint, n:1
Q2 Q4 Q2 Q4
D1 D2 D1 D2

(c) (d)
iO iO

Q1 Tfor Tfly Q3 Q1 Tfor Tfly Q3

n:1 n:1 n:1 n:1
VLlkg VLlkg
VCc iD1 iD2 VO VCc iD1 iD2 VO
iLlkgLlkg Lm,for Lm,fly Cc CO RO iLlkgLlkg Lm,for Lm,fly Cc CO RO
VS VLm,for VLm,fly VS VLm,for VLm,fly
Tint, n:1 Tint, n:1
Q2 Q4 Q2 Q4
D1 D2 D1 D2

(e) (f)
iO iO

Q1 Tfor Tfly Q3 Q1 Tfor Tfly Q3

n:1 n:1 n:1 n:1
VLlkg VLlkg
VCc iD1 iD2 VO VCc iD1 iD2 VO
iLlkgLlkg Lm,for Lm,fly Cc CO RO iLlkgLlkg Lm,for Lm,fly Cc CO RO
VS VLm,for VLm,fly VS VLm,for VLm,fly
Tint, n:1 Tint, n:1
Q2 Q4 Q2 Q4
D1 D2 D1 D2

(g) (h)
iO iO

Q1 Tfor Tfly Q3 Q1 Tfor Tfly Q3

n:1 n:1 n:1 n:1
VLlkg VLlkg
VCc iD1 iD2 VO VCc iD1 iD2 VO
iLlkgLlkg Lm,for Lm,fly Cc CO RO iLlkgLlkg Lm,for Lm,fly Cc CO RO
VS VLm,for VLm,fly VS VLm,for VLm,fly
Tint, n:1 Tint, n:1
Q2 Q4 Q2 Q4
D1 D2 D1 D2

(i) (j)

Figure
Figure6.6.Topological
Topologicalstate stateofofproposed
proposedconverter.converter.(a) (a)Mode1(t
Mode 10–t (t01).
–t(b) Mode2(t
1 ). (b) Mode1–t ).1(c)
2 2(t –t2 Mode3(t
). (c) Mode2–t33 ).
(d) Mode4(t
(t2 –t 3 ). (d) 3–t
Mode4). (e)
4 Mode5(t
(t –t
3 4 ). (e)4–t
Mode
5 ). (f) Mode6(t
5 (t –t
4 5 ). –t
(f)
5 6 ).
Mode(g) Mode7(t
6 (t –t
5 6 ).
6 –t
(g)
7 ). (h)
Mode Mode8(t
7 (t –t
6 77 –t
). 8 ).
(h) (i) Mode9(t
Mode 8 (t 7 8).
8–t 9

(j) Mode 9 (t98–t–t0’).

(i)Mode10(t 9 ). (j) Mode 10 (t –t
9 0 ’).

Mode 2 [t1 –t2 , Figure 6b]: After t1 , Q1 and Q4 are turned

i (t ) i (t )
off, and mode 2 begins. iLm,fly is the
Llkg 3 Llkg 4
same as the reflected load current (IO /n) charges Coss1 and Coss4 and discharges Coss2 and Coss3 . Thus,
Llkg Llkg
the voltages across Q 1 and
Ceq1 Q (vds1 Cand
eq2 vvds4(t) )simultaneously increaseCto eq3 VS /2, and the voltages across
v (t 4) ds2 3 v (t )
ds4 3 ds4 4
=V /2
Q2 and Q3 (vds2 and vds3 ) decrease to VS /2=Vand
/2 VCc –VS /2, respectively. Thus,
S =V the voltage across L
S
m,fly
S

(vLm,fly ) is decreased from VS –nVO to –nVO so that the sum of the voltages across Lm,fly and Lm,for is
zero at the end of this mode.
Mode 3 [t2 –t3 , Figure 6c]: vLm,fly reaches –nVO at t2 , D1 , and D2 start to conduct. The leakage
inductance of the integrated transformer (Llkg ) resonates with parasitic output capacitors (Coss1 , Coss2,
Coss3 , and Coss4 ). The equivalent circuit of this mode is illustrated in Figure 7a. From this Figure,
the energy stored in Llkg charges Coss1 and Coss4 and discharges Coss2 and Coss3 . Thus, vds1 and
vds4 are increased, and vds1 is clamped to VS . Meanwhile, vds2 and vds3 are decreased to zero and
VCc –VS , respectively.
Energies 2020, 13, 863 7 of 17

iLlkg(t3) iLlkg(t4)

Llkg Llkg
Ceq1 Ceq2 Ceq3
vds2(t3) vds4(t3) vds4(t4)
=VS/2 =VS/2 =VS

Energies 2019, 12, x FOR PEER REVIEW 7 of 17

(a) (b)
iLlkg(t7) iLlkg(t8)

Llkg Llkg
Ceq1 Ceq2 Ceq3
vds1(t7) vds4(t7) vds3(t8)
=VS/2 =VS/2 =VS

(c) (d)

Figure 7.
Figure Equivalent circuit
7. Equivalent circuitof
ofthe
theproposed
proposedconverter
converterduring switching
during transitions.
switching (a) (a)
transitions. Mode 3 (t2 –t
Mode3 ). 3).
(t23–t
(b) Mode 4 (t –t ). (c) Mode 8 (t
(b) Mode4 (t33–t44). (c) Mode8 (t7–t –t ). (d) Mode 9 (t –t
7 8).8 (d) Mode9 (t8–t89). 9 ).

Mode 4 [t3 –t4 , Figure 6d]: After vds2 reaches to zero at t3 , mode 4 starts. In this mode, only
VCc
Coss3 and Coss4 are continuously discharged iLlkg (t ) = iandLlkg (t 4 ) −
charged (tby− tthe4).
resonance with Llkg , respectively. vds3 (5)
L lkg
decreases to zero and vds4 increases to VCc . The equivalent circuit of this mode is depicted in Figure 7b.
Based From
on Mode(5), the commutation
3 and Mode 4, theperiod, ZVS conditionwhere the of Q input
2 andpower Q3 are:is not transferred to the output, can
be approximated as LlkgIO/(nVCc).
1 the 1 VS 2 D2 ends, the voltage on D1 reaches
 
Mode 6 [t5–t6, Figure 6f]: After Llkg i2Llkg commutation
(t2 ) ≥ Coss VofCcD +1 and , (4)
VCc/n and the reset operation of T2for starts by vLm,for 2 (=nVO–VCc).2Meanwhile, the energy stored in Tfly is
delivered
where Cossto =C the output because vLm,fly is –nVO. As a result, iLm,for, iLm,fly, and current of D2 (iD2) are
oss1 = Coss2 = Coss3 = Coss4 .
expressed as follows:
Mode 5 [t4 –t5 , Figure 6e]: At time t4 , vds2 and vds3 are 0 V, and iLkkg flows through body diodes
of Q2 and Q3 . As a result, Q2 and Q3 can achieveVCc the− nVZVS O operation. Moreover, since the sum of
iLm , for (t ) = iLm , for (t5 ) − (t − t5 ) , (6)
vLm.for and vLm.fly is zero, –VCc is applied to Llkg . Thus, Lm , foriLlkg is linearly decreased to iLm.for with the
commutation between D1 and D2 . iLlkg at this mode is: nV
iLm , fly (t ) = iLlkg (t ) = iLm , fly (t5 ) − O
(t − t 5 ) , (7)
L
VCc flym ,
iLlkg (t) = iLlkg (t4 ) − ( t − t4 ) . (5)
iLm , fly (t ) − iLmL, lkg
for (t )
iD 2 (t ) = . (8)
n
From (5), the commutation period, where the input power is not transferred to the output, can be
Mode 7 [t6–t7, Figure 6g]: After t6, Q2 and Q3 are turned off, and mode 7 starts. iLm,for charges Coss2 and
approximated as Llkg IO /(nVCc ).
Coss3 and discharges Coss1 and Coss4. Thus, vds2 and vds3 are increased to VCc/2 . vLm,for is increased from VCc–nVO
Mode 6 [t5 –t6 , Figure 6f]: After the commutation of D1 and D2 ends, the voltage on D1 reaches
to nVO. On the other hand, vds1 and vds4 are decreased to VS–VCc/2 and VCc/2, respectively. This mode ends
VCc /n and the reset operation of Tfor starts by vLm,for (=nVO –VCc ). Meanwhile, the energy stored in Tfly
when vLm,for reaches to nVO and the sum vLm,fly of isthe–nVvoltage on the magnetizing inductances is zero.
is delivered to the output because O . As a result, iLm,for , iLm,fly , and current of D2 (iD2 ) are
Modeas
expressed 8 [t 7–t8, Figure 6h]: vLm,for reaches nVO at t7 and D1 and D2 conduct. Thus, Llkg resonates with
follows:
Coss1, Coss2, Coss3, and Coss4. The equivalent circuit of this V mode − nVOis illustrated as in Figure 7(. From this
iLm, f or (t) = iLm, f or (t5 ) − Cc (t − t5 ), (6)
Figure, the energy stored in Llkg charges Coss2 and Coss3 and Lm, fdischarges
or Coss1 and Coss4. Thus, vds2 and vds3
are increased and vds2 is clamped to VS, whereas vds1 and vds4 are decreased to zero and VCc–VS,
nVO
respectively. iLm, f ly (t) = iLlkg (t) = iLm, f ly (t5 ) − ( t − t5 ) , (7)
Lm, f ly
Mode 9 [t8–t9, Figure 6i]: After vds1 reaches to zero at t8, Mode 9 begins. In this mode, only Coss3
and Coss4 are continuously charged and discharged iLm, f ly (t)in Lm, f or (t)
− iaccordance with the resonance with Llkg. As a
iD2 (t) = . (8)
result, vds4 is decreased to zero and vds3 is increasedn to VCc. The equivalent circuit of this mode is
depicted
Mode in 7Figure
[t6 –t7 ,7d. Based
Figure 6g]:onAfterModet6 ,8Q and
2 and Mode Q3 are 9, theturnedZVS off, condition
and mode of Q71 starts.
and Q4iLm,for
is: charges
Cc /2. vLm,for is
Coss2 and Coss3 and discharges Coss1 and Coss4 . Thus, v and 2v are increased to V
1 2 1  ds2 VS  ds3
increased from VCc –nVO to nVO . L On i the
lkg Llkg 7(t ) ≥
other Chand, V
oss  Cc ds1
v + and  ds4
. v are decreased to V S –VCc /2 and(9)
2 2  2  and the sum of the voltage on the
VCc /2, respectively. This mode ends when vLm,for reaches to nV O
Mode 10 [t 9 –t0 ',
magnetizing inductances is zero. Figure 6j]: After v ds1 and v ds4 become 0V, iLlkg flows through body diodes of Q1 and

Q4. Thus,ModeQ81 [t and Q4 can achieve the ZVS condition. Moreover, similar to Mode 5, since the sum of
7 –t8 , Figure 6h]: vLm,for reaches nVO at t7 and D1 and D2 conduct. Thus, Llkg resonates
vwith and
Lm.for C v is
oss1 , Coss2, Coss3
Lm.fly zero,
, andVSCoss4
is applied to the Lcircuit
. The equivalent lkg. Thus, iLlkgmode
of this is linearly increased
is illustrated as into iLm.flly7.with
Figure Fromthe
commutation between D1 and D2. iLlkg at this mode is:
V
iLlkg (t ) = iLlkg (t9 ) + S (t − t9 ) . (10)
Llkg
From (10), the commutation period can be derived as LlkgIO/(nVS).
3.1. DC Conversion Ratio
For simplifying analysis of the proposed converter, Llkg and the dead time among Q1–Q4 are
ignored. In Figure 8, VS–nVO and –nVO are applied to the Lm,fly during DTS and (1–D)TS, respectively.
Thus, the2020,
Energies DC 13,
conversion
863 ratio can be approximated as in (12) by the voltage second balance of8 of
Lm,fly
17 .

(VS − nVO ) DTS − nVO (1 − D ) TS = 0 , (11)

this Figure, the energy stored in Llkg charges VO CD and Coss3 and discharges Coss1 and Coss4 . Thus,
= oss2. (12)
vds2 and vds3 are increased and vds2 is clamped VS ton S whereas vds1 and vds4 are decreased to zero and
V ,
VCc –VS , respectively.
Moreover, based on the voltage second balance of Lm,for and Figure 8, VCc can be achieved as
follows:Mode 9 [t8 –t9 , Figure 6i]: After vds1 reaches to zero at t8 , Mode 9 begins. In this mode, only Coss3
( )
and Coss4 are continuously charged and discharged in accordance with the resonance with Llkg . As
nVO DTS − VCc − nVO (1 − D ) TS = 0 ,
a result, vds4 is decreased to zero and vds3 is increased to VCc . The equivalent circuit of this mode is
(13)
depicted in Figure 7d. Based on Mode 8 and nVOModeD9, the ZVS condition of Q1 and Q4 is:
VCc = = VS . (14)
1− D 1− D  2
From Figure 9, the DC conversion 1 ratio 1 VS
Llkg i2Llkg (and
t7 ) ≥VCcCcan be recalculated
oss VCc + . by considering the duty loss1
(9)
2
(DL1) caused by the commutation operation when2 the Q1 and 2Q4 are turned on, the duty loss2 (DL2)
resulting from10the
Mode [t9commutation
–t0 ’, Figure 6j]:operation
After vds1 at
andthe Q2become
vds4 and Q30turn-on instant
V, iLlkg flows as follows:
through body diodes of Q1
and Q4 . Thus, Q1 and Q4 can achieve the ZVS condition. Moreover, similar to Mode 5, since the sum
of vLm.for and vLm.fly is zero, VS isVapplied
1 to the Llkg . LThus, iLlkg is linearly increased to iLm.flly with the
O
= D −(
commutation between D1 and D2 . iLlkg at this mode
VS n
DL1 is: )L
m , for
,
+ Llkg
(15)
m , for

nVO i Lm ,(for + Llkg D−D (tV−S t9=). D VS ,

VLS1
VCc = Llkg t) = iLlkg=(t9 ) +
L
(10)
(16)
1 − D − DL 2 Lm , for 1 − D − lkg
DL 2 1− D
where IFromO is the
(10),output load current,
the commutation fS can
period is the switching
be derived as Lfrequency,
lkg IO /(nVS ).
DL1 is LlkgIOfS/nVS, and DL2 is
LlkgIOfS/nVCc.
3. Therefore,
Analysis andtheDesign Consideration
DC conversion ratio of the proposed converter is almost the same as that of the
conventional
In thisACF converter.
chapter, characteristics of the proposed converter are analyzed. Moreover, the design
consideration of the proposed integrated transformer will be discussed to achieve high power density
3.2.and
Output Current
simple Ripplestructure of the proposed converter.
secondary
The conventional isolated converters, such as PSFB and ACF converters, generally adopt two
3.1. DC Conversion Ratio
magnetics: (1) transformer to transfer power from the input to the output and (2) output inductor to
control Forthe simplifying analysis
output current rippleofand
the output
proposed converter,
voltage LlkgMeanwhile,
ripple. and the dead onetime among Q
integrated 1 –Q4 are
transformer
ignored.
of the In Figure
proposed 8, VS –nV
converter and role
canOplay –nVOasare
twoapplied
traditional Lm,fly during
to themagnetics. TforDT andintegrated
ofS the (1–D)TS , respectively.
transformer
Thus, the DC conversion ratio can be approximated as in (12) by the voltage
operates as the transformer of the conventional isolated converter and Tfly plays role as the second balance of Loutput
m,fly .
inductor of the conventional converters. In addition, as shown in Figure 9, the difference of iLm.for and
(VS − nVO )DTS − nVO (1 − D)TS = 0, (11)
iLm.fly is reflected to the output current. As a result, the magnitude of Lm,for and Lm,fly determines the
output current ripple and output voltage ripple. VO From D Figure 9, the output current ripples can be
= . (12)
represented as in (17) and (18). The maximumVSoutput n current ripple can be decided on the larger
value between (17) and (18):

vgs Q2,Q3 Q1,Q4 Q2,Q3 Q1,Q4

DTs (1-D)Ts

nVO
VLm,for
VCc-nVO

VS-nVO
VLm,fly
nVO

Figure 8. Applied voltage on Lm,for and Lm,fly of the proposed converter.

Figure 8. Applied voltage on Lm,for and Lm,fly of the proposed converter.
Moreover, based on the voltage second balance of Lm,for and Figure 8, VCc can be achieved
as follows:
nVO DTS − (VCc − nVO )(1 − D)TS = 0, (13)
nVO D
VCc = = VS . (14)
1−D 1−D
 Energies 2020, 13, 863 9 of 17

From Figure 9, the DC conversion ratio and VCc can be recalculated by considering the duty loss1
(DL1 ) caused by the commutation operation when the Q1 and Q4 are turned on, the duty loss2 (DL2 )
resulting from the commutation operation at the Q2 and Q3 turn-on instant as follows:

VO 1 Lm, f or
= (D − DL1 ) , (15)
VS n Lm, f or + Llkg

nVO Lm, f or + Llkg D − DL1 D

VCc = = VS = VS , (16)
1 − D − DL2 Lm, f or 1 − D − DL2 1−D
where IO is the output load current, fS is the switching frequency, DL1 is Llkg IO fS /nVS , and DL2 is
Energies O fS /nV
Llkg I2019, 12,Ccx.FOR PEER REVIEW 9 of 17

DTs
DL1Ts DeffTs DL2Ts D＇
eff Ts

Q1,Q4 Q2,Q3 Q1,Q4

iLm,fly
iLlkg
iLm,for

ΔIO2 IO
iD2
ΔIO1
iD1
t0 t1 t2 t3 t0'

Figure 9. Primary and secondary current waveforms of proposed converter neglecting the dead-time.
Figure 9. Primary and secondary current waveforms of proposed converter neglecting the dead-time.
Therefore, the DC conversion ratio of the proposed converter is almost the same as that of the
conventional ACF − nVO nVO 
kVS converter.  kVS − nVO nVO  kn 2VO TS
ΔI O1 = 
 L
−  n ( D − DL1 ) TS =  −  , (17)
 m , fly Lm , for   Lm , fly Lm , for  VS
3.2. Output Current Ripple
 − nVO nVO − kVCc   −nVO nVO − kVCc  kn 2VO TS
ΔThe
I O 2 =conventional
 − isolated converters, n (1 − D − DLsuch ) T as= PSFB
 and− ACF converters,  generally
. adopt two
(18)
L
magnetics: (1)mtransformer L  2 S  L L V
, fly 
m , forto transfer power from the  input
m , fly to themoutput
, for  andCc(2) output inductor to
control
where k=L the output current ripple and output voltage ripple. Meanwhile, one integrated transformer of
m,for/(Lm,for + Llkg).
the proposed L
Therefore, converter can play role as two traditional magnetics. T proposed
m,fly and Lm,for of the integrated transformer in the for
of the integrated transformer
converter should be
operates as the transformer of the conventional isolated converter and Tfly plays role as the output
adequately designed and chosen to satisfy the requirement of the output current and voltage ripples.
inductor of the conventional converters. In addition, as shown in Figure 9, the difference of iLm.for and
3.3.iLm.fly is reflected
Transformer to the
Design andoutput current. As a result, the magnitude of Lm,for and Lm,fly determines the
Core loss
output current ripple and output voltage ripple. From Figure 9, the output current ripples can be
The proposed
represented converter
as in (17) with
and (18). Thethe integrated
maximum transformer
output shown
current ripple canin
beFigure
decided10oncan
theminimize the
larger value
number
between of the
(17)magnetic
and (18): components through the integration of Tfor and Tfly. Moreover, the integrated
transformer enables the proposed converter ! to simplify the secondary side without ! 2 snubber circuits
for the secondary kV − nV nV kV − nV nV kn VO TS studies have
∆IO1 diodes.
= STo implement
O
− O ann(integrated
D − DL1 )TStransformer,
= S various
O
− research
O and , (17)
been conducted [16,17]. m,However,L f ly L m, fthese
or methods have several L m, f ly L
disadvantages
m, f or V S such as large

conduction losses due to separate primary and secondary windings and EMI problem caused by the
−nVO nVO − kVCc kn2 VO TS
! !
−nVO nVO − kVCc
∆IO2 = outside
windings wound −the core, which n(1requires
− D − DL2additional
)TS = bulky− and expensive shield .to reduce (18)
Lm, f ly Lm, f or Lm, f ly Lm, f or VCc
the adverse effect of the EMI.
where k =paper,
In this Lm,for /(Lby + Llkga). characteristic that the primary currents of the forward and flyback
m,forusing
Therefore, L
transformers are them,fly and
same, an Lm,for of the integrated
integrated transformer transformer
for Tfor andinTthe proposed converter should be
fly is proposed where two cores are
adequately designed and chosen to satisfy the
separate and share the primary winding. In Figure 10, both the primaryrequirement of the output current and voltage
winding ripples.
and secondary
busbar are wound inside the core. As a result, the proposed integrated transformer can reduce the
3.3. Transformer Design and Core Loss
length of the transformer windings than those of the conventional integrated transformers in [16,17],
The proposed
which results in lower converter
conduction withlossthe integrated transformer
of the transformer. shown indue
Moreover, Figure 10 can
to the minimize
windings the
wound
number of the magnetic components through
inside the core, the proposed integrated transformer can have for the integration of T and
better EMI Tfly . Moreover, the integrated
characteristics than the
conventional integrated transformers [16,17]. Therefore, no additional shield is required in the
proposed converter. In addition, as shown in Figure 10b, it is noted that the proposed converter can
significantly simplify the secondary rectifier structure because the secondary busbar is directly
connected to the output capacitor, which results in higher power density. Furthermore, there is no
flux interference because two cores are separate from each other.
Energies 2020, 13, 863 10 of 17

transformer enables the proposed converter to simplify the secondary side without snubber circuits for
the secondary diodes. To implement an integrated transformer, various research and studies have
been conducted [16,17]. However, these methods have several disadvantages such as large conduction
losses due to separate primary and secondary windings and EMI problem caused by the windings
wound outside the core, which requires additional bulky and expensive shield to reduce the adverse
Energies
effect 2019,
of the 12, x FOR PEER REVIEW
EMI. 10 of 17

(a) (b)

Figure 10. Integrated

Figure transformer
10. Integrated of the proposed
transformer converter.converter.
of the proposed (a) Structure
(a)ofStructure
the integrated transformer.
of the integrated
(b)transformer.
Concise secondary side structure.
(b) Concise secondary side structure.

In this paper, by using a characteristic that

( D + Dthe
ΔB transformer
=
L 2 ) nVO TS
primary currents of the forward and flyback
, Tfly is proposed where two cores are (19)
transformers are the same, an integrated for for T and
N P Ae , for for
separate and share the primary winding. In Figure 10, both the primary winding and secondary busbar
are wound inside the core. As a result, the (proposed ) nVO TS , transformer can reduce the length
1 − D + DL1 integrated
ΔB fly = (20)
of the transformer windings than those of the conventional N A
P e , fly integrated transformers in [16,17], which
results
where in N
lower conduction
P is the number ofloss of the windings
primary transformer. Moreover,
of the integrated duetransformer
to the windings
and A wound
e,for andinside thethe
Ae,fly are
core, the proposed integrated transformer
effective cross-section area of each core. can have better EMI characteristics than the conventional
integratedTo transformers
analyze the core [16,17].
lossTherefore, no additional
of the proposed shieldtransformer,
integrated is required inthetheimproved
proposed converter.
generalized
In Steinmetz
addition, as shown in Figure 10b, it is noted that the proposed converter can
equation (IGSE) can be adopted because the flux variations of both cores are not sinusoidal.significantly simplify
theThe
secondary
transformer rectifier
core structure
loss basedbecause
on the IGSE the secondary
can be expressedbusbar as is directly
follows: connected to the output
capacitor, which results in higher power density. α
Furthermore, there is no flux interference because
1 T dB
two cores are separate from each other. Pcore =  ki (ΔB ) β −α dt , (21)
T 0 dt
The flux density of the proposed integrated transformer can be simply calculated by considering
where ΔB is the peak-to-peak flux variation, and
its operation. When Q1 and Q4 are turned on, D1 conducts and the power is transferred to the output
k
through Tfor . At that time, Tfly stores =
ki energy since 2π
D2 is reverse biased
α β −α
, and there is no current on Tfly
(22)
0 D2 conducts. Thus, the energy stored in Tfly starts to
α −1
and D2 . Whereas, when Q2 and Q3 are turned on, (2 π ) cos θ 2 d θ
be where
transferred to the output
parameters k, α, andthrough Tflysame
β are the and D 2 , while Tfor
parameters asisused
resetinbytheVCc . Duringequation
Steinmetz these two[20].
periods,
the fluxAssuming
variations that
of both
thecores
transformer Tfly ) can
(Tfor andturns the be expressed
ratio of the as follows:and conventional integrated
proposed
transformers the same way, the core loss of the proposed integrated transformer is the same as that
(D + DL2 )nVO TS
∆B f or =
of the conventional integrated transformer for the ACF ,converters. Meanwhile, the proposed (19)
NP Ae, f or
integrated transformer can have slightly larger core loss than the conventional PSFB converter with
a transformer and output inductor. This is because the turns-ratio of the proposed integrated
(1 − D + DL1 )nVO TS
transformer is restricted due to the ∆Bshared
f ly = primary windings. Thus,, the number of primary windings(20)
NP Ae, f ly
of the proposed integrated transformer can be lower than that of the transformer and output inductor
where NP conventional
in the is the numberPSFBof primary windings
converter, of the
which can integrated transformer
increase the core lossand Ae,forproposed
of the and Ae,fly converter
are the
effective cross-section
compared area of each
to the conventional core.converter. Since ΔIO is determined by the Lm,for and Lm,fly, relatively
PSFB
small Lm,for and Lm,fly should be designed to satisfy the requirement of ΔIO. Due to the relatively larger
core loss and magnetizing current, the proposed converter may have lower light load efficiency than
the conventional PSFB converter. On the other hand, the proposed integrated transformer results in
high heavy load efficiency because single primary windings and optimized busbar structure decrease
the conduction loss caused by the output current. As mentioned in introduction section, the
importance of heavy load efficiency in eco-friendly vehicles has been increasing more than before as
the electric load of the vehicle has considerably increased. Therefore, the proposed integrated
transformer is appropriate for the LDC converter of eco-friendly vehicles. Furthermore, the proposed
integrated transformer not only reduces the volume of the converter but also achieves a high price
Energies 2020, 13, 863 11 of 17

To analyze the core loss of the proposed integrated transformer, the improved generalized
Steinmetz equation (IGSE) can be adopted because the flux variations of both cores are not sinusoidal.
The transformer core loss based on the IGSE can be expressed as follows:

T
dB α
Z
1
Pcore = ki (∆B)β−α dt, (21)
T 0 dt

where ∆B is the peak-to-peak flux variation, and

k
ki = , (22)
α−1 2π
|cos θ|α 2β−α dθ
R
(2π) 0

where parameters k, α, and β are the same parameters as used in the Steinmetz equation [20].
Assuming that the transformer turns the ratio of the proposed and conventional integrated
transformers the same way, the core loss of the proposed integrated transformer is the same as that of
the conventional integrated transformer for the ACF converters. Meanwhile, the proposed integrated
transformer can have slightly larger core loss than the conventional PSFB converter with a transformer
and output inductor. This is because the turns-ratio of the proposed integrated transformer is restricted
due to the shared primary windings. Thus, the number of primary windings of the proposed integrated
transformer can be lower than that of the transformer and output inductor in the conventional PSFB
converter, which can increase the core loss of the proposed converter compared to the conventional
PSFB converter. Since ∆IO is determined by the Lm,for and Lm,fly , relatively small Lm,for and Lm,fly should
be designed to satisfy the requirement of ∆IO . Due to the relatively larger core loss and magnetizing
current, the proposed converter may have lower light load efficiency than the conventional PSFB
converter. On the other hand, the proposed integrated transformer results in high heavy load efficiency
because single primary windings and optimized busbar structure decrease the conduction loss caused
by the output current. As mentioned in introduction section, the importance of heavy load efficiency
in eco-friendly vehicles has been increasing more than before as the electric load of the vehicle has
considerably increased. Therefore, the proposed integrated transformer is appropriate for the LDC
converter of eco-friendly vehicles. Furthermore, the proposed integrated transformer not only reduces
the volume of the converter but also achieves a high price competitiveness due to the concise secondary
rectifier structure as shown in Figure 10b.

3.4. Conduction Loss and Voltage Stresses on Switches and Diodes

For the sake of analysis, it is assumed that (1) Lm,for and Lm,fly are large enough to ignore the
effect of the magnetizing current during a switching period and (2) Llkg is small enough to neglect
the effect of the commutation period. Based on this assumption, RMS currents and voltage stress
on the primary switches and secondary diodes can be derived for the conventional PSFB converter,
conventional ACF converter, and proposed converter (Table 1). From Table 1, it can be seen that the
proposed converter has negligible RMS currents on Q2 and Q3 , inducing the ignorable conduction loss.
Thus, the conduction loss on primary switches is much smaller than that of the conventional PSFB
converter and this tendency becomes larger as the output current goes to heavier load condition.
Due to the full-bridge active clamp structure, the proposed converter can achieve lower maximum
voltage stresses on primary switches (Q1 and Q2 : 310 V, Q3 and Q4 : 238.6 V under experimental
conditions) compared to the conventional ACF converter (Qmain and Qaux : 477.7 V). Thus, considering a
30% voltage margin, the proposed converter can adopt Si-MOSFETs with low cost and low on-resistance
rather than SiC-MOSFETs having high cost and high voltage rating characteristics (Table 2). Moreover,
the proposed converter reduces the maximum voltage stresses on D1 and D2 (D1 : 29.8 V, D2 : 38.8 V
without considering voltage ringing under experimental conditions) than the conventional PSFB
converter (D1 and D2 : 62 V). Therefore, the proposed converter can utilize low voltage and high current
rating diodes without bulky and lossy snubber circuit.
Energies 2020, 13, 863 12 of 17

Table 1. Components stresses comparison among the conventional and proposed converters.
Energies 2019, 12, x FOR PEER REVIEW 12 of 17
Stress Type PSFB ACF Proposed Converter
IO √ √
The DSP isRMS
used to implement the
currents output voltage control
Q1 –Q4 : I√O
and
Qmain : n the Q1 , Q4 : InOvariation.
D switching frequency D The
on switches n 2 Q : –
duty to output voltage transfer function of the proposed converter can be derived
aux Q 2 , Q : –
3 like a buck
converter Voltage
as follows:
stress 1
Qmain : 1−D VS Q1 , Q2 : VS
Q1 –Q4 :VS D
on switches V 1 Qaux : 1−D
1
VS Q3 , Q4 : 1−D VS
Gvd ( s ) = O ,
D Lm , fly CO 2 DL1m: , fly D VS D
D1 : n(1−D V (23)
Voltage stresses
D1 , D2 : 2V
s + n ( +
1−D1) ) S
n 2γ n 2γDRO: VS
S
n
on diodes
2 n D2 : VnS
where γ is 1 + Lm,fly/Lm,for.
Table 2. Price comparison of the primary switches among the conventional and proposed converters.
Table 3. Design Parameters.
Price List PSFB ACF Proposed Converter
Components Conventional PSFB Proposed Converter
Qmain :
Primary switch Q1, Q4 : IPW60R080
Q1 –Q4 : C3M0065090/9.375 Q1 , Q4 : IPW60R080/3.59
Part number IPW60R105, 4EA (600 V, 80 mΩ)
Primary Switch IPW60R105/3.37 Q aux : Q2 , Q3 : IPW60R190/1.74
/Price ($)
(600 V, 105 mΩ) C3M0120090/6.025
Q2, Q3 : IPW60R190
Total price of (600 V, 190 mΩ)
13.48 15.4 10.66
primary switches ($) STPS40170, 6 EA M80QZ12N, 2 EA
Secondary diode
(170 V, 40 A, VF = 0.79 V) (120 V, 160 A, VF = 0.78 V)
Clamp
4. Experimental capacitor
Results – PCPW225 MKP (630V, 1 uF)
Core: PQ4730 Core: PQ6640 custom
To prove the validity of the proposed converter, a 1.8 kW prototype shown in Figure 11a was
Transformer Lm = 140 uH, Llkg = 1.7 uH Lm,for = 50 uH, Lm,fly = 40 uH
built with the specification of VS = 200–310 V, VO = 13.6 V, fS = 125 kHz at 200 V input – 150 kHz at
Np : Ns = 10:1 Llkg = 5 uH, Np: Ns = 8: 1
310 V input. We also implemented a conventional PSFB converter. Table 3 summarizes the details of
Core: EER6028
two prototypes. In this
Output chapter, the commercialized PSFB converter was– designed for IONIQ HEV
inductor
LO = 1.7 uH, 5 turns
(made by HYUHNDAI motor company) and is used as the conventional converter to compare the
Output capacitor MLCC: 17 uF x 4 EA MLCC: 22 uF x 6 EA
performance of the proposed converter.

Tfor Tfly
n:1 n:1
Q1 Q3

iLlkgLlkg Lm,for Lm,fly Cc Co Ro

VS
Tint, n:1

D1 D2
Q2 Q4

Driver

PWM Digital ADC

Ramp Function
Comp Gate Mode
Change
Frequency
Modulation Gvc(z)
Iref[n]
Burst Mode vref[n]
TMS320F28069 MCU

(a) (b)

Figure 11. Prototype

Prototype and control block diagram of proposed
proposed converter.
converter. (a) Prototype.
Prototype. (b) Control
block diagram.

The loop gain (Tv(z)) of the proposed converter adopting the voltage compensator is illustrated
in Figure 12. The voltage compensator (Gvc(z)) was designed for minimum 360 Hz bandwidth and 45°
phase margin for the prototype of this paper.
 Energies 2020, 13, 863 13 of 17

Table 3. Design Parameters.

Components Conventional PSFB Proposed Converter

Q1 , Q4 : IPW60R080
IPW60R105, 4 EA (600 V, 80 mΩ)
Primary Switch
(600 V, 105 mΩ) Q2 , Q3 : IPW60R190
(600 V, 190 mΩ)
STPS40170, 6 EA M80QZ12N, 2 EA
Secondary diode
(170 V, 40 A, VF = 0.79 V) (120 V, 160 A, VF = 0.78 V)
Clamp capacitor – PCPW225 MKP (630 V, 1 uF)
Core: PQ4730 Core: PQ6640 custom
Transformer Lm = 140 uH, Llkg = 1.7 uH Lm,for = 50 uH, Lm,fly = 40 uH
Np : Ns = 10:1 Llkg = 5 uH, Np : Ns = 8: 1
Output inductor Core: EER6028LO = 1.7 uH, 5 turns –
Output capacitor MLCC: 17 uF × 4 EA MLCC: 22 uF × 6 EA

To regulate the output voltage, as shown in Figure 11b, the proposed converter used a DSP that is
TMS320F28069PZT with 90 MHz clock frequency and 12-bit analog to digital conversion module. The
DSP is used to implement the output voltage control and the switching frequency variation. The duty
to output voltage transfer function of the proposed converter can be derived like a buck converter
as follows:
V 1
Gvd (s) = O L , (23)
D m, f ly CO s2 + Lm, f ly + 1
n2 γ n2 γRO

where γ is 1 + Lm,fly /Lm,for .

The loop gain (Tv (z)) of the proposed converter adopting the voltage compensator is illustrated in
Figure 12. The voltage compensator (Gvc (z)) was designed for minimum 360 Hz bandwidth and 45◦
phase
Energies margin
2019, for PEER
12, x FOR the prototype
REVIEW of this paper. 13 of 17

Figure
Figure 12.12. Loop
Loop gainofofthe
gain theproposed
proposed converter
converter with
withvoltage
voltagecompensator.
compensator.

In addition, since the DSP is placed in the secondary side, the pulse transformer which can transfer
In addition, since the DSP is placed in the secondary side, the pulse transformer which can transfer
gate signals from the secondary side to the primary side is implemented. In addition, for measuring
gatethe
signals from the secondary side to the primary side is implemented. In addition, for measuring the
performance of the conventional and proposed converters, NFES2000S is used as an input power
performance of theDC
supply, Chroma conventional and63203
Electronic load proposed converters,
as an output NFES2000S
electronic is used as WT1600
load, YOKOGAWA an inputaspower
an
supply,
inputChroma DC Electronic
power analyzer, FLUKEload 63203 as
45A digital an outputfor
multi-meter electronic load,
the output YOKOGAWA
voltage and currentWT1600
measuring,as an
input power analyzer, FLUKE 45A digital multi-meter for the output
and Wave-runner 64xi TELEDYNE LECROY to capture the experimental waveforms. voltage and current measuring,
and Wave-runner 64xi TELEDYNE LECROY to capture the experimental waveforms.
Figure 13 shows the experimental waveforms of the proposed converter at the nominal input
voltage (VS = 270 V) and full-load condition with the 150 kHz switching frequency. As shown in Figure
13a, due to the ACF structure, there is no circulating current and only small commutation current
occurs during the switch transition. Moreover, voltage stresses on the primary switches of the
 Energies 2019, 12, x FOR PEER REVIEW 14 of 17
Energies 2020, 13, 863 14 of 17
Figure 17 shows the measured efficiency of the proposed and conventional PSFB converters. In
the minimum input voltage condition, the efficiency of the proposed converter is almost the same as
thatFigure
of PSFB 13converter
shows the experimental
because the PSFBwaveforms of the proposed
converter operates with a dutyconverter
ratio nearat0.5.
theMeanwhile,
nominal input
in
voltage (V
the nominal = 270 V) and full-load condition with the 150 kHz switching
S and maximum input voltage conditions, as previously analyzed, the proposed frequency. Asconverter
shown in
Figure
shows 13a, due to
higher the ACFover
efficiency structure,
the 30% there
loadisconditions
no circulating
duecurrent and onlycirculating
to the reduced small commutation current
and conduction
occurs during
loss of the Qthe switch
2 and transition.
Q3 switches. On Moreover, voltage
the other hand, stresses
because ofon thecore
large primary switches
loss and smallofmagnetizing
the proposed
converter is faroflower
inductances than 650 Vtransformer,
the integrated which is general breakdown
the efficiency voltage
of the of high-performance
proposed converter is similarSi-MOSFETs.
to that
Asofathe conventional
result, the primaryPSFBconduction
converter underloss light load
of the condition.
proposed However,
converter since
can be the importancereduced
considerably of the
high heavy
compared loadconventional
to the efficiency is PSFB
gradually increased,
converter. the proposed
Moreover, converter
the propose is attractive
converter forproduction
cuts the the LDC
converter
cost of theSi-MOSFETs
by utilizing vehicle applications. Moreover, transformer
and the integrated the proposedwithconverter
singleisand
a very promising
inside woundedconverter
primary
forsecondary
and other widewindings.
input and high output power applications due to its high efficiency and high power
density characteristics.

(a) (b)

Figure13.
Figure 13. Key
Key experimental
experimental waveforms
waveformsatat270
270V V
input andand
input 100% loadload
100% conditions (D = (D
conditions = 0.605).
0.605). (a)
(a)Primary
Primaryside
sidekey
keyexperimental waveforms.
experimental (b) (b)
waveforms. Secondary sideside
Secondary key key
experimental waveforms.
experimental waveforms.

Figures 14 and 15 present the key experimental waveforms at the minimum and maximum input
voltage conditions under the full load condition. As shown in Figure 14, in the minimum input voltage
condition (VS = 200 V), since the maximum switch voltage stresses are determined by the actual duty
ratio that is sum of the effective duty ratio and the duty loss during the commutation period, the
switching frequency varies from 150 kHz to 125 kHz at the minimum input voltage condition to reduce
the ratio of the commutation period in the total switching period. As a result, the voltage stresses on
the primary switches are well restricted near 400 V, and the secondary diode voltage stresses are under
100 V. Since the duty ratio (D) of the proposed converter can be designed to be over 0.5, the proposed
converter well regulates the output voltage at the minimum input voltage condition with D = 0.605.
Moreover, as can be seen (a)
in Figure 15, the voltage stresses on the switches (b)
and diodes are under 400 V
and 100 V in the maximum input voltage condition (VS = 310 V). Although the voltage stresses on the
Figure 14. Key experimental waveforms at 200 V input and 100% load conditions (D = 0.464). (a)
switches and diodes varies according to the input voltage conditions, all of them are well controlled
Primary side key experimental waveforms. (b) Secondary side key experimental waveforms.
and restricted to be suitable for high performance Si-MOSFET with low cost and low on-resistance.
Furthermore, the ZVS operation of the proposed converter is achieved even in the worst-case condition
such as the high input voltage and full-load conditions shown in Figure 16a. Figure 16b shows the
output voltage ripple of the proposed converter. The maximum output voltage ripple is under 500 mV
regardless of the input voltage and load conditions (500 mV is the output voltage ripple requirement of
LDC converter for vehicle applications). This verifies that the magnetizing inductances of the proposed
integrated transformer is adequately designed and chosen. Thus, despite the integrated transformer,
the proposed converter can effectively constrain the output current ripple.

(a) (b)

Figure 15. Key experimental waveforms at 310 V input and 100% load conditions (D = 0.412). (a)
Primary side key experimental waveforms. (b) Secondary side key experimental waveforms.
 (a) (b)
(a) (b)
Figure 13. Key experimental waveforms at 270 V input and 100% load conditions (D = 0.605). (a)
Figure
Energies 2020, 13.
13, Key experimental waveforms at 270 V input and 100% load conditions (D = 0.605). (a)15 of 17
863
Primary side key experimental waveforms. (b) Secondary side key experimental waveforms.
Primary side key experimental waveforms. (b) Secondary side key experimental waveforms.

(a) (b)
(a) (b)
Figure 14. Key experimental waveforms at 200 V input and 100% load conditions (D = 0.464). (a)
Figure 14.
Figure Keyexperimental
14. Key experimental waveforms
waveforms at at
200200 V input
V input andand 100%
100% loadload conditions
conditions = 0.464).
(D =(D0.464). (a)
Primary side key experimental waveforms. (b) Secondary side key experimental waveforms.
(a) Primary side key experimental waveforms. (b) Secondary side key experimental waveforms.
Primary side key experimental waveforms. (b) Secondary side key experimental waveforms.

(a) (b)
(a) (b)
Figure 15.15. Key
Keyexperimental
experimentalwaveforms
waveformsat at
310 VV
310 input and
input and100% load
100% conditions
load = 0.412).
(D =(D0.412).
conditions (a)
Figure
Energies 2019, 15. xKey
12, FOR experimental
PEER REVIEW waveforms at 310 V input and 100% load conditions (D = 0.412). (a)
Primary
(a) Primarysideside
keykey
experimental waveforms.
experimental (b) (b)
waveforms. Secondary sideside
Secondary keykey
experimental waveforms. 15 of 17
waveforms.
experimental
Primary side key experimental waveforms. (b) Secondary side key experimental waveforms.

(a) (b)

Figure
Figure 16.
16. ZVS
ZVSand
andoutput
outputvoltage
voltage ripple
ripple waveforms
waveforms at
at worst
worst case
case conditions.
conditions. (a)
(a) ZVS
ZVS waveforms
waveforms at
at
310
310 V
V input
input and
and 100%
100% load
load conditions.
conditions. (b)
(b)Output
Outputvoltage
voltageripple
ripplewaveforms
waveformsatat200
200VVinput
inputand
and100%
100%
load
load conditions.
conditions.

Figure 17 shows the measured efficiency of the proposed and conventional PSFB converters. In
93.0
93.0
the 92.5
minimum input voltage condition, the efficiency of92.5the proposed converter is almost the same as
92.0
92.0
that91.5
of PSFB converter because the PSFB converter operates 91.5
with a duty ratio near 0.5. Meanwhile, in
Efficiency [%]

Efficiency [%]

the 91.0
nominal and maximum input voltage conditions, as 91.0previously analyzed, the proposed converter
90.5
90.5
shows
90.0 higher efficiency over the 30% load conditions due to the reduced circulating and conduction
90.0
loss89.5
of the Q2 and Q3 switches. On the
Proposed other hand, because
200V 89.5 of large core loss and small magnetizing
Proposed 270V
89.0
89.0
inductances
88.5 of the integrated transformer,
PSFB 200V the efficiency
88.5
of the proposed converter is similar
PSFB 270V to that of
the 88.0
conventional
10 20 30
PSFB
40 50
converter
60 70 80
under light
90 100 110 120 130
load condition.
88.0 However, since the importance of the
10 20 30 40 50 60 70 80 90 100 110 120 130
high heavy load efficiency is gradually increased, the proposed converter is
Load [A]
Loadattractive
[A] for the LDC

(a) (b)
93.0
92.5
92.0
91.5
[%]
Energies 2020, 13, 863 16 of 17
(a) (b)

Figureof
converter 16.the
ZVS and output
vehicle voltage ripple
applications. waveforms
Moreover, at worst case
the proposed conditions.
converter (a) ZVS
is a very waveforms
promising at
converter
310 V input and 100% load conditions. (b) Output voltage ripple waveforms at 200 V input
for other wide input and high output power applications due to its high efficiency and high power and 100%
loadcharacteristics.
density conditions.

93.0
93.0
92.5
92.5
92.0
92.0
91.5
91.5
Efficiency [%]

Efficiency [%]
91.0
91.0
90.5
90.5
90.0
90.0
89.5
Proposed 200V 89.5
89.0 Proposed 270V
PSFB 200V 89.0
88.5 PSFB 270V
88.5
88.0
88.0
10 20 30 40 50 60 70 80 90 100 110 120 130
10 20 30 40 50 60 70 80 90 100 110 120 130
Load [A]
Load [A]

(a) (b)
93.0
92.5
92.0
91.5
Efficiency [%]

91.0
90.5
90.0
89.5
Proposed 310V
89.0
PSFB 310V
88.5
88.0
10 20 30 40 50 60 70 80 90 100 110 120 130
Load [A]

(c)

Figure17.
Figure 17.Measured
Measuredefficiency
efficiency according
according to to input
input voltage.
voltage. (a) (a) Minimum
Minimum input (VS =
input (V200
S = 200
V, DV,= 0.605).
D=
(b) Nominal input (VS = 270 V, D = 0.464). (c) Maximum input (VS = 310 V, D = 0.412).
0.605). (b) Nominal input (V S = 270 V, D = 0.464). (c) Maximum input (V S = 310 V, D = 0.412 ).

5. Conclusions
5. Conclusion
In this paper, a novel FBACFF converter with an integrated transformer sharing primary windings
is proposed
In this to achieve
paper, high efficiency
a novel FBACFF and high power
converter with density LDC converter
an integrated for vehicle
transformer sharing applications.
primary
windings is proposed to achieve high efficiency and high power density LDC converter forproposed
The operation principles and features are analyzed and illustrated, and the effectiveness of the vehicle
converter is verified
applications. by theprinciples
The operation experimental and results
featureswith 13.6 V and
are analyzed and1.8illustrated,
kW prototype. In the
and the proposed
effectiveness
converter,
of due toconverter
the proposed the full-bridge active-clamp
is verified structure, the results
by the experimental proposed converter
with can reduce
13.6 V and 1.8 kW the primary
prototype.
conduction
In loss converter,
the proposed by eliminating
due tothe circulating
the full-bridge current and utilize
active-clamp low cost
structure, theSi-MOSFETs by relieving
proposed converter can
burdenthe
reduce of the primary
primary voltage stress.
conduction In addition,
loss by eliminating thethe
proposed converter
circulating currentcanand
improve
utilizepower density
low cost Si-
through the integrated transformer with the shared and wounded inside windings.
MOSFETs by relieving burden of the primary voltage stress. In addition, the proposed converter can Furthermore, the
secondary
improve side structure
power can be simplified
density through and optimized.
the integrated transformer Based
withon these
the advantages,
shared the proposed
and wounded inside
converter can achieve not only high efficiency and high power density but also low
windings. Furthermore, the secondary side structure can be simplified and optimized. Based on these cost. Therefore, the
proposed converter is expected to be widely adopted for applications with wide
advantages, the proposed converter can achieve not only high efficiency and high power density but input voltage range
and low
also highcost.
output current such
Therefore, as the LDC
the proposed converterisfor
converter vehicleto
expected applications. The efficiency
be widely adopted and power
for applications
density of the proposed converter can be much improved with planar transformer and synchronous
rectification techniques.

Author Contributions: J.B. and H.-S.Y. were the main researchers who initiated and organized research reported
in the paper. All authors including H.-S.Y. were responsible for making the prototype of the proposed system and
carrying out the experiment. All authors have read and agreed to the published version of the manuscript.
Funding: This work was supported by Incheon National University (International Cooperative) Research Grant
in 2019.
Conflicts of Interest: The authors declare not conflict of interest.
Energies 2020, 13, 863 17 of 17

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