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Vlsi Design 2023-24

This document outlines the BTECH (SEM VII) Theory Examination for VLSI Design, scheduled for 2023-24, with a total of 100 marks and a duration of 3 hours. It includes three sections: Section A with brief questions, Section B with detailed problems, and Section C with options for in-depth discussion. The questions cover various topics related to VLSI design, including CMOS logic, power dissipation, and testing methodologies.

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86 views1 page

Vlsi Design 2023-24

This document outlines the BTECH (SEM VII) Theory Examination for VLSI Design, scheduled for 2023-24, with a total of 100 marks and a duration of 3 hours. It includes three sections: Section A with brief questions, Section B with detailed problems, and Section C with options for in-depth discussion. The questions cover various topics related to VLSI design, including CMOS logic, power dissipation, and testing methodologies.

Uploaded by

bgmrohan043
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Subject Code: KEC072


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BTECH
(SEM VII) THEORY EXAMINATION 2023-24
VLSI DESIGN
TIME: 3 HRS M.MARKS: 100

Note: 1. Attempt all Sections. If require any missing data; then choose suitably.
SECTION A

1. Attempt all questions in brief.


Q no. Question Marks CO
a. Why we need a low power VLSI circuit in today's scenario? 2 1
b. Define LSI, MSI, VLSI, and ULSI on number of transistor basis. 2 1
c. What is parasitic delay? 2 2
d. Define logical effort with example. 2 2
e. Differentiate between static power and dynamic power. 2 3
f. What are the problems in single-phase clocking? 2 3
g. Distinguish between SRAM and DRAM. 2 4
h. Enlist the advantages of using address multiplexing scheme in DRAM cell. 2 4
i. Explain the term controllability 2 5
j. Define the terms- Defects, Errors 2 5
SECTION B
64

51
2. Attempt any three of the following:
_1

0.
a. Implement the CMOS logic for the following Boolean expression: (i) Y= (A+B+C).D 10 1
P1

.3
(ii) Y= (A+B+C)(D+E).F (iii) 3 input NOR gate

20
b. Explain the Elmore Delay Model with suitable diagram. 10 2
4D

c. Enlist the advantages of dynamic logic circuit over static logic circuit. Explain NORA 10 3

.1
CMOS logic circuit with suitable example
P2

03
d. Explain the various types of power dissipation in CMOS circuits. 10 4
Q

|1

e. What are the different scan based techniques explain built in self-test technique. 10 5
SECTION C
51

3. Attempt any one part of the following:


2:

a. What is need of VLSI Testing? Discuss about Functional and manufacturing tests. 10 1
:2

b. What are various processes of CMOS fabrication? Explain Twin tub processes with 10 1
13

suitable sketch
4. Attempt any one part of the following:
4
02

a. Draw and explain the working of Lumped RC-model for interconnects 10 2


b. Write short note on: (i) Logical Effort (ii) Parasitic Delay 10 2
-2

5. Attempt any one part of the following:


01

a. Explain CMOS Domino circuit along with its features. How it can be cascaded in VLSI 10 3
7-

circuits.
b. Explain the term Voltage Boot Strapping in CMOS logic with suitable examples. 10 3
|2

6. Attempt any one part of the following:


a. Write short note on DRAM cell. Explain leakage and refresh operation in DRAM cells 10 4
b. Draw the circuit diagram of SRAM and explain read and write operation. 10 4
7. Attempt any one part of the following:
a. Explain the following: (i) Ad Hoc testable design techniques. (ii) Fault types and 10 5
models.
b. Explain Adiabatic Logic Circuits 10 5

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QP24DP1_164 | 27-01-2024 13:22:51 | 103.120.30.51

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