Letters

https://doi.org/10.1038/s41565-017-0010-1

Steep-slope hysteresis-free negative capacitance

MoS2 transistors
Mengwei Si1,2, Chun-Jung Su3, Chunsheng Jiang1,4, Nathan J. Conrad1,2, Hong Zhou1,2, Kerry D. Maize1,2,
Gang Qiu1,2, Chien-Ting Wu3, Ali Shakouri1,2, Muhammad A. Alam1 and Peide D. Ye1,2*

The so-called Boltzmann tyranny defines the fundamen- simultaneous fulfilment of internal gain and the non-hysteretic con-
tal thermionic limit of the subthreshold slope of a metal– dition is crucial to the proper design of capacitance matching in a
oxide–semiconductor field-effect transistor (MOSFET) at stable NC-FET. Meanwhile, channel transport in NC-FETs remains
60 mV dec−1 at room temperature and therefore precludes low- unperturbed. Therefore, coupled with the flatness of the body
ering of the supply voltage and overall power consumption1,2. capacitance of TMD materials and symmetrical operation around
Adding a ferroelectric negative capacitor to the gate stack of a the zero-charge point in a JL transistor, performance in 2D JL-NC-
MOSFET may offer a promising solution to bypassing this fun- FETs is expected to improve for both on and off states. Accordingly,
damental barrier3. Meanwhile, two-dimensional semiconduc- it would be highly desirable to integrate a ferroelectric insula-
tors such as atomically thin transition-metal dichalcogenides, tor and 2D ultrathin channel materials to create a 2D JL-NC-FET
due to their low dielectric constant and ease of integration to achieve high on-state performance for high operating speed and
into a junctionless transistor topology, offer enhanced elec- sub-thermionic SS for low power dissipation.
trostatic control of the channel4–12. Here, we combine these
two advantages and demonstrate a molybdenum disulfide
(MoS2) two-dimensional steep-slope transistor with a ferro-
electric hafnium zirconium oxide layer in the gate dielectric a MoS2
stack. This device exhibits excellent performance in both on
and off states, with a maximum drain current of 510 μ​A μ​m−1
Al2O3
and a sub-thermionic subthreshold slope, and is essentially
hysteresis-free. Negative differential resistance was observed Hf0.5Zr0.5O2
at room temperature in the MoS2 negative-capacitance FETs
as the result of negative capacitance due to the negative Si
drain-induced barrier lowering. A high on-current-induced
self-heating effect was also observed and studied.
Transition-metal dichalcogenides (TMDs) have been extensively b c MoS2 10 nm
explored as two-dimensional (2D) semiconductors for future device Al2O3
technologies. Atomically thin MoS2 has been widely studied as a MoS2 Hf0.5Zr0.5O2
highly promising channel material because it offers ideal electro- Si
static control of the channel, ambient stability, an appropriate direct
Hf Zr Al
bandgap and moderate mobility. The TMD is generally configured Al2O3
in a junctionless (JL) form, with metal–semiconductor contacts
replacing the source–drain p–n junctions of a bulk transistor. JL
MoS2 field-effect transistors (FETs) exhibit high on/off ratios and O Mo S
strong immunity to short channel effects for transistor applications
with channel length Lch down to sub-5 nm (refs. 4–12). However, the 2 nm Hf0.5Zr0.5O2
power dissipation issue remains unresolved, similar to the situa-
tion for silicon-based metal–oxide–semiconductor FET (MOSFET)
scaling. To overcome the thermionic limit, several novel device con- Fig. 1 | Schematic and fabrication of MoS2 NC-FETs. a, Schematic view
cepts have been proposed that have potential subthreshold slopes of a MoS2 NC-FET. The gate stack includes heavily doped Si as the gate
(SS) less than 60 mV dec−1 at room temperature, including impact- electrode, 20 nm HZO as the ferroelectric capacitor, 2 nm Al2O3 as
ionization FETs (II-FET)13, tunnelling FETs (T-FET)14,15, nanoelec- the capping layer and capacitance-matching layer. A 100 nm Ni layer
tromechanical FETs (NEMFET)16 and negative-capacitance (NC) was deposited using an electron-beam evaporator as the source–drain
FETs17–28. In a NC-FET, the insulating ferroelectric layer serves as electrode. b, Cross-sectional view of a representative sample showing
a negative capacitor so that the channel surface potential can be the bilayer MoS2 channel, amorphous Al2O3 and polycrystalline HZO gate
amplified more than the gate voltage, and hence the device can dielectric. c, Corresponding EDS elemental map showing the distribution of
operate with SS less than 60 mV dec−1 at room temperature3. The Hf, Zr, Al, O, Mo and S.

School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN 47907, USA. 2Birck Nanotechnology Center, Purdue University,
1

West Lafayette, IN 47907, USA. 3National Nano Device Laboratories, Hsinchu 300, Taiwan. 4Tsinghua National Laboratory for Information Science and
Technology, Institute of Microelectronics, Tsinghua University, Beijing 100084, China. *e-mail: yep@purdue.edu

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Here, we demonstrate steep-slope MoS2 NC-FETs by introduc- performance is sustained despite significant self-heating in the tran-
ing ferroelectric hafnium zirconium oxide (HZO) into the gate sistors, in contrast to traditional bulk MOSFETs.
stack. These transistors exhibit essentially hysteresis-free switching The MoS2 NC-FET shown in Fig. 1a consists of a monolayer to a
characteristics with a maximum drain current of 510 μ​A μ​m−1 and dozen layers of MoS2 as the channel, a 2 nm amorphous aluminium
sub-thermionic SS. The maximum drain current of the NC-FETs oxide (Al2O3) layer and a 20 nm polycrystalline HZO layer as the gate
fabricated in this work was found to be around five times larger dielectric, heavily doped silicon substrate as the gate electrode and
than in MoS2 FETs fabricated on 90 nm SiO2 using the same process. nickel source–drain contacts. HZO was chosen for its ferroelectricity,
As will be discussed in the following, this is a direct consequence its CMOS-compatible manufacturing, and the ability to scale down
of on-state current enhancement in a JL-NC-FET. Negative differ- its equivalent oxide thickness (EOT) to ultrathin dimensions23–28.
ential resistance (NDR), correlated to the negative drain-induced The amorphous Al2O3 layer was applied for capacitance match-
barrier lowering (DIBL) at the off state, is observed because of the ing and gate leakage current reduction through the polycrystalline
drain-coupled negative capacitance effect. Remarkably, the high HZO. A cross-sectional transmission electron microscopy (TEM)

a b 140

10 –6 120

100

SS (mV dec–1)
10–8
ID (A μm–1)

80
–10
10 60
NC forward
VDS=0.1 V 40 NC reverse
10–12 20 nm Al2O3
VDS=0.9 V 20
NC simulation
–14
10 0
–1.5 –1.0 –0.5 0.0 0.5 1.0 10–13 10 –12 –11
10 –10
10 10–9 10–8 10–7
VGS (V) –1
ID (A μm )

c d
140
10–6
VDS=0.1 V 120
–8 100
10
SS (mV dec–1)
ID (A μm–1)

80
10–10
60
Slow 40
10–12 Min #1
Medium
20
Fast Min #2
10–14 0
–1.5 –1.0 –0.5 0.0 0.5 1.0 10–14 10 –12
10–10 10–8 10–6
VGS (V) –1
ID (A μm )

e 100 f
80
Forward Forward
2.3 kB T/q
80 Reverse min #1 Reverse min #1
Reverse min #2 60 Reverse min #2
SS (mV dec–1)

SS (mV dec–1)

60
40
40

20
20

0 0
1 2 3 4 5 160 180 200 220 240 260 280
No. of layers Temperature (K)

Fig. 2 | Off-state switching characteristics of MoS2 NC-FETs. a, ID–VGS characteristics measured at room temperature and at VDS =​0.1 V and 0.9 V. VGS
step is 0.5 mV. The thickness of the MoS2 flake is 8.6 nm, measured by AFM. The device has a channel length of 2 μ​m and channel width of 3.2 μ​m, and
RTA was performed at 500 °C during substrate preparation. b, SS versus ID characteristics of the device in a, showing minimum SS below 60 mV dec−1 for
both forward and reverse sweeps. Also shown is a comparison of SS versus ID characteristics with simulation results on the same device structure and an
experimental MoS2 FET with 20 nm Al2O3 only as gate oxide. c, ID–VGS characteristics measured at room temperature and at VDS =​0.1 V at different gate
voltage sweep speeds. VGS steps were set to be from 0.3 to 5 mV. The thickness of the MoS2 flake is 5.1 nm. This device has a channel length of 1 μ​m and
channel width of 1.56 μ​m. The RTA temperature was 400 °C for the gate dielectric. d, SS versus ID characteristics during fast reverse sweep of the device
in c. The SS versus ID characteristics show two local minima (min #1 and min #2). min #2 suggests switching between different polarization states of
the ferroelectric HZO. e, Layer dependence of SS for one to five layers. The SS of the MoS2 NC-FETs shows weak thickness dependence. f, Temperature
dependence of SS from 160 K to 280 K. The measured SS is below the thermionic limit down to 220 K. SS below 190 K is above the thermionic limit
because of the stronger impact of the Schottky barrier on SS.

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Nature Nanotechnology Letters
image of a representative MoS2 NC-FET is shown in Fig. 1b, and simulation results and experimental results with only 20 nm Al2O3
a detailed energy-dispersive X-ray spectrometry (EDS) elemen- as the gate dielectric. MoS2 FETs fabricated on a 20 nm Al2O3 con-
tal map is presented in Fig. 1c. The EDS analysis confirmed the ventional dielectric present a typical SS of 80–90 mV dec−1, much
presence and uniform distribution of elements Hf, Zr, Al, O, Mo larger than the values for NC-FETs. The SS was extracted for both
and S. No obvious interdiffusion of Hf, Zr and Al was found. forward sweep (SSFor) and reverse sweep (SSRev), and the device was
The gate stack was assessed for its rapid thermal annealing (RTA) observed to exhibit SSRev =​ 52.3 mV dec−1 and SSFor =​ 57.6 mV dec−1.
temperature dependence with a metal–oxide–semiconductor capac- SS values below 60 mV dec−1 at room temperature are thus conclu-
itor structure by carrying out fast I–V measurements. Measured sively demonstrated for both forward and reverse sweeps in this
hysteresis loops for polarization versus electric field (P–E) as well near hysteresis-free device.
as X-ray diffraction (XRD) results suggest that RTA at 400–500 °C Because the HZO polarization depends on the sweep rate, elec-
after atomic layer deposition (ALD) enhances the ferroelectricity trical characterization of the MoS2 NC-FETs was also carried out
(Supplementary Section 1). at different VGS sweep speeds. This speed was controlled by modi-
The electrical characteristics of MoS2 NC-FETs are strongly fying the VGS measurement step from 0.3 mV to 5 mV. Figure 2c
dependent on the ferroelectricity of the HZO layer, which is defined presents ID–VGS characteristics for a few-layer MoS2 NC-FET mea-
by the film annealing temperature and gate–source voltage (VGS) sured at slow, medium and fast sweep speeds, corresponding to
sweep speed. In addition to standard I–V measurements, hyster- VGS steps of 0.3, 1 and 5 mV. Hysteresis of the MoS2 NC-FETs was
esis was measured as the difference in VGS in forward (from low to found to be diminished by reducing the sweep speed. A plateau and
high) and reverse (from high to low) VGS sweeps at ID =​ 1 nA μ​m−1 a minimum characterize the SS vs ID plot during the reverse sweep.
and VDS =​ 0.1 V. Here, we study the room-temperature charac- These features (SSRev,min#1 and SS Rev,min#2) were observed in almost
teristics of MoS2 NC-FETs. Figure 2a presents the ID–VGS char- all the fabricated devices when measured with fast sweep VGS, as
acteristics of a device with the gate dielectric annealed at 500 °C, shown in Fig. 2d. The second local minimum of SS is the result of
measured in VGS steps of 0.5 mV. This device has a channel length switching between two polarization states of the ferroelectric oxide,
of 2 μ​m, channel width of 3.2 μ​m and channel thickness of 8.6 nm. which is associated with loss of capacitance matching at high speed.
The hysteresis (~12 mV) is small and essentially negligible, consistent When measured in fast sweep mode with a VGS step of 5 mV, the
with theory for the NC-FET, and the gate leakage current IG is neg- device exhibits SSFor =​ 59.6 mV dec−1, SSRev,min#1 =​ 41.7 mV dec−1
ligible (Supplementary Section 2). Figure 2b presents SS vs ID data and SSRev,min#2 =​ 5.6 mV dec−1. Overall, the average SS is less than
for the device examined in Fig. 2a, as well as a comparison of the 60 mV dec−1 for over four decades of drain current. In slow sweep

a b
VDS=0.1 V
0.020
10–5 VDS=0.5 V

0.015
ID (μA μm–1)

10–7
ID (A μm–1)

10–9
ID (A μm–1)

10–9 0.010
10–10

10–11 0.005
-0.8 -0.7
VGS (V)

10–13 0.000
–1.0 –0.5 0.0 0.5 1.0 0.0 0.2 0.4 0.6 0.8 1.0
VGS (V) VDS (V )
c d
Negative DIBL

–0.50
Low VDS VGS from –0.65 V to –0.55 V
EC in 0.025 V steps
–0.55
High VDS
Vmos (V)

VDS
–0.60

Ni Ni Vmos –0.65
VGS Al2O3 Cfr
–0.70
HZO 0.0 0.2 0.4 0.6 0.8 1.0
Si VDS (V )

Fig. 3 | NDR and negative DIBL in MoS2 NC-FETs. a, ID–VGS characteristics measured at room temperature and at VDS =​0.1 V and 0.5 V. The VGS step during
measurement was 5 mV. Inset: Zoom-in of the ID–VGS curve between −​0.8 and −​0.7 V. A threshold voltage shift towards the positive can be observed at
high VDS, indicating a negative DIBL effect. The thickness of the MoS2 flake is 5.3 nm, estimated from AFM characterization. This device has a channel
length of 2 μ​m and channel width 5.6 μ​m. A 500 °C RTA procedure in N2 was performed for 1 min during preparation of the gate dielectric. b, ID–VDS
characteristics measured at room temperature at VGS from −​0.65 to −​0.55 V in 0.025 V steps. Clear NDR can be observed because of the negative DIBL
effect induced by negative capacitance. c, Band diagram of the negative DIBL effect. The negative DIBL origins from capacitance coupling from the drain
to the interfacial layer between Al2O3 and HZO. d, Simulation of interfacial potential vs VDS. When VDS is increased, the interfacial potential is reduced, and
the carrier density in the MoS2 channel is reduced. Thus, the channel resistance is increased and drain current is reduced.

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Letters Nature Nanotechnology

a 600 b and devices with RTA at 400 °C and 600 °C. Therefore, RTA tem-
VGSfrom –1 to 9 V in 0.5 V steps
500 L = 100 nm
400 VGS = 9 V perature engineering could be useful in achieving both steep slope
400
ch
300
and low hysteresis.

gD (µS µm–1)
ID (µA µm–1)

DIBL is widely noted as major evidence for short-channel

300 200
NDR effects in MOSFETs2. In conventional MOSFETs, the threshold
200
100 voltage Vth shifts in the negative direction, relative to the drain
100
0
voltage. The DIBL, defined as −​Δ​Vth/Δ​VDS, is usually positive.
0
It has been predicted theoretically that with a ferroelectric insu-
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
lator introduced into the gate stack of a practical transistor, the
VDS (V) VDS (V)
DIBL could be reversed in NC-FETs29. NDR can occur naturally
c Source as a result of the negative DIBL effect. Figure 3a shows negative
Channel
DIBL in the ID–VGS characteristics of another device with a chan-
nel length of 2 μ​m, channel width of 5.6 μ​m, channel thickness of
7.1 nm, and with 2 nm Al2O3 and 20 nm HZO as the gate dielec-
Drain tric. It is evident that the ID–VGS curve shifts positively when VDS
d
increases from 0.1 to 0.5 V. As this negative DIBL occurs around
the off state, NDR is also observed simultaneously in the same
ΔT = 16 K device in the off state, as shown in Fig. 3b. Figure 3c presents the
D S D S D S
band diagram for the negative DIBL effect. This negative DIBL
C C C originates from capacitance coupling from the drain to the inter-
0.6 W mm–1 1.2 W mm–1 1.8 W mm–1
facial layer between Al2O3 and HZO. The interfacial layer potential
ΔT = 0 K
Vmos can be estimated as a constant when the thickness of the ferro-
electric oxide layer is thin (Supplementary Section 7). Simulation
Fig. 4 | On-state characteristics and self-heating of MoS2 NC-FETs.
of Vmos shows that, when VDS is increased, the interfacial poten-
a, ID–VDS characteristics measured at room temperature at VGS from −​1 V
tial is reduced (Fig. 3d), indicating that the carrier density in the
to 9 V in 0.5 V steps. The thickness of the MoS2 flake is 3 nm. This device
MoS2 channel is reduced. Thus, the channel resistance is increased,
has a channel length of 100 nm. The maximum stress voltage/EOT in this
leading to the NDR effect.
device is about 2 V nm−1. Maximum drain current is 510 μ​A μ​m−1. Clear
The EOT of the gate stack (2 nm Al2O3 and 20 nm HZO) in this
negative drain differential resistance can be observed at high VGS. b, gD–VDS
work was measured to be 4.4 nm by C–V measurements. The break-
characteristics for the device in a at VGS =​ 9 V. gD less than zero at high
down voltage was consistently measured to be ~11 V. Breakdown
VDS highlights the NDR effect due to self-heating. c,d, Thermoreflectance
voltage/EOT was 2.5 V nm−1, which is about 2.5 times larger than the
images (c) and temperature maps (d) at power densities from 0.6 W mm−1
value for SiO2. It can be verified easily that breakdown voltage/EOT
to 1.8 W mm−1. The heated channel suggests that the self-heating effect has
is proportional to the electric displacement field. As it is well known
to be taken into account in MoS2 NC-FETs with large drain current.
from Maxwell’s equations that the electric displacement field is pro-
portional to charge density, higher breakdown voltage/EOT could
mode, no obvious second local minimum and hysteresis can be lead to a higher carrier density. Figure 4a presents the ID–VDS char-
observed, as shown in Fig. 2a, reflecting well-matched capacitances acteristics (measured at room temperature) of a MoS2 NC-FET with
throughout the subthreshold region. Figure 2e shows the thickness 100 nm channel length. The thickness of the MoS2 flake is 3 nm. The
dependence of SS from a monolayer to five layers of MoS2 for the gate voltage was stressed up to 9 V and the maximum gate voltage/
channel (see Supplementary Section 4 for determination of layer EOT in the device was ~2 V nm−1. A maximum drain current of
number). No obvious thickness dependence is observed. Figure 2f 510 μ​A μ​m−1 was achieved, which is about five times larger than in
shows the temperature dependence of SS for a MoS2 NC-FET control devices using 90 nm SiO2 as the gate dielectric. Note that
measured from 280 K to 160 K. The measured SS is below the therm- this maximum drain current was obtained without special contact
ionic limit down to 220 K. SS below 190 K is above the thermionic engineering such as doping11 or using a heterostructure contact
limit because of the stronger impact of the Schottky barrier at lower stack10; indeed, as discussed in the Supplementary Section 7, the
temperatures. Detailed I–V characteristics at low temperature are JL topology is key to improving the performance of the transistor.
provided in Supplementary Section 5. This is an important but unexplored advantage of using a ferroelec-
Although the above MoS2 NC-FET shows an average SS during tric gate stack to enhance on-state performance. Another type of
reverse sweep of <​60 mV dec−1 for more than four decades, low NDR (Fig. 4b) is also clearly observed when the device is biased at
hysteresis is generally required for any transistor application. A high VGS because of the self-heating effect from large drain current
detailed discussion of the non-hysteretic and internal gain condi- and voltage. Figure 4c presents thermo-reflectance images taken at
tions of the MoS2 NC-FET is provided in Supplementary Section 7 power densities from 0.6 W mm−1 to 1.8 W mm−1. The heated chan-
using experimentally measured P–E results taken directly on HZO nel, with its temperature increased to ~40 °C, suggests the self-heat-
films. We found that both SS and hysteresis in MoS2 NC-FETs ing effect. This potentially degrades channel mobility and limits the
are sensitive to the annealing temperature for the gate dielectric. maximum drain current, and thus has to be taken into account in
The dependence of SS on different RTA temperatures was stud- MoS2 NC-FETs.
ied systematically (Supplementary Section 3), and it was found In conclusion, we have successfully demonstrated MoS2 2D
that MoS2 NC-FETs with RTA at 400 °C and 500 °C have smaller NC-FETs with promising on- and off-state characteristics. The
SS values than as-grown samples and 600 °C annealed samples, stable, non-hysteretic and bidirectional sub-thermionic switching
as shown in Supplementary Fig. 4. This conclusion can also be characteristics have been unambiguously confirmed to be the result
obtained from the hysteresis loop of plots of P–E, because the gate of a NC effect. On-state performance is enhanced, with a maximum
stacks with RTA at 400 °C and 500 °C show larger remnant polar- drain current of 510 μ​A μ​m−1 at room temperature, which leads to
ization, indicating stronger ferroelectricity. A statistical study on the self-heating effect. Finally, we have shown that the observed
temperature-dependent hysteresis is provided in Supplementary NDR is induced by the negative DIBL effect. After submission and
Fig. 4d. It was found that MoS2 NC-FETs with 500 °C RTA exhibit during revision of this manuscript, the authors became aware of a
the lowest hysteresis when compared with devices without RTA related work being published30.

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Nature Nanotechnology Letters
Methods 21. McGuire, F. A., Cheng, Z., Price, K. & Franklin, A. D. Sub-60 mV/decade
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Methods MoS2 flakes were transferred to the substrate by scotch tape-based mechanical
ALD deposition. Hf1−xZrxO2 film was deposited on a heavily doped silicon exfoliation. Electrical contacts formed from a 100 nm nickel electrode were
substrate. Before deposition, the substrate was cleaned by RCA standard cleaning fabricated using electron-beam lithography, electron-beam evaporation and a
and a diluted HF dip to remove organic and metallic contaminants, particles and lift-off process.
unintentional oxides, followed by a deionized water rinse and drying. The substrate
was then transferred to an ALD chamber to deposit Hf1−xZrxO2 film at 250 °C, using Device characterization. The thickness of the MoS2 was measured using a
[(CH3)2N]4Hf (TDMAHf), [(CH3)2N]4Zr (TDMAZr) and H2O as the Hf precursor, Veeco Dimension 3100 atomic force microscope (AFM) system. Electrical
Zr precursor and oxygen source, respectively. The Hf1−xZrxO2 film (x =​  0.5) was (d.c.) characterization was carried out with a Keysight B1500 system. Fast I–V
achieved by controlling the HfO2:ZrO2 cycle ratio of 1:1. To encapsulate the measurements were performed using a Keysight B1530A fast measurement unit,
Hf1−xZrxO2 film, an Al2O3 layer was in situ deposited using Al(CH3)3 (TMA) and and C–V measurements with an Agilent E4980A LCR meter. Room-temperature
H2O, also at 250 °C. electrical data were collected with a Cascade Summit probe station and low-
temperature electrical data were collected with a Lakeshore TTP4 probe station.
Device fabrication. A 20 nm Hf0.5Zr0.5O2 layer was deposited by ALD as a Thermoreflectance imaging was done with a Microsanj thermoreflectance image
ferroelectric insulator layer on the heavily doped silicon substrate after standard analyser. Raman and photoluminescence measurements were carried out on a
surface cleaning. Another 10 nm aluminium oxide layer was deposited as an HORIBA LabRAM HR800 Raman spectrometer.
encapsulation layer to prevent the degradation of HZO by reaction with moisture
in the air. A BCl3/Ar dry etching process was carried out to adjust the thickness of
the Al2O3 down to 2 nm for capacitance matching. The rapid thermal annealing Data availability. The data that support the findings of the study are available from
process was then performed in nitrogen ambient for 1 min at various temperatures. the corresponding author upon reasonable request.

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