A Novel Glitch-Free Integrated Clock Gating Cell

for High Reliability

Tasnuva Noor and Emre Salman

Department of Electrical and Computer Engineering
Stony Brook University (SUNY), Stony Brook, New York 11794
Email: emre.salman@stonybrook.edu

Abstract—A novel glitch-free integrated clock gating (ICG)

cell is developed and demonstrated in 45 nm CMOS technology.
The proposed cell is more reliable as it produces an uninterrupted
gated clock signal in cases where glitches occur in the enable
signal during clock transitions. A detailed comparison of the
proposed cell with the existing integrated clock gating cells is also
presented. Glitch-free operation (and therefore high reliability) is
achieved at the expense of larger power and delay, as quantified
for 45 nm CMOS technology. The proposed ICG cell is shown
to be highly applicable to dual edge triggered flip-flops where
existing ICGs fail if there are glitches in the enable signal during
clock transitions.

I. I NTRODUCTION
In modern system-on-chip (SoC) design, power consump-
tion has become a major issue due to both battery life and
Fig. 1. Generic clock tree with ICG cells in front of registers.
thermal integrity. Although static power is of great significance
in the design of nanoscale CMOS circuits, managing dynamic ICG cells further up the clock tree have reduced the dynamic
power consumption is currently the most effective strategy for power consumption to a greater extent [13].
power reduction, particularly for nanoscale FinFET technolo-
gies where leakage power has been significantly reduced [1], The existing ICG cells designed for single edge triggered
[2]. flip-flops are compact and effective. However, these existing
ICGs are not entirely reliable if the enable signal exhibits
There are various techniques to reduce dynamic power glitches during clock transitions. In this paper, a new design is
consumption such as reducing the operating frequency, voltage proposed to obtain a glitch-free ICG cell for high reliability.
swing or the capacitive load of the clock distribution network
[3]–[9]. Power consumption can be further reduced by intro- The enable signal, produced from a combinational circuit,
ducing techniques to reduce the supply voltage although it can can be prone to glitches at any point in time. Thus, the pro-
be challenging due to the difficulty in scaling the threshold posed ICG cell is simulated with an enable signal that exhibits
voltage [10]. Each of these techniques exhibits different trade- glitches at different times. In this paper, it is demonstrated that,
offs with performance and reliability. Alternatively, reducing irrespective of the occurrence time of the glitch, the proposed
the activity factor of the clock signal by ensuring that it ICG cell generates a glitch-free gated clock signal, thereby
does not switch when not needed can significantly reduce enhancing the overall reliability of the circuit.
the dynamic power consumption without affecting the supply
voltage or the frequency. II. BACKGROUND
Clock gating refers to shutting off the clock signal when A. Existing Integrated Clock Gating Cells
the flip-flops are idle. It has been successfully used in custom
ASICs, microprocessors, and FPGAs [11]. The most primitive The particular clock gating strategy that would be imple-
way to achieve clock gating is to include an enable signal mented in a circuit is decided during the synthesis stage and
and gate the clock signal by using an AND or a NOR gate, depends primarily on the specific design characteristics such
depending on the type of flip-flops used. The output of this as the number of registers that use the clock signal, choice of
gate is referred to as a gated clock, which does not switch symmetrical cells and the threshold voltage of the ICG cells
when the enable signal is active [12]. The enable signal is [14]. There are multiple available ICG cell topologies [15],
achieved internally or externally from a combinational circuit [16]. Among these cells, the two most commonly used are the
depending on the approach used. latch-based ICG cells. Latch based ICG cells are improved
versions of the previous approaches that use only an AND
A typical method of inserting ICG cells throughout the or NOR gate. The outputs of the flip-flops driven by these
clock tree is shown in Fig. 1. Although ICG cells were initially ICG cells have one clock cycle delay added to the propagation
added adjacent to the registers, alternative approaches to insert time due to the latch insertion [17]. These designs, however,

978-1-7281-0397-6/19/$31.00 ©2019 IEEE

are preferred as they reduce the possibility of a hazard in the 1

gated clock signal (GClk) that can occur due to the transition

Clock (V)
0.5
time difference between enable (En) and clock signal (Clk).
0
1) Latch-AND based ICG: A latch-AND ICG cell consists 0 1 2 3 4
Time (ns)
5 6 7 8
×10 -9
of an active low latch followed by an AND gate, and is 1

Enable (V)
primarily used to drive positive edge triggered flip-flops. The 0.5
latch is added to eliminate any hazard in the En signal which
otherwise could propagate to the GClk. 0
0 1 2 3 4 5 6 7 8
Time (ns) ×10 -9
1

Gated Clock (V)

0.5

0
0 1 2 3 4 5 6 7 8
Time (ns) ×10 -9

Fig. 4. Gated clock from latch-AND based ICG cell when En has glitches.

Fig. 2. Latch-AND based ICG cell for positive edge triggered flip-flops.
flip-flops where glitches are not expected to occur during
Using the active low latch helps to synchronize the GClk the rising transition of the clock. However, for a negative or
and prevents the propagation of any glitches that occur in the dual edge triggered flip-flop based design, using this ICG cell
En signal. A NAND gate can be used instead of the AND to degrades reliability due to the faulty GClk signal.
achieve a gated high ICG cell, if needed.
2) Latch-NOR based ICG: A latch-NOR ICG cell performs 1

similar to the latch-AND based ICG cell with the exception

Clock (V)
0.5
that this latch is active high and there is a NOR gate instead
of an AND at the output stage, as depicted in Fig. 3. 0
0 1 2 3 4 5 6 7 8
Time (ns) ×10 -9
Enable (V) 1

0.5

0
0 1 2 3 4 5 6 7 8
Time (ns) ×10 -9
1
Gated Clock (V)

0.5

Fig. 3. Latcth-NOR ICG cell for negative edge triggered flip-flops. 0

0 1 2 3 4 5 6 7 8
Time (ns) ×10 -9

This ICG cell topology is primarily used for circuits having

Fig. 5. Gated clock from latch-NOR based ICG cell when En has glitches.
negative edge triggered flip-flops. The latch eliminates the
propagation of any hazard in the En to the GClk signal. Also
As shown in Fig. 5 (where latch-NOR based ICG cell is
note that this ICG changes the polarity of the global clock
used), the GClk misses one clock cycle if there is a glitch in
signal.
the En signal during the falling transition of the global clock.
Thus, a latch-NOR based ICG cell can be effectively used to
III. P ROPOSED A PPROACH drive negative edge triggered flip-fops, where glitches are not
A. Limitations of Existing Topologies expected to occur during the falling transition of the clock.
An ICG cell is used in the clock tree to achieve lower As seen from the figures, the ICG cells currently used for
power consumption by controlling the clock (Clk) signal. It single edge triggered flip-flops cannot be fully reliable as En
incorporates an enable (En) signal that controls the clock signal can exhibit glitches during both the rising and falling
operation. As a result, a new gated clock (GClk) signal is transitions of the clock signal. This phenomenon is particularly
achieved which does not switch when En is inactive. The En true for dual edge triggered flip-flops that latch data at both
signal is generated from a combinational circuit and can have clock edges. Thus, it is critical to have an uninterrupted GClk
glitches at arbitrary points in time. when the En is high, but exhibit glitches.
In Figs. 4 and 5, the En is considered to have glitches
B. Proposed Topology
at four different time instances: when Clk is high, when
Clk is low and during both the high-to-low and low-to-high The proposed ICG cell is shown in Fig. 6. The gated clock
transitions of the Clk signal. Note that a latch-AND based ICG signals at the output of an active low latch-NAND ICG (A)
is used in Fig. 4 whereas a latch-NOR based ICG is used in and an active high latch-NOR ICG (B) cells are selected by a
Fig. 5. As shown in Fig. 4, if there is a glitch in the En during MUX. The select signal of the MUX is the AND-ed output of
the rising transition of the global clock, that particular clock the Clk and the En signals, so that the final GClk is sensitive
cycle does not propagate to the GClk. This issue makes a latch- to the state of En. The result is an inverted GClk, which is
AND based ICG cell effective for only positive edge triggered then connected to an inverter to obtain the final GClk signal.
 Fig. 9. Layout of the proposed ICG cell.

Data D Positive
Q
[Object] Latch
Clk
[Object]
0
Y
1 Output
Fig. 6. Gate level schematic of the proposed ICG cell. SEL0
[Object]
D Negative
Q
Clock Clk Latch
1
[Object] [Object]
Clock (V)

0.5

0
0 1 2 3 4 5 6 7 8
Time (ns) ×10 -9
Fig. 10. Traditional dual edge triggered DFF using latches and MUX [23].
1
Enable (V)

0.5

In summary, each of the ICG cells for single edge triggered

0
0 1 2 3 4
Time (ns)
5 6 7 8 flip-flops ensures that the glitches propagated to the GClk by
×10 -9
1 the other one are eliminated. The final result of the circuit is
Gated Clock (V)

an uninterrupted gated clock signal when the En is high. The

0.5
layout of the proposed ICG cell in 45 nm CMOS technology
0
0 1 2 3 4 5 6 7 8
is depicted in Fig. 9.
Time (ns) ×10 -9

Fig. 7. Gated clock of the proposed ICG cell when En has glitches. C. Use of the Proposed ICG Cell for Dual Edge Triggered
Flip-flops
The use of dual edge triggered flip-flops has gained pop-
A detailed timing diagram and waveforms are shown in
ularity in low voltage, low power circuits for its ability to
Fig. 8 where the proper functionality of the proposed ICG
provide the same throughput while operating at half the clock
cell is illustrated. When En is at logic high, the output of the
frequency [18], [19]. Furthermore, registers having dual edge
triggered flip-flops are more efficient in saving energy than
1 the single edge triggered flip-flops [20], [21]. Thus, dual edge
Clock (V)

0.5
triggered flip-flops are frequently used in SoCs for low power
0
0 0.1 0.2 0.3 0.4 0.5
Time (ns)
0.6 0.7 0.8 0.9
×10 -8
1
applications that require high throughput. There are various
1
approaches for dual edge triggered flip-flops with inherent
Enable (V)

0.5

0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
clock gating techniques [22]. One important aim of this paper
1
Time (ns) ×10 -8
is to design an ICG cell that can be used for any kind of flip-
flop. The proposed cell is particularly effective for dual edge
A (V)

0.5

0
0 0.1 0.2 0.3 0.4 0.5
Time (ns)
0.6 0.7 0.8 0.9
×10
1
-8
triggered flip-flops as the glitches that may occur in the En
1
signal at any clock transition are eliminated at the gated clock
B (V)

0.5

0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
signal, thereby ensuring that the dual edge triggered flip-flop
1
Time (ns) ×10 -8
does not miss any of the clock edges to properly latch data.
Select (V)

0.5

0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
A traditional dual edge triggered flip-flop is used [23].
Time (ns) ×10 -8
1 The flip-flop incorporates two opposite latches and a MUX, as
GClk (V)

0.5
shown in Fig. 10. The select of the MUX is the clock signal so
0
0 0.1 0.2 0.3 0.4 0.5
Time (ns)
0.6 0.7 0.8 0.9
×10
1
-8 that the output of the positive level sensitive latch is selected
when clock is 0 and the output of the negative level sensitive
latch is selected when the clock is 1. The output of the MUX
Fig. 8. Gated clock of the proposed ICG cell including the intermediate produces the output of the flip-flop.
signals.
Figs. 11, 12 and 13 are shown simultaneously to illustrate
MUX follows the clock signal. When clock is 0, signal A the difference between using the proposed ICG cell for clock
is selected ensuring that no clock edge is missed if there is a gating as opposed to using the existing ICGs. As the latch-
glitch in the En signal during the falling transition of the clock. AND and latch-NOR ICGs miss clock edges when En signal
Alternatively, when clock is 1, signal B is selected to ensure has glitches during the clock transitions, the dual edge trig-
that all of the clock edges are present at GClk even when gered flip-flop cannot latch the data for those clock edges, thus
there is a glitch at the En during the rising clock transition. providing a wrong output. As shown in Fig. 13, the dual edge
 proposed cell is compared with the existing ICG cells in terms

Clock (V)
1
0.5
0
of power consumption, delay and layout area.
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Time (ns) ×10 -8
Gated Clock (V) Enable (V)
1 The performance of the proposed ICG cell is compared
0.5
0
with the existing ICG cells. All of the ICG cells are simulated
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Time (ns) ×10 -8 using 45 nm CMOS technology and are operated by a supply
1
0.5
voltage of 1.0 V at a clock frequency of 1 GHz.
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Time (ns) ×10 -8
1
Data (V)

0.5
TABLE I. P ERFORMANCE COMPARISON OF THE PROPOSED ICG CELL
0 WITH THE EXISTING ICG CELLS .
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Time (ns) ×10 -8
Avg. Power Avg. Power
Output (V)

1
0.5 Consump- Consump- Clk to Glitch
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 ICG tion when tion when GClk Layout Character-
Time (ns) -8
×10 cell Clock is Clock is Delay Area istics
Not Gated Gated
(µW ) (µW ) (ps) (µm2 )
Fig. 11. Faulty operation of a dual edge triggered flip-flop when gated by a Latch- glitches
latch-AND based ICG cell. AND 9.13 2.22 51.11 3.816 occur1
based
Latch- glitches
NOR 7.47 1.72 42.36 3.816 occur2
Clock (V)

1
0.5
0
based
0 0.1 0.2 0.3 0.4 0.5
Time (ns)
0.6 0.7 0.8 0.9 1 Proposed no
×10 -8
ICG 22.31 4.09 86.14 10.137 glitches3
Gated Clock (V) Enable (V)

1
0.5 cell
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Time (ns) ×10 -8
1
0.5
0
A comparative analysis between the proposed ICG cell
0 0.1 0.2 0.3 0.4 0.5
Time (ns)
0.6 0.7 0.8 0.9
×10 -8
1
and the existing ICG cells are listed in Table I. According
1
to Table I, the proposed ICG cell has higher latency and
Data (V)

0.5
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 increased power consumption (by almost a factor of 2 to 2.5
Time (ns) ×10 -8
when compared to the existing ICGs). However, note that a
Output (V)

1
0.5
0
reliable and glitch-free gated clock signal is obtained despite
0 0.1 0.2 0.3 0.4 0.5
Time (ns)
0.6 0.7 0.8 0.9
×10 -8
1
the glitches in the enable signal. Furthermore, the proposed
ICG cell is particularly applicable to dual edge triggered flip-
flops since the enable signal may exhibit glitches during both
Fig. 12. Faulty operation of a dual edge triggered flip-flop when gated by a transitions.
latch-NOR based ICG cell.

V. C ONCLUSION
triggered flip-flop produces the correct output as the proposed Integrated clock gating cell is an important component of
ICG does not miss any clock edge in GClk. low power circuits since clock gating is a typical practice to
reduce dynamic power consumption. New techniques such as
IV. R ESULTS intelligent clock gating and energy recovery clock gating have
been proposed to satisfy the demand of low power and high
As discussed above, the proposed ICG cell provides a speed circuits [24], [25].
glitch-free and uninterrupted gated clock signal for all of the
three kinds of flip-flops when the En signal is high. The In this paper, a new ICG cell is proposed with guaranteed
glitch-free gated clock signal for both single edge and dual
edge triggered flip-flops. The proposed cell is compared with
the existing ICG cells. The existing ICG cells produce a faulty
Clock (V)

1
0.5 gated clock signal if glitches occur in the enable signal during
0
0 0.1 0.2 0.3 0.4 0.5
Time (ns)
0.6 0.7 0.8 0.9
×10 -8
1 the transitions of the clock. The proposed ICG cell eliminates
this issue and ensures an uninterrupted gated clock. As dual
Gated Clock (V) Enable (V)

1
0.5
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
edge triggered flip-flops are preferable for high throughput
1
Time (ns) ×10 -8 circuits, the proposed ICG cell can be highly useful for these
0.5 applications.
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

1
Time (ns) ×10
-8
All of the three ICG cells were designed and simulated in
Data (V)

0.5 45 nm CMOS technology. The comparison results demonstrate

0
0 0.1 0.2 0.3 0.4 0.5
Time (ns)
0.6 0.7 0.8 0.9
×10 -8
1
that higher reliability is achieved at the expense of higher delay
and greater power consumption.
Output (V)

1
0.5
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Time (ns) ×10
-8

1 When there is a glitch in the En during rising clock transition.

2 When
there is a glitch in the En during falling clock transition.
Fig. 13. Proper operation of a dual edge triggered flip-flop when gated by 3 When there is a glitch in the En during both rising and falling clock
the proposed ICG cell. transitions.
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