Genesys Logic, Inc.

GL850A
USB 2.0
Low-Power
HUB Controller

Datasheet
Revision 1.69
Jul. 19, 2007
 GL850A USB 2.0 Low-Power HUB Controller

Copyright:
Copyright © 2007 Genesys Logic Incorporated. All rights reserved. No part of the materials may be
reproduced in any form or by any means without prior written consent of Genesys Logic, Inc.

Disclaimer:
ALL MATERIALS ARE PROVIDED “AS IS” WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY
KIND. NO LICENSE OR RIGHT IS GRANTED UNDER ANY PATENT OR TRADEMARK OF
GENESYS LOGIC INC.. GENESYS LOGIC HEREBY DISCLAIMS ALL WARRANTIES AND
CONDITIONS IN REGARD TO MATERIALS, INCLUDING ALL WARRANTIES, IMPLIED OR
EXPRESS, OF MERCHANTABILITY, FITNESS FOR ANY PARTICULAR PURPOSE, AND
NON-INFRINGEMENT OF INTELLECTUAL PROPERTY. IN NO EVENT SHALL GENESYS LOGIC
BE LIABLE FOR ANY DAMAGES INCLUDING, WITHOUT LIMITATION, DAMAGES RESULTING
FROM LOSS OF INFORMATION OR PROFITS. PLEASE BE ADVISED THAT THE MATERIALS
MAY CONTAIN ERRORS OR OMMISIONS. GENESYS LOGIC MAY MAKE CHANGES TO THE
MATERIALS OR TO THE PRODUCTS DESCRIBED THEREIN AT ANY TIME WITHOUT NOTICE.

Trademarks:

is a registered trademark of Genesys Logic, Inc.

All trademarks are the properties of their respective owners.

Office:
Genesys Logic, Inc.
12F, No. 205, Sec. 3, Beishin Rd., Shindian City,
Taipei, Taiwan
Tel: (886-2) 8913-1888
Fax: (886-2) 6629-6168
http ://www.genesyslogic.com

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 GL850A USB 2.0 Low-Power HUB Controller

Revision History

Revision Date Description

1.0 03/21/2005 First release
1. Modify GREEN1~4 and AMBER1~4, Ch. 3.3, p.11
1.50 04/21/2005 2. Add MaxPower Describe, Ch. 5.2.5, p.20
3. Add Ch.6.4 –Power Consumption, p.23
1.51 04/25/2005 Modify “MaxPoer” to “MaxPower”, table 5.1, p.20

1.52 04/26/2005 Modify Table3.3 Pin Descriptions(PSELF),p.11

1.60 06/20/2005 Modify Table 8.1 Ordering Information,p27

1. Modify pin#46 ,pin#36 ,GL850A 48pin Pinout, Ch3.1,p.9
2. Modify pin#61 ,pin#49 ,GL850A 64pin Pinout Ch3.1,p.10
1.61 07/07/2005 3. Add Pin name “EE_CS/EE_DI”, Hub Interface,table3.4, p.12
4. Modify Fosc ,table 6.1- Maximum Ratings,p.24
5. Modify Vcc ,table 6.2 – Operating Ranges,p.24
1.62 09/07/2005 Modify Pin Descriptions ,table3.3 ,p.12

1.63 09/15/2005 Modify HUB Interface ,table3.3 Pin Description, p.13

1.64 12/28/2005 Modify Pin List and Pin Descriptions of EE_CS, EE_DI, EE_SK, p.11~12

1.65 03/29/2006 Add Input Voltage for digital I/O(Ovcur1-4,Pself,Reset) pins,p.24

1.66 11/03/2006 Modify 93C46 Configuration, Table 5.1, p.22

1.67 01/17/2007 Modify Table 6.1-Maximum Ratings, p.24
1.68 03/12/2007 Modify RESET# Setting, Ch5.2.1, p.18
1.69 07/19/2007 Modify PGANG/SUSPND Setting, Ch5.2.2, p.19

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 GL850A USB 2.0 Low-Power HUB Controller

TABLE OF CONTENTS

CHAPTER 1 GENERAL DESCRIPTION................................................... 7

CHAPTER 2 FEATURES .............................................................................. 8
CHAPTER 3 PIN ASSIGNMENT ................................................................ 9
3.1 PINOUTS...................................................................................................... 9
3.2 PIN LIST.................................................................................................... 11
3.3 PIN DESCRIPTIONS ................................................................................... 12
CHAPTER 4 BLOCK DIAGRAM.............................................................. 15
CHAPTER 5 FUNCTION DESCRIPTION ............................................... 16
5.1 GENERAL .................................................................................................. 16
5.2 CONFIGURATION AND I/O SETTINGS ....................................................... 18
CHAPTER 6 ELECTRICAL CHARACTERISTICS............................... 24
6.1 MAXIMUM RATINGS................................................................................. 24
6.2 OPERATING RANGES ................................................................................ 24
6.3 DC CHARACTERISTICS ............................................................................ 24
6.4 POWER CONSUMPTION ............................................................................ 26
CHAPTER 7 PACKAGE DIMENSION..................................................... 27
CHAPTER 8 ORDERING INFORMATION ............................................ 29

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 GL850A USB 2.0 Low-Power HUB Controller

LIST OF FIGURES

FIGURE 3.1－
－GL850A 48 PIN LQFP PINOUT DIAGRAM ................................................... 9
FIGURE 3.2－
－GL850A 64 PIN LQFP PINOUT DIAGRAM ................................................. 10
FIGURE 4.1 – GL850A BLOCK DIAGRAM (SINGLE TT).................................................... 15
FIGURE 5.1 – OPERATING IN USB 1.1 SCHEME ................................................................. 17
FIGURE 5.2 – OPERATING IN USB 2.0 SCHEME ................................................................. 18
FIGURE 5.3 – RESET# (EXTERNAL RESET) SETTING AND APPLICATION ........................ 19
FIGURE 5.4 – POWER ON SEQUENCE OF GL850A ............................................................. 19
FIGURE 5.5 – TIMING OF PGANG/SUSPND STRAPPING ................................................. 20
FIGURE 5.6 – GANG MODE SETTING ............................................................................... 20
FIGURE 5.7 – SELF/BUS POWER SETTING ...................................................................... 21
FIGURE 5.8 – LED CONNECTION ...................................................................................... 21
FIGURE 5.9 – SCHEMATICS BETWEEN GL850A AND 93C46 ............................................ 23
FIGURE 7.1 – GL850A 48 PIN LQFP PACKAGE ............................................................... 27
FIGURE 7.2 – GL850A 64 PIN LQFP PACKAGE ............................................................... 28

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 GL850A USB 2.0 Low-Power HUB Controller

LIST OF TABLES

TABLE 3.1－
－GL850A 48 PIN LIST .................................................................................... 11
TABLE 3.2 －GL850A 64 PIN LIST ................................................................................... 11
TABLE 3.3 - PIN DESCRIPTIONS ......................................................................................... 12
TABLE 5.1 – 93C46 CONFIGURATION ............................................................................... 22
TABLE 6.1 – MAXIMUM RATINGS ...................................................................................... 24
TABLE 6.2 – OPERATING RANGES ..................................................................................... 24
TABLE 6.3 – DC CHARACTERISTICS EXCEPT USB SIGNALS............................................ 24
TABLE 6.4 – DC CHARACTERISTICS OF USB SIGNALS UNDER FS/LS MODE ................. 25
TABLE 6.5 – DC CHARACTERISTICS OF USB SIGNALS UNDER HS MODE ...................... 25
TABLE 6.6 – DC SUPPLY CURRENT ................................................................................... 26
TABLE 8.1 – ORDERING INFORMATION ............................................................................. 29

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 GL850A USB 2.0 Low-Power HUB Controller

CHAPTER 1 GENERAL DESCRIPTION

GL850A is Genesys Logic’s advanced version Hub solutions which fully comply with Universal Serial Bus
Specification Revision 2.0.

GL850A embeds an 8-bit RISC processor to manipulate the control/status registers and respond to the requests
from USB host. Firmware of GL850A will control its general purpose I/O (GPIO) to access the external
EEPROM and then respond to the host the customized PID and VID configured in the external EEPROM.
Default settings in the internal mask ROM is responded to the host without having external EEROM. GL850A
is designed for customers with much flexibility. The more complicated settings such as PID, VID, and number
of downstream ports settings are easily achieved by programming the external EEPROM (Ref. to Chapter 5).

Each downstream port of GL850A supports two-color (green/amber) status LEDs to indicate normal/abnormal
status. GL850A also support both Individual and Gang modes (4 ports as a group) for power management.
The GL850A (64-pin) is a full function solution which supports both Individual/Gang power management
modes and the two-color (green/amber) status LEDs. The low pin-count version GL850A (48-pin) only
supports Gang mode. Please refer the table in the end of this chapter for more detail.

To fully meet the cost/performance requirement, GL850A is a single TT hub solution for the cost requirement.
Genesys Logic also provides GL852 for multiple TT hub solution to target on systems which require higher
performance for full/low-speed devices, like docking station, embedded system … etc.. Please refer to GL852
datasheet for more detailed information.

*TT (transaction translator) is the main traffic control engine in an USB 2.0 hub to handle the unbalanced
traffic speed between the upstream port and the downstream ports.

Product Name Package type Power mode LED support

GL850A 64LQFP Individual/Gang Green/Amber
GL850A 48LQFP Gang Green/Amber

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 GL850A USB 2.0 Low-Power HUB Controller

CHAPTER 2 FEATURES

• Compliant to USB specification Revision 2.0

− 4 downstream ports
− Upstream port supports both high-speed (HS) and full-speed (FS) traffic
− Downstream ports support HS, FS, and low-speed (LS) traffic
− 1 control pipe (endpoint 0, 64-byte data payload) and 1 interrupt pipe (endpoint 1, 1-byte data payload)
− Backward compatible to USB specification Revision 1.1

• On-chip 8-bit micro-processor

− RISC-like architecture
− USB optimized instruction set
− Dual cycle instruction execution
− Performance: 6 MIPS @ 12MHz
− With 64-byte RAM and 2K internal ROM
− Support customized PID, VID by reading external EEPROM
− Support downstream port configuration by reading external EEPROM
• Single Transaction Translator (STT)
− Single TT shares the same TT control logics for all downstream port devices. This is the most cost
effective solution for TT. Multiple TT provides individual TT control logics for each downstream port.
This is a performance better choice for USB 2.0 hub. Please refer to GL852 datasheet for more
detailed information.
• Each downstream port supports two-color status indicator, with automatic and manual modes compliant to
USB specification Revision 2.0
• Support both individual and gang modes of power management and over-current detection for
downstream ports (64-pin LQFP)
• Support gang mode of power management and over-current detection for downstream ports
• Conform to bus power requirements
• Automatic switching between self-powered and bus-powered modes
• Integrate USB 2.0 transceiver
• PLL embedded with external 12 MHz crystal
• Operate on 3.3 Volts
• Embed serial resister for USB signals and integrate pull-up resister for upstream USB signal
• Improve output drivers with slew-rate control for EMI reduction
• Internal power-fail detection for ESD recovery
• 64/48-pin LQFP package
• Applications:
− Stand-alone USB hub
− PC motherboard USB hub, Docking of notebook
− Any compound device to support USB HUB function

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 GL850A USB 2.0 Low-Power HUB Controller

CHAPTER 3 PIN ASSIGNMENT

3.1 Pinouts

GREEN2/EE_DO
AMBER2/EE_DI

AMBER3

AMBER4
GREEN3

RESET#
DVDD

DGND

DVDD

DGND
TEST
NC
36

35

34

33

32

31

30

29

28

27

26

25
PSELF 37 24 GREEN4

DGND 38 23 DP4

DVDD 39 22 DM4

PGANG/SUSPND 40 21 AGND

OVCUR1# 41 20 AVDD

PWREN1# 42 19 DP3

DGND

DVDD
43

44
GL850A 18

17
DM3

AGND

GREEN1/EE_SK 45 16 AVDD

AMBER1/EE_CS 46 15 X2

DGND 47 14 X1
LQFP - 48
DVDD 48 13 AGND
10

11

12
1

9
DM0

DP0

DM1

DP1

DM2

DP2
AVDD

AGND

AVDD

AGND

RREF

AVDD

Figure 3.1 －GL850A 48 Pin LQFP Pinout Diagram

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 GL850A USB 2.0 Low-Power HUB Controller

Figure 3.2 －GL850A 64 Pin LQFP Pinout Diagram

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 GL850A USB 2.0 Low-Power HUB Controller

3.2 Pin List

Table 3.1 －GL850A 48 Pin List
Pin# Pin Name Type Pin# Pin Name Type Pin# Pin Name Type Pin# Pin Name Type
1 AVDD P 13 AGND P 25 AMBER4 O 37 PSELF I
2 AGND P 14 X1 I 26 DGND P 38 DGND P
3 DM0 B 15 X2 O 27 DVDD P 39 DVDD P
PGANG/
4 DP0 B 16 AVDD P 28 RESET# I 40 B
SUSPND
5 DM1 B 17 AGND P 29 TEST I 41 OVCUR1# I
6 DP1 B 18 DM3 B 30 NC - 42 PWREN1# O
7 AVDD P 19 DP3 B 31 GREEN3 O 43 DGND P
8 AGND P 20 AVDD P 32 AMBER3 O 44 DVDD P
GREEN1/
9 DM2 B 21 AGND P 33 DGND P 45 O
EE_SK
AMBER1/
10 DP2 B 22 DM4 B 34 DVDD P 46 O
EE_CS
GREEN2/
11 RREF B 23 DP4 B 35 B 47 DGND P
EE_DO
AMBER2/
12 AVDD P 24 GREEN4 O 36 O 48 AVDD P
EE_DI

Table 3.2 －GL850A 64 Pin List

Pin# Pin Name Type Pin# Pin Name Type Pin# Pin Name Type Pin# Pin Name Type
AMBER2/
1 AGND P 17 RREF B 33 NC - 49 O
EE_DI
2 NC - 18 AVDD P 34 GREEN4 O 50 PSELF I
3 DM0 B 19 AGND P 35 AMBER4 O 51 DGND P
4 DP0 B 20 X1 I 36 DGND P 52 DVDD P
PGANG/
5 NC - 21 X2 O 37 DVDD P 53 B
SUSPND
6 NC - 22 AVDD P 38 RESET# I 54 OVCUR2# I
7 NC - 23 AGND P 39 TEST I 55 PWREN2# O
8 DM1 B 24 NC - 40 OVCUR4# I 56 OVCUR1# I
9 DP1 B 25 DM3 B 41 PWREN4# O 57 PWREN1# O
10 NC - 26 DP3 B 42 OVCUR3# I 58 DGND P
11 AVDD P 27 NC - 43 PWREN3# O 59 DVDD P
GREEN1/
12 AGND P 28 AVDD P 44 GREEN3 O 60 O
EE_SK
AMBER1/
13 NC - 29 AGND P 45 AMBER3 O 61 O
EE_CS
14 DM2 B 30 NC - 46 DGND P 62 DGND P

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 GL850A USB 2.0 Low-Power HUB Controller

15 DP2 B 31 DM4 B 47 DVDD P 63 AVDD P

GREEN2/
16 NC - 32 DP4 B 48 B 64 AVDD P
EE_DO

3.3 Pin Descriptions

Table 3.3 - Pin Descriptions

USB Interface
GL850A
Pin Name I/O Type Description
48Pin# 64 Pin#
DM0,DP0 3,4 3,4 B USB signals for USPORT
DM1,DP1 5,6 8,9 B USB signals for DSPORT1
DM2,DP2 9,10 14,15 B USB signals for DSPORT2
DM3,DP3 18,19 25,26 B USB signals for DSPORT3
DM4,DP4 22,23 31,32 B USB signals for DSPORT4
A 680Ω resister must be connected between RREF and
RREF 11 17 B
analog ground (AGND).
Note: USB signals must be carefully handled in PCB routing. For detailed information, please refer to
GL850A Design Guideline.

HUB Interface
GL850A
Pin Name I/O Type Description
48Pin# 64 Pin#
Active low. Over current indicator for DSPORT1~4
56,54, I
OVCUR1#~4 41 OVCUR1# is the only over current flag for GANG
42,40 (pu)
mode.
Active low. Power enable output for DSPORT1~4
57,55,
PWREN1#~4 42 O PWREN1# is the only power-enable output for GANG
43,41
mode.
1,3,4: O Green LED indicator for DSPORT1~4
45,35, 60,48,
GREEN1~4 2: B *GREEN[1~2] are also used to access the external EEPROM
31,24 44,34
(pd) For detailed information, please refer to Chapter 5.
46,36, 61,49, O Amber LED indicator for DSPORT1~4
AMBER1~4
32,25 45,35 (pd) *Amber[1~2] are also used to access the external EEPROM
EE_CS/ Used to access the external EEPROM.
- - I
EE_DI For detailed information, please refer to Chapter 5.
0: GL850A is bus-powered.
PSELF 37 50 I
1: GL850A is self-powered.
This pin is default put in input mode after power-on
PGANG/
40 53 B reset. Individual/gang mode is strapped during this
SUSPND
period. After the strapping period, this pin will be set to

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 GL850A USB 2.0 Low-Power HUB Controller

output mode, and then output high for normal mode.

When GL850A is suspended, this pin will output low.
*For detailed explanation, please see Chapter 5
Gang input:1, output: 0@normal, 1@suspend
Individual input:0, output: 1@normal, 0@suspend

Clock and Reset Interface

GL850A
Pin Name I/O Type Description
48Pin# 64Pin#
X1 14 20 I 12MHz crystal clock input.
X2 15 21 O 12MHz crystal clock output.
Active low. External reset input, default pull high 10KΩ.
RESET# 28 38 I When RESET# = low, whole chip is reset to the initial
state.

System Interface
GL850A
Pin Name I/O Type Description
48Pin# 64 Pin#
I 0: Normal operation.
TEST 29 39
(pd) 1: Chip will be put in test mode.

Power / Ground
GL850A
Pin Name I/O Type Description
48Pin# 64 Pin#
1,7,12, 11,18,22,
AVDD 16,20 28,64
P 3.3V analog power input for analog circuits.
2,8,13, 1,12,19,
AGND P Analog ground input for analog circuits.
17,21 23,29
27,34, 37,47,
DVDD 39,44 52,59
P 3.3V digital power input for digital circuits
26,33,
36,46,
DGND 38,
51,58,62
P Digital ground input for digital circuits.
43,47
2,5~7,
10,13,16,
NC 30 - No connection
24,27,30,
33
Note: Analog circuits are quite sensitive to power and ground noise. PCB layout must take care the power
routing and the ground plane. For detailed information, please refer to GL850A Design Guideline.

Notation:
Type O Output
I Input
B Bi-directional
B/I Bi-directional, default input
B/O Bi-directional, default output
P Power / Ground

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 GL850A USB 2.0 Low-Power HUB Controller

A Analog
SO Automatic output low when suspend
pu Internal pull up
pd Internal pull down
odpu Open drain with internal pull up

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 GL850A USB 2.0 Low-Power HUB Controller

CHAPTER 4 BLOCK DIAGRAM

12MHz

D+ D-

USPORT PLL RAM ROM GPIO

FRTIMER
Transceiver x40, x10 CPU

USPORT Control/Status
UTMI SIE
Logic Register

REPEATER TT (Transaction Translator)

REPEATER / TT Routing Logic

DSPORT1 Logic DSPORT2 Logic DSPORT3 Logic DSPORT4 Logic

DSPORT DSPORT DSPORT DSPORT

Transceiver Transceiver Transceiver Transceiver

D+ D- LED/ D+ D- LED/ D+ D- LED/ D+ D- LED/

OVCUR/ OVCUR/ OVCUR/ OVCUR/
PWRENB PWRENB PWRENB PWRENB

Figure 4.1 – GL850A Block Diagram (single TT)

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 GL850A USB 2.0 Low-Power HUB Controller

CHAPTER 5 FUNCTION DESCRIPTION

5.1 General
5.1.1 USPORT Transceiver
USPORT (upstream port) transceiver is the analog circuit that supports both full-speed and high-speed
electrical characteristics defined in chapter 7 of USB specification Revision 2.0. USPORT transceiver will
operate in full-speed electrical signaling when GL850A is plugged into a 1.1 host/hub. USPORT transceiver
will operate in high-speed electrical signaling when GL850A is plugged into a 2.0 host/hub.

5.1.2 PLL (Phase Lock Loop)

GL850A contains a 40x PLL. PLL generates the clock sources for the whole chip. The generated clocks are
proven quite accurate that help in generating high speed signal without jitter.

5.1.3 FRTIMER
This module implements hub (micro)frame timer. The (micro)frame timer is derived from the hub’s local
clock and is synchronized to the host (micro)frame period by the host generated Start of (micro)frame
(SOF). FRTIMER keeps tracking the host’s SOF such that GL850A is always safely synchronized to the
host. The functionality of FRTIMER is described in section 11.2 of USB Specification Revision 2.0.

5.1.4 µC
µC is the micro-processor unit of GL850A. It is an 8-bit RISC processor with 2K ROM and 64 bytes RAM.
It operates at 6MIPS of 12Mhz clock to decode the USB command issued from host and then prepares the
data to respond to the host. In addition, µC can handle GPIO (general purpose I/O) settings and reading
content of EEPROM to support high flexibility for customers of different configurations of hub. These
configurations include self/bus power mode setting, individual/gang mode setting, downstream port number
setting, device removable/non-removable setting, and PID/VID setting.

5.1.5 UTMI (USB 2.0 Transceiver Macrocell Interface)

UTMI handles the low level USB protocol and signaling. It’s designed based on the Intel’s UTMI
specification 1.01. The major functions of UTMI logic are to handle the data and clock recovery, NRZI
encoding/decoding, Bit stuffing /de-stuffing, supporting USB 2.0 test modes, and serial/parallel conversion.

5.1.6 USPORT logic

USPORT implements the upstream port logic defined in section 11.6 of USB specification Revision 2.0. It
mainly manipulates traffics in the upstream direction. The main functions include the state machines of
Receiver and Transmitter, interfaces between UTMI and SIE, and traffic control to/from the REPEATER
and TT.

5.1.7 SIE (Serial Interface Engine)

SIE handles the USB protocol defined in chapter 8 of USB specification Revision 2.0. It co-works with c Μ
to play the role of the hub kernel. The main functions of SIE include the state machine of USB protocol
flow, CRC check, PID error check, and timeout check. Unlike USB 1.1, bit stuffing/de-stuffing is
implemented in UTMI, not in SIE.

5.1.8 Control/Status register

Control/Status register is the interface register between hardware and firmware. This register contains the
information necessary to control endpoint0 and endpoint1 pipelines. Through the firmware based
architecture, GL850A possesses higher flexibility to control the USB protocol easily and correctly.

5.1.9 REPEATER
Repeater logic implements the control logic defined in section 11.4 and section 11.7 of USB specification
Revision 2.0. REPEATER controls the traffic flow when upstream port and downstream port are signaling
in the same speed. In addition, REPEATER will generate internal resume signal whenever a wakeup event
is issued under the situation that hub is globally suspended.

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 GL850A USB 2.0 Low-Power HUB Controller

5.1.10. TT (Transaction Translator)

TT implements the control logic defined in section 11.14 ~ 11.22 of USB specification Revision 2.0. TT
basically handles the unbalanced traffic speed between the USPORT (operating in HS) and DSPORTS
(operating in FS/LS) of hub. GL850A adopts the single TT architecture to provide the most cost effective
solution. Single TT shares the same buffer control module for each downstream port. GL852 adopts
multiple TT architecture to provide the most performance effective solution. Multiple TT provides control
logics for each downstream port respectively. Please refer to GL852 datasheet for more detailed
information.

5.1.11 REPEATER/TT routing logic

REPEATER and TT are the major traffic control machines in the USB 2.0 hub. Under situation that
USPORT and DSPORT are signaling in the same speed, REPEATER/TT routing logic switches the traffic
channel to the REPEATER. Under situation that USPORT is in the high speed signaling and DSPORT is in
the full/low speed signaling, REPEATER/TT routing logic switches the traffic channel to the TT.

5.1.11.1 Connected to 1.1 Host/Hub

If an USB 2.0 hub is connected to the downstream port of an USB 1.1 host/hub, it will operate in USB 1.1
mode. For an USB 1.1 hub, both upstream direction traffic and downstream direction traffic are passing
through REPEATER. That is, the REPEATER/TT routing logic will route the traffic channel to the
REPEATER.

USB1.1 HOST/HUB

USPORToperating
in FS signaling

Traffic channel
is routed to
REPEATER TT
REPEATER

DSPORT operating
in FS/LS signaling

Figure 5.1 – Operating in USB 1.1 scheme

5.1.11.2 Connected to USB 2.0 Host/Hub

If an USB 2.0 hub is connected to an USB 2.0 host/hub, it will operate in USB 2.0 mode. The upstream port
signaling is in high speed with bandwidth of 480 Mbps under this environment. The traffic channel will
then be routed to the REPEATER when the device connected to the downstream port is signaling also in
high speed. On the other hand, the traffic channel will then be routed to TT when the device connected to
the downstream port is signaling in full/low speed.

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 GL850A USB 2.0 Low-Power HUB Controller

USB2.0 HOST/HUB

USPORToperating
in HS signaling

HS vs. HS:
Traffic channel is HS vs. FS/LS:
routed to REPEATER REPEATER TT
Traffic channel
is routed to TT

DSPORT operating DSPORT operating

in HS signaling in FS/LS signaling

Figure 5.2 – Operating in USB 2.0 scheme

5.12 DSPORT logic

DSPORT (downstream port) logic implements the control logic defined in section 11.5 of USB specification
Revision 2.0. It mainly manipulates the state machine, the connection/disconnection detection, over current
detection and power enable control, and the status LED control of the downstream port. Besides, it also
output the control signals to the DSPORT transceiver.

5.13 DSPORT Transceiver

DSPORT transceiver is the analog circuit that supports high-speed, full-speed, and low-speed electrical
characteristics defined in chapter 7 of USB specification Revision 2.0. In addition, each DSPORT
transceiver accurately controls its own squelch level to detect the detachment and attachment of devices.

5.2 Configuration and I/O Settings

5.2.1 RESET# Setting
GL850A integrates in the pull-up 1.5KΩ resister of the upstream port. When RESET# is enabled, the
internal 1.5KΩ pull-up resister will be disconnected to the 3.3V power. To meet the requirement (p.141) of
the USB 2.0 specification, pull-up resister should be disconnected while lacking of USB cable power
(Vbus). Therefore, we suggest designing the RESET# circuit as following figure to meet the requirement
mentioned above.

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 GL850A USB 2.0 Low-Power HUB Controller

Vbus
RESET# R (5V)

C R

AVDD
1.5K ohm (3.3V)

33 ohm DP0

On PCB
Inside GL850A

Figure 5.3 – RESET# (External Reset) setting and application

GL850A internally contains a power on reset circuit. The power on sequence is depicted in the next picture.
To fully control the reset process of GL850A, we suggest the reset time applied in the external reset circuit
should longer than that of the internal reset circuit.

VCC(3.3V)
Power good voltage, 2.5~2.8V

≒ 2.7 μs
Internal reset

External reset

Figure 5.4 – Power on sequence of GL850A

5.2.2 PGANG/SUSPND Setting

To save pin count, GL850A uses the same pin to decide individual/gang mode as well as to output the
suspend flag. The individual/gang mode is decided within 20us after power on reset. Then, about 50ms later,
this pin is changed to output mode. GL850A outputs the suspend flag once it is globally suspended. For
individual mode, a pull low resister greater than 100KΩ should be placed. For gang mode, a pull high
resister greater than 100KΩ should be placed. In figure 5.6, we also depict the suspend LED indicator
schematics. It should be noticed that the polarity of LED must be followed, otherwise the suspend current
will be over spec limitation (2.5mA).

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 GL850A USB 2.0 Low-Power HUB Controller

RESET#
50ms
GANG_CTL

Input mode, strapping Output mode, indicating

to decide individual or GL850A is in normal
gang mode mode or suspend mode

Figure 5.5 – Timing of PGANG/SUSPND strapping

GAND Mode
DVDD(3.3V)
DVDD(3.3V)

Suspend LED
"0": Individual Mode 100K ohm
Indicator
"1": GANG Mode

PGANG
SUSPNDO

GANG_CTL
100K ohm Suspend LED
Indicator
Inside GL850A
On PCB
Individual
Mode

Figure 5.6 – GANG Mode Setting

5.2.3 SELF/BUS Power Setting

GL850A can operate under bus power and conform to the power consumption limitation completely
(suspend current < 2.5 mA, normal operation current < 100 mA). By setting PSELF, GL850A can be
configured as a bus-power or a self-power hub.

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 GL850A USB 2.0 Low-Power HUB Controller

1: Power Self PSELF

0: Power Bus

Inside GL850A
On PCB

Figure 5.7 – SELF/BUS Power Setting

5.2.4 LED Connections

GL850A controls the LED lighting according to the flow defined in section 11.5.3 of Universal Serial Bus
Specification Revision2.0. Both manual mode and Automatic mode are supported in GL850A. When
GL850A is globally suspended, GL850A will turn off the LED to save power.

AMBER/GREEN
LED

DGND

Inside GL850A
On PCB

Figure 5.8 – LED Connection

5.2.5 EEPROM Setting

GL850A replies to host commands by the default settings in the internal ROM. GL850A also offers the
ability to reply to the host according to the settings in the external EEPROM(93C46). The following table
shows the configuration of 93C46.

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 GL850A USB 2.0 Low-Power HUB Controller

Table 5.1 – 93C46 Configuration

Unit: Byte

00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
DEVICE PORT
00h VID_L VID_H PID_L PID_H CHKSUM FF REMOVABLE NUMBER MaxPower FF FF FF FF FF FF FF

VENDOR
10h LENGTH
start

20h Vendor string (ASC II code)

30h end
PRODUCT
40h LENGTH
start

50h Product String(ASC II code)

60h end

SERIAL
start Serial Number String(ASC II code)

70h NUMBER
LENGTH end

Note: 1. VID_H/VID_L: high/low byte of VID value

2. PID_H/PID_L: high/low byte of PID value
3. CHKSUM: CHKSUM must equal to VID_H + VID_L + PID_H + PID_L + 1,otherwise
firmware will ignore the EEPROM settings.
4. PORT_NO: port number, value must be 1~4.
5. MaxPower : Describe the maximum power consumption, range=0Ma~500Ma .
Value -> 00H~FAH (unit = 2Ma)
6. DEVICE REMOVALBE:
PORT4 PORT3 PORT2 PORT1
- - - -
REMOVABLE REMOVABLE REMOVABLE REMOVABLE
0: Device attached to this port is removable.
1: Device attached to this port is non-removable.

7. VENDOR LENGTH: offset 10h contains the length of the vendor string. Values of vendor string is
contained from 11h~3Fh.
8. PRODUCT LENGTH: offset 40h contains the length of product string. Values of product string is
contained from 41h~6Fh.
9. SERIAL NUMBER LENGTH: offset 70h contains the value of serial number string. Values of serial
number string is contained after offset 71h.

©2000-2007 Genesys Logic Inc. - All rights reserved. Page 22

 GL850A USB 2.0 Low-Power HUB Controller

The schematics between GL850A and 93C46 is depicted in the following figures:
DVDD

EE_CS CS VCC

EE_SK SK NC

EE_DI DI NC

EE_DO DO GND

93C46

Figure 5.9 – Schematics Between GL850A and 93C46

GL850A firstly verifies the check sum after power on reset. If the check sum is correct, GL850A will take
the configuration of 93C46 as part of the descriptor contents. To prevent the content of 93C46 from being
over-written, amber LED will be disabled when 93C46 exists.

©2000-2007 Genesys Logic Inc. - All rights reserved. Page 23

 GL850A USB 2.0 Low-Power HUB Controller

CHAPTER 6 ELECTRICAL CHARACTERISTICS

6.1 Maximum Ratings
Table 6.1 – Maximum Ratings

Symbol Parameter Min. Max. Unit

VCC Power Supply -0.5 +3.6 V
VIN Input Voltage for digital I/O(EE_DO) pins -0.5 +3.6 V
VIN Input Voltage for digital I/O(Ovcur1-4,Pself,Reset) pins -0.5 +5.25 V
VINUSB Input Voltage for USB signal (DP, DM) pins -0.5 +3.6 V
o
TS Storage Temperature under bias -60 +100 C
FOSC Frequency 12 MHz ± 0.05%

6.2 Operating Ranges

Table 6.2 – Operating Ranges

Symbol Parameter Min. Typ. Max. Unit

VCC Power Supply 3.0 3.3 3.6 V
VIND Input Voltage for digital I/O pins -0.5 3.3 3.6 V
VINUSB Input Voltage for USB signal (DP, DM) pins 0.5 3.3 3.6 V
o
TA Ambient Temperature 0 - 70 C

6.3 DC Characteristics
Table 6.3 – DC Characteristics Except USB Signals

Symbol Parameter Min. Typ. Max. Unit

PD Power Dissipation 70 - 180 mA
VDD Power Supply Voltage 3 3.3 3.6 V
VIL LOW level input voltage - - 0.9 V
VIH HIGH level input voltage 2.0 - - V
VTLH LOW to HIGH threshold voltage 1.36 1.48 1.62 V
VTHL HIGH to LOW threshold voltage 1.36 1.48 1.62 V
VOL LOW level output voltage when IOL=8Ma - - 0.4 V
VOH HIGH level output voltage when IOH=8Ma 2.4 - - V
Leakage current for pads with internal pull up or pull
IOLK - - 30 µA
down resistor
RDN Pad internal pull down resister 81K 103K 181K Ω
RUP Pad internal pull up resister 81K 103K 181K Ω

©2000-2007 Genesys Logic Inc. - All rights reserved. Page 24

 GL850A USB 2.0 Low-Power HUB Controller

Table 6.4 – DC Characteristics of USB Signals Under FS/LS Mode

Symbol Parameter Min. Typ. Max. Unit

VOL DPF/DMF static output LOW(RL of 1.5K to 3.6V ) 0 - 0.3 V
VOH DPF/DMF static output HIGH (RL of 15K to GND ) 2.8 - 3.6 V
VDI Differential input sensitivity 0.2 - - V
VCM Differential common mode range 0.8 - 2.5 V
VSE Single-ended receiver threshold 0.2 - - V
CIN Transceiver capacitance - - 20 Pf
ILO Hi-Z state data line leakage -10 - +10 µA
ZDRV Driver output resistance 28 - 43 Ω

Table 6.5 – DC Characteristics of USB Signals Under HS Mode

Symbol Parameter Min. Typ. Max. Unit

VOL DPH/DMH static output LOW(RL of 1.5K to 3.6V ) - - 0.1 V
CIN Transceiver capacitance 4 4.5 5 Pf
ILO Hi-Z state data line leakage -5 0 +5 µA
ZDRV Driver output resistance for USB 2.0 HS 48 45 42 Ω

©2000-2007 Genesys Logic Inc. - All rights reserved. Page 25

 GL850A USB 2.0 Low-Power HUB Controller

6.4 Power Consumption

Table 6.6 – DC Supply Current

Condition
Symbol Typ. Unit
Active ports Host Device
ISUSP Suspend 540/800*1 µA
*2
F F 93 mA
4 H H 180 mA
H F 115 mA
F F 91 mA
3 H H 160 mA
H F 111 mA
F F 89 mA
ICC
2 H H 140 mA
H F 106 mA
F F 87 mA
1 H H 115 mA
H F 102 mA
F 80 mA
No Active
H 95 mA
*1: 48/64-pin package types
*2: F: Full-Speed, H: High-Speed

©2000-2007 Genesys Logic Inc. - All rights reserved. Page 26

 GL850A USB 2.0 Low-Power HUB Controller

CHAPTER 7 PACKAGE DIMENSION

D
D1
A
D2
D A2
A1

0.05 S
36 25
37 24

N : Normal package
Internal No. G : Green package
A
GL850A B

AAAAAAAGAA
E1
E2
E

YWWXXXXXXXX Version
No.
Date Code Lot Code

48 13
aaa C A B D
12 4X

L1
1
4X bbb H A B D
e c
b
ddd M C A B s D s
0- 1

0- C SEATING
ccc C PLANE

CONTROL DIMENSIONS ARE IN MILLIMETERS.

MILLIMETER INCH
0- 2 SYMBOL
MIN. NOM. MAX. MIN. NOM. MAX.
A 1.60 0.063
R1 A1 0.05 0.15 0.002 0.006
A2 1.35 1.40 1.45 0.053 0.055 0.057
R2 D 9.00 BASIC 0.354 BASIC
H
E 9.00 BASIC 0.354 BASIC
GAGE PLANE D1 7.00 BASIC 0.276 BASIC
0.25mm
S L E1 7.00 BASIC 0.276 BASIC
D2 5.50 BASIC 0.217 BASIC
0- 3 E2 5.50 BASIC 0.217 BASIC
R1 0.08 0.003
R2 0.08 0.20 0.003 0.008
0- 0° 3.5° 7° 0° 3.5° 7°
0- 1 0° 0°
NOTES : 0- 2 11° 12° 13° 11° 12° 13°
0- 3 11° 12° 13° 11° 12° 13°
1. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 mm c 0.09 0.20 0.004 0.008
PER SIDE. D1 AND E1 ARE MAXIMUM PLASTIC BODY L 0.45 0.60 0.75 0.018 0.024 0.030
SIZE DIMENSIONS INCLUDING MOLD MISMATCH. L1 1.00 REF 0.039 REF
S 0.20 0.008
2. DIMENSION b DOES NOT INCLUDE DAMBAR b 0.17 0.20 0.27 0.007 0.008 0.011
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION e 0.50 BASIC 0.020 BASIC
SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED THE TOLERANCES OF FORM AND POSITION
MAXIMUM b DIMENSION BY MORE THAN 0.08mm. aaa 0.20 0.008
DAMBAR CAN NOT BE LOCATED ON THE LOWER bbb 0.20 0.008
RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN ccc 0.08 0.003
PROTRUSION AND AN ADJACENT LEAD IS 0.07mm. ddd 0.08 0.003

Figure 7.1 – GL850A 48 Pin LQFP Package

©2000-2007 Genesys Logic Inc. - All rights reserved. Page 27

 GL850A USB 2.0 Low-Power HUB Controller

D
D1 A
D2
D A2
A1

0.05 S
48 33
49 32

N : Normal package
InternalNo G : Green package
. B
A
GL850A
E1
E2

AAAAAAAGAA
E

YWWXXXXXXXX Version
No.
Date Code Lot Code

64 17
16 4X aaa C A B D

L1
1
4X bbb H A B D
e c
b ddd M C A B s D s
0- 1

0- C SEATING
PLANE
ccc C

CONTROL DIMENSIONS ARE IN MILLIMETERS.

0- 2 MILLIMETER INCH
SYMBOL
MIN. NOM. MAX. MIN. NOM. MAX.
R1 A 1.60 0.063
A1 0.05 0.15 0.002 0.006
R2 A2 1.35 1.40 1.45 0.053 0.055 0.057
H
D 12.00 BASIC 0.472 BASIC
GAGE PLANE
0.25mm E 12.00 BASIC 0.472 BASIC
S L D1 10.00 BASIC 0.393 BASIC
E1 10.00 BASIC 0.393 BASIC
0- 3 D2 7.50 BASIC 0.295 BASIC
E2 7.50 BASIC 0.295 BASIC
R1 0.08 0.003
R2 0.08 0.20 0.003 0.008
0- 0 3.5 7 0 3.5 7
NOTES : 0- 1 0 0
0- 2 11 12 13 11 12 13
1. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD 0- 3 11 12 13 11 12 13
PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 mm c 0.09 0.20 0.004 0.008
PER SIDE. D1 AND E1 ARE MAXIMUM PLASTIC BODY L 0.45 0.60 0.75 0.018 0.024 0.030
SIZE DIMENSIONS INCLUDING MOLD MISMATCH. L1 1.00 REF 0.039 REF
2.
DIMENSION b DOES NOT INCLUDE DAMBAR S 0.20 0.008
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION b 0.17 0.20 0.27 0.007 0.008 0.011
SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED THE e 0.50 BASIC 0.020 BASIC
MAXIMUM b DIMENSION BY MORE THAN 0.08mm. TOLERANCES OF FORM AND POSITION
DAMBAR CAN NOT BE LOCATED ON THE LOWER aaa 0.20 0.008
RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN bbb 0.20 0.008
PROTRUSION AND AN ADJACENT LEAD IS 0.07mm.
ccc 0.08 0.003
ddd 0.08 0.003

Figure 7.2 – GL850A 64 Pin LQFP Package

©2000-2007 Genesys Logic Inc. - All rights reserved. Page 28

 GL850A USB 2.0 Low-Power HUB Controller

CHAPTER 8 ORDERING INFORMATION

Table 8.1 – Ordering Information

Part Number Package Normal/Green Version Status

GL850A-MSNXX 64-pin LQFP Normal Package XX Available
GL850A-MNNXX 48-pin LQFP Normal Package XX Available
GL850A-MSGXX 64-pin LQFP Green Package XX Available
GL850A-MNGXX 48-pin LQFP Green Package XX Available

©2000-2007 Genesys Logic Inc. - All rights reserved. Page 29