D a ta S h e e t , R ev . 1 .

5 1, J u n e 20 0 7

TLE 7263E
I n t e g r a t e d H S - C A N , L IN , L D O a n d
HS Switch
System Basis Chip

Automotive Power

Never stop thinking.

Integrated HS-CAN, LIN, LDO and HS Switch TLE 7263E
System Basis Chip

1 Overview

Features
• Two Low Drop Voltage Regulators
• Window watchdog
• Standard 16-bit SPI-interface
• Supports µController Stop Mode
• Sleep Mode (50µA)
• VBAT Monitoring and fail-safe output
• Overtemperature and short circuit protection PG-DSO-36-24
• Power on and undervoltage reset generator
• High side switch, 150 mA
• 4 Monitoring / wake-up inputs
• Exposed Pad Package
• AEC Qualified
• Green (RoHS Compliant) product

HS CAN Transceiver
• CAN data transmission rate up to 1 MBaud
• Low power mode management
• Supports sleep and receive-only modes
• Bus wake-up capability via CAN message
• Bus pins are short circuit proof to ground and battery voltage

LIN Transceiver
• Single-wire transceiver
• Transmission rate up to 20 kBaud
• Compatible to LIN specification 1.3 and 2.0
• Very low current consumption in Sleep Mode
• Short circuit proof to GND and battery

Type Package Marking

TLE 7263E PG-DSO-36-24

Data Sheet 2 Rev. 1.51, 2007-06-22

 TLE 7263E

Overview

Dual-Voltage Regulator
• Low-dropout voltage regulator, dual voltage-supply
• V1, 150 mA, 5 V ±2% for external devices, e.g. microcontrollers
• V2, 150 mA, 5 V ±2% for internal CAN module and external devices.

Description
The TLE 7263E is a monolithic integrated circuit in an enhanced power package. The IC
is designed for CAN-LIN gateway applications.
To support these applications the TLE 7263E covers smart power functions such as HS-
CAN transceiver and LIN transceiver for data transmission, dual low dropout voltage
regulator (LDO) for external 5 V supply, and high-side switch as well as a 16-bit SPI
(serial peripheral interface) to control and monitor the IC. There is also a window
watchdog circuit with a reset feature, a fail-safe output, a voltage sensing input and a
undervoltage reset feature implemented.
The device offer low power modes in order to support modules directly connected to the
battery (KL. 30). A wake-up from the low power mode is possible via a message on the
bus or via the bi level sensitive monitoring/wake-up inputs. The integrated High-Side
switch can also be used to periodically supply an external wake-up circuitry in the low
power mode, by choosing a special function. The integrated bus transceivers offer a
receive-only mode for software diagnosis functions.
The IC is designed to withstand the severe conditions of automotive applications.

Data Sheet 3 Rev. 1.51, 2007-06-22

 TLE 7263E

Pin Configuration

2 Pin Configuration

GND 1 36 GND
GND 2 35 TxDLIN
NC 3 TLE7263E 34 RxDLIN
LIN 4 DSO 36 - Exposed Pad 33
FSO
MTS 5 32
WKO
GND 6 31
CSN
OUTHS 7 30
CLK
VS 8 29
DI
MON1 9
cooling tab
28 DO
MON2 10 (GND) 27 STS
MON3 11 26 RO
MON4 12 25 RxDCAN
SI 13 24
TxDCAN
GND 14 23 GND
VCC1 15 22 CANL
VCC2 16 21 SPLIT
INT 17 20 CANH
GND 18 19 GND
Pinnout_7263_SO-36EP

Figure 1 Pin Configuration (top view)

Data Sheet 4 Rev. 1.51, 2007-06-22

 TLE 7263E

Pin Configuration

Table 1 Pin Definitions and Functions

Pin Symbol Function
9 MON1, Monitoring / Wake-Up Inputs; bi level sensitive inputs used
10 MON2, to monitor signals coming from, for example, an external
11 MON3, switch panel; also used as wake-up input during cyclic
12 MON4 sensing in low power modes (MON4 is exempted from
“cyclic sense” as this input is permanently active)
8 VS Power Supply Input; block to GND directly at the IC with
ceramic capacitor; (ferrite recommended for better EMC
behavior)
15 VCC1 Voltage Regulator Output (V1); 5 V supply; to stabilize
block to GND with an external capacitor CQ ≥ 10 µF,
ESR < 6 Ω
16 VCC2 Voltage Regulator Output (V2); 5 V supply; to stabilize
block to GND with an external capacitor CQ ≥ 10 µF,
ESR < 6 Ω
32 WKO Wake-Up Event Output; indicates wake up via monitoring
inputs, CAN or LIN during Sleep or Stop Mode; active low;
wake up sets device to Standby Mode
33 FSO Fail Safe Output; to supervise and control critical
applications, high when watchdog is correctly served, low at
any reset condition; active low
26 RO Reset Output; open drain output, integrated pull-up,
active low
13 SI Sense Comparator Input; for monitoring of external
voltages, to program the detection level connect external
voltage divider
17 INT Interrupt Output; output to monitor sense comparator input
condition; input for enabling the Flash Programming Mode
(voltage to be applied > 7 V)
5 MTS Master Termination Switch; output used to turn-on the
termination/pull-up resistor of a LIN master
34 RxDLIN LIN Transceiver Data Output; according to the ISO 9141
and LIN specification 1.3 and 2.0; push-pull output; LOW in
dominant state
35 TxDLIN LIN Transceiver Data Input; according to ISO 9141 and
LIN specification 1.3 and 2.0

Data Sheet 5 Rev. 1.51, 2007-06-22

 TLE 7263E

Pin Configuration

Table 1 Pin Definitions and Functions (cont’d)

Pin Symbol Function
4 LIN LIN Bus; Bus Line for the LIN interface, according to
ISO 9141 and LIN specification 1.3 and 2.0
29 DISPI SPI Data Input; receives serial data from the control device;
serial data transmitted to DI is a 16-bit control word with the
Least Significant Bit (LSB) transferred first: the input has a
pull-down and requires CMOS logic level inputs; DI will
accept data on the falling edge of CLK-signal
28 DOSPI SPI Data Output; this tri-state output transfers diagnosis
data to the control device; the output will remain 3-stated
unless the device is selected by a low on Chip-Select-Not
(CSN)
30 CLKSPI SPI Clock Input; clock input for shift register; CLK has an
internal pull-down and requires CMOS logic level inputs
31 CSNSPI SPI Chip Select Not Input; CSN is an active low input; serial
communication is enabled by pulling the CSN terminal low;
CSN input should only be transitioned when CLK is low; CSN
has an internal pull-up and requires CMOS logic level inputs
7 OUTHS High Side Switch Output; controlled via SPI, in SBC Sleep
Mode controlled by internal cyclic sense function when
selected
24 TxDCAN CAN Transmit Data Input; integrated pull-up
25 RxDCAN CAN Receive Data Output
21 SPLIT CAN Termination Output; to support the recessive voltage
level of the bus lines
20 CANH CAN High Line Output
22 CANL CAN Low Line Input
27 STS Send-to-Sleep; to switch the SBC back into low current
mode during cyclic wake
1, 2, GND Ground
6,14,
18,19,
23,36
3 NC Not Connected Internally; leave open or connect to GND
EP EP Exposed Pad; internally connected to GND; connect to
GND on board

Data Sheet 6 Rev. 1.51, 2007-06-22

 TLE 7263E

Block Diagram

3 Block Diagram

VS OUTHS
Interrupt STS
control
Drive +
Protection CSN
INT Early Warning CLK
VS Supervisor SPI
SI DI

DO

VCC1
Over Oscillator V CC1
Current Timebase
Over -
voltage +
Reset
Generator
Band RO
+
Gap
LDO 1 Window
FSO
Watchdog

V CC2
Over
Current LDO 2
Over
voltage
MON1

MON2
Wake-Up HS-CAN
MON3 Logic Mode Control
V CC1
MON4

CANH Driver
Output Diagnosis Logic WKO
CANL Stage Temp.-
Protection

+ TxDCAN
timeout
VCC1

SPLIT

MUX RxDCAN

Receiver + Bus
HS-CAN Transceiver Failure Detection

VS
Vs MTS
LIN Mode
Control
Driver
30 kOhm
Output Temp.- TxDLIN
LIN Stage Protection V CC1

Receiver

Filter /
RxDLIN
Wake-Up

LIN Transceiver

GND blockdiagramm7263

Figure 2 Functional Block Diagram

Data Sheet 7 Rev. 1.51, 2007-06-22

 TLE 7263E

Features

4 Features
The TLE 7263E incorporates a lot of features, that are listed in Table 2 below. A short
description of the features is given in “Operation Modes” on Page 9.
Table 2 Truth Table of the TLE 7263E
Feature SBC SBC SBC SBC CAN
Active Standby Stop Sleep RxD-only
Mode Mode Mode Mode Mode
VCC, V1, 5 V ON ON ON OFF ON
VCC, V2, 5 V ON ON/OFF ON/OFF OFF1) ON
Reset RO ON ON ON OFF ON
Window Watchdog ON ON ON/OFF OFF/[ON] ON
Fail Safe Output ON ON ON OFF ON
Sense input ON ON ON OFF ON
Monitoring pins ON ON ON ON ON
HS-switch ON ON ON OFF ON
HS-cyclic-sense OFF OFF ON ON OFF
16-bit SPI ON ON ON OFF ON
CAN/LIN wake-up OFF/“Sleep” ON ON ON OFF
via bus message
CAN Transmit ON/“Sleep” OFF OFF OFF OFF
CAN Receive ON/“Sleep” OFF OFF OFF ON
LIN Transmit ON/“Sleep” OFF OFF OFF ON
LIN Receive ON/“Sleep” OFF OFF OFF ON
RxDLIN L/H active low active low low L/H
wake-up wake-up
interrupt interrupt
RxDCAN L/H active low active low low L/H
wake-up wake-up
interrupt interrupt
INT output active low active low active low low active low
early early early early
warning warning warning warning
WKO output OFF active low active low low OFF
wake-up wake-up
1) In Sleep Mode the Vcc2 should be switched off. This is the default setting at the SPI

Data Sheet 8 Rev. 1.51, 2007-06-22

 TLE 7263E

Features

4.1 Operation Modes

This System Basis Chip (SBC) offers five main operation modes that are controlled via
three mode select bits MS1, MS2 and MS3 within the SPI: SBC Active, Standby, Sleep
and Stop mode, as well as CAN Receive-Only mode. After powering-up the SBC, it
starts-up in SBC Standby Mode, waiting for the microcontroller to finish its startup and
initialization sequences. From this transition mode the SBC can be switched via SPI
command into the desired operating mode (The device should not be switched directly
from Standby Mode to Sleep or Stop Mode). All modes are selected via SPI bits or
certain operation conditions, e.g. external wake-up events.
The SBC Active Mode, that is used in order to transmit and receive CAN and LIN
messages, supports two additional sub-modes, “CAN Sleep” and “LIN Sleep”. During
these sub-modes the SBC remains its voltage regulators running in order to supply
external devices. Also, the line termination of the “sleeping” bus transceiver is turned-off
respectively.
During SBC Sleep Mode, the lowest power consumption is achieved, by having its main
voltage regulator switched-off. As the microcontroller can not be supplied, the integrated
window watchdog might be disabled in Sleep Mode via SPI bit. However, it can be
turned-on for periodically waking-up the system, e.g. ECU, by generating a reset.
In case an external microcontroller needs to be supplied with its quiescent current, the
SBC Stop Mode can be chosen. In this mode the main voltage regulator remains active.
Optionally, the second voltage regulator can be turned-on or off via the SPI prior to
entering one of the respective power saving modes. The integrated window watchdog
remains active until the microcontroller enters its power saving mode (“Stop Mode”). This
power saving mode is assumed to be reached once the current consumption is below a
certain threshold (see Watchdog current threshold, Table and “Window Watchdog,
Reset” on Page 26).
In both low power modes the internal bus transceivers, including the line termination, are
turned off while the wake-up capabilities via bus message or monitoring pins are still
active. The SBC offers Sleep and Stop Mode in conjunction with or without the Cyclic
Sense/Wake feature. If the Cyclic Sense/Wake feature is selected, two possible states
can be entered during Sleep/Stop Mode: HS-On and HS-Off (see text and respective
state diagram).
The Cyclic Sense feature can be used to supply an external wake-up circuitry
periodically, and is entered upon activation via SPI command. In cyclic sense HS-On
state, the High-Side switch is activated for a certain “on-time” and provides supply
voltage at its OUTHS pin. Within this on-time the SBC starts sampling of the
monitoring/wake-up lines. On-time as well as time period are programmable via the SPI
control word. A wake-up at the monitoring / wake-up pins during the on-time as well as
a message at the CAN or LIN bus lines automatically sets the TLE 7263E into SBC
Standby mode, and turns-on the main voltage regulator VCC1. The digital RxDCAN/RxDLIN
lines, that are monitored by the microcontroller during power saving, are pulled low with

Data Sheet 9 Rev. 1.51, 2007-06-22

 TLE 7263E

Features

respect to the wake-up source (CAN or LIN). Furthermore, the wake-up source is
indicated within the SPI status word. Additionally, the wake-up capabilities of the
monitoring / wake-up pins can be configured via SPI.
If Cyclic Wake is entered upon SPI command, the High-Side switch is turned-on
immediately (HS-On state), providing supply voltage at the OUTHS pin. Once the HS-
On state is entered, a transition to the HS-Off state can be triggered by a pulse with a
minimum width at the STS pin (see STS pulse width, Table ). The microcontroller fully
controls the signal level at the STS pin, and this way determines the duration of the HS-
On state. As of now the HS-Off state is automatically terminated according to the Cyclic
Wake period selected via SPI, or by a CAN or LIN message.

Start Up
Power Up

SBC Standby Mode

Vcc1
ON

SBC Stop Mode SBC Sleep Mode

MS2 MS1 MS0 Vcc1 MS2 MS1 MS0 Vcc1

1 1 1 ON 1 0 0 OFF

SBC Active Mode

MS2 MS1 MS0 Vcc1

0 1 1 ON

SBC Active Mode:

CAN RxD Only
„CAN Sleep“
MS2 MS1 MS0 Vcc1 MS2 MS1 MS0 Vcc1
0 0 1 ON 1 0 1 ON

SBC Active Mode:

LIN RxD Only
„LIN Sleep“
MS2 MS1 MS0 Vcc1 MS2 MS1 MS0 Vcc1
0 1 0 ON 1 1 0 ON

modes_TLE7263

Figure 3 Functional Overview “SBC Operation Modes”

Data Sheet 10 Rev. 1.51, 2007-06-22

 TLE 7263E

Features

4.2 SBC Sleep Mode without Cyclic Sense

In order to reduce the current consumption to a minimum, the SBC offers a Sleep Mode
without Cyclic Sense (see Figure 4). This mode is entered via SPI command, and turns-
off the integrated bus transceivers and respective termination, main voltage regulator as
well as the High-Side switch. Upon a voltage level change at the monitoring/wake-up
pins or by a CAN or LIN message the SBC Sleep Mode will be terminated and the SBC
Standby Mode will automatically be entered.

SBC Active Mode

SBC Standby Mode Start Up
MS2 MS1 MS0 Vcc1 Vcc1 Power Up
0 0/1 0/1 ON ON

µController SPI-Command:
- disable „cyclic sense function“ via SPI Timing Bits
- select SBC Sleep Mode via SPI Mode Bits
transition caused by:
- window watchdog activation / deactivation via SPI
- event at MONx inputs
[can remain active as periodic reset timer]
- CAN message
- LIN message
[SPI indicates source]

Initialization of
MONx inputs 1)

SBC Sleep Mode

MS2 MS1 MS0 Vcc1

1 0 0 OFF

HS-Switch = OFF 1)
if initialization fails, device is
switched into SBC Standby mode

sleep_TLE7263

Figure 4 State Diagram “SBC Sleep Mode without Cyclic Sense”

Note: To switch into Low Power Mode from Standby Mode the device should be
switched into Normal Mode first. This is required to reset the CAN and LIN
transceiver to ensure correct wakeup as well as to ensure the correct function of
the RO pin when going to Sleep Mode. The time the device is in Normal Mode
before going to Low Power Mode should be long enough that the Vcc2 is up. This
can be released by a wait time or by reading the status of Vcc2 via SPI (bit13).

Data Sheet 11 Rev. 1.51, 2007-06-22

 TLE 7263E

Features

4.3 SBC Sleep Mode with Cyclic Sense

In order to reduce the current consumption to a minimum, but still supply a wake-up
circuit periodically, the SBC offers a Sleep Mode with Cyclic Sense (see Figure 5). This
mode is entered via SPI command, and turns-off the integrated bus transceivers and
respective termination, as well as the main voltage regulator. The High-Side switch is
turned-on according to the SPI timings setting for cyclic sense, as there is the cyclic
sense period and the on-time. Upon a voltage level change at the monitoring/wake-up
pins or by a CAN or LIN message the SBC Sleep Mode will be terminated and the SBC
Standby Mode will automatically be entered. The respective RxD pin of the transceiver
that generated the wake-up will be pulled low.

SBC Active Mode

SBC Standby Mode Start Up
MS2 MS1 MS0 Vcc1 Vcc1 Power Up
0 0/1 0/1 ON ON

µController SPI-Command:
- select „cyclic sense period“ via SPI Timing Bits
- select HS-Switch on-time via SPI „On-Time Bit“
- select SBC Sleep Mode via SPI Mode Bits
transition caused by:
- window watchdog activation / deactivation via SPI
- event at MON1 - 3 inputs
[can remain active as periodic reset timer]
[only during HS-ON state]
- event at MON4 input
- CAN message
Initialization of - LIN message
MONx inputs 1) [SPI indicates source]

SBC Sleep Mode

MS2 MS1 MS0 Vcc1

1 0 0 OFF

HS-Switch = OFF

„sense period“ after „on-time“

HS cyclic sense

MS2 MS1 MS0 Vcc1

1 0 0 OFF
1)
HS-Switch = ON if initialization fails, device is
switched into SBC Standby mode

cyclic_sense_sleep_TLE7263

Figure 5 State Diagram “SBC Sleep Mode with Cyclic Sense”

Data Sheet 12 Rev. 1.51, 2007-06-22

 TLE 7263E

Features

4.4 SBC Sleep Mode with Cyclic Wake

The SBC Sleep Mode has the advantage of reducing the current consumption to a
minimum. During this mode the integrated voltage regulator for external supply is turned
off. In case the connected microcontroller needs to get activated periodically, the Cyclic
Wake feature in combination with the SBC Sleep Mode can be activated (see Figure 6).

SBC Active Mode

SBC Standby Mode Start Up
MS2 MS1 MS0 Vcc1 Vcc1 Power Up
0 0/1 0/1 ON ON

µController SPI-Command:
- select „cyclic wake“ via SPI Bit
- select „cyclic wake period“ via SPI Timing Bits
- select HS-Switch on-time via SPI „On-Time Bit“
- select SBC Sleep Mode via SPI Mode Bits
- window watchdog activation / deactivation via SPI

SBC Sleep Mode

select SBC
Initialization of MS2 MS1 MS0 Vcc1
operating mode
MONx inputs 1) 1 1 1 OFF

HS-Switch = OFF

automatic transition by:

- cyclic wake period
- CAN message STS
- LIN message µC 2)

HS Cyclic Wake
WKO
MS2 MS1 MS0 Vcc1
cyclic wake-up
1 1 1 ON
sampling of MON1…3 inputs
HS-Switch = ON
[MON4 active permanently]

1)
if initialization fails, device is
switched into SBC Standby mode cyclic_wake_sleep_TLE7263

Figure 6 State Diagram “SBC Sleep Mode with Cyclic Wake”

Data Sheet 13 Rev. 1.51, 2007-06-22

 TLE 7263E

Features

4.5 SBC Stop Mode without Cyclic Sense

The SBC Stop Mode has the advantage of reducing the current consumption to a
minimum, while supplying the microcontroller with its quiescent current during its power
saving mode (“Stop”). This mode is entered via SPI command, and turns-off the
integrated bus transceivers and respective termination, but the main voltage regulator
remains active.
A voltage level change at the monitoring / wake-up pins will, in contrast to the behavior
in Sleep Mode, generate a pulse at the WKO pin that is monitored by the microcontroller,
e.g. at an external interrupt input. In case the wake-up event was a CAN or LIN message,
the respective RxD pin will be pulled low. (The microcontroller itself has to take care of
switching SBC modes after a wake-up event notification (see Figure 7).)

SBC Active Mode

SBC Standby Mode Start Up
MS2 MS1 MS0 Vcc1 Vcc1 Power Up
0 0/1 0/1 ON ON

transition caused by:

- event at MONx inputs
- CAN message
µController SPI-Command: - LIN message
- disable „cyclic sense function“ via SPI Timing Bits [SPI indicates source]
- select SBC Stop Mode via SPI Mode Bits
- window watchdog activation / deactivation via SPI
[„off“ once current consumption below threshold]

wake event notification [to µC]:

Initialization of - CAN msg. => RxDCAN (low)
MONx inputs 1) - LIN msg. => RxDLIN (low)
- MONx => WKO

SBC Stop Mode

MS2 MS1 MS0 Vcc1

1 1 1 ON
1)
HS-Switch = OFF if initialization fails, device is
switched into SBC Standby mode

stop_TLE7263

Figure 7 State Diagram “SBC Stop Mode without Cyclic Sense”

Data Sheet 14 Rev. 1.51, 2007-06-22

 TLE 7263E

Features

4.6 SBC Stop Mode with Cyclic Sense

The SBC Stop Mode has the advantage of reducing the current consumption to a
minimum, while supplying the microcontroller with its quiescent current during its power
saving mode (“Stop”). This mode is entered via SPI command, and turns-off the
integrated bus transceivers and respective termination, but the main voltage regulator
remains active. The High-Side switch is turned-on according to the SPI timings setting
for cyclic sense, as there is the cyclic sense period and the on-time. A voltage level
change at the monitoring/wake-up pins will, in contrast to the behavior in Sleep Mode,
generate a pulse at the WKO pin that is monitored by the microcontroller, e.g. at an
external interrupt input. In case the wake-up event was a CAN or LIN message, the
respective RxD pin will be pulled low. (The microcontroller itself has to take care of
switching SBC modes after a wake-up event notification (see Figure 8).)

SBC Active Mode

SBC Standby Mode Start Up
MS2 MS1 MS0 Vcc1 Vcc1 Power Up
0 0/1 0/1 ON ON

transition caused by:

- event at MON1 - 3 inputs
µController SPI-Command:
[only during HS-ON state]
- select „cyclic sense period“ via SPI Timing Bits
- event at MON4 input
- select HS-Switch on-time via SPI „On-Time Bit“
- CAN message
- select SBC Stop Mode via SPI Mode Bits
- LIN message
- window watchdog activation / deactivation via SPI
[SPI indicates source]
[„off“ once current consumption below threshold]

Initialization of
MONx inputs 1)

wake event notification [to µC]:

SBC Stop Mode - CAN msg. => RxDCAN (low)
- LIN msg. => RxDLIN (low)
MS2 MS1 MS0 Vcc1
- MONx => WKO
1 1 1 ON

HS-Switch = OFF

“sense period“ after „on-time“

1)
if initialization fails, device is
HS Cyclic Sense switched into SBC Standby mode
MS2 MS1 MS0 Vcc1
1 1 1 ON

HS-Switch = ON

cyclic_sense_stop_TLE7263

Figure 8 State Diagram “SBC Stop Mode with Cyclic Sense”

Data Sheet 15 Rev. 1.51, 2007-06-22

 TLE 7263E

Features

4.7 SBC Stop Mode with Cyclic Wake

The SBC Stop Mode has the advantage of reducing the current consumption to a
minimum, while supplying the microcontroller with its quiescent current during its power
saving mode (“Stop”). This mode is entered via SPI command, and turns-off the
integrated bus transceivers and respective termination, but the main voltage regulator
remains active. In contrast to Cyclic Sense the HS-On state is entered once Cyclic Wake
is selected, immediately providing supply voltage at the OUTHS pin. The microcontroller
determines the duration of the HS-On state via the STS input pin (see Figure 9). Further
transitions from that HS-Off into the HS-On state are done by the selected cyclic wake
period or by a bus message. The microcontroller is notified by the WKO (Wake-Up
Output) that the HS-On state has been entered. Further notification is done in the same
way as for Cyclic Sense in Stop Mode.

SBC Active Mode

SBC Standby Mode Start Up
MS2 MS1 MS0 Vcc1 Vcc1 Power Up
0 0/1 0/1 ON ON

µController SPI-Command:
- select „cyclic wake“ via SPI Bit
- select „cyclic wake period“ via SPI Timing Bits
- select HS-Switch on-time via SPI „On-Time Bit“
- select SBC Stop Mode via SPI Mode Bits
- window watchdog activation / deactivation via SPI
[„off“ once current consumption below threshold]

SBC Stop Mode

select SBC
Initialization of MS2 MS1 MS0 Vcc1
operating mode
MONx inputs 1) 1 1 1 ON

HS-Switch = OFF

automatic transition by:

- cyclic wake period
- CAN message via STS pin STS
- LIN message or µC 2)
after „on-time“

HS Cyclic Wake
WKO
MS2 MS1 MS0 Vcc1
cyclic wake-up
1 1 1 ON
sampling of MON1…3 inputs
HS-Switch = ON
[MON4 active permanently]
µC wake-up inputs

1) if initialization fails, device is

switched into SBC Standby mode

2)
window watchdog activated
automatically once current
threshold is exceeded cyclic_wake_stop_TLE7263

Figure 9 State Diagram “SBC Stop Mode with Cyclic Wake”

Data Sheet 16 Rev. 1.51, 2007-06-22

 TLE 7263E

Features

Continuous Timer Mode (CTM) for “Cyclic Wake Timer”

Upon start of the “cyclic wake timer” in Cyclic Wake Mode the operating mode might be
changed to “SBC Active Mode” by the microcontroller, e.g. in order to transmit data via
the CAN or LIN transceiver. In this case the timer continues running with the selected
period started in Cyclic Wake Mode. This behavior guarantees the periodic generation
of a wake-up signal at the WKO pin, even in case of a mode switch. However, this
provides that the time spent in SBC Active Mode is not exceeding the selected period.
Should a time-out (end of selected period) occur in SBC Active Mode before the Cyclic
Wake Mode is re-entered, the SBC will generate an interrupt signal at its WKO pin if the
CTM feature is enabled via the respective SPI bit (see Figure 11).
When the CTM feature is set in the SPI, a wake-up event at the CAN bus in “SBC Active
CAN Sleep” mode or at the LIN bus in the “SBC Active LIN Sleep” mode results in
switching WKO “low” in addition to switching the RxD to “low”.

4.8 Dual Low Dropout Voltage Regulator

The dual low dropout voltage regulator integrated in the TLE 7263E is able to drive
external as well as internal loads, e.g. CAN-circuit supplied via VCC2, even in case of a
bus short circuit. Its output voltage tolerance is better than ±2%. The maximum output
current for external loads is limited to 150 mA (VCC1), e.g. for microcontroller supply, and
150 mA (VCC2) for internal CAN module and, e.g. for external sensor supply. The two
voltage regulator outputs are protected against overload and overtemperature. The
thermal pre-warning flag might be used by the microcontroller to reduce the power
dissipation of the TLE 7263E by switching off functions of minor priority until the
temperature threshold of the thermal shutdown is reached.
An external reverse current protection is required at the pin VS to prevent the output
capacitor from being discharged by negative transients or low input voltage.
A capacitor of 10 µF at the supply voltage input VS buffers the input voltage. In
combination with the required reverse polarity diode this prevents the device from
detecting power down conditions in case of negative transients on the supply line.
Stability of the output voltage is guaranteed for output capacitors CQ ≥ 100 nF,
nevertheless it is recommended to use capacitors CQ ≥ 10 µF to buffer the output voltage
and therefore improve the reset behavior at input voltage transients.

Data Sheet 17 Rev. 1.51, 2007-06-22

 TLE 7263E

Features

4.9 CAN Transceiver

The TLE 7263E is optimized for high speed data transmission up to 1 MBaud in
automotive applications and is compatible to the ISO 11898 standard. It works as an
interface between the CAN protocol controller and the physical bus lines.
This HS-CAN module also supports extended bus error detection via a general error flag
as well as individual notification flags, e.g. temperature shutdown and TxD time-out flag,
within the SPI.
To reduce EMI the dynamic slopes of the CANL and CANH signals both are limited and
symmetric. This allows the use of an unshielded twisted or parallel pair of wires for the
bus.
Furthermore there is implemented a time-out feature to prevent the bus from being
blocked by a permanently dominant TxD input signal. Both, the CANL and CANH output
stage are automatically disabled after the delay time tTxD.
In order to protect the transceiver output stages from being damaged by shorts on the
bus lines, current limiting circuits are integrated. The CANL and CANH output stage
respectively are protected by an additional temperature sensor, that disables them as
soon as the junction temperature exceeds the maximum value. During the temperature
shut-down condition of the CAN output stages receiving messages from the bus lines is
still possible.
Wake-Up Indication: A bus wake-up via a CAN message (minimum dominant time
t > tWU) from low power mode sets the RxD pin and the WKO pin to low. In addition, the
Vcc2, which supplies the CAN output stage is switched ON.The CAN transceiver has to
be enabled to reset the wake-up capability after a bus wake event and after power-up.
Bus Failure Flag: signalizes a bus line short circuit condition to GND, VS or VCCx via
SPI bit 11 in the SPI Output Data “CAN Bus Failure”.
Remarks: Flag is set after four consecutive recessive to dominant cycles on pin TxD
when trying to drive the bus dominant. The bus failure flag is cleared upon 4 recessive
to dominant edges at TxD without failure condition.
Local Failure Flag: signalizes the local failure conditions listed in the text below via SPI
bit 10 in the SPI Output Data “CAN Local Failure”.
Remark: Flag is cleared upon dominant level at RxD while TxD is recessive.
General: release of the transmitter stage only after transition into CAN RxD Only mode
and transition back into SBC Active Mode.
TxD Dominant Failure Detection
At permanent dominant signal for t > tTxD at TxD the local failure flag is set and the
transmitter stage is turned off.
Remarks: none

Data Sheet 18 Rev. 1.51, 2007-06-22

 TLE 7263E

Features

RxD Permanent Recessive Clamping

Internal RxD signal does not match signal at RxD pin because the RxD pin is pulled to
HIGH (permanent HIGH). This results in setting the local failure flag and disabling of the
receiver stage
Remark: the flag is cleared when RxD signal gets dominant.
TxD to RxD Short Circuit
Caused by a short circuit between RxD and TxD. The local failure flag is set and the
transmitter stage is disabled.
Remark: the flag is cleared once the short circuit condition is removed.
Bus Dominant Clamping
At a permanent dominant signal at the CAN bus for t > tBUS the local failure flag is set.
Remark: none
Over Temperature Detection
Once the maximum junction temperature at the driving stages exceeded, the local failure
flag is set and the transmitter stage is disabled.
Remark: the flag is cleared once RxD gets dominant. Bus only released after the next
dominant bit in TxD.

Split Circuit
The split circuitry is activated during SBC Active and RxD Only Mode and deactivated
(SPLIT pin high omic) during SBC Sleep, Stop and Standby Mode. The SPLIT pin is used
to stabilize the recessive common mode signal in SBC Active Mode and RxD Only mode.
This is realized with a stabilized voltage of 0.5 VCC2 at the SPLIT pin.
A correct application of the SPLIT pin is shown in Figure 10. The split termination for the
left and right node is realized with two 60 Ohm resistances and one 10nF capacitor. The
center node in this example is a stub node and the recommended value for the split
resistances is 1.5 kOhm.

Data Sheet 19 Rev. 1.51, 2007-06-22

 TLE 7263E

Features

CANH CANH

TLE 7263 R 60Ohm 60Ohm TLE 7263 R

split CAN
SPLIT split
termination Bus SPLIT
termination
10nF 10nF

60Ohm 60Ohm

CANL CANL
10nF

split 1,5 kOhm 1,5 kOhm

termination
at stub

CANH SPLIT CANL

TLE 7263 R

Figure 10 Application of the SPLIT pin for normal nodes and one stub node

4.10 LIN Transceiver

The TLE 7263E offers a transceiver, which is compatible to ISO 9141 and LIN
specification 2.0. For fail safe reasons the transceiver already has a pull-up resistor of
30 kΩ implemented. In order to achieve the required timing for the dominant to recessive
transition of the bus signal an additional external termination resistor of 1 kΩ is required,
when the LIN node is used as a master. This termination resistor will automatically be
turned off via the “Master Termination Switch” pin (MTS) once the LIN module enters LIN
Sleep Mode or when the SBC enters Sleep Mode. The transceiver is protected against
short to battery and short to GND.
For LIN automotive applications in the United States a dedicated mode by the name
“Low Slope Mode” can be used. This mode limits the maximum data transmission rate
to 10.4 kBaud by switching to a different slew rate. Operating with the default slew rate
at up to 20 kBaud may cause interferences with the AM radio band.
A bus wake-up via a LIN message (minimum dominant time t > twake) from low power
mode sets the RxD pin and the WKO pin to low. in addition the MTS is switched ON. The
LIN transceiver has to be enabled to reset the wake-up capability after a bus wake event
and after power-up.
In case of a “TxD dominant time out failure” or a “transmitter thermal shutdown” the SPI
bit 9 is set. After a SPI read-out this bit will be reset unless one of the failure conditions
is still present.
Note: In case of a short to GND on the LIN bus a RxD dominant signal is generated by
the SBC. In the case that RxD is dominant the device can not go into low power
mode from normal mode.

Data Sheet 20 Rev. 1.51, 2007-06-22

 TLE 7263E

Features

4.11 SPI (Serial Peripheral Interface)

The 16-bit wide Programming or Input Word (see Table 3) is read in via the data input
DI, which is synchronized with the clock input CLK supplied by the µC. The Diagnosis or
Output Word appears synchronously at the data output DO (see Figure 10).
The transmission cycle begins when the chip is selected by the Chip Select Not input
CSN (“low” active). After the CSN input returns from L to H, the word that has been read
in becomes the new control word. The DO output switches to tristate status at this point,
thereby releasing the DO bus for other usage.
The state of DI is shifted into the input register with every falling edge on CLK. The state
of DO is shifted out of the output register after every rising edge on CLK. The number of
received input clocks is supervised by a modulo-16 operation and the Input / Control
Word is discarded in case of a mismatch. This error is flagged by the WKO set to “low”
and in the following SPI output by a “high” at the data output (DO pin) before the first
rising edge of the clock is received.

MSB LSB

Input 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Data
CS1 CS0 MS2 MS1 MS0

WD VCC2 Configuration Mode Selection

On/Off On/off Configuration Registers Select
Bits

SI MON4 MON3 MON2 MON1 LIN Reset Reset 00 000

Res.
On/Off On/Off On/Off On/Off On/Off 10.4k Delay Thres. not valid

OUTHS 01 Active 001

Reserved On/Off
CAN Sleep

CTM
Select
OUTHS
OUTHS
Cyclic
Sense /
Cyclic Sense / Wake Timing 10 Active 010
On/Off
„off“
On-Time
Wake Bit Position: 9 .. 5 LIN Sleep

Window Watchdog Timing 11 011

Reserved 0
Bit Position: 10 .. 5
Active
(Watchdog Trigger Register)
100
Sleep

101
CAN RxD Only

110
LIN RxD Only

111
Stop
SPI_Bit_Settings

Figure 11 16-Bit SPI Input Data / Control Word

Data Sheet 21 Rev. 1.51, 2007-06-22

 TLE 7263E

Features

Table 3 SPI Input Data Bits

IBIT Input Data
0…2 Mode Selection
3…4 Configuration Selection (determine meaning of “Configuration Setting Bits”)
5 … 13 Configuration Settings (meaning based on “Configuration Selection Bits”)
14 VCC2 Activation (power saving modes only)
15 Window Watchdog “on”/“off” (power saving modes only)

Table 4 Mode Selection Bits

MS2 MS1 MS0 Mode Selection: SBC Mode
0 0 0 “reserved” / not valid
0 0 1 SBC Active Mode: “CAN Sleep”
0 1 0 SBC Active Mode: “LIN Sleep”
0 1 1 SBC Active Mode (CAN & LIN “on”)
1 0 0 SBC Sleep (CAN, LIN & VReg “off”)
1 0 1 SBC Active mode : CAN Transceiver: RxD-Only
1 1 0 SBC Active mode : LIN Transceiver: RxD-Only
1 1 1 SBC Stop Mode (CAN & LIN “off”)

Table 5 Configuration Selection Bits

CS1 CS0 Configuration Selection
0 0 General Configuration
0 1 Integrated Switch Configuration
1 0 Cyclic Sense / Wake Configuration
1 1 Window Watchdog Configuration

Data Sheet 22 Rev. 1.51, 2007-06-22

 TLE 7263E

Features

Table 6 General & Integrated Switch Configuration

Pos. General Configuration1) Integrated Switch Configuration2)
5 Reset Threshold (see Table : “Reset OUTHS “on” / “off”
Generator”, “0” = VRT1 /
“1” = VRT2)
6 Reset Delay (“0” = 5 ms / “1” = 0.5 ms) “reserved” / not used
7 LIN “Low Slope Mode” (10.4 kBaud) “reserved” / not used
8 MON1 Input Wake-Up Capability “reserved” / not used
9 MON2 Input Wake-Up Capability “reserved” / not used
10 MON3 Input Wake-Up Capability “reserved” / not used
11 MON4 Input Wake-Up Capability “reserved” / not used
12 Sense Input (SI) “on” / “off” “reserved” / not used
13 “reserved” / not used “reserved” / not used
1) “1” = ON (enable), “0” = OFF (disable)
2) “1” = ON, “0” = OFF

Table 7 Cyclic Sense / Wake & Window Watchdog Period Settings1)

Pos. Cyclic Sense / Wake Configuration Window Watchdog Configuration
5 Cyclic Period Bit 0 (T0) Watchdog Period Bit 0 (T0)
6 Cyclic Period Bit 1 (T1) Watchdog Period Bit 1 (T1)
7 Cyclic Period Bit 2 (T2) Watchdog Period Bit 2 (T2)
8 Cyclic Period Bit 3 (T3) Watchdog Period Bit 3 (T3)
9 Cyclic Period Bit 4 (T4) Watchdog Period Bit 4 (T4)
10 Cyclic Sense / Wake Selection Watchdog Period Bit 5 (T5)
(“0” = Cyclic Sense / “1” = Cyclic Wake)
11 OUTHS On-Time Selection “0” [mandatory]
(“0” = 500 µs / “1” = 100 µs)
12 Cyclic Wake Mode only: “reserved” / not used
Select OUTHS “off” via STS / On-Time
(“0” = via STS / “1” = via HS On-Time)
13 Continuous Timer Mode (incl. WKO) “reserved” / not used
(“0” = “off” / “1” = “on” )
1) “1” = ON, “0” = OFF

Data Sheet 23 Rev. 1.51, 2007-06-22

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Features

Table 8 Cyclic Sense / Wake Period Settings

T4 T3 T2 T1 T0 Cyclic Sense or
Cyclic Wake Period
0 0 0 0 0 Cyclic Sense / Wake “off”
0 0 0 0 1 16 ms
0 0 0 1 0 32 ms
0 0 0 1 1 48 ms
0 0 1 0 0 64 ms
0 0 1 0 1 80 ms
0 0 1 1 0 96 ms
… … … … … … ms
1 1 1 1 1 496 ms

Table 9 Window Watchdog Reset Period Settings

T5 T4 T3 T2 T1 T0 Window Watchdog
Reset Period
0 0 0 0 0 0 “not a valid selection”
0 0 0 0 0 1 16 ms
0 0 0 0 1 0 32 ms
0 0 0 0 1 1 48 ms
0 0 0 1 0 0 64 ms
0 0 0 1 0 1 80 ms
0 0 0 1 1 0 96 ms
0 … … … … … … ms
1 1 1 1 1 1 1008 ms

Data Sheet 24 Rev. 1.51, 2007-06-22

 TLE 7263E

Features

Table 10 SPI Output Data

Pos. Output Data “active”1) Output Data “after wake-up”2)
0 VCC1 Temperature Prewarning VCC1 Temperature Prewarning
1 HS Overcurrent HS Overcurrent
2 OUTHS UV / Temp. Shut-Down OUTHS UV / Temp. Shut-Down
3 Window Watchdog Reset Window Watchdog Reset
4 MON1 Logic Input Level Wake-Up via MON1
5 MON2 Logic Input Level Wake-Up via MON2
6 MON3 Logic Input Level Wake-Up via MON3
7 MON4 Logic Input Level Wake-Up via MON4
8 MONx Initialization Failure MONx Initialization Failure
9 LIN Failure Bus Wake-Up via LIN Msg.
10 CAN Local Failure Bus Wake-Up via CAN Msg.
11 CAN Bus Failure End of Cyclic Wake Period
12 VCC1 Fail (active low) VCC1 Fail (active low)
13 VCC2 Fail (active low) VCC2 Fail (active low)
14 VINT Fail (active low) VINT Fail (active low)
15 “reserved” / not used “reserved” / not used
1) “1” = ON (enable), “0” = OFF (disable)
2) “1” = ON, “0” = OFF

Data Sheet 25 Rev. 1.51, 2007-06-22

 TLE 7263E

Features

4.12 Window Watchdog, Reset

When the output voltage Vcc1 exceeds the reset threshold voltage the reset output RO is
switched HIGH after a delay time of typ. 5 ms. This is necessary for a defined start of the
microcontroller when the application is switched on. As soon as an undervoltage
condition of the output voltage (VCC1 < VRT) appears, the reset output RO is switched
LOW again. The LOW signal is guaranteed down to an output voltage VCC1 ≥ 1 V. Please
refer to Figure 19, Reset Timing Diagram.
After the above described delayed reset (LOW to HIGH transition of RO) the window
watchdog circuit is started by opening a long open window of typ. 64 ms. The long open
window allows the microcontroller to run its initialization sequences and then to trigger
the watchdog via the SPI. A watchdog trigger is detected as a write access to the
“window watchdog period bit field” within the SPI control word. In order to distinguish the
watchdog from the cyclic sense/wake timing register the “Configuration Select Bits”
needs to be set accordingly (see “SPI (Serial Peripheral Interface)” on Page 21). The
trigger is accepted when the CSN input becomes HIGH after the transmission of the SPI
word.
A correct watchdog trigger results in starting the window watchdog by opening a closed
window with a width of 50% of the selected window watchdog reset period. This period,
selected via the window watchdog timing bit field, is in the range between 16 ms and
1008 ms. This closed window is followed by a open window, with a width of 50% of the
selected period. From now on the microcontroller has to service the watchdog by
periodically writing to the window watchdog timing bit field. This write access has to meet
the open window. A correct watchdog service immediately results in starting the next
closed window (see Figure 17 "Watchdog Time-Out Definitions" on Page 54, safe
trigger area).
Should the trigger signal not meet the open window a watchdog reset is created by
setting the reset output RO low (see Reset delay time tRD). Then the watchdog again
starts by opening a long open window. In addition, a “window watchdog reset flag” is set
within the SPI until the next successful watchdog trigger to monitor a watchdog reset. For
fail safe reasons the TLE 7263E is automatically switched in SBC Standby mode if a
watchdog trigger failure occurs. This minimizes the power consumption in case of a
permanent faulty microcontroller.
In case of a watchdog reset the watchdog immediately starts with a long open window
in SBC Standby Mode.
When entering a low power mode the watchdog can be requested to be disabled via an
SPI bit (see “SPI (Serial Peripheral Interface)” on Page 21). Upon this request the
watchdog is only turned off once the current consumption at VCC1 falls below the
“watchdog current threshold”.

Data Sheet 26 Rev. 1.51, 2007-06-22

 TLE 7263E

Features

4.13 Sense Comparator using Sense Input SI and Interrupt Output

INT
The sense comparator (early warning function) compares a voltage defined by the user
to an internal reference voltage. Therefore the voltage to be supervised has to be scaled
down by a voltage divider in order to compare it to the internal sense threshold VSIth. This
feature can be used e.g. to supervise the battery voltage in front of the reverse protection
diode. The microcontroller is given a prewarning before an undervoltage reset due to low
input voltage occurs. The prewarning is flagged by setting the interrupt output INT low in
SBC Active, Standby, and Stop, as well as in CAN Receive - Only Mode, when activated
by SPI. In SBC Sleep Mode the sense function is inactive.
Calculation of the voltage divider can be easily done since the sense input current can
be neglected. An internal blanking time prevents from false triggering due to line
transients. Further improvement is possible by the use of an external ceramic capacitor
at the SI pin (see Figure 22, Application Circuit).

4.14 VINT/VCC Fail Detection via SPI Bit

Should the internal supply voltage become lower than the internal threshold VINT, th (typ.
2.5 V) the VINT-Fail, threshold SPI bit will be reset in order to indicate the low voltage
condition. All other SPI settings are also reset by this condition. The VINT Fail feature can
also be used to give an indication when the ECU has been changed and therefore a pre-
setting routine of the microcontroller has to be started.
Further there is also a VCC monitor implemented, where the VCCx is compared to the
threshold voltage VCCx-Fail, threshold and the VCC SPI bit is reset accordingly. This
monitoring is only available during voltage-regulator operation.

4.15 Monitoring / Wake-Up Inputs MON1/2/3/4 and Wake-Up Output

WKO
In addition to a wake-up from SBC Sleep mode via the CAN or LIN bus lines it is also
possible to wake-up the TLE 7263E from low power mode via the monitoring/wake-up
inputs. These inputs are sensitive to a transition of the voltage level, either from high to
low or vice versa. Monitoring is available in Active Mode and indicates the voltage level
of the inputs.
A positive or negative voltage edge at MONx in SBC Sleep or Stop Mode results in
setting the output WKO low to signal a wake-up. After a wake-up via MONx the first
transmission of the SPI diagnosis word in SBC Standby mode indicates the wake-up
source. Further SPI status word transmissions show the logic level of the monitoring
inputs.
When switching the TLE 7263E into SBC Sleep mode (cyclic sense feature activated)
the voltage level at the wake-up inputs is sensed 2 times to initialize the reference
voltage. Should this initialization fail (2 samples are unequal) the device is automatically

Data Sheet 27 Rev. 1.51, 2007-06-22

 TLE 7263E

Features

set in SBC Standby mode and the initialization error is shown indicated in the SPI status
word.
To have a defined level at a floating MONx pin a hold current is implemented. For high
level at MONx a pull up current IPU,MON is driven out of the MONx pin, for low level at
MONx a pull down current IPD,MON is drawn into the MONx pin.

4.16 High Side Switch

The high side output OUTHS is able to switch loads up to 150 mA. Its on-resistance is
2.5 Ω typ. @ 25 °C. In SBC Active, Standby, as well as in CAN and LIN Receive-Only
mode the high side output is switched on and off, respectively via an SPI input bit.
To supply external wake-up circuits in SBC Sleep Mode the output OUTHS can be
periodically switched on by the TLE 7263E itself. How Cyclic Sense works and how it is
activated is described in detail in “Operation Modes” on Page 9. Beside the cyclic
sense period can the on-time of the OUTHS be programmed to either 500 µs (default
setting) or 100 µs via SPI input bit. OUTHS undervoltage, temperature shutdown,
overcurrent as well as a temperature pre-warning is indicated by the SPI status word.
The OUTHS is protected against short circuit and overload. As soon as the undervoltage
condition of the supply voltage is met (VS < VUVOFF), the switch is automatically disabled
by the undervoltage lockout circuit. Moreover the switch is automatically disabled when
a reset or watchdog reset occurs.

4.17 Fail Safe Feature

The output FSO becomes HIGH when the watchdog is correctly serviced by the
microcontroller for the fourth time. As soon as either an undervoltage reset or watchdog
reset occurs, it is set LOW again. This feature is very useful to control critical applications
independent of the microcontroller e.g. to disable the power supply in case of a
microcontroller failure.

4.18 Send to Sleep Input STS

During Cyclic Wake the STS input is used to switch the SBC back to a low current mode
(High-Side switch “off”) when the microcontroller has completed its tasks during the
periodic wake-up phase, and before it enters its power saving mode (“Stop”) again.

4.19 Flash Program Mode

For flash programming it is useful to disable the window watchdog function. This can be
done by applying a voltage of VINT > 7.0 V at pin INT. This is useful e.g. if the flash-
memory of the micro has to be programmed and therefore a regular watchdog triggering
is not possible.

Data Sheet 28 Rev. 1.51, 2007-06-22

 TLE 7263E

Features

Additionally, the transmission rate of the integrated LIN transceiver will be changed to
maximal 150 kBaud.
The Sense Comparator using Sense Input and Interrupt Output INT can not be used with
Flash Program Mode. The Sense Input feature must be switched off via SPI.

Hints for Unused Pins

• SI: connect to GND
• OUTHS: leave open
• MON1/2/3/4: connect to GND
• INT / WKO: leave open
• RO / FSO: leave open

Data Sheet 29 Rev. 1.51, 2007-06-22

 TLE 7263E

General Product Characteristics

5 General Product Characteristics

5.1 Maximum Ratings

Table 11 Absolute Maximum Ratings

Parameter Symbol Limit Values Unit Remarks
Min. Max.
Voltages
Supply voltage VS -0.3 40 V –
Regulator output voltage VCC1, -0.3 5.5 V –
VCC2
CAN bus voltage (CANH, VCANH/L -27 40 V –
CANL)
Input voltage at SPLIT VSPLIT -27 40 V –
Input voltage at MONx and SI VWK/SI -27 40 V –
Output voltage at OUTHS and VO -27 VS + 0.3 V –
MTS
Logic input voltages (DI, CLK, VI -0.3 VCC + 0.3 V 0 V<VS<24V
CSN, STS, TxD) 0 V<VCC<5.5V
Logic output voltage (DO, RO, VDRI,RD -0.3 VCC + 0.3 V 0 V<VS<24V
INT, RxD, FSO, WKO) 0 V<VCC<5.5V
Input voltage at Pin INT VINT -27 40 V Sense Input off
LIN line bus input voltages Vbus -27 40 V –
ESD resistivity
ESD at RxD pin versus GND VESD,RxD -2 1.5 kV HBM1)
ESD all other pins. versus GND VESD1 -2 2 kV HBM1)
ESD at pin CANH, CANL, VESD1 -6 6 kV HBM1)
SPLIT, LIN, MONx versus GND
Temperatures
Junction temperature Tj -40 150 °C –
Storage temperature Tstg -50 150 °C –
1) ESD susceptibility HBM according to EIA/JESD 22-A 114B.

Note: Maximum ratings are absolute ratings; exceeding any one of these values may
cause irreversible damage to the integrated circuit.

Data Sheet 30 Rev. 1.51, 2007-06-22

 TLE 7263E

General Product Characteristics

5.2 Operating Range

Table 12 Operating Range
Parameter Symbol Limit Values Unit Remarks
Min. Max.
Supply voltage VS VUV OFF 27 V After VS rising
above VUV ON
Supply voltage VS VUV OFF 40 V 40 V load dump
Supply voltage slew rate dVS/dt -0.5 5 V/µs –
Logic input voltage (DI, CLK, VI -0.3 VCC1 V –
CSN, TxD, STS)
Output capacitor CCC1/2 100 – nF ESR < 6 Ω
@ f = 10 kHz
SPI clock frequency fclk – 4 MHz –
Junction temperature Tj -40 150 °C –

5.3 Thermal Resistance

Parameter Symbol Limit Values Unit Remarks

Min. Typ. Max.
Junction to Case1) RthjC 1 5 K/W
Junction to Ambient1) RthjA 25 K/W 2)

1) Not subject to production test, specified by design.

2) According to Jedec JESD51-2,-5,-7 at natural convection on 2s2p board for 1W. Board: 76.2x114.3x1.5mm³
with 2 inner copper layers (70µm thick)., with thermal via array under the exposed pad contacted the first inner
copper layer

Data Sheet 31 Rev. 1.51, 2007-06-22

 TLE 7263E

Electrical Characteristics

6 Electrical Characteristics

Table 13 Electrical Characteristics

VS = 13.5 V; ICC1 = 1 mA; 4.9 V < VCC1/2 < 5.1 V; SBC Active Mode; all outputs open;
-40 °C < Tj < 150 °C (max. 125 °C for CAN circuit characteristics); all voltages with
respect to ground; positive current defined flowing into pin; unless otherwise specified.
Parameter Symbol Limit Values Unit Test Condition
Min. Typ. Max.
Quiescent Current; Pin VS
Current consumption IQ – 6 8 mA SBC Active Mode
1.2 2 mA Active [CAN Sleep]
1.7 3 mA => LIN dominant;
without RL
4 6 mA Active [LIN Sleep]
Current consumption IQ – 68 80 µA stand-by mode;
Tj = 25 °C; VCC2 “off”
IQ – 580 900 µA stand-by mode;
Tj = 25 °C; VCC2 “off”;
after LIN wake-up /
power-up
Current consumption IQ – 68 80 µA stop mode;
Tj = 25 °C; VCC2 “off”;
without cyclic sense
Current consumption IQ – 76 88 µA stop mode;
Tj = 85 °C; VCC2 “off”;
without cyclic sense
Current consumption IQ – 49 60 µA sleep mode;
Tj = 25 °C; VCC2 “off”;
without cyclic sense
Current consumption IQ – 53 65 µA sleep mode;
Tj = 85°C; VCC2 “off”;
without cyclic sense
Current consumption IQ – 220 300 µA sleep mode, during
HS-On phase;
Tj = 25 °C; VCC2 “off”

Data Sheet 32 Rev. 1.51, 2007-06-22

 TLE 7263E

Electrical Characteristics

Table 13 Electrical Characteristics (cont’d)

VS = 13.5 V; ICC1 = 1 mA; 4.9 V < VCC1/2 < 5.1 V; SBC Active Mode; all outputs open;
-40 °C < Tj < 150 °C (max. 125 °C for CAN circuit characteristics); all voltages with
respect to ground; positive current defined flowing into pin; unless otherwise specified.
Parameter Symbol Limit Values Unit Test Condition
Min. Typ. Max.
Current consumption IQ – 240 330 µA sleep mode, during
HS-On phase;
Tj = 85°C; VCC2 “off”

Voltage Regulator; Pin VCC1/2

Output voltage VCC1/2 4.9 5.0 5.1 V 1 mA<ICC1/2<100 mA;
6 V < VS < 20 V
Line regulation ∆VCC1/2 – – 20 mV 6 V < VS < 16 V;
ICC = 1 mA
Load regulation ∆VCC1/2 – – 50 mV 5 mA<ICC1/2<100 mA;
VS = 6 V
Power supply ripple PSRR – 40 – dB Vr = 1 Vpp;
rejection fr = 100 Hz;
specified by design;
not subject to
production test
Output current limit ICC1/2max 200 – 500 mA VCC1/2 = 4.5 V;
power transistor
thermally monitored;
150 mA for external
load
Drop voltage VDR – – 0.5 V ICC1/2 = 150 mA;
internal modules not
supplied;
4.5V < VS < 5.4V

Data Sheet 33 Rev. 1.51, 2007-06-22

 TLE 7263E

Electrical Characteristics

Table 13 Electrical Characteristics (cont’d)

VS = 13.5 V; ICC1 = 1 mA; 4.9 V < VCC1/2 < 5.1 V; SBC Active Mode; all outputs open;
-40 °C < Tj < 150 °C (max. 125 °C for CAN circuit characteristics); all voltages with
respect to ground; positive current defined flowing into pin; unless otherwise specified.
Parameter Symbol Limit Values Unit Test Condition
Min. Typ. Max.
Oscillator
Oscillating frequency fOSC – 256 – kHz –
Internal cycling time tCYL 400 500 600 µs –
(1/128 × fOSC)
Reset Generator; Pin RO
Reset threshold voltage VRT1 4.5 4.65 4.8 V default SPI setting
VRT2 3.2 3.35 3.5 V SPI option; VS ≥ 4 V
Reset threshold VRT,hys – 100 – mV –
hysteresis
Reset low output VRO – 0.2 0.4 V IRESET = 1 mA for
voltage VCC1 = VRT1/2 ;
IRESET = 200 µA for
VRT1/2> VCC1 ≥ 1 V
Reset high output VRO 0.7 x – VCC1 V –
voltage VCC1 + 0.1
Reset pull-up current IRO 20 150 500 µA VRO = 0 V
Reset reaction time tRR 4 10 26 µs VCC1 < VRT1/2
to RO = L
Reset delay time tRD1 4.0 5.0 6.0 ms default SPI setting;
after Power-On-Reset
tRD2 0.4 0.5 0.6 ms SPI setting option
Fail Safe Output; Pin FSO
Watchdog edge count nFS – 4 – – –
difference to set HIGH
Fail Safe low output VFS – 0.2 0.4 V IFSO = 1 mA for
voltage VCC1 = VRT1/2 or
IFSO = 200 µA for
VCC1 ≥ 1 V
Fail Safe high output VFS VCC- – VCC + V IFSO = -1 mA for
voltage 0.6 0.1 VCC1 ≥ VRT1/2

Data Sheet 34 Rev. 1.51, 2007-06-22

 TLE 7263E

Electrical Characteristics

Table 13 Electrical Characteristics (cont’d)

VS = 13.5 V; ICC1 = 1 mA; 4.9 V < VCC1/2 < 5.1 V; SBC Active Mode; all outputs open;
-40 °C < Tj < 150 °C (max. 125 °C for CAN circuit characteristics); all voltages with
respect to ground; positive current defined flowing into pin; unless otherwise specified.
Parameter Symbol Limit Values Unit Test Condition
Min. Typ. Max.
Sense Input (Early Warning) SI, VCCx-Fail, Interrupt Output INT
Sense In threshold VSI,th 1.8 2.3 2.8 V VSI decreasing
voltage
Sense In threshold VSI,hys 100 200 300 mV –
hysteresis
Sense reaction time tS,r 5 10 20 µs VSI < VSI,th to
INT = low
Interrupt Out high VINThigh 0.7 × – VCC1 V I0 = -20 µA
voltage VCC1
Interrupt Out low VINTlow 0 – 1.2 V I0 = 1.25 mA
voltage
Interrupt pull-up current IINT 20 150 500 µA VINT = 0 V
Input voltage for Flash VINT 7 – – V
Programming Mode at
pin INT
VCC1-Fail threshold VVCC1,th 2.1 2.6 3.1 V –
voltage
VCC1-Fail reaction time tVCC1,r 10 20 30 µs –
Watchdog Generator
Long open window tLW 51 64 77 ms –
(128 cyl.)
Watchdog reset-pulse tWDR1 3.6 5.0 6.0 ms default SPI setting
tWDR2 0.012 0.5 0.6 ms SPI setting option
Watchdog current IWD,th 0.5 – 8 mA –
threshold
Monitoring Inputs MONx
MONx input threshold VMONxth 2 3 4 V –
voltage
Input hysteresis VI, hys. 0.1 – 0.7 V

Data Sheet 35 Rev. 1.51, 2007-06-22

 TLE 7263E

Electrical Characteristics

Table 13 Electrical Characteristics (cont’d)

VS = 13.5 V; ICC1 = 1 mA; 4.9 V < VCC1/2 < 5.1 V; SBC Active Mode; all outputs open;
-40 °C < Tj < 150 °C (max. 125 °C for CAN circuit characteristics); all voltages with
respect to ground; positive current defined flowing into pin; unless otherwise specified.
Parameter Symbol Limit Values Unit Test Condition
Min. Typ. Max.
Pull up current IPU,MON -30 -10 -3 µA VMON = 3.8V
Pull down current IPD,MON 3 10 30 µA VMON = 2V
MONx filter time tMONx, f 10 – 20 µs –
Input current IMONx -2 – 2 µA VMONx = 0 V;
VMONx > 5V
High Side Output OUTHS
Static Drain-Source RDSON HS – 2.5 3.5 Ω Tj = 25 °C
ON-Resistance; – – 6.0 Ω –
IOUTH = -150 mA
Active Zener voltage VOUTHS – VS-45 – V IOUTHS = -0.15 A
Leakage current IQLHS -10 – – µA VOUTHS = 0 V
Switch ON delay time tdONHS – – 20 µs CSN high to OUTHS
Switch OFF delay time tdOFFHS – – 20 µs CSN high to OUTHS
Overcurrent shutdown ISDHS -0.8 -0.4 -0.2 A –
threshold
Shutdown filter time tdSDHS 10 25 40 µs –
UV-Switch-ON voltage VUV ON – 5.35 6.00 V VS increasing
UV-Switch-OFF voltage VUV OFF 4.50 4.85 – V VS decreasing
UV-ON/OFF-Hysteresis VUV HY 0.1 0.2 – V VUV ON - VUV OFF
Cyclic sense period tP CS – 16 to – ms selectable via SPI
512 bits;
tolerance depending
on internal oscillator
Cyclic sense ON time tCS on1 0.4 0.5 0.6 ms default SPI setting
tCS on2 0.08 0.1 0.12 ms SPI option

Data Sheet 36 Rev. 1.51, 2007-06-22

 TLE 7263E

Electrical Characteristics

Table 13 Electrical Characteristics (cont’d)

VS = 13.5 V; ICC1 = 1 mA; 4.9 V < VCC1/2 < 5.1 V; SBC Active Mode; all outputs open;
-40 °C < Tj < 150 °C (max. 125 °C for CAN circuit characteristics); all voltages with
respect to ground; positive current defined flowing into pin; unless otherwise specified.
Parameter Symbol Limit Values Unit Test Condition
Min. Typ. Max.
Send to Sleep Input (STS)
H-input voltage VIH – – 0.7 × V –
threshold VCC1
L-input voltage VIL 0.3 × – – V –
threshold VCC1
Hysteresis of input VIHY 0.8 – 1.5 V –
voltage
Pull-down resistance at RISTS 20 40 80 kΩ VSTS = 0.2 × VCC1
pin STS
STS pulse width tSTS 10 – – µs one oscillator period
Wake Event Output WKO
HIGH level output VWKO,H 0.8 × – – V IWKO = -1.6 mA
voltage VCC1
LOW level output VWKO,L – – 0.2 × V IWKO = 1.6 mA
voltage VCC1
CAN Transceiver Characteristics
Receiver Output RxD
HIGH level output IRD,H – -4 -2 mA VRD = 0.8 × VCC1;
current Vdiff < 0.4 V1)
LOW level output IRD,L 2 4 – mA VRD = 0.2 × VCC1;
current Vdiff > 1 V1)
Transmission Input TxD
HIGH level input voltage VTD,H – 0.5 × 0.7 × V recessive state
threshold VCC1 VCC1
TxD input hysteresis VTD,hys – 0.4 – V –
LOW level input voltage VTD,L 0.3 × 0.5 × – V dominant state
threshold VCC1 VCC1
TxD pull-up resistance RTD 10 20 40 kΩ –

Data Sheet 37 Rev. 1.51, 2007-06-22

 TLE 7263E

Electrical Characteristics

Table 13 Electrical Characteristics (cont’d)

VS = 13.5 V; ICC1 = 1 mA; 4.9 V < VCC1/2 < 5.1 V; SBC Active Mode; all outputs open;
-40 °C < Tj < 150 °C (max. 125 °C for CAN circuit characteristics); all voltages with
respect to ground; positive current defined flowing into pin; unless otherwise specified.
Parameter Symbol Limit Values Unit Test Condition
Min. Typ. Max.
CAN Bus Receiver
Differential receiver Vdiff,d – 0.80 0.90 V Vdiff = VCANH - VCANL
threshold voltage, “active mode”
recessive to dominant
edge
Differential receiver Vdiff,r 0.50 0.60 – V Vdiff = VCANH - VCANL
threshold voltage, “active mode”
dominant to recessive
edge
Common Mode Range CMR -12 – 12 V –
Differential receiver Vdiff,hys – 110 – mV “active mode”
hysteresis
CANH, CANL input Ri 10 20 30 kΩ recessive state
resistance
Differential input Rdiff 20 40 60 kΩ recessive state
resistance
Wake-up Receiver Vdiff, d – 0.8 1.15 V “sleep/stop mode”
threshold voltage,
recessive to dominant
edge
Wake-up Receiver Vdiff, r 0.4 0.7 – V “sleep/stop mode”
threshold voltage,
dominant to recessive
edge
Wake-up Receiver Vdiff, hys. – 120 – mV “sleep/stop mode”
differential receiver
hysteresis

Data Sheet 38 Rev. 1.51, 2007-06-22

 TLE 7263E

Electrical Characteristics

Table 13 Electrical Characteristics (cont’d)

VS = 13.5 V; ICC1 = 1 mA; 4.9 V < VCC1/2 < 5.1 V; SBC Active Mode; all outputs open;
-40 °C < Tj < 150 °C (max. 125 °C for CAN circuit characteristics); all voltages with
respect to ground; positive current defined flowing into pin; unless otherwise specified.
Parameter Symbol Limit Values Unit Test Condition
Min. Typ. Max.
CAN Bus Transmitter
CANL/CANH recessive VCANL/H 2.0 – 3.0 V no load
output voltage
CANH, CANL recessive Vdiff -500 – 50 mV VTxD = VCC1;
output voltage no load
difference
Vdiff = VCANH - VCANL
CANL dominant output VCANL 0.5 – 2.25 V VTxD = 0 V;
voltage VCC2 = 5 V
CANH dominant output VCANH 2.75 – 4.5 V VTxD = 0 V;
voltage VCC2 = 5 V
CANH, CANL dominant Vdiff 1.5 – 3.0 V VTxD = 0 V;
output voltage VCC2 = 5 V
difference
Vdiff = VCANH - VCANL
CANH short circuit ICANHsc -200 -80 -50 mA VCANHshort = 0 V
current
CANL short circuit ICANLsc 50 80 200 mA VCANLshort = 18 V
current
Leakage current ICANH,lk – 25 – µA VS = VCC2 = 0 V;
ICANL,lk 0 V < VCANH,L< 5 V
Split Termination Output; Pin SPLIT
Split output voltage VSPLIT 0.3 × 0.5 × 0.7 × V normal mode;
VCC2 VCC2 VCC2 -500 µA < ISPLIT <
500 µA
Leakage current ISPLIT -5 0 5 µA standby mode;
-22 V < VSPLIT < 35 V
SPLIT output resistance RSPLIT – 600 – Ω –

Data Sheet 39 Rev. 1.51, 2007-06-22

 TLE 7263E

Electrical Characteristics

Table 13 Electrical Characteristics (cont’d)

VS = 13.5 V; ICC1 = 1 mA; 4.9 V < VCC1/2 < 5.1 V; SBC Active Mode; all outputs open;
-40 °C < Tj < 150 °C (max. 125 °C for CAN circuit characteristics); all voltages with
respect to ground; positive current defined flowing into pin; unless otherwise specified.
Parameter Symbol Limit Values Unit Test Condition
Min. Typ. Max.
Dynamic CAN-Transceiver Characteristics
Propagation delay td(L),TR – 150 255 ns CL = 47 pF;
TxD-to-RxD LOW RL = 60 Ω;
(recessive to dominant) VCC1/2 = 5 V;
CRxD = 20 pF
Propagation delay td(H),TR – 150 255 ns CL = 47 pF;
TxD-to-RxD HIGH RL = 60 Ω;
(dominant to recessive) VCC1/2 = 5 V;
CRxD = 20 pF
Propagation delay td(L),T – 50 120 ns CL = 47 pF;
TxD LOW to bus RL = 60 Ω;
dominant VCC1/2 = 5 V
Propagation delay td(H),T – 50 120 ns CL = 47 pF;
TxD HIGH to bus RL = 60 Ω;
recessive VCC1/2 = 5 V
Propagation delay td(L),R – 100 135 ns CL = 47 pF;
bus dominant to RxD RL = 60 Ω;
LOW VCC1/2 = 5 V;
CRxD = 20 pF
Propagation delay td(H),R – 100 135 ns CL = 47 pF;
bus recessive to RxD RL = 60 Ω;
HIGH VCC1/2 = 5 V;
CRxD = 20 pF
Min. dominant time for tWU 1 3 5 µs –
bus wake-up
TxD permanent tTxD 0.3 – 1.0 ms –
dominant disable time

Data Sheet 40 Rev. 1.51, 2007-06-22

 TLE 7263E

Electrical Characteristics

Table 13 Electrical Characteristics (cont’d)

VS = 13.5 V; ICC1 = 1 mA; 4.9 V < VCC1/2 < 5.1 V; SBC Active Mode; all outputs open;
-40 °C < Tj < 150 °C (max. 125 °C for CAN circuit characteristics); all voltages with
respect to ground; positive current defined flowing into pin; unless otherwise specified.
Parameter Symbol Limit Values Unit Test Condition
Min. Typ. Max.
LIN Transceiver Characteristics
Receive Output RxD
HIGH level output VRxD,H 0.8 × – – V IRxD(LIN) = -1.6 mA;
voltage VCC1 Vbus = VS
LOW level output VRxD,L – – 0.2 × V IRxD(LIN) = 1.6 mA;
voltage VCC1 Vbus = 0 V
Transmission Input TxD
HIGH level input voltage VTxD,H – – 0.7 × V recessive state
threshold VCC1
TxD input hysteresis VTxD,hys 0.8 1.5 V –
LOW level input voltage VTxD,L 0.3 × – – V dominant state
threshold VCC1
TxD pull-up Resistor RTxD 20 40 80 kΩ VTxD = 0 V
Bus Receiver
Receiver threshold Vbus,rd 0.42 0.48 × – V –
voltage, recessive to × VS VS
dominant edge
Receiver dominant Vbusdom – – 0.40 V (LIN Spec 1.3 (2.0);
state × VS Line 10.1.9 (3.1.9))
Receiver threshold Vbus,dr – 0.52 × 0.58 V Vbus,rec < Vbus < 27 V
voltage, dominant to VS × VS
recessive edge
Receiver recessive Vbusrec 0.6 × – – – (LIN Spec 1.3 (2.0);
state VS Line 10.1.10 (3.1.10))
Receiver center voltage Vbuscent 0.475 0.5 × 0.525 V (LIN Spec 1.3 (2.0);
× VS VS × VS Line 10.1.11 (3.1.11))
Receiver hysteresis Vbus,hys 0.02 0.04 × 0.1 × V Vbus,hys =
× VS VS VS Vbus,rec - Vbus,dom
(LIN Spec 1.3 (2.0);
Line 10.1.12 (3.1.12))

Data Sheet 41 Rev. 1.51, 2007-06-22

 TLE 7263E

Electrical Characteristics

Table 13 Electrical Characteristics (cont’d)

VS = 13.5 V; ICC1 = 1 mA; 4.9 V < VCC1/2 < 5.1 V; SBC Active Mode; all outputs open;
-40 °C < Tj < 150 °C (max. 125 °C for CAN circuit characteristics); all voltages with
respect to ground; positive current defined flowing into pin; unless otherwise specified.
Parameter Symbol Limit Values Unit Test Condition
Min. Typ. Max.
Wake-up threshold Vwake 0.40 0.5 × 0.6 × V –
voltage × VS VS VS
Bus Transmitter
Bus serial diode voltage Vserdiode 0.4 0.7 1.0 V VTxD = high Level
drop
Bus dominant output Vbus,dom – – 1.2 V VTxD = 0 V; VS = 7 V;
voltage RL = 500 Ω;
(LIN Spec 1.3;
Line 10.1.13)
– – 2.0 V VS = 18 V;
RL = 500 Ω;
(LIN Spec 1.3;
Line 10.1.14)
Bus dominant output Vbus,dom 0.6 – – V VTxD = 0 V; VS = 7 V;
voltage RL = 1 kΩ;
(LIN Spec 1.3;
Line 10.1.15)
0.8 – – V VS = 18 V; RL = 1 kΩ;
(LIN Spec 1.3;
Line 10.1.16)
Bus short circuit current Ibus,sc 40 100 150 mA Vbus,short = 18 V
(LIN Spec 1.3 (2.0);
Line 10.1.4 (3.1.4))

Data Sheet 42 Rev. 1.51, 2007-06-22

 TLE 7263E

Electrical Characteristics

Table 13 Electrical Characteristics (cont’d)

VS = 13.5 V; ICC1 = 1 mA; 4.9 V < VCC1/2 < 5.1 V; SBC Active Mode; all outputs open;
-40 °C < Tj < 150 °C (max. 125 °C for CAN circuit characteristics); all voltages with
respect to ground; positive current defined flowing into pin; unless otherwise specified.
Parameter Symbol Limit Values Unit Test Condition
Min. Typ. Max.
Leakage current Ibus,lk -500 -140 – µA VS = 0 V; Vbus = -8 V
(LIN Spec 1.3 (2.0);
Line 10.1.7 (3.1.7))
– 10 25 µA VS = 0 V; Vbus = 18 V
(LIN Spec 1.3 (2.0);
Line 10.1.8 (3.1.8))
-1 – – mA VS = 18 V; Vbus = 0 V
(LIN Spec 1.3 (2.0);
Line 10.1.5(3.1.5))
– – 20 µA VBUS =18V VS = 8V
(LIN Spec 1.3 (2.0);
Line 10.1.6 (3.1.6))
Bus pull-up resistance Rbus 20 30 60 kΩ Active/Standby mode
(LIN Spec 1.3 (2.0);
Line 10.2.2 (3.2.2))
LIN output current Ilin 5 20 60 µA Sleep mode;Vbus = 0V

Data Sheet 43 Rev. 1.51, 2007-06-22

 TLE 7263E

Electrical Characteristics

Table 13 Electrical Characteristics (cont’d)

VS = 13.5 V; ICC1 = 1 mA; 4.9 V < VCC1/2 < 5.1 V; SBC Active Mode; all outputs open;
-40 °C < Tj < 150 °C (max. 125 °C for CAN circuit characteristics); all voltages with
respect to ground; positive current defined flowing into pin; unless otherwise specified.
Parameter Symbol Limit Values Unit Test Condition
Min. Typ. Max.
Dynamic Transceiver Characteristics
Slew rate falling edge Sfslope -3 – -1 V/µs 60% > Vbus > 40%
1 µs < (τ = Rl × Cbus)
< 5 µs;
VS = 13.5 V;
Active mode
(LIN Spec 1.3;
Line 10.3.1)
Slew rate rising edge Srslope 1 – 3 V/µs 40% < Vbus < 60%
1 µs < (τ = Rl × Cbus)
< 5 µs;
VS = 13.5 V;
Active mode.
(LIN Spec 1.3;
Line 10.3.1)
Slope symmetry tslopesym -5 – 5 µs tfslope - trslope;
VS = 13.5 V
(LIN Spec 1.3;
Line 10.3.3)
Propagation delay td(L),T – 1 4 µs (LIN Spec 1.3;
TxD LOW to bus Line 10.3.6)
Propagation delay td(H),T – 1 4 µs (LIN Spec 1.3;
TxD HIGH to bus Line 10.3.6)
Propagation delay td(L),R – 1 6 µs CRxD = 20 pF;
bus dominant to RxD (LIN Spec 1.3;
LOW Line 10.3.7)
Propagation delay td(H),R – 1 6 µs CRxD = 20 pF;
bus recessive to RxD (LIN Spec 1.3;
HIGH Line 10.3.7)
Receiver delay tsym,R -2 – 2 µs tsym,R = td(L),R - td(H),R
symmetry (LIN Spec 1.3;
Line 10.3.8)

Data Sheet 44 Rev. 1.51, 2007-06-22

 TLE 7263E

Electrical Characteristics

Table 13 Electrical Characteristics (cont’d)

VS = 13.5 V; ICC1 = 1 mA; 4.9 V < VCC1/2 < 5.1 V; SBC Active Mode; all outputs open;
-40 °C < Tj < 150 °C (max. 125 °C for CAN circuit characteristics); all voltages with
respect to ground; positive current defined flowing into pin; unless otherwise specified.
Parameter Symbol Limit Values Unit Test Condition
Min. Typ. Max.
Transmitter delay tsym,T -2 – 2 µs tsym,T = td(L),T - td(H),T
symmetry (LIN Spec 1.3;
Line 10.3.9)
Wake-up delay time twake 30 100 150 µs Tj ≤ 125 °C
– – 170 µs Tj ≤ 150 °C
TxD dominant time out ttimeout 6 12 20 ms VTxD = 0 V
TxD dominant time out ttorec – 10 – µs VTxD = 5 V
recovery time Not subject to production
test. Specified by design

Transfer Rate 20 kBit/s; 1 µs < τ = RL × Cbus < 5 µs

Duty cycle D1 D1 0.396 – – duty cycle 1:
THRec(max) =
0.744 × VS;
THDom(max) =
0.581 × VS;
VS = 7.0 … 18 V;
tbit = 50 µs;
D1 = tbus_rec(min)/[2 tbit]
(LIN Spec 2.0;
line 3.3.1)
Duty cycle D2 D2 – – 0.581 duty cycle 2:
THRec(min) =
0.422 × VS;
THDom(min) =
0.284 × VS;
VS = 7.6 … 18 V;
tbit = 50 µs;
D2 = tbus_rec(max)/[2 tbit]
(LIN Spec 2.0;
line 3.3.2)

Data Sheet 45 Rev. 1.51, 2007-06-22

 TLE 7263E

Electrical Characteristics

Table 13 Electrical Characteristics (cont’d)

VS = 13.5 V; ICC1 = 1 mA; 4.9 V < VCC1/2 < 5.1 V; SBC Active Mode; all outputs open;
-40 °C < Tj < 150 °C (max. 125 °C for CAN circuit characteristics); all voltages with
respect to ground; positive current defined flowing into pin; unless otherwise specified.
Parameter Symbol Limit Values Unit Test Condition
Min. Typ. Max.
Transfer Rate 10.4 kBit/s; 1 µs < τ = RL × Cbus < 5 µs
Slew Rate falling edge Sfslope -1.5 – -0.5 V/µs 60% > Vbus > 40%;
“Low Slope/US Mode” τ = RI × Cbus;
1 µs < τ < 5 µs;
VS = 7 … 18 V
Slew Rate rising edge Srslope 0.5 – 1.5 V/µs 40% < Vbus < 60%;
“Low Slope/US Mode” τ = RI × Cbus;
1 µs < τ < 5 µs;
VS = 7 … 18 V
Duty cycle D3 D3 0.417 – – duty cycle 3
THRec(max) =
0.778 × VS;
THDom(max) =
0.616 × VS;
VS = 7.0 … 18 V;
tbit = 96 µs;
D3 = tbus_rec(min)/[2 tbit]
(LIN Spec 2.0;
line 3.4.1)
Duty cycle D4 D4 – – 0.590 duty cycle 4
THRec(min) =
0.389 × VS;
THDom(min) =
0.251 × VS;
VS = 7.6 … 18 V;
tbit = 96 µs;
D4 = tbus_rec(max)/[2 tbit]
(LIN Spec 2.0;
line 3.4.2)
Master Termination Switch Output; Pin MTS
Ron resistance RonMTS – 33 60 Ω IMTS = -15 mA
Maximum output IMTS 40 – 150 mA VMTS = 0 V
current

Data Sheet 46 Rev. 1.51, 2007-06-22

 TLE 7263E

Electrical Characteristics

Table 13 Electrical Characteristics (cont’d)

VS = 13.5 V; ICC1 = 1 mA; 4.9 V < VCC1/2 < 5.1 V; SBC Active Mode; all outputs open;
-40 °C < Tj < 150 °C (max. 125 °C for CAN circuit characteristics); all voltages with
respect to ground; positive current defined flowing into pin; unless otherwise specified.
Parameter Symbol Limit Values Unit Test Condition
Min. Typ. Max.
Leakage current IMTS,lk -5.0 – 5.0 µA sleep mode;
VMTS = 0 V

Data Sheet 47 Rev. 1.51, 2007-06-22

 TLE 7263E

Electrical Characteristics

Table 13 Electrical Characteristics (cont’d)

VS = 13.5 V; ICC1 = 1 mA; 4.9 V < VCC1/2 < 5.1 V; SBC Active Mode; all outputs open;
-40 °C < Tj < 150 °C (max. 125 °C for CAN circuit characteristics); all voltages with
respect to ground; positive current defined flowing into pin; unless otherwise specified.
Parameter Symbol Limit Values Unit Test Condition
Min. Typ. Max.
SPI-Interface
Logic Inputs DI, CLK and CSN
H-input voltage VIH – – 0.7 × V –
threshold VCC1
L-input voltage VIL 0.3 × – – V –
threshold VCC1
Hysteresis of input VIHY 0.8 1.5 V –
voltage
Pull-up resistance at pin RICSN 20 40 80 kΩ VCSN = 0.7 × VCC1
CSN
Pull-down resistance at RICLK/DI 20 40 80 kΩ VDI/CLK = 0.2 × VCC1
pin DI and CLK
Input capacitance CI – 10 15 pF Not subject to production
at pin CSN, DI or CLK test. Specified by design

Logic Output DO
H-output voltage level VDOH VCC1 VCC1 - – V IDOH = -1 mA
-0.4 0.2
L-output voltage level VDOL – 0.2 0.4 V IDOL = 1.6 mA
Tri-state leakage IDOLK -10 – 10 µA VCSN = VCC1;
current 0 V < VDO < VCC1
Tri-state input CDO – 10 15 pF Not subject to production
capacitance test. Specified by design

Data Input Timing Not subject to production test. Specified by design

Clock period tpCLK 250 – – ns –
Clock high time tCLKH 125 – – ns –
Clock low time tCLKL 125 – – ns –
Clock low before CSN tbef 125 – – ns –
low
CSN setup time tlead 250 – – ns –

Data Sheet 48 Rev. 1.51, 2007-06-22

 TLE 7263E

Electrical Characteristics

Table 13 Electrical Characteristics (cont’d)

VS = 13.5 V; ICC1 = 1 mA; 4.9 V < VCC1/2 < 5.1 V; SBC Active Mode; all outputs open;
-40 °C < Tj < 150 °C (max. 125 °C for CAN circuit characteristics); all voltages with
respect to ground; positive current defined flowing into pin; unless otherwise specified.
Parameter Symbol Limit Values Unit Test Condition
Min. Typ. Max.
CLK setup time tlag 250 – – ns –
Clock low after CSN tbeh 125 – – ns –
high
DI setup time tDISU 50 – – ns –
DI hold time tDIHO 50 – – ns –
Input signal rise time trIN – – 50 ns –
at pin DI, CLK and CSN
Input signal fall time tfIN – – 50 ns –
at pin DI, CLK and CSN
Delay time for mode tfIN – – 10 µs –
change from Normal
Mode to Sleep Mode
CSN high time tCSN(high) 15 – – µs two oscillator periods
Data Output Timing Not subject to production test. Specified by design
DO rise time trDO – 30 80 ns CL = 100 pF
DO fall time tfDO – 30 80 ns CL = 100 pF
DO enable time tENDO – – 50 ns low impedance
DO disable time tDISDO – – 50 ns high impedance
Thermal Prewarning and Shutdown (junction temperatures)
(Not subject to production test. Specified by design)
VCC1 thermal TjPW 120 145 170 °C bit 0 of SPI diagnosis
prewarning word
ON temperature
VCC1 thermal ∆T – 25 – K –
prewarning hyst.
VCC1/2 thermal TjSD 155 185 200 °C hysteresis 35 K (typ.)
shutdown temp.
VCC1 ratio of SD to PW TjSD/ – 1.20 – – –
temp. TjPW

Data Sheet 49 Rev. 1.51, 2007-06-22

 TLE 7263E

Electrical Characteristics

Table 13 Electrical Characteristics (cont’d)

VS = 13.5 V; ICC1 = 1 mA; 4.9 V < VCC1/2 < 5.1 V; SBC Active Mode; all outputs open;
-40 °C < Tj < 150 °C (max. 125 °C for CAN circuit characteristics); all voltages with
respect to ground; positive current defined flowing into pin; unless otherwise specified.
Parameter Symbol Limit Values Unit Test Condition
Min. Typ. Max.
OUTHS thermal TjSD 150 175 200 °C –
shutdown temp.
OUTHS thermal ∆T – 10 – K –
shutdown hyst.
CAN Transmitter TjSD 150 – 190 °C –
thermal shutdown temp.
CAN Transmitter ∆T – 10 – K –
thermal shutdown hyst.
LIN Transmitter thermal TjSD 150 – 190 °C –
shutdown temp.
LIN Transmitter thermal ∆T – 10 – K –
shutdown hyst.
1) Vdiff = VCANH - VCANL

Data Sheet 50 Rev. 1.51, 2007-06-22

 TLE 7263E

Electrical Characteristics

Timing Diagrams

CSN high to low: DO is enabled. Status information transferred to output shift register

CSN
time
CSN low to high: data from shift register is transferred to output functions

CLK
time
Actual data New data
DI FI 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FI 0 1
- + +
time
DI: will accept data on the falling edge of CLK signal
Actual status New status
DO FO 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FO 0 1
- + +
time
DO: will change state on the rising edge of CLK signal

e.g. HS switch Old data Actual data

time
SPI_data_transfer_timing

Figure 12 SPI-Data Transfer Timing

Data Sheet 51 Rev. 1.51, 2007-06-22

 TLE 7263E

Electrical Characteristics

Figure 13 SPI-Input Timing

Figure 14 Turn OFF/ON Time

Data Sheet 52 Rev. 1.51, 2007-06-22

 TLE 7263E

Electrical Characteristics

Figure 15 DO Valid Data Delay Time and Valid Time

Figure 16 DO Enable and Disable Time

Data Sheet 53 Rev. 1.51, 2007-06-22

 TLE 7263E

Electrical Characteristics

tWD
tCWmax tOWmax

t CWmin tOWmin

closed window open window

t / [tWDPER]
safe trigger area

0.4 0.6 0.8 1.0 1.2

tWWRP

tWWRP : Window Watchdog Reset Period set via SPI, see table 9

Figure 17 Watchdog Time-Out Definitions

tCW tOW tCW tOW tLW

tCW tOW tCW +tOW tLW tLW tCW tCW tOW
WD
Trigger

tWDR t
Reset
Out

Watchdog t
timer reset

normal timeout normal timeout normal

operation (too long) operation (too short) operation

Figure 18 Watchdog Timing Diagram

Data Sheet 54 Rev. 1.51, 2007-06-22

 TLE 7263E

Electrical Characteristics

VCC
VRTx
t < tRR
VCC1-Fail

t
tRD1 tLW tCW tOW tRDx tCW
WD tLW tLW
Trigger

t
Reset tWDRx tRR
Out

t
Watchdog
timer reset
start up normal operation undervoltage start up
VCC1 tVCC, r
fail HIGH
flag

LOW
t
activation by µC
[first SPI transmission]

Figure 19 Reset Timing Diagram

Data Sheet 55 Rev. 1.51, 2007-06-22

 TLE 7263E

Electrical Characteristics

VTxD
VCC

GND

VDIFF td(L), T td(H), T t

VDIFF(d)
VDIFF(r)

VRxD t
td(L), R td(H), R
VCC
0.7VCC

0.3VCC
GND

td(L), TR td(H), TR t
AET02926

Figure 20 CAN Dynamic Characteristics Timing Diagram

Data Sheet 56 Rev. 1.51, 2007-06-22

 TLE 7263E

Electrical Characteristics

VCC

VTxD

GND
t
td(L),T td(H),T
VS

Vbus Vbus,rd Vbus,dr

GND

td(L),R td(H),R t
VCC

0.7*VCC
VRxD
0.3*VCC

GND
td(L),TR td(H),TR t

Figure 21 LIN Dynamic Characteristics Timing Diagram

Data Sheet 57 Rev. 1.51, 2007-06-22

 TLE 7263E

Application Information

7 Application Information

7.1 ESD Tests

Tests for ESD robustness according to IEC61000-4-2 “gun test” (150pF, 330Ω) have
been performed. The results and test condition are available in a test report.

Table 14 ESD “GUN test”

Performed Test Result Unit Remarks
1)
ESD at pin CANH, CANL, LIN, Vs ≥ +8 kV Positive pulse
versus GND
1)
ESD at pin CANH, CANL, LIN, Vs ≤ -8 kV Negative pulse
versus GND
1) ESD susceptibility “ESD GUN” according LIN EMC 1.3 Test Specification, Section 4.3. (IEC 61000-4-2) -
Tested by external test house (IBEE Zwickau, EMC Test report Nr. 11-11-06).

Data Sheet 58 Rev. 1.51, 2007-06-22

 TLE 7263E

Application Information

7.2 Application Example

Vbat
60Ohms
4.7nF
CAN
bus

60Ohms

SPLIT FSO

CANH RxDCAN

CANL TxDCAN

CSN
OUTHS
CLK
MON4
DO
1kOhm
MON3 DI

INT
MON2
10 kOhm RO
MON1
WKO

STS
MTS

VS
VCC1

100 nF 68 µF
TLE 7263 100 nF 10 µF µC
1 kOhm e.g. XC164CM
TxDLIN
VCC2
LIN
Bus VCC2 RxDLIN
10 µF 0.1 µF
LIN GND
SI GND
1 nF
160 kOhm

100 kOhm 4.7 nF

Appl_7263

Figure 22 Application Circuit

Data Sheet 59 Rev. 1.51, 2007-06-22

 TLE 7263E

Package Outlines

8 Package Outlines

STAND OFF
0.35 x 45˚

2.65 MAX.
2.45 -0.2
0...0.15

0.23 +0.09
7.6 -0.2 1)

8˚ MAX.
12˚

1.1
0.65 0.7 ±0.2
C 0.1 C 36x
10.3 ±0.3
SEATING PLANE D
17 x 0.65 = 11.05

0.33 ±0.08 2)
0.17 M A-B C D 36x Bottom View
A
36 19 19 36
Exposed Diepad
5.1

1 18 18 1 Index Marking
7
B
12.8 -0.21)

Index Marking

1) Does not include plastic or metal protrusion of 0.15 max. per side
2) Does not include dambar protrusion of 0.05 max. per side
GPS01153

Figure 23 PG-DSO-36-24 (Plastic Dual Small Outline with Exposed Pad)

Green Product (RoHS Compliant)

To meet the world-wide customer requirements for environmentally friendly products
and to be compliant with government regulations the device is available as a green
product. Green products are RoHS-Compliant (i.e Pb-free finish on leads and suitable
for Pb-free soldering according to IPC/JEDEC J-STD-020)

You can find all of our packages, sorts of packing and others in our
Infineon Internet Page “Products”: http://www.infineon.com/products. Dimensions in mm

Data Sheet 60 Rev. 1.51, 2007-06-22

 TLE 7263E

Revision History

9 Revision History

TLE 7263E

Revision History: 2007-06-22 Rev. 1.51

Previous Version: Revision 1.50
Page Subjects (major changes since last revision)
40 Propagation Delay valus (td(L),T; td(H),T; td(L),R ; td(H,)R) changed.
Previous Version: Preliminary Data Sheet 1.41
Page Subjects (major changes since last revision)
2 New package picture
32/33 Typical values added and update quiescent current; pin VS
60 Latest package drawing

Data Sheet 61 Rev. 1.51, 2007-06-22

Edition 2007-06-22
Published by
Infineon Technologies AG
81726 München, Germany
© Infineon Technologies AG 2007.
All Rights Reserved.

Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics (“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values
stated herein and/or any information regarding the application of the device, Infineon Technologies hereby
disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-
infringement of intellectual property rights of any third party.

Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com).

Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
www.infineon.com

Published by Infineon Technologies AG