T1 MSD Scheme & Solutions
18th April 2024
1. With the help of a neat circuit diagram, justify the need for current mirrors in integrated circuit
design. 05
Solution:
Transistors need to be biased (usually in the saturation region) so that they can provide a stable current
output. Referring to the circuit of Figure 1, the output current (ignoring channel length modulation) is
given by:
2
µnCoxW R2
IOUT = VDD −VT
2L R1 + R2
The problem of this method of biasing is that the output current is dependent on
• process corners (because VT and Cox is process-dependent)
• supply voltage VDD
• temperature (since µn and VT depend on temperature)
Hence, even if the biasing voltage VGS is well-defined, the drain current is not! (2)
..............................................................................................
Assuming that a reference current independent of PVT variations is available, circuits called current
mirrors are designed as shown in Figure 2 which essentially copy the reference current for biasing other
circuits of interest. Let IREF = f (VGS ). Then M1 computes VGS = f −1 (IREF ) and feeds it to M2 so that
IOUT = f (VGS ) = f ( f −1 (IREF )) = IREF
assuming that the transistors M1 and M2 are identical.
VDD
VDD
R1
IOUT IREF
M1
IOUT
R2 M1 M2
Figure 1: Voltage-divider biasing Figure 2: Basic Current Mirror
(1)
...................................................................................................
However, it is not necessary that the aspect ratios of M1 and M2 should be same; in which case ignoring
channel length modulation, we have:
(W /L)2
IOUT = IREF
(W /L)1
1
The key property of this topology is that it allows precise copying of the current with no dependence on
process and temperature. The ratio of IOUT and IREF is given by the ratio of device dimensions which
can be controlled with reasonable accuracy. It is good design practice to employ the same length for mir-
roring transistors so as to minimize errors due to the side-diffusion of the source and drain areas (LD ). (2)
2. Demonstrate the condition under which a change in the input common-mode level to a differential
pair with resistive load leads to a change in the output common-mode voltage. 05
Solution:
In a differential pair, a change in the input common-mode level leads to a change in the output common-
mode voltage when the output resistance RSS of the tail current source is finite, as shown in Figure 3.
(1)
..............................................................................................
Now, if the input vic changes slightly, then small-signal currents gm vgs will flow through both M1 and M2
in the same direction. Hence, a net small-signal current of 2gm vgs flows into node P; thereby increasing
the voltage at node P.
VDD VDD VDD
RD RD RD RD RD
voc voc voc voc voc
vic M1 M2 vic vic M1 M2 vic vic M1
P P
RSS 2RSS 2RSS 2RSS
Figure 3: Small-Signal Common- Figure 4: Preparing for half circuit Figure 5: Half cir-
mode Analysis analysis cuit analysis
(2)
...................................................................................................
Due to symmetry, one half circuit can be considered for small-signal analysis to find the small-signal
common-mode gain, as shown in Figure 5. Noting its similarity to the common-source amplifier with
source degeneration, we can write the small-signal common-mode gain as:
voc gm RD RD gm RD
ACM = =− ≈− =−
vic [1 + 2RSS (gm + gmb + 1/ro )] 2RSS + 1/gm 1 + 2gm RSS
(ignoring channel-length modulation and body-effect). The common-mode gain indicates the factor by
which the output common-mode voltage changes when there is a change in the input common-mode
voltage. (2)
3. Find the output voltage of a source follower shown in Fig. 1 given a fixed input voltage of 0.3 V,
µ pCox = 65 µA/V2 , W /L = 50/0.5, ID = 200 µA and threshold voltage VT = 0.7 V, assuming that
M1 is in saturation. Also comment on the small-signal voltage gain of this circuit. 05
2
VDD
200 µA
vout
vin M1
Fig. 1: Question 3
Solution:
VG = Vin , VS = Vout
|VGS | = |Vin −Vout | = |0.3 −Vout | = Vout − 0.3
µ pCoxW
ID ≈ (|VGS | − |VT |)2
2L
65µ × 50
200µ = (Vout − 0.3 − 0.7)2 ⇒ (Vout − 1)2 = 4/65
2 ×p0.5
Vout = 1 ± 4/65 = 1.2481 or 0.7519 V
Since the output voltage has to be greater than the input voltage by at least a threshold voltage, the only
feasible solution is Vout ≈ 1.25 V. (4)
..............................................................................................
The small-signal gain of a source follower (ignoring channel length modulation) is given by:
gm RS
Av ≈
1 + (gm + gmb )RS
gm 1
Since the load is an ideal current source, RS → ∞ ⇒ Av ≈ = ≈1 (1)
gm + gmb 1 + η
4. Illustrate the effect of shielding in a Common-Source Common-Gate cascode amplifier with the
help of a neat circuit diagram. 05
Solution:
X Y
ID1 ID2
vx
VB2
M3 M4
X Y Q ro3
P
ID1 ID2
gm3 vgs gmb3 vbs
VB VB1
M1 M2 M1 M2 vp
(c) Replace M3 by its small signal
(a) Without cascode connection (b) Cascode amplifier pair model
Figure 6: Common-Source Common-Gate Cascode Amplifier
The difference in drain currents between two transistions having same VGS but different VDS as shown in
Figure 6(a) is given by:
µnCoxW
ID1 − ID2 = (VB −VT H )2 λ (VX −VY ) (1)
2L
..............................................................................................
3
Refering to the circuit with cascode connection in Figure 6(b), we are interested in knowing how a
change in VX and VY causes a change in voltages VP and VQ . Hence replace M3 by small signal model,
noting that vx is the input and v p the output as shown in Figure 6(c). Obtain the small-signal gain by
finding Gm and Rout .
To find Gm , short vout (v p ) to ground. ∴ vgs = vbs = 0.
iout = vx /ro3
Gm = iout /vx = 1/ro3 (1)
..............................................................................................
To find Rout , short vin (vx ) to ground. Let v p = vt , then vgs = vbs = −vt . Therefore, the current sources
become resistors only.
1 1 1
Rout = ro3 ≈
gm3 gmb3 gm3 + gmb3
1
Av = Gm Rout ≈ (2)
(gm3 + gmb3 ) ro3
..............................................................................................
As before,
µnCoxW
ID1 − ID2 = (VB −VT H )2 (VP −VQ )
2L
VX −VY
VP −VQ = Av (VX −VY ) ≈
(gm3 + gmb3 )ro3
∴ Current mismatch (ID1 − ID2 ) is reduced by a factor of intrinsic transistor gain (of M3 /M4 ) due to
cascoding. (1)
5. Analyze the circuit shown in Fig. 2 to determine the input voltage that places M1 at the edge of
triode region. Also calculate the small-signal gain under this condition; given: (W /L) = 20/0.5,
RD = 5 kΩ, λ = 0, µnCox = 120 µA/V2 , threshold voltage VT = 0.7 V and VDD = 3 V. 10
VDD
RD
vout
vin M1
Fig. 2: Question 5
Solution:
At the edge of triode region, VDS = VGS −VT .
Here, VGS = Vin ,VDS = Vout ⇒ Vin = VT +Vout . (1)
..............................................................................................
VDD −Vout
Also, Vout = VDD − ID RD ⇒ ID = (1)
RD
..............................................................................................
µnCox W µnCox W
ID = (VGS −VT )2 = (Vout )2
2 L 2 L
VDD −Vout
ID =
RD
4
µnCox W 2 VDD −Vout
∴ V =
2 L out RD
120 × 10−6 20 2 3 −Vout
V =
2 0.5 out 5 × 103
2
12Vout = 3 −Vout
2
12Vout +Vout − 3 = 0
p √
−1 ± (1)2 − 4 × 12 × (−3) −1 ± 145
∴ Vout = = = 0.46 or − 0.54 V
2 × 12 24
Since the output must be positive, choose Vout = 0.46 V.
∴ Vin = VT +Vout = 0.7 + 0.46 = 1.16 V. (5)
..............................................................................................
VDD −Vout 3 − 0.46
∴ ID = = = 0.508 mA
RD 5 × 103
r r
W 20
gm = 2µnCox ID = 2 × 120 × 10−6 × × 0.508 × 10−3 = 2.208 mS
L 0.5
∴ Av = −gm RD = −2.208 × 10−3 × 5 × 103 = −11.042 ≈ −11 (3)
6. With the help of neat diagrams, perform the qualitative analysis of a differential pair and obtain
the limits on output voltage swing. 10
Solution:
VDD
RD RD
vout1 vout2
vin1 M1 M2 vin2
ISS
Figure 7: Basic Differential Pair
(2)
..............................................................................................
Let us assume that in Figure 7, Vin1 −Vin2 varies from −∞ to +∞. If Vin1 is much more negative than Vin2 ,
M1 is off, M2 is on, and ID2 = ISS . Thus, Vout1 = VDD and Vout2 = VDD − ISS RD . As Vin1 is brought closer
to Vin2 , M1 gradually turns on, drawing a fraction of ISS and hence lowering Vout1 . Since ID1 + ID2 = ISS ,
the drain current of M2 decreases and Vout2 rises. As shown in Figure 8a, for Vin1 = Vin2 , we have
Vout1 = Vout2 = VDD − ISS RD /2. As Vin1 becomes more positive than Vin2 , M1 carries a greater current
than does M2 and Vout1 drops below Vout2 . For sufficiently large Vin1 −Vin2 , M1 hogs all of ISS , turning
M2 off. As a result, Vout1 = VDD − ISS RD and Vout2 = VDD . The plot of Vout1 −Vout2 versus Vin1 −Vin2 is
shown in Figure 8b.
The above analysis shows that:
• the maximum and minimum levels at the output are well-defined and independent of the input
common-mode level.
• the small-signal gain (given by the slope of the curve in Figure 8b) is maximum for Vin1 = Vin2 ,
gradually falling off to zero as |Vin1 −Vin2 | increases. In other words, the circuit becomes nonlinear
as the input voltage swing increases. (3)
5
Figure 8: Input-output characteristics of a differential pair
Figure 9: Differential pair sensing an input common-mode change and Common-mode input-output charac-
teristics
..............................................................................................
The role of the tail current source is to suppress the effect of input common-mode level variations on the
operation of M1 and M2 and the output level. Set Vin1 = Vin2 = Vin,CM and vary Vin,CM from 0 to VDD .
Figure 9a shows the circuit with ISS implemented by an NMOS transistor. Note that due to symmetry of
the circuit, we have Vout1 = Vout2 .
When Vin,CM = 0, the gate potentials of M1 and M2 are not more positive than their source potentials;
so both devices are off, yielding ID3 = 0. This indicates that M3 is in deep triode region since Vb is high
enough to create an inversion layer in the transistor. With ID1 = ID2 = 0, the circuit is incapable of signal
amplification, and Vout1 = Vout2 = VDD .
Now suppose Vin,CM becomes more positive, we note that M1 and M2 turn on if Vin,CM ≥ VT . Beyond
this point, ID1 and ID2 continue to increase and for a sufficiently high Vin,CM , the drain-source voltage
of M3 exceeds VDS,sat , allowing the device to operate in saturation. The total current through M1 and
M2 then remains constant. Hence, for proper operation, Vin,CM ≥ VGS1 + VDS3,sat . If Vin,CM rises fur-
ther, since Vout1 and Vout2 are relatively constant, we expect that M1 and M2 enter the triode region if
Vin,CM > Vout1 +VT = VDD − ISS RD /2 +VT
This sets an upper limit on the input common-mode level. In summary, the allowable level of Vin,CM is
bounded as follows:
ISS
VGS1 +VDS3,sat ≤ Vin,CM ≤ min VDD − RD +VT ,VDD (4)
2
..............................................................................................
Output swings: For M1 and M2 to be in saturation, each output can go as high as VDD but as low as about
Vin,CM −VT . So, higher the input common-mode level, the smaller the allowable output swings. For this
reason, it is desirable to choose a relatively low Vin,CM , but the preceding stage may not provide such a
level easily. (1)
