Computer

Organization
&
Architecture
Dr. Manoj Kumar Mishra

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 Basic Structure of Computers

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 Computer Architecture
Computer Architecture :: refers to those attributes of a system visible to a
programmer and these attributes have a direct impact on the Logical
Execution of the Program.
Examples ::
• Instruction Set
• The no of bits used to represent various data types (Nos & Characters etc)
• I / O Mechanism
• Techniques for Addressing Memory

Computer Architecture refers to an entire structure and details needed to make it

functional.

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 Computer Organization
Computer Organization :: referes to the Operational units and their inter-
connections that realize the Architectural Specifications.
Organizational Attributres :: inculdes those Hardware details trasparent to the
Programmer such as

• Control Signals
• Interfaces between the Computer and Peripherals
• Memory Technology used
• Etc

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 Architecture vs Organization
Example::
• It is an Architectural issue whether a Computer will have a Multiply
Instruction.

• It is an Organizational issue whether that Instruction will be

impletemented by special Multiply Unit by a mechanism that makes
repeated use of the Add Unit of the System.

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 Contd...
• The Organizational decision may be based on the anticipated frequency of
use of the Multiply Instruction, the related speed of the two approaches,
and the Cost and Physical size of a special Multiply Unit.

• A particular Architecture may span many years and encompas a number of

different Computer Models, but its organization changing with changing
Technlogy.
• Ex : IBM Sys/370, 1970

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 Functional Units of a Computer System

Arithmetic
Input and
logic

Memory

Output
Control

I/O Processor

Basic Functional Units of a Computer

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 Functional Units of a Computer System
• Instructions or Machine Instructions are
explicit commands that govern the the
transfer of information within a computer as
well as between the computer and its I/O
devices
and
• Specifies the Arthimatic & Logic
Operations to be performed.

Information(Programs+Data)-->Input Unit-->Computer Memory--> Processed Information ----->

Output unit
The Computer is completely controlled by the Stored Program
All activities inside the Machine / Computer are directed and co-ordinated by the Control-Unit.

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 Functional Units of a Computer System

Input Unit :: Computers read through input units(Keyboard/Mouse/Joystick etc) --> Memory -
-> Processor

Output Unit :: Processed results to the output units (Printer / Display unit etc).

I/O Units are slower than Processor

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 Functional Units of a Computer System
Memory Unit ::
Stores Program & Data
Classes of Storage ::
Primary :: (also called Main Memory)
Semiconductor Storage Cells | Fast |
Electronic Speed |
Fixed Size group of Bits called Memory Words,
identified by distinct address, is written / Read
one word at a time holds sections of the program and data
Called RAM :: Random Access Memory :: Any currently being executed
Location is accessed by short & Fixed amount Secondary Storage :: used to store
of time, called Memory Access Time large amounts of data and programs
Cache :: Much Smaller Faster RAM Magnetic Disk / Optical Disk etc
Tightly Coupled with Processor (fabricated
on the processor chip) Expensive &

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 Arithmetic and Logic Unit
o p e r a t i o n s a r e (ALU)
Memory

• Most computer
executed in ALU of the Processor.
• Arithmetic or Logic Operations is initiated
by loading the operands into memory – MAR MDR

bring them to the processor registers – PC R0

Control Unit

perform operation in ALU – store the result R1

back to memory or retain in the processor.

IR

ALU
• Each Register can store one word of data. Rn - 1

(fastest storage elements) n general purpose

registers

ALU contains ::
Memory address register (MAR)
Memory Data Register (MDR)
Instruction register (IR)
Program counter (PC)
General-purpose register (R0 – Rn-1)
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 Arithmetic and Logic Unit Memory

(ALU)
MDR :: contains a word of data to be stored in
memory, or is used to receive a word from memory. MAR MDR

MAR :: Specifies the address in memory of the word

Control

PC R0

to be written from or read into the MDR. IR

R1

Both MAR & MDR facilitate communication with Rn - 1

ALU

the memory n general purpose

registers

IR :: holds the instruction that is currently being

executed & its output is available to control Ckts. ALU contains ::
PC :: It keeps track of the execution of a program. It Special Purpose Register::
contains memory address of the next instruction to be Memory address register (MAR)
fetched & executed. Memory Data Register (MDR)
General Registers :: Employed to hold temporarily Instruction register (IR)
operands & results of ALU operations. Program counter (PC)
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General-purpose register (R0 – Rn-1) 12
 Control Unit
• All activities (Computer Operations) of the Computer System are directed, co-
ordinated and are controlled by the Control Unit.
• The Timing Signals that govern the I/O Transfers are also generated by the
Control Unit.
• Operations of a Computer ::
► Accept information in the form of Programs and Data through an Input
Unit and store it in the Memory
► Fetch the information stored in the Memory, under Program Control, into
an ALU, where the information is processed
► Output the processed information through an Output Unit

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 Basic Operational Concepts
Typical Operating Steps Memory

Typically an Instruction goes through 4 steps MAR MDR

Control

PC R0

Instruction Fetch R1
IR

ALU

Operand Fetch Rn - 1

n general purpose
registers

Storing the Result Connection Between the Processor and the Memory

Increament PC

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 Basic Operational Concepts
Typical Operating Steps :: 1 Memory

Instruction Fetch ::
Programs reside in the memory & get there through
input devices
• Execution starts when PC is set to point to the first
MAR MDR
Control

instruction of the program PC R0

R1
• The contents of PC are transferred to MAR IR

• A Read signal is sent to the memory Rn - 1

ALU

• The first instruction is read out and loaded into MDR n general purpose
registers

• The contents of MDR are transferred to IR

• At this point, the instruction is ready to be decoded Connection Between the Processor and the Memory
and executed
Memory
Content Of PC ----Transffered------> MAR -------out-------> MDR --Out----> IR (Decoded & Executed)
Read Signal

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 Basic Operational Concepts
Typical Operating Steps :: 2 Memory

Operand Fetch ::
• If required, Operand residing in Memory, is
then fetched by sending its address to the MAR MDR

MAR and initiating a Read Cycle Control

R0
• The Operand is read from the Memory into
PC

R1

MDR, it is transferred from MDR, it is IR

transffered from to the ALU to perform the

ALU
Rn - 1

designed operation. n general purpose

registers

Connection Between the Processor and the Memory

Memory
Operand Adress (IR) ----------> MAR --------------------> MDR--Out---------->
ALU Read Signal

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 Basic Operational Concepts
Typical Operating Steps :: 3 Memory

Storing The Result ::

• To store the result of this operation, the MAR MDR

result is sent to MDR R0

Control

• The address of the location where the

PC

R1

result is to be stored is sent to the MAR IR

and a Write Cycle is initiated.

ALU
Rn - 1

n general purpose
registers

Connection Between the Processor and the Memory

Result ----------> MDR -------> Written into ------------> Memory

Address ----------> MAR

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 Basic Operational Concepts
Typical Operating Steps :: 4 Memory

Increment PC ::
• At some point during the execution of the MAR MDR

current instruction, the the conetnt of PC R0

Control

the(address) PC is incremented to point to R1

the next instruction to be executed

IR

ALU
Rn - 1

n general purpose

• As soon as the execution of the current

registers

instruction is completed, a new fetch cycle Connection Between the Processor and the Memory
may be initiated.
• PC = PC + 1

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 Basic Operational Concepts
A Typical Instruction
• ADD LOCA, R0
Ø Add the operand at Memory Location LOCA to the Operand in a
Register R0 in the Processor.
Ø Place the SUM into Register R0.
Ø The original contents of LOCA are preserved.
Ø The original contents of R0 is overwritten.
Ø Instruction is fetched from the Memory into the Processor – the Operand
at LOCA is fetched and added to the contents of R0 – the resulting SUM is
stored in Register R0.

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 Memory Access & ALU Operation

Example:-
• Load LOCA, R1

• Add R1, R0

• Whose contents will be overwritten?

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 Interrupt
• Normal Execution of Programs may be preempted if some
device requires urgent Servicing.
• The normal execution of the current Program must be
interrupted – the device raises an Interrupt Signal.
• Interrupt-Service Routine
• Current System information Backup and Restore (PC, General-
Purpose Registers, Control Information, specific information)

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 Bus Structures
Bus ::
• is a Communication Pathway connecting more
than one devices
• A group of lines that serves as a connecting path
for several devices is called a Bus.
• Each line transmits one bit (0 / 1)
• No of lines are required to transmit one word of
data to get reasonable speed.
• External / System bus connects Major Computer
Components (Processor / Memory I/O etc).

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 Bus Structures
• Internal bus is internal to
the Processor.
• Bus Classification ::
Address/Data/Control Bus
& a Power line
• Bus :: Serial | Parallel

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 Speed Issue
Different devices have different
transfer/operating speed.
If the speed of bus is bounded by the
slowest device connected to it, the
efficiency will be very low.
How to solve this?
A common approach – use buffers.

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 Performance
• The most important measure of a computer is how quickly it can execute programs.
• Three factors affect performance:
► Hardware design
► Instruction set
Main Cache
► Compiler memory memory
Processor

Bus

• Processor Time to execute a Program depends on the Hardware involved in

the execution of individual Machine Instructions.

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 Processor Clock
• Clock :- Processor Circuits are controlled by Timing Signal
• Clock Cycle:- A regular time interval (Ex. Cycle length P)
• Clock Rate (R):- Inverse of Clock Cycle { R = ⅟p } which is
measured in Cycles per Second.
• The execution of each Instruction is divided into several
steps, each of which completes in one Clock Cycle.
• Hertz (Hz) – Cycles per Second

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 Basic Performance Equation
• T – Processor Time required to execute a Program that has been prepared in
High-Level Language
• N – Number of actual Machine Language Instructions needed to complete the
execution (note: loop)
• S – Average number of Basic Steps needed to execute one Machine Instruction.
Each step completes in one Clock Cycle
• R – Clock Rate
✓ Note:- These are not independent to each other

T = N ×S
How to improve T ?
✓Reduce N & S
R
✓Increase R

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 Pipeline & Superscalar Operation
• If source program complied in fewer machine instruction
✓ Reduced Instruction Set Computers (RISC)
✓ Complex Instruction Set Computers (CISC)
• Goal – reduce N
• Instructions are not necessarily executed one after another.
• The value of S doesn’t have to be the number of clock cycles to execute one instruction.
• Pipelining – overlapping the execution of successive instructions.
• Superscalar operation – multiple instruction pipelines are implemented in the processor.
• Goal – reduce S
• Increase clock rate
► Improve the integrated-circuit (IC) technology to make the circuits faster
► Reduce the amount of processing done in one basic step
• Increases in R that are entirely caused by improvements in IC technology affect all aspects
of the processor’s operation equally except the time to access the main memory.

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 CISC vs. RISC Organizations

Microprogrammed
Control Unit Hardwared
Cache Control Unit
Microprogrammed
Control Memory Instruction Data
Cache Cache

Main Memory Main Memory

(a) CISC Organization (b) RISC Organization

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 Compiler
• A Compiler translates a High-Level Language Program into a sequence of
Machine Instructions.
• To reduce N, we need a suitable Machine Instruction set and a Compiler
that makes good use of it.
• Goal – reduce N×S
• A Compiler may not be designed for a specific processor; however, a high-
quality Compiler is usually designed for, and with, a specific Processor.

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 Multiprocessors & Multicomputer
• Multiprocessor
► Execute a number of different application tasks in parallel
► Execute subtasks of a single large task in parallel
► All processors have access to all of the memory – shared- memory
multiprocessor
► Cost – processors, memory units, complex interconnection networks
• Multicomputer
► Each computer only have access to its own memory
► Exchange message via a communication network – message- passing
multicomputer

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 UMA vs. NUMA Computers

P1 P2 Pn P1 P2 Pn

Cache Cache Cache Cache Cache Cache

Bus
Main Main Main
Memory Memory Memory
Main
Memory

Network

(a) UMA Model (b) NUMA Model

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 Memory Location, Addresses,& Operation
n bits
• Memory consists of many millions of
first word
storage cells, each of which can store 1 second word
bit data as 0/1.
• Data is usually accessed in groups, in •
n-bit as Word •
•

i th word

(Where n is called word length ).

•
•
•

last word

Memory words.

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 Memory Location, Addresses & Operation
• 32-bit word length example
32 bits

b31 b30 b1 b0

•
•
•
Sign bit: b31= 0 for positive numbers
b31= 1 for negative numbers

(a) A signed integer

8 bits 8 bits 8 bits 8 bits

ASCII ASCII ASCII ASCII

character character character character
(b) Four characters

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 Memory Location, Addresses & Operation
• Namely 0 to 2k - 1 ➔ called as Memory Space.
• To retrieve information from memory, either for one word or one byte
(8-bit), addresses for each location are needed.
• A k-bit address memory has 2k memory locations
• Example:-
• 24-bit memory: 224 = 16,777,216 = 16M (1M=220)
• 32-bit memory: 232 = 4G (1G=230)
• 1K(kilo)=210
• 1T(tera)=240

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 Memory Location, Addresses & Operation
• It is impractical to assign distinct addresses to individual bit locations in
the memory.
• The most practical assignment is to have successive addresses refer to
successive byte locations in the memory called as ➔ byte-addressable
memory.
• Byte locations have addresses 0, 1, 2, …
• If word length is 32 bits, they successive words are located at addresses
0, 4, 8,…, with each word consists of four bytes.

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 Von Neumann Architecture
• Von Neumann architecture was first published by
John von Neumann in 1945.
• Von Neumann architecture is based on the stored-
program computer concept (Reffered As IAS
Computer, Developed at the Princeton Institute for
Advanced Studies).
• Where instruction Data and Program are stored in
the same memory. This design is still used in most
computers produced today.
• His computer architecture design consists of a
Control Unit, Arithmetic and Logic Unit (ALU),
Memory Unit, Registers and Inputs/Outputs.

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 Von Neumann Cond...
Central Processing Unit (CPU) ::
• The Central Processing Unit (CPU) is the
electronic circuit responsible for executing the
instructions of a computer program.
• It is sometimes referred to as the microprocessor or
processor.

• Registers are high speed storage areas in the CPU.

All data must be stored in a register before it can
be processed.

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 Von Neumann Cond...
• MAR (Memory Address Register) :: Holds the
memory location of data that needs to be accessed
• MDR (Memory Data Register) :: Holds data that
is being transferred to or from memory
• AC (Accumulator):: Where intermediate
arithmetic and logic results are stored
• PC (Program Counter) :: Contains the address of
the next instruction to be executed
• CIR(Current Instruction Register) :: Contains the
current instruction during processing

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 Von Neumann Cond...
Arithmetic and Logic Unit (ALU)
• The ALU allows arithmetic (add, subtract etc) and
logic (AND, OR, NOT etc) operations to be carried
out.
Control Unit (CU)
• The control unit controls the operation of the
computer’s ALU, memory and input/output devices,
telling them how to respond to the program
instructions it has just read and interpreted from the
memory unit.
• The control unit also provides the timing and control
signals required by other computer components.

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 Von Neumann Cond...
• Buses :: Buses are the means by which data is transmitted from one part of a
computer to another, connecting all major internal components to the CPU
and memory.
• A standard CPU system bus is comprised of a control bus, data bus and
address bus.
• Address Bus :: Carries the addresses of data (but not the data) between the
processor and memory
• Data Bus :: Carries data between the processor, the memory unit and the
input/output devices
• Control Bus :: Carries control signals/commands from the CPU (and status
signals from other devices) in order to control and coordinate all the
activities within the computer

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 Von Neumann Cond...
Memory Unit ::
• The memory unit consists of RAM, sometimes referred to as primary
or main memory, Called M .
• RAM is split into partitions both Data & Instructions. This memory
is fast and also directly accessible by the CPU.
• RAM is split into partitions. Each partition consists of an address
and its contents (both in binary form).
• The address will uniquely identify every location in the memory.

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 Von Neumann Cond...
Memory 4096
• Stored Program Organization :: The computer is Instructions (Program)
organized to have one processor register & an
instruction code format with two parts.
Operand (Data)
• The First part specifies the operation to be
performed and the second part specifies an address.
15 12-11 0 ----------- -------------------

22 ADD 457
OPCODE ADDRESS
---------- ---------------
15 0
Operand
OPERAND 457

PROCESSOR REGISTER (AC)

212 = 4096 (No of Memory Words)

24 = 16 Operations (4-bits)
Memory Word Length = 16-bit AC
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 Harvard Architecture
• Harvard architecture is a type of
computer architecture that
separates its memory into two
parts.
• Data and Instructions are stored
separately.
• The architecture also has
separate buses for data transfers
and instruction fetches.
• This allows the CPU to fetch data
and instructions at the same time.
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 Harvard Architecture

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 Harvard Architecture
Harvard Architecture
• The Harvard architecture stores machine instructions and data
in separate memory units that are connected by different
busses.
• In this case, there are at least two memory address spaces to
work with, so there is a memory register for machine
instructions and another memory register for data.
• Computers designed with the Harvard architecture are able to run a program and
access data independently, and therefore simultaneously.

• Harvard architecture has a strict separation between data and code.

• Thus, Harvard architecture is more complicated but separate pipelines remove the
bottleneck that Von Neumann creates.
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 Von-Neumann Architecture
Von-Neumann architecture
• In a Von-Neumann architecture, the same
memory and bus are used to store both data and
instructions that run the program.

• Since you cannot access program memory and data memory

simultaneously, the Von Neumann architecture is susceptible
to bottlenecks and system performance is affected.

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 Modified Harvard Architecture
• The majority of modern computers have no physical separation between the memory
spaces used by both data and programs/code/machine instructions, and therefore
could be described technically as Von Neumann for this reason.
• However, the better way to represent the majority of modern computers is a
“Modified Harvard architecture.”
• Modern processors might share memory but have mechanisms like special
instructions that keep data from being mistaken for code.
• Some call this “modified Harvard architecture.” However, modified Harvard
architecture does have two separate pathways (busses) for signal (code) and storage
(memory), while the memory itself is one shared, physical piece. The memory
controller is where the modification is seated, since it handles the memory and how it
is used.

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 Big-Endian & Little-Endian Assignments
Word address Byte address Byte address
✓Big-Endian Organization :- Puts the
0 0 1 2 3 0 3 2 1 0
most significant byte, i.e. the big end
at the first byte (lower byte addresses) 4 4 5 6 7 4 7 6 5 4

and least significant bytes after it.

• •
✓Little-Endian Oraganization : - Stores • •
the least significant byte, the little end, • •
at the lower byte addresses and most k k k k k k k k k k
significant bytes at the higher byte 2 -4 2 -4 2 -3 2- 2 2-1 2 - 4 2- 1 2 - 2 2 - 2 -4

address. (a) Big-endian assignment (b) Little-endian assignment

Byte and word addressing.

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 Big-Endian & Little-Endian Assignments
CPU Word
CPU word bit location b31 ....b24 b23 .... b16 b15 .... b8 b7 .... b0

Big-Endian Byte Address 0 1 2 3

Little-Endian Byte Address 3 2 1 0

Example :: To Store 0 R A J J A R 0
RAJ KUMAR 03 4 K U M A A M U K 4

8 R 0 0 0 0 0 0 R 8

12 0 0 0 03 0 0 0 03 12
Big-Endian Little-Endian

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 8-Bit & 16-Bit Representation “HELLO”
16-Bit 16-Bit 8- 8-
Bit Bit
H E E H H
H
L L L L E E

O O L L

L L

O O
Big-Endian 16 Bit Little-Endian16-Bit

Big-Endian Little-Endian

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 Instruction Set Architecture(ISA)

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 CENTRAL PROCESSING UNIT
• Introduction

• Types of computer Organization

• Instruction Formats

• Addressing Modes

•Instruction Set Completeness

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