x86-64 - Wikipedia https://en.wikipedia.

org/wiki/X86-64

x86-64
x86-64 (also known as x64, x86_64, AMD64, and Intel
64)[note 1] is a 64-bit version of the x86 instruction set, first
announced in 1999. It introduced two new modes of operation,
64-bit mode and compatibility mode, along with a new 4-level
paging mode.

With 64-bit mode and the new paging mode, it supports vastly
larger amounts of virtual memory and physical memory than
was possible on its 32-bit predecessors, allowing programs to
store larger amounts of data in memory. x86-64 also expands
general-purpose registers to 64-bit, and expands the number of
them from 8 (some of which had limited or fixed functionality, AMD Opteron, the first CPU to
e.g. for stack management) to 16 (fully general), and provides introduce the x86-64 extensions in
numerous other enhancements. Floating-point arithmetic is April 2003
supported via mandatory SSE2-like instructions, and x87/
MMX style registers are generally not used (but still available
even in 64-bit mode); instead, a set of 16 vector registers, 128
bits each, is used. (Each register can store one or two double-
precision numbers or one to four single-precision numbers, or
various integer formats.) In 64-bit mode, instructions are
modified to support 64-bit operands and 64-bit addressing
mode.

The compatibility mode defined in the architecture allows 16-

The five-volume set of the x86-64
bit and 32-bit user applications to run unmodified, coexisting Architecture Programmer's Manual,
with 64-bit applications if the 64-bit operating system supports as published and distributed by
them.[11][note 2] As the full x86 16-bit and 32-bit instruction sets AMD in 2002
remain implemented in hardware without any intervening
emulation, these older executables can run with little or no
performance penalty,[13] while newer or modified applications can take advantage of new features
of the processor design to achieve performance improvements. Also, a processor supporting
x86-64 still powers on in real mode for full backward compatibility with the 8086, as x86
processors supporting protected mode have done since the 80286.

The original specification, created by AMD and released in 2000, has been implemented by AMD,
Intel, and VIA. The AMD K8 microarchitecture, in the Opteron and Athlon 64 processors, was the
first to implement it. This was the first significant addition to the x86 architecture designed by a
company other than Intel. Intel was forced to follow suit and introduced a modified NetBurst
family which was software-compatible with AMD's specification. VIA Technologies introduced

1 of 32 31/07/2024, 15:42
x86-64 - Wikipedia https://en.wikipedia.org/wiki/X86-64

x86-64 in their VIA Isaiah architecture, with the VIA Nano.

The x86-64 architecture was quickly adopted for desktop and laptop personal computers and
servers which were commonly configured for 16 GiB (gibibytes) of memory or more. It has
effectively replaced the discontinued Intel Itanium architecture (formerly IA-64), which was
originally intended to replace the x86 architecture. x86-64 and Itanium are not compatible on the
native instruction set level, and operating systems and applications compiled for one architecture
cannot be run on the other natively.

AMD64

History
AMD64 (also variously referred to by AMD in their literature and
documentation as “AMD 64-bit Technology” and “AMD x86-64 Architecture”)
was created as an alternative to the radically different IA-64 architecture
designed by Intel and Hewlett-Packard, which was backward-incompatible AMD64 logo
with IA-32, the 32-bit version of the x86 architecture. AMD originally
announced AMD64 in 1999[14] with a full specification available in August
2000.[15] As AMD was never invited to be a contributing party for the IA-64 architecture and any
kind of licensing seemed unlikely, the AMD64 architecture was positioned by AMD from the
beginning as an evolutionary way to add 64-bit computing capabilities to the existing x86
architecture while supporting legacy 32-bit x86 code, as opposed to Intel's approach of creating an
entirely new, completely x86-incompatible 64-bit architecture with IA-64.

The first AMD64-based processor, the Opteron, was released in April 2003.

Implementations
AMD's processors implementing the AMD64 architecture include Opteron, Athlon 64, Athlon 64
X2, Athlon 64 FX, Athlon II (followed by "X2", "X3", or "X4" to indicate the number of cores, and
XLT models), Turion 64, Turion 64 X2, Sempron ("Palermo" E6 stepping and all "Manila"
models), Phenom (followed by "X3" or "X4" to indicate the number of cores), Phenom II (followed
by "X2", "X3", "X4" or "X6" to indicate the number of cores), FX, Fusion/APU and Ryzen/Epyc.

Architectural features
The primary defining characteristic of AMD64 is the availability of 64-bit general-purpose
processor registers (for example, rax), 64-bit integer arithmetic and logical operations, and 64-bit
virtual addresses.[16] The designers took the opportunity to make other improvements as well.

Notable changes in the 64-bit extensions include:

64-bit integer capability

2 of 32 31/07/2024, 15:42
x86-64 - Wikipedia https://en.wikipedia.org/wiki/X86-64

All general-purpose registers (GPRs) are expanded from 32 bits to 64 bits, and all arithmetic
and logical operations, memory-to-register and register-to-memory operations, etc., can
operate directly on 64-bit integers. Pushes and pops on the stack default to 8-byte strides,
and pointers are 8 bytes wide.
Additional registers
In addition to increasing the size of the general-purpose registers, the number of named
general-purpose registers is increased from eight (i.e. eax, ecx, edx, ebx, esp, ebp, esi,
edi) in x86 to 16 (i.e. rax, rcx, rdx, rbx, rsp, rbp, rsi, rdi, r8, r9, r10, r11, r12, r13,
r14, r15). It is therefore possible to keep more local variables in registers rather than on the
stack, and to let registers hold frequently accessed constants; arguments for small and fast
subroutines may also be passed in registers to a greater extent.
AMD64 still has fewer registers than many RISC instruction sets (e.g. Power ISA has 32
GPRs; 64-bit ARM, RISC-V I, SPARC, Alpha, MIPS, and PA-RISC have 31) or VLIW-like
machines such as the IA-64 (which has 128 registers). However, an AMD64 implementation
may have far more internal registers than the number of architectural registers exposed by
the instruction set (see register renaming). (For example, AMD Zen cores have 168 64-bit
integer and 160 128-bit vector floating-point physical internal registers.)
Additional XMM (SSE) registers
Similarly, the number of 128-bit XMM registers (used for Streaming SIMD instructions) is also
increased from 8 to 16.
The traditional x87 FPU register stack is not included in the register file size extension in 64-
bit mode, compared with the XMM registers used by SSE2, which did get extended. The x87
register stack is not a simple register file although it does allow direct access to individual
registers by low cost exchange operations.
Larger virtual address space
The AMD64 architecture defines a 64-bit virtual address format, of which the low-order 48
bits are used in current implementations.[11]: 120 This allows up to 256 TiB (248 bytes) of
virtual address space. The architecture definition allows this limit to be raised in future
implementations to the full 64 bits,[11]: 2 : 3 : 13 : 117 : 120 extending the virtual address space to
16 EiB (264 bytes).[17] This is compared to just 4 GiB (232 bytes) for the x86.[18]
This means that very large files can be operated on by mapping the entire file into the
process's address space (which is often much faster than working with file read/write calls),
rather than having to map regions of the file into and out of the address space.
Larger physical address space
The original implementation of the AMD64 architecture implemented 40-bit physical
addresses and so could address up to 1 TiB (240 bytes) of RAM.[11]: 24 Current
implementations of the AMD64 architecture (starting from AMD 10h microarchitecture)
extend this to 48-bit physical addresses[19] and therefore can address up to 256 TiB (248
bytes) of RAM. The architecture permits extending this to 52 bits in the future[11]: 24 [20]
(limited by the page table entry format);[11]: 131 this would allow addressing of up to 4 PiB of
RAM. For comparison, 32-bit x86 processors are limited to 64 GiB of RAM in Physical
Address Extension (PAE) mode,[21] or 4 GiB of RAM without PAE mode.[11]: 4
Larger physical address space in legacy mode
When operating in legacy mode the AMD64 architecture supports Physical Address
Extension (PAE) mode, as do most current x86 processors, but AMD64 extends PAE from 36
bits to an architectural limit of 52 bits of physical address. Any implementation, therefore,
allows the same physical address limit as under long mode.[11]: 24
Instruction pointer relative data access
Instructions can now reference data relative to the instruction pointer (RIP register). This
makes position-independent code, as is often used in shared libraries and code loaded at run

3 of 32 31/07/2024, 15:42
x86-64 - Wikipedia https://en.wikipedia.org/wiki/X86-64

time, more efficient.

SSE instructions
The original AMD64 architecture adopted Intel's SSE and SSE2 as core instructions. These
instruction sets provide a vector supplement to the scalar x87 FPU, for the single-precision
and double-precision data types. SSE2 also offers integer vector operations, for data types
ranging from 8bit to 64bit precision. This makes the vector capabilities of the architecture on
par with those of the most advanced x86 processors of its time. These instructions can also
be used in 32-bit mode. The proliferation of 64-bit processors has made these vector
capabilities ubiquitous in home computers, allowing the improvement of the standards of 32-
bit applications. The 32-bit edition of Windows 8, for example, requires the presence of SSE2
instructions.[22] SSE3 instructions and later Streaming SIMD Extensions instruction sets are
not standard features of the architecture.
No-Execute bit
The No-Execute bit or NX bit (bit 63 of the page table entry) allows the operating system to
specify which pages of virtual address space can contain executable code and which cannot.
An attempt to execute code from a page tagged "no execute" will result in a memory access
violation, similar to an attempt to write to a read-only page. This should make it more difficult
for malicious code to take control of the system via "buffer overrun" or "unchecked buffer"
attacks. A similar feature has been available on x86 processors since the 80286 as an
attribute of segment descriptors; however, this works only on an entire segment at a time.
Segmented addressing has long been considered an obsolete mode of operation, and all
current PC operating systems in effect bypass it, setting all segments to a base address of
zero and (in their 32-bit implementation) a size of 4 GiB. AMD was the first x86-family vendor
to implement no-execute in linear addressing mode. The feature is also available in legacy
mode on AMD64 processors, and recent Intel x86 processors, when PAE is used.
Removal of older features
A few "system programming" features of the x86 architecture were either unused or
underused in modern operating systems and are either not available on AMD64 in long (64-
bit and compatibility) mode, or exist only in limited form. These include segmented
addressing (although the FS and GS segments are retained in vestigial form for use as extra-
base pointers to operating system structures),[11]: 70 the task state switch mechanism, and
virtual 8086 mode. These features remain fully implemented in "legacy mode", allowing these
processors to run 32-bit and 16-bit operating systems without modifications. Some
instructions that proved to be rarely useful are not supported in 64-bit mode, including
saving/restoring of segment registers on the stack, saving/restoring of all registers (PUSHA/
POPA), decimal arithmetic, BOUND and INTO instructions, and "far" jumps and calls with
immediate operands.

Virtual address space details

Canonical form addresses

Although virtual addresses are 64 bits wide in 64-bit mode, current implementations (and all chips
that are known to be in the planning stages) do not allow the entire virtual address space of 264
bytes (16 EiB) to be used. This would be approximately four billion times the size of the virtual
address space on 32-bit machines. Most operating systems and applications will not need such a
large address space for the foreseeable future, so implementing such wide virtual addresses would
simply increase the complexity and cost of address translation with no real benefit. AMD,
therefore, decided that, in the first implementations of the architecture, only the least significant

4 of 32 31/07/2024, 15:42
x86-64 - Wikipedia https://en.wikipedia.org/wiki/X86-64

48 bits of a virtual address

Canonical address space implementations (diagrams not to scale)
would actually be used in
address translation (page
table lookup).[11]: 120

In addition, the AMD

specification requires that
the most significant 16 bits
of any virtual address, bits
48 through 63, must be
copies of bit 47 (in a manner
akin to sign extension). If
this requirement is not met,
the processor will raise an
exception.[11]: 131 Addresses Current 48-bit 57-bit implementation 64-bit implementation
complying with this rule are implementation
referred to as "canonical
form."[11]: 130 Canonical form
addresses run from 0 through 00007FFF'FFFFFFFF, and from FFFF8000'00000000 through
FFFFFFFF'FFFFFFFF, for a total of 256 TiB of usable virtual address space. This is still 65,536
times larger than the virtual 4 GiB address space of 32-bit machines.

This feature eases later scalability to true 64-bit addressing. Many operating systems (including,
but not limited to, the Windows NT family) take the higher-addressed half of the address space
(named kernel space) for themselves and leave the lower-addressed half (user space) for
application code, user mode stacks, heaps, and other data regions.[23] The "canonical address"
design ensures that every AMD64 compliant implementation has, in effect, two memory halves:
the lower half starts at 00000000'00000000 and "grows upwards" as more virtual address bits
become available, while the higher half is "docked" to the top of the address space and grows
downwards. Also, enforcing the "canonical form" of addresses by checking the unused address bits
prevents their use by the operating system in tagged pointers as flags, privilege markers, etc., as
such use could become problematic when the architecture is extended to implement more virtual
address bits.

The first versions of Windows for x64 did not even use the full 256 TiB; they were restricted to just
8 TiB of user space and 8 TiB of kernel space.[23] Windows did not support the entire 48-bit
address space until Windows 8.1, which was released in October 2013.[23]

Page table structure

The 64-bit addressing mode ("long mode") is a superset of Physical Address Extensions (PAE);
because of this, page sizes may be 4 KiB (212 bytes) or 2 MiB (221 bytes).[11]: 120 Long mode also
supports page sizes of 1 GiB (230 bytes).[11]: 120 Rather than the three-level page table system used
by systems in PAE mode, systems running in long mode use four levels of page table: PAE's Page-
Directory Pointer Table is extended from four entries to 512, and an additional Page-Map Level 4
(PML4) Table is added, containing 512 entries in 48-bit implementations.[11]: 131 A full mapping

5 of 32 31/07/2024, 15:42
x86-64 - Wikipedia https://en.wikipedia.org/wiki/X86-64

hierarchy of 4 KiB
pages for the whole
48-bit space would
take a bit more
than 512 GiB of
memory (about
0.195% of the
256 TiB virtual
space).

64 bit page table entry

Bits: 63 62 … 52 51 … 32

Content: NX reserved Bit 51…32 of base address

Bits: 31 … 12 11 … 9 8 7 6 5 4 3 2 1 0

Content: Bit 31…12 of base address ign. G PAT D A PCD PWT U/S R/W P

Intel has implemented a scheme with a 5-level page table, which allows Intel 64 processors to
support a 57-bit virtual address space.[24] Further extensions may allow full 64-bit virtual address
space and physical memory with 12-bit page table descriptors and 16- or 21-bit memory offsets for
64 KiB and 2 MiB page allocation sizes; the page table entry would be expanded to 128 bits to
support additional hardware flags for page size and virtual address space size.[25]

Operating system limits

The operating system can also limit the virtual address space. Details, where applicable, are given
in the "Operating system compatibility and characteristics" section.

Physical address space details

Current AMD64 processors support a physical address space of up to 248 bytes of RAM, or 256 TiB.
[19] However, as of 2020, there were no known x86-64 motherboards that support 256 TiB of

RAM.[26][27][28][29] The operating system may place additional limits on the amount of RAM that
is usable or supported. Details on this point are given in the "Operating system compatibility and
characteristics" section of this article.

Operating modes
The architecture has two primary modes of operation: long mode and legacy mode.

6 of 32 31/07/2024, 15:42
x86-64 - Wikipedia https://en.wikipedia.org/wiki/X86-64

Operating Size (in bits) No. of

Type of
Operating system operands general-
code
mode sub-mode required addresses (default in purpose
being run
italics) registers

64-bit OS, 64-bit UEFI

firmware, or the previous
64-bit mode two interacting via a 64- 64-bit 64 8, 16, 32, 64 16
bit firmware's UEFI
Long interface
mode
32-bit 32 8, 16, 32 8
Compatibility 16-bit
Bootloader or 64-bit OS
mode protected 16 8, 16, 32 8
mode

Bootloader, 32-bit OS,

32-bit UEFI firmware, or
the latter two interacting 32-bit 32 8, 16, 32 8
Protected via the firmware's UEFI
mode interface

16-bit
16-bit protected mode OS protected 16 8, 16, 32[m 1] 8
mode
Legacy
mode Virtual 8086 16-bit protected mode or subset of
16 8, 16, 32[m 1] 8
mode 32-bit OS real mode

Bootloader or real mode

Unreal mode real mode 16, 20, 32 8, 16, 32[m 1] 8
OS

Bootloader, real mode

OS, or any OS interfacing
Real mode
with a firmware's BIOS
real mode 16, 20, 21 8, 16, 32[m 1] 8
interface[30]

1. Note that 16-bit code written for the 80286 and below does not use 32-bit operand instructions.
Code written for the 80386 and above can use the operand-size override prefix (0x66).
Normally this prefix is used by protected and long mode code for the purpose of using 16-bit
operands, as that code would be running in a code segment with a default operand size of 32
bits. In real mode, the default operand size is 16 bits, so the 0x66 prefix is interpreted
differently, changing operand size to 32 bits.

Long mode
Long mode is the architecture's intended primary mode of operation; it is a combination of the
processor's native 64-bit mode and a combined 32-bit and 16-bit compatibility mode. It is used by
64-bit operating systems. Under a 64-bit operating system, 64-bit programs run under 64-bit
mode, and 32-bit and 16-bit protected mode applications (that do not need to use either real mode
or virtual 8086 mode in order to execute at any time) run under compatibility mode. Real-mode
programs and programs that use virtual 8086 mode at any time cannot be run in long mode unless
those modes are emulated in software.[11]: 11 However, such programs may be started from an
operating system running in long mode on processors supporting VT-x or AMD-V by creating a
virtual processor running in the desired mode.

7 of 32 31/07/2024, 15:42
x86-64 - Wikipedia https://en.wikipedia.org/wiki/X86-64

Since the basic instruction set is the

same, there is almost no performance
penalty for executing protected mode
x86 code. This is unlike Intel's IA-64,
where differences in the underlying
instruction set mean that running 32-
bit code must be done either in
emulation of x86 (making the process
slower) or with a dedicated x86
coprocessor. However, on the x86-64
platform, many x86 applications
could benefit from a 64-bit recompile,
due to the additional registers in 64-
bit code and guaranteed SSE2-based
FPU support, which a compiler can
use for optimization. However, State diagram of the x86-64 operating modes
applications that regularly handle
integers wider than 32 bits, such as
cryptographic algorithms, will need a rewrite of the code handling the huge integers in order to
take advantage of the 64-bit registers.

Legacy mode
Legacy mode is the mode that the processor is in when it is not in long mode.[11]: 14 In this mode,
the processor acts like an older x86 processor, and only 16-bit and 32-bit code can be executed.
Legacy mode allows for a maximum of 32 bit virtual addressing which limits the virtual address
space to 4 GiB.[11]: 14 : 24 : 118 64-bit programs cannot be run from legacy mode.

Protected mode
Protected mode is made into a submode of legacy mode.[11]: 14 It is the submode that 32-bit
operating systems and 16-bit protected mode operating systems operate in when running on an
x86-64 CPU.[11]: 14

Real mode
Real mode is the initial mode of operation when the processor is initialized, and is a submode of
legacy mode. It is backwards compatible with the original Intel 8086 and Intel 8088 processors.
Real mode is primarily used today by operating system bootloaders, which are required by the
architecture to configure virtual memory details before transitioning to higher modes. This mode is
also used by any operating system that needs to communicate with the system firmware with a
traditional BIOS-style interface.[30]

Intel 64

8 of 32 31/07/2024, 15:42
x86-64 - Wikipedia https://en.wikipedia.org/wiki/X86-64

Intel 64 is Intel's implementation of x86-64, used and implemented in various processors made
by Intel.

History
Historically, AMD has developed and produced processors with instruction sets patterned after
Intel's original designs, but with x86-64, roles were reversed: Intel found itself in the position of
adopting the ISA that AMD created as an extension to Intel's own x86 processor line.

Intel's project was originally codenamed Yamhill[31] (after the Yamhill River in Oregon's
Willamette Valley). After several years of denying its existence, Intel announced at the February
2004 IDF that the project was indeed underway. Intel's chairman at the time, Craig Barrett,
admitted that this was one of their worst-kept secrets.[32][33]

Intel's name for this instruction set has changed several times. The name used at the IDF was
CT[34] (presumably for Clackamas Technology, another codename from an Oregon river); within
weeks they began referring to it as IA-32e (for IA-32 extensions) and in March 2004 unveiled the
"official" name EM64T (Extended Memory 64 Technology). In late 2006 Intel began instead using
the name Intel 64 for its implementation, paralleling AMD's use of the name AMD64.[35]

The first processor to implement Intel 64 was the multi-socket processor Xeon code-named
Nocona in June 2004. In contrast, the initial Prescott chips (February 2004) did not enable this
feature. Intel subsequently began selling Intel 64-enabled Pentium 4s using the E0 revision of the
Prescott core, being sold on the OEM market as the Pentium 4, model F. The E0 revision also adds
eXecute Disable (XD) (Intel's name for the NX bit) to Intel 64, and has been included in then
current Xeon code-named Irwindale. Intel's official launch of Intel 64 (under the name EM64T at
that time) in mainstream desktop processors was the N0 stepping Prescott-2M.

The first Intel mobile processor implementing Intel 64 is the Merom version of the Core 2
processor, which was released on July 27, 2006. None of Intel's earlier notebook CPUs (Core Duo,
Pentium M, Celeron M, Mobile Pentium 4) implement Intel 64.

Implementations
Intel's processors implementing the Intel64 architecture include the Pentium 4 F-series/5x1 series,
506, and 516, Celeron D models 3x1, 3x6, 355, 347, 352, 360, and 365 and all later Celerons, all
models of Xeon since "Nocona", all models of Pentium Dual-Core processors since "Merom-2M",
the Atom 230, 330, D410, D425, D510, D525, N450, N455, N470, N475, N550, N570, N2600 and
N2800, all versions of the Pentium D, Pentium Extreme Edition, Core 2, Core i9, Core i7, Core i5,
and Core i3 processors, and the Xeon Phi 7200 series processors.

X86S
X86S is a simplification of x86-64 proposed by Intel in May 2023 for their "Intel 64" products.[36]
The new architecture would remove support for 16-bit and 32-bit operating systems, while 32-bit
programs will still run under a 64-bit OS. A CPU would no longer have legacy mode, and start

9 of 32 31/07/2024, 15:42
x86-64 - Wikipedia https://en.wikipedia.org/wiki/X86-64

directly in 64-bit long mode. There will be a way to switch to 5-level paging without going through
the unpaged mode. Specific removed features include:[37]

▪ Segmentation gates
▪ 32-bit ring 0
▪ VT-x will no longer emulate this feature
▪ Rings 1 and 2
▪ Ring 3 I/O port (IN/OUT) access; see port-mapped I/O
▪ String port I/O (INS/OUTS)
▪ Real mode (including huge real mode), 16-bit protected mode, VM86
▪ 16-bit addressing mode
▪ VT-x will no longer provide unrestricted mode
▪ 8259 support; the only APIC supported would be X2APIC
▪ Some unused operating system mode bits
▪ 16-bit and 32-bit Startup IPI (SIPI)
Intel believes the change follows logically after the removal of the A20 gate in 2008 and the
removal of 16-bit and 32-bit OS support in Intel firmware in 2020. Support for legacy operating
systems would be accomplished via hardware-accelerated virtualization and/or ring 0 emulation.
[37]

VIA's x86-64 implementation

VIA Technologies introduced their first implementation of the x86-64 architecture in 2008 after
five years of development by its CPU division, Centaur Technology.[38] Codenamed "Isaiah", the
64-bit architecture was unveiled on January 24, 2008,[39] and launched on May 29 under the VIA
Nano brand name.[40]

The processor supports a number of VIA-specific x86 extensions designed to boost efficiency in
low-power appliances. It is expected that the Isaiah architecture will be twice as fast in integer
performance and four times as fast in floating-point performance as the previous-generation VIA
Esther at an equivalent clock speed. Power consumption is also expected to be on par with the
previous-generation VIA CPUs, with thermal design power ranging from 5 W to 25 W.[41] Being a
completely new design, the Isaiah architecture was built with support for features like the x86-64
instruction set and x86 virtualization which were unavailable on its predecessors, the VIA C7 line,
while retaining their encryption extensions.

Microarchitecture levels
In 2020, through a collaboration between AMD, Intel, Red Hat, and SUSE, three microarchitecture
levels (or feature levels) on top of the x86-64 baseline were defined: x86-64-v2, x86-64-v3, and
x86-64-v4.[42][43] These levels define specific features that can be targeted by programmers to
provide compile-time optimizations. The features exposed by each level are as follows:[44]

10 of 32 31/07/2024, 15:42
x86-64 - Wikipedia https://en.wikipedia.org/wiki/X86-64

CPU microarchitecture levels

x86-64 Example
CPU features Supported processors
Level instruction

CMOV cmov

CX8 cmpxchg8b

FPU fld

FXSR fxsave all x86-64 CPUs

v1 MMX emms
matches the initial 2003 AMD K8 architecture
OSFXSR fxsave
(excluding AMD-specific instructions)
SCE syscall

SSE cvtss2si

SSE2 cvtpi2pd

CMPXCHG16B cmpxchg16b
Intel Nehalem and newer Intel "big" cores
LAHF-SAHF lahf
Intel (Atom) Silvermont and newer Intel "small" cores
POPCNT popcnt AMD Bulldozer and newer AMD "big" cores
v2 SSE3 addsubpd
AMD Jaguar
VIA Nano and Eden "C"
SSE4_1 blendpd

SSE4_2 pcmpestri feature level matches the 2008 Intel Nehalem

architecture (excluding Intel-specific instructions)
SSSE3 pshufb

AVX vzeroall

AVX2 vpermd
Intel Haswell and newer Intel "big" cores (AVX2
BMI1 andn enabled models only)
BMI2 bzhi Intel (Atom) Gracemont and newer Intel "small" cores
v3 F16C vcvtph2ps
AMD Excavator and newer AMD "big" cores
QEMU emulation (as of version 7.2)[45][46]
FMA vfmadd132pd

LZCNT lzcnt feature level matches the 2013 Intel Haswell

MOVBE movbe architecture (excluding Intel-specific instructions)
OSXSAVE xgetbv

AVX512F kmovw
Intel Skylake and newer Intel "big" cores (AVX512
AVX512BW vdbpsadbw enabled models only)
v4 AVX512CD vplzcntd
AMD Zen 4 cores

AVX512DQ vpmullq feature level matches the 2017 Intel Skylake-X

architecture (excluding Intel-specific instructions)
AVX512VL —

11 of 32 31/07/2024, 15:42
x86-64 - Wikipedia https://en.wikipedia.org/wiki/X86-64

All levels include features found in the previous levels. Instruction set extensions not concerned
with general-purpose computation, including AES-NI and RDRAND, are excluded from the level
requirements.

Differences between AMD64 and Intel 64

Although nearly identical, there are some differences between the two instruction sets in the
semantics of a few seldom used machine instructions (or situations), which are mainly used for
system programming.[47] Compilers generally produce executables (i.e. machine code) that avoid
any differences, at least for ordinary application programs. This is therefore of interest mainly to
developers of compilers, operating systems and similar, which must deal with individual and
special system instructions.

Recent implementations
▪ Intel 64's BSF and BSR instructions act differently than AMD64's when the source is zero and
the operand size is 32 bits. The processor sets the zero flag and leaves the upper 32 bits of the
destination undefined. Note that Intel documents that the destination register has an undefined
value in this case, but in practice in silicon implements the same behaviour as AMD
(destination unmodified). The separate claim about maybe not preserving bits in the upper 32
has not been verified, but has only been ruled out for Core 2 and Skylake,[48] not all Intel
microarchitectures like 64-bit Pentium 4 or low-power Atom.
▪ AMD64 requires a different microcode update format and control MSRs (model-specific
registers), while Intel 64 implements microcode update unchanged from their 32-bit only
processors.
▪ Intel 64 lacks some MSRs that are considered architectural in AMD64. These include SYSCFG,
TOP_MEM, and TOP_MEM2.
▪ Intel 64 allows SYSCALL/SYSRET only in 64-bit mode (not in compatibility mode),[49] and allows
SYSENTER/SYSEXIT in both modes.[50] AMD64 lacks SYSENTER/SYSEXIT in both sub-modes of
long mode.[11]: 33
▪ In 64-bit mode, near branches with the 66H (operand size override) prefix behave differently.
Intel 64 ignores this prefix: the instruction has a 32-bit sign extended offset, and instruction
pointer is not truncated. AMD64 uses a 16-bit offset field in the instruction, and clears the top
48 bits of instruction pointer.
▪ On Intel 64 but not AMD64, the REX.W prefix can be used with the far-pointer instructions (LFS,
LGS, LSS, JMP FAR, CALL FAR) to increase the size of their far pointer argument to 80 bits (64-
bit offset + 16-bit segment).
▪ Intel 64 lacks the ability to save and restore a reduced (and thus faster) version of the floating-
point state (involving the FXSAVE and FXRSTOR instructions).
▪ AMD processors ever since Opteron Rev. E and Athlon 64 Rev. D have reintroduced limited
support for segmentation, via the Long Mode Segment Limit Enable (LMSLE) bit, to ease
virtualization of 64-bit guests.[51][52] LMLSE support was removed in the Zen 3 processor. [53]
▪ When returning to a non-canonical address using SYSRET, AMD64 processors execute the
general protection fault handler in privilege level 3,[54] while on Intel 64 processors it is
executed in privilege level 0.[55]

12 of 32 31/07/2024, 15:42
x86-64 - Wikipedia https://en.wikipedia.org/wiki/X86-64

▪ The ordering guarantees provided by some memory ordering instructions such as LFENCE and
MFENCE differ between Intel 64 and AMD64:
▪ LFENCE is dispatch-serializing (enabling it to be used as a speculation fence) on Intel 64 but
is not architecturally guaranteed to be dispatch-serializing on AMD64.[56]
▪ MFENCE is a fully serializing instruction (including instruction fetch serialization) on AMD64
but not Intel 64.

Older implementations
▪ The AMD64 processors prior to Revision F[57] (distinguished by the switch from DDR to DDR2
memory and new sockets AM2, F and S1) of 2006 lacked the CMPXCHG16B instruction, which is
an extension of the CMPXCHG8B instruction present on most post-80486 processors. Similar to
CMPXCHG8B, CMPXCHG16B allows for atomic operations on octa-words (128-bit values). This is
useful for parallel algorithms that use compare and swap on data larger than the size of a
pointer, common in lock-free and wait-free algorithms. Without CMPXCHG16B one must use
workarounds, such as a critical section or alternative lock-free approaches.[58] Its absence also
prevents 64-bit Windows prior to Windows 8.1 from having a user-mode address space larger
than 8 TiB.[59] The 64-bit version of Windows 8.1 requires the instruction.[60]
▪ Early AMD64 and Intel 64 CPUs lacked LAHF and SAHF instructions in 64-bit mode. AMD
introduced these instructions (also in 64-bit mode) with their 90 nm (revision D) processors,
starting with Athlon 64 in October 2004.[61][62] Intel introduced the instructions in October 2005
with the 0F47h and later revisions of NetBurst.[68] The 64-bit version of Windows 8.1 requires
this feature.[60]
▪ Early Intel CPUs with Intel 64 also lack the NX bit of the AMD64 architecture. It was added in
the stepping E0 (0F41h) Pentium 4 in October 2004.[69] This feature is required by all versions
of Windows 8.
▪ Early Intel 64 implementations had a 36-bit (64 GiB) physical addressing of memory while
original AMD64 implementations had a 40-bit (1 TiB) physical addressing. Intel used the 40-bit
physical addressing first on Xeon MP (Potomac), launched on 29 March 2005.[70] The
difference is not a difference of the user-visible ISAs. In 2007 AMD 10h-based Opteron was the
first to provide a 48-bit (256 TiB) physical address space.[71][72] Intel 64's physical addressing
was extended to 44 bits (16 TiB) in Nehalem-EX in 2010[73] and to 46 bits (64 TiB) in Sandy
Bridge E in 2011.[74][75] With the Ice Lake 3rd gen Xeon Scalable processors, Intel increased
the virtual addressing to 57 bits (128 PiB) and physical to 52 bits (4 PiB) in 2021, necessitating
a 5-level paging.[76] The following year AMD64 added the same in 4th generation EPYC
(Genoa).[77] Non-server CPUs retain smaller address spaces for longer.

Adoption
In supercomputers tracked by TOP500, the appearance of 64-bit extensions for the x86
architecture enabled 64-bit x86 processors by AMD and Intel to replace most RISC processor
architectures previously used in such systems (including PA-RISC, SPARC, Alpha and others), as
well as 32-bit x86, even though Intel itself initially tried unsuccessfully to replace x86 with a new
incompatible 64-bit architecture in the Itanium processor.

As of 2023, a HPE EPYC-based supercomputer called Frontier is number one. The first ARM-based

13 of 32 31/07/2024, 15:42
x86-64 - Wikipedia https://en.wikipedia.org/wiki/X86-64

supercomputer appeared on the list in

2018[79] and, in recent years, non-CPU
architecture co-processors (GPGPU) have
also played a big role in performance. Intel's
Xeon Phi "Knights Corner" coprocessors,
which implement a subset of x86-64 with
some vector extensions,[80] are also used,
along with x86-64 processors, in the
Tianhe-2 supercomputer.[81]

An area chart showing the representation of different

families of microprocessors in the TOP500 supercomputer
ranking list, from 1993 to 2020[78]

Operating system compatibility and characteristics

The following operating systems and releases support the x86-64 architecture in long mode.

BSD

DragonFly BSD
Preliminary infrastructure work was started in February 2004 for a x86-64 port.[82] This
development later stalled. Development started again during July 2007[83] and continued during
Google Summer of Code 2008 and SoC 2009.[84][85] The first official release to contain x86-64
support was version 2.4.[86]

FreeBSD
FreeBSD first added x86-64 support under the name "amd64" as an experimental architecture in
5.1-RELEASE in June 2003. It was included as a standard distribution architecture as of 5.2-
RELEASE in January 2004. Since then, FreeBSD has designated it as a Tier 1 platform. The 6.0-
RELEASE version cleaned up some quirks with running x86 executables under amd64, and most
drivers work just as they do on the x86 architecture. Work is currently being done to integrate
more fully the x86 application binary interface (ABI), in the same manner as the Linux 32-bit ABI
compatibility currently works.

NetBSD
x86-64 architecture support was first committed to the NetBSD source tree on June 19, 2001. As of
NetBSD 2.0, released on December 9, 2004, NetBSD/amd64 is a fully integrated and supported

14 of 32 31/07/2024, 15:42
x86-64 - Wikipedia https://en.wikipedia.org/wiki/X86-64

port. 32-bit code is still supported in 64-bit mode, with a netbsd-32 kernel compatibility layer for
32-bit syscalls. The NX bit is used to provide non-executable stack and heap with per-page
granularity (segment granularity being used on 32-bit x86).

OpenBSD
OpenBSD has supported AMD64 since OpenBSD 3.5, released on May 1, 2004. Complete in-tree
implementation of AMD64 support was achieved prior to the hardware's initial release because
AMD had loaned several machines for the project's hackathon that year. OpenBSD developers have
taken to the platform because of its support for the NX bit, which allowed for an easy
implementation of the W^X feature.

The code for the AMD64 port of OpenBSD also runs on Intel 64 processors which contains cloned
use of the AMD64 extensions, but since Intel left out the page table NX bit in early Intel 64
processors, there is no W^X capability on those Intel CPUs; later Intel 64 processors added the NX
bit under the name "XD bit". Symmetric multiprocessing (SMP) works on OpenBSD's AMD64 port,
starting with release 3.6 on November 1, 2004.

DOS
It is possible to enter long mode under DOS without a DOS extender,[87] but the user must return
to real mode in order to call BIOS or DOS interrupts.

It may also be possible to enter long mode with a DOS extender similar to DOS/4GW, but more
complex since x86-64 lacks virtual 8086 mode. DOS itself is not aware of that, and no benefits
should be expected unless running DOS in an emulation with an adequate virtualization driver
backend, for example: the mass storage interface.

Linux
Linux was the first operating system kernel to run the x86-64 architecture in long mode, starting
with the 2.4 version in 2001 (preceding the hardware's availability).[88][89] Linux also provides
backward compatibility for running 32-bit executables. This permits programs to be recompiled
into long mode while retaining the use of 32-bit programs. Current Linux distributions ship with
x86-64-native kernels and userlands. Some, such as Arch Linux,[90] SUSE, Mandriva, and Debian,
allow users to install a set of 32-bit components and libraries when installing off a 64-bit
distribution medium, thus allowing most existing 32-bit applications to run alongside the 64-bit
OS.

x32 ABI (Application Binary Interface), introduced in Linux 3.4, allows programs compiled for the
x32 ABI to run in the 64-bit mode of x86-64 while only using 32-bit pointers and data fields.[91][92]
[93] Though this limits the program to a virtual address space of 4 GiB it also decreases the memory

footprint of the program and in some cases can allow it to run faster.[91][92][93]

64-bit Linux allows up to 128 TiB of virtual address space for individual processes, and can address
approximately 64 TiB of physical memory, subject to processor and system limitations,[94] or up to

15 of 32 31/07/2024, 15:42
x86-64 - Wikipedia https://en.wikipedia.org/wiki/X86-64

128 PiB (virtual) and 4 PiB (physical) with 5-level paging enabled.[95]

macOS
Mac OS X 10.4.7 and higher versions of Mac OS X 10.4 run 64-bit command-line tools using the
POSIX and math libraries on 64-bit Intel-based machines, just as all versions of Mac OS X 10.4
and 10.5 run them on 64-bit PowerPC machines. No other libraries or frameworks work with 64-
bit applications in Mac OS X 10.4.[96] The kernel, and all kernel extensions, are 32-bit only.

Mac OS X 10.5 supports 64-bit GUI applications using Cocoa, Quartz, OpenGL, and X11 on 64-bit
Intel-based machines, as well as on 64-bit PowerPC machines.[97] All non-GUI libraries and
frameworks also support 64-bit applications on those platforms. The kernel, and all kernel
extensions, are 32-bit only.

Mac OS X 10.6 is the first version of macOS that supports a 64-bit kernel. However, not all 64-bit
computers can run the 64-bit kernel, and not all 64-bit computers that can run the 64-bit kernel
will do so by default.[98] The 64-bit kernel, like the 32-bit kernel, supports 32-bit applications; both
kernels also support 64-bit applications. 32-bit applications have a virtual address space limit of
4 GiB under either kernel.[99][100] The 64-bit kernel does not support 32-bit kernel extensions, and
the 32-bit kernel does not support 64-bit kernel extensions.

OS X 10.8 includes only the 64-bit kernel, but continues to support 32-bit applications; it does not
support 32-bit kernel extensions, however.

macOS 10.15 includes only the 64-bit kernel and no longer supports 32-bit applications. This
removal of support has presented a problem for WineHQ (and the commercial version CrossOver),
as it needs to still be able to run 32-bit Windows applications. The solution, termed wine32on64,
was to add thunks that bring the CPU in and out of 32-bit compatibility mode in the nominally 64-
bit application.[101][102]

macOS uses the universal binary format to package 32- and 64-bit versions of application and
library code into a single file; the most appropriate version is automatically selected at load time.
In Mac OS X 10.6, the universal binary format is also used for the kernel and for those kernel
extensions that support both 32-bit and 64-bit kernels.

Solaris
Solaris 10 and later releases support the x86-64 architecture.

For Solaris 10, just as with the SPARC architecture, there is only one operating system image,
which contains a 32-bit kernel and a 64-bit kernel; this is labeled as the "x64/x86" DVD-ROM
image. The default behavior is to boot a 64-bit kernel, allowing both 64-bit and existing or new 32-
bit executables to be run. A 32-bit kernel can also be manually selected, in which case only 32-bit
executables will run. The isainfo command can be used to determine if a system is running a 64-
bit kernel.

16 of 32 31/07/2024, 15:42
x86-64 - Wikipedia https://en.wikipedia.org/wiki/X86-64

For Solaris 11, only the 64-bit kernel is provided. However, the 64-bit kernel supports both 32- and
64-bit executables, libraries, and system calls.

Windows
x64 editions of Microsoft Windows client and server—Windows XP Professional x64 Edition and
Windows Server 2003 x64 Edition—were released in March 2005.[103] Internally they are actually
the same build (5.2.3790.1830 SP1),[104][105] as they share the same source base and operating
system binaries, so even system updates are released in unified packages, much in the manner as
Windows 2000 Professional and Server editions for x86. Windows Vista, which also has many
different editions, was released in January 2007. Windows 7 was released in July 2009. Windows
Server 2008 R2 was sold in only x64 and Itanium editions; later versions of Windows Server only
offer an x64 edition.

Versions of Windows for x64 prior to Windows 8.1 and Windows Server 2012 R2 offer the
following:

▪ 8 TiB of virtual address space per process, accessible from both user mode and kernel mode,
referred to as the user mode address space. An x64 program can use all of this, subject to
backing store limits on the system, and provided it is linked with the "large address aware"
option, which is present by default.[106] This is a 4096-fold increase over the default 2 GiB user-
mode virtual address space offered by 32-bit Windows.[107][108]
▪ 8 TiB of kernel mode virtual address space for the operating system.[107] As with the user
mode address space, this is a 4096-fold increase over 32-bit Windows versions. The increased
space primarily benefits the file system cache and kernel mode "heaps" (non-paged pool and
paged pool). Windows only uses a total of 16 TiB out of the 256 TiB implemented by the
processors because early AMD64 processors lacked a CMPXCHG16B instruction.[109]
Under Windows 8.1 and Windows Server 2012 R2, both user mode and kernel mode virtual
address spaces have been extended to 128 TiB.[23] These versions of Windows will not install on
processors that lack the CMPXCHG16B instruction.

The following additional characteristics apply to all x64 versions of Windows:

▪ Ability to run existing 32-bit applications (.exe programs) and dynamic link libraries (.dlls)
using WoW64 if WoW64 is supported on that version. Furthermore, a 32-bit program, if it was
linked with the "large address aware" option,[106] can use up to 4 GiB of virtual address space
in 64-bit Windows, instead of the default 2 GiB (optional 3 GiB with /3GiB boot option and
"large address aware" link option) offered by 32-bit Windows.[110] Unlike the use of the /3GiB
boot option on x86, this does not reduce the kernel mode virtual address space available to the
operating system. 32-bit applications can, therefore, benefit from running on x64 Windows
even if they are not recompiled for x86-64.
▪ Both 32- and 64-bit applications, if not linked with "large address aware", are limited to 2 GiB of
virtual address space.
▪ Ability to use up to 128 GiB (Windows XP/Vista), 192 GiB (Windows 7), 512 GiB (Windows 8),
1 TiB (Windows Server 2003), 2 TiB (Windows Server 2008/Windows 10), 4 TiB (Windows
Server 2012), or 24 TiB (Windows Server 2016/2019) of physical random access memory
(RAM).[111]

17 of 32 31/07/2024, 15:42
x86-64 - Wikipedia https://en.wikipedia.org/wiki/X86-64

▪ LLP64 data model: in C/C++, "int" and "long" types are 32 bits wide, "long long" is 64 bits, while
pointers and types derived from pointers are 64 bits wide.
▪ Kernel mode device drivers must be 64-bit versions; there is no way to run 32-bit kernel mode
executables within the 64-bit operating system. User mode device drivers can be either 32-bit
or 64-bit.
▪ 16-bit Windows (Win16) and DOS applications will not run on x86-64 versions of Windows due
to the removal of the virtual DOS machine subsystem (NTVDM) which relied upon the ability to
use virtual 8086 mode. Virtual 8086 mode cannot be entered while running in long mode.
▪ Full implementation of the NX (No Execute) page protection feature. This is also implemented
on recent 32-bit versions of Windows when they are started in PAE mode.
▪ Instead of FS segment descriptor on x86 versions of the Windows NT family, GS segment
descriptor is used to point to two operating system defined structures: Thread Information
Block (NT_TIB) in user mode and Processor Control Region (KPCR) in kernel mode. Thus, for
example, in user mode GS:0 is the address of the first member of the Thread Information
Block. Maintaining this convention made the x86-64 port easier, but required AMD to retain the
function of the FS and GS segments in long mode – even though segmented addressing per
se is not really used by any modern operating system.[107]
▪ Early reports claimed that the operating system scheduler would not save and restore the x87
FPU machine state across thread context switches. Observed behavior shows that this is not
the case: the x87 state is saved and restored, except for kernel mode-only threads (a limitation
that exists in the 32-bit version as well). The most recent documentation available from
Microsoft states that the x87/MMX/3DNow! instructions may be used in long mode, but that
they are deprecated and may cause compatibility problems in the future.[110] (3DNow! is no
longer available on AMD processors, with the exception of the PREFETCH and PREFETCHW
instructions,[112] which are also supported on Intel processors as of Broadwell.)
▪ Some components like Jet Database Engine and Data Access Objects will not be ported to 64-
bit architectures such as x86-64 and IA-64.[113][114][115]
▪ Microsoft Visual Studio can compile native applications to target either the x86-64 architecture,
which can run only on 64-bit Microsoft Windows, or the IA-32 architecture, which can run as a
32-bit application on 32-bit Microsoft Windows or 64-bit Microsoft Windows in WoW64
emulation mode. Managed applications can be compiled either in IA-32, x86-64 or AnyCPU
modes. Software created in the first two modes behave like their IA-32 or x86-64 native code
counterparts respectively; When using the AnyCPU mode, however, applications in 32-bit
versions of Microsoft Windows run as 32-bit applications, while they run as a 64-bit application
in 64-bit editions of Microsoft Windows.

Video game consoles

Both the PlayStation 4 and Xbox One, and all variants of those consoles, incorporate AMD x86-64
processors, based on the Jaguar microarchitecture.[116][117] Firmware and games are written in
x86-64 code; no legacy x86 code is involved.

The current generation, the PlayStation 5 and the Xbox Series X and Series S respectively, also
incorporate AMD x86-64 processors, based on the Zen 2 microarchitecture.[118][119]

Although considered a PC, the Steam Deck uses a custom AMD x86-64 accelerated processing unit
(APU), based on the Zen 2 microarchitecture.[120]

18 of 32 31/07/2024, 15:42
x86-64 - Wikipedia https://en.wikipedia.org/wiki/X86-64

Industry naming conventions

Since AMD64 and Intel 64 are substantially similar, many software and hardware products use one
vendor-neutral term to indicate their compatibility with both implementations. AMD's original
designation for this processor architecture, "x86-64", is still used for this purpose,[2] as is the
variant "x86_64".[3][4] Other companies, such as Microsoft[6] and Sun Microsystems/Oracle
Corporation,[5] use the contraction "x64" in marketing material.

The term IA-64 refers to the Itanium processor, and should not be confused with x86-64, as it is a
completely different instruction set.

Many operating systems and products, especially those that introduced x86-64 support prior to
Intel's entry into the market, use the term "AMD64" or "amd64" to refer to both AMD64 and Intel
64.

▪ amd64
▪ Most BSD systems such as FreeBSD, MidnightBSD, NetBSD and OpenBSD refer to both
AMD64 and Intel 64 under the architecture name "amd64".
▪ Some Linux distributions such as Debian, Ubuntu, Gentoo Linux refer to both AMD64 and
Intel 64 under the architecture name "amd64".
▪ Microsoft Windows's x64 versions use the AMD64 moniker internally to designate various
components which use or are compatible with this architecture. For example, the
environment variable PROCESSOR_ARCHITECTURE is assigned the value "AMD64" as
opposed to "x86" in 32-bit versions, and the system directory on a Windows x64 Edition
installation CD-ROM is named "AMD64", in contrast to "i386" in 32-bit versions.[121]
▪ Sun's Solaris's isalist command identifies both AMD64- and Intel 64-based systems as
"amd64".
▪ Java Development Kit (JDK): the name "amd64" is used in directory names containing
x86-64 files.
▪ x86_64
▪ The Linux kernel[122] and the GNU Compiler Collection refers to 64-bit architecture as
"x86_64".
▪ Some Linux distributions, such as Fedora, openSUSE, Arch Linux, Gentoo Linux refer to
this 64-bit architecture as "x86_64".
▪ Apple macOS refers to 64-bit architecture as "x86-64" or "x86_64", as seen in the Terminal
command arch[3] and in their developer documentation.[2][4]
▪ Breaking with most other BSD systems, DragonFly BSD refers to 64-bit architecture as
"x86_64".
▪ Haiku refers to 64-bit architecture as "x86_64".

Licensing
x86-64/AMD64 was solely developed by AMD. AMD holds patents on techniques used in AMD64;

19 of 32 31/07/2024, 15:42
x86-64 - Wikipedia https://en.wikipedia.org/wiki/X86-64

[123][124][125]
those patents must be licensed from AMD in order to implement AMD64. Intel
entered into a cross-licensing agreement with AMD, licensing to AMD their patents on existing x86
techniques, and licensing from AMD their patents on techniques used in x86-64.[126] In 2009,
AMD and Intel settled several lawsuits and cross-licensing disagreements, extending their cross-
licensing agreements.[127][128][129]

See also
▪ AMD Generic Encapsulated Software Architecture (AGESA)
▪ Transient execution CPU vulnerability

Notes
1. Various names are used for the instruction set. Prior to the launch, x86-64 and x86_64 were
used, while upon the release AMD named it AMD64.[1] Intel initially used the names IA-32e
and EM64T before finally settling on "Intel 64" for its implementation. Some in the industry,
including Apple,[2][3][4] use x86-64 and x86_64, while others, notably Sun Microsystems[5] (now
Oracle Corporation) and Microsoft,[6] use x64. The BSD family of OSs and several Linux
distributions[7][8] use AMD64, as does Microsoft Windows internally.[9][10]
2. In practice, 64-bit operating systems generally do not support 16-bit applications, although
modern versions of Microsoft Windows contain a limited workaround that effectively supports
16-bit InstallShield and Microsoft ACME installers by silently substituting them with 32-bit code.
[12]

a. The Register reported that the stepping G1 (0F49h) of Pentium 4 will sample on October 17
and ship in volume on November 14.[66] However, Intel's document says that samples are
available on September 9, whereas October 17 is the "date of first availability of post-
conversion material", which Intel defines as "the projected date that a customer may expect to
receive the post-conversion materials. ... customers should be prepared to receive the post-
converted materials on this date".[67]

References
1. "Debian AMD64 FAQ" (http://wiki.debian.org/DebianAMD64Faq). Debian Wiki. Archived (http
s://web.archive.org/web/20190926163758/https://wiki.debian.org/DebianAMD64Faq) from the
original on September 26, 2019. Retrieved May 3, 2012.
2. "x86-64 Code Model" (https://developer.apple.com/library/mac/#documentation/developertools/
Conceptual/MachOTopics/1-Articles/x86_64_code.html). Apple. Archived (https://web.archive.o
rg/web/20120602013413/https://developer.apple.com/library/mac/#documentation/developerto
ols/Conceptual/MachOTopics/1-Articles/x86_64_code.html) from the original on June 2, 2012.
Retrieved November 23, 2012.
3. arch(1) (https://keith.github.io/xcode-man-pages/arch.1.html) – Darwin and
macOS General Commands Manual

20 of 32 31/07/2024, 15:42
x86-64 - Wikipedia https://en.wikipedia.org/wiki/X86-64

4. Kevin Van Vechten (August 9, 2006). "re: Intel XNU bug report" (https://web.archive.org/web/20
200201090447/https://lists.apple.com/archives/Darwin-dev/2006/Aug/msg00095.html). Darwin-
dev mailing list. Apple Computer. Archived from the original (http://lists.apple.com/archives/Dar
win-dev/2006/Aug/msg00095.html) on February 1, 2020. Retrieved October 5, 2006. "The
kernel and developer tools have standardized on "x86_64" for the name of the Mach-O
architecture"
5. "Solaris 10 on AMD Opteron" (http://www.oracle.com/technetwork/server-storage/solaris/overvi
ew/solaris10amdopteron-jsp-140575.html). Oracle. Archived (https://web.archive.org/web/2017
0725114435/http://www.oracle.com/technetwork/server-storage/solaris/overview/solaris10amdo
pteron-jsp-140575.html) from the original on July 25, 2017. Retrieved December 9, 2010.
6. "Microsoft 64-Bit Computing" (https://web.archive.org/web/20101212040212/http://www.micros
oft.com/windowsserver2008/en/us/64bit-computing.aspx). Microsoft. Archived from the original
(http://www.microsoft.com/windowsserver2008/en/us/64bit-computing.aspx) on December 12,
2010. Retrieved December 9, 2010.
7. "AMD64 Port" (http://www.debian.org/ports/amd64/). Debian. Archived (https://web.archive.org/
web/20190926060654/https://www.debian.org/ports/amd64/) from the original on September
26, 2019. Retrieved November 23, 2012.
8. "Gentoo/AMD64 Project" (http://www.gentoo.org/proj/en/base/amd64/). Gentoo Project.
Archived (https://web.archive.org/web/20130603152916/http://www.gentoo.org/proj/en/base/am
d64/) from the original on June 3, 2013. Retrieved May 27, 2013.
9. "WOW64 Implementation Details" (https://msdn.microsoft.com/en-us/library/windows/desktop/a
a384274(v=vs.85).aspx). Archived (https://web.archive.org/web/20180413001932/https://msd
n.microsoft.com/en-us/library/windows/desktop/aa384274(v=vs.85).aspx) from the original on
April 13, 2018. Retrieved January 24, 2016.
10. "ProcessorArchitecture Class" (https://msdn.microsoft.com/en-us/library/microsoft.build.utilitie
s.processorarchitecture.aspx). Archived (https://web.archive.org/web/20170603232543/https://
msdn.microsoft.com/en-us/library/microsoft.build.utilities.processorarchitecture.aspx) from the
original on June 3, 2017. Retrieved January 24, 2016.
11. AMD Corporation (December 2016). "Volume 2: System Programming" (http://support.amd.co
m/TechDocs/24593.pdf) (PDF). AMD64 Architecture Programmer's Manual. AMD Corporation.
Archived (https://web.archive.org/web/20180713145424/https://support.amd.com/TechDocs/24
593.pdf) (PDF) from the original on July 13, 2018. Retrieved March 25, 2017.
12. Raymond Chen (October 31, 2013). "If there is no 16-bit emulation layer in 64-bit Windows,
how come certain 16-bit installers are allowed to run?" (https://devblogs.microsoft.com/oldnewt
hing/20131031-00/?p=2783). Archived (https://web.archive.org/web/20210714084610/https://d
evblogs.microsoft.com/oldnewthing/20131031-00/?p=2783) from the original on July 14, 2021.
Retrieved July 14, 2021.
13. "IBM WebSphere Application Server 64-bit Performance Demystified" (ftp://ftp.software.ibm.co
m/software/webserver/appserv/was/64bitPerf.pdf) (PDF). IBM Corporation. September 6, 2007.
p. 14. Archived (https://web.archive.org/web/20220125121650/ftp://ftp.software.ibm.com/softwa
re/webserver/appserv/was/64bitPerf.pdf) (PDF) from the original on January 25, 2022.
Retrieved April 9, 2010. "Figures 5, 6 and 7 also show the 32-bit version of WAS runs
applications at full native hardware performance on the POWER and x86-64 platforms. Unlike
some 64-bit processor architectures, the POWER and x86-64 hardware does not emulate 32-
bit mode. Therefore applications that do not benefit from 64-bit features can run with full
performance on the 32-bit version of WebSphere running on the above mentioned 64-bit
platforms."

21 of 32 31/07/2024, 15:42
x86-64 - Wikipedia https://en.wikipedia.org/wiki/X86-64

14. "AMD Discloses New Technologies At Microporcessor Forum" (https://web.archive.org/web/201

20308030806/http://www.amd.com/us/press-releases/Pages/Press_Release_751.aspx) (Press
release). AMD. October 5, 1999. Archived from the original (https://www.amd.com/us/press-rel
eases/Pages/Press_Release_751.aspx) on March 8, 2012. Retrieved November 9, 2010.
15. "AMD Releases x86-64 Architectural Specification; Enables Market Driven Migration to 64-Bit
Computing" (https://web.archive.org/web/20120308025559/http://www.amd.com/us/press-relea
ses/Pages/Press_Release_715.aspx) (Press release). AMD. August 10, 2000. Archived from
the original (https://www.amd.com/us/press-releases/Pages/Press_Release_715.aspx) on
March 8, 2012. Retrieved November 9, 2010.
16. AMD64 Architecture Programmer's Manual (https://www.amd.com/content/dam/amd/en/docum
ents/processor-tech-docs/programmer-references/24592.pdf) (PDF). p. 1.
17. Mauerer, W. (2010). Professional Linux kernel architecture. John Wiley & Sons.
18. "Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A: System
Programming Guide, Part 1" (http://www.intel.com/Assets/PDF/manual/253668.pdf) (PDF).
pp. 4–7. Archived (https://web.archive.org/web/20110516145322/http://www.intel.com/Assets/P
DF/manual/253668.pdf) (PDF) from the original on May 16, 2011. Retrieved July 10, 2019.
19. "BIOS and Kernel Developer's Guide (BKDG) For AMD Family 10h Processors" (http://develop
er.amd.com/wordpress/media/2012/10/31116.pdf) (PDF). p. 24. Archived (https://web.archive.o
rg/web/20160418185513/http://developer.amd.com/wordpress/media/2012/10/31116.pdf)
(PDF) from the original on April 18, 2016. Retrieved February 27, 2016. "Physical address
space increased to 48 bits."
20. "Myth and facts about 64-bit Linux" (https://web.archive.org/web/20101010233951/http://www.a
md64.org/fileadmin/user_upload/pub/64bit_Linux-Myths_and_Facts.pdf) (PDF). March 2, 2008.
p. 7. Archived from the original (http://www.amd64.org/fileadmin/user_upload/pub/64bit_Linux-
Myths_and_Facts.pdf) (PDF) on October 10, 2010. Retrieved May 30, 2010. "Physical address
space increased to 48 bits"
21. Shanley, Tom (1998). Pentium Pro and Pentium II System Architecture (https://archive.org/deta
ils/pentiumpropentiu00shan/page/445). PC System Architecture Series (Second ed.). Addison-
Wesley. p. 445 (https://archive.org/details/pentiumpropentiu00shan/page/445).
ISBN 0-201-30973-4.
22. Microsoft Corporation. "What is PAE, NX, and SSE2 and why does my PC need to support
them to run Windows 8 ?" (http://windows.microsoft.com/en-GB/windows-8/what-is-pae-nx-sse
2). Archived (https://web.archive.org/web/20130411004411/http://windows.microsoft.com/en-G
B/windows-8/what-is-pae-nx-sse2) from the original on April 11, 2013. Retrieved March 19,
2013.
23. "Memory Limits for Windows Releases" (http://msdn.microsoft.com/en-us/library/windows/deskt
op/aa366778(v=vs.85).aspx#memory_limits). MSDN. Microsoft. November 16, 2013. Archived
(https://web.archive.org/web/20140106195757/http://msdn.microsoft.com/en-us/library/window
s/desktop/aa366778(v=vs.85).aspx#memory_limits) from the original on January 6, 2014.
Retrieved January 20, 2014.
24. "5-Level Paging and 5-Level EPT" (https://software.intel.com/sites/default/files/managed/2b/8
0/5-level_paging_white_paper.pdf) (PDF). Intel. May 2017. Archived (https://web.archive.org/w
eb/20181205041235/https://software.intel.com/sites/default/files/managed/2b/80/5-level_pagin
g_white_paper.pdf) (PDF) from the original on December 5, 2018. Retrieved June 17, 2017.
25. US patent 9858198 (https://worldwide.espacenet.com/textdoc?DB=EPODOC&IDX=US985819
8), Larry Seiler, "64KB page system that supports 4KB page operation", published 2016-12-29,
issued 2018-01-02, assigned to Intel Corp.

22 of 32 31/07/2024, 15:42
x86-64 - Wikipedia https://en.wikipedia.org/wiki/X86-64

26. "Opteron 6100 Series Motherboards" (http://www.supermicro.com/Aplus/motherboard/Opteron

6100/). Supermicro Corporation. Archived (https://web.archive.org/web/20100603182215/http://
www.supermicro.com/Aplus/motherboard/Opteron6100/) from the original on June 3, 2010.
Retrieved June 22, 2010.
27. "Supermicro XeonSolutions" (http://www.supermicro.com/products/motherboard/Xeon1333/#13
66). Supermicro Corporation. Archived (https://web.archive.org/web/20100527224603/http://ww
w.supermicro.com/products/motherboard/Xeon1333/#1366) from the original on May 27, 2010.
Retrieved June 20, 2010.
28. "Opteron 8000 Series Motherboards" (http://www.supermicro.com/Aplus/motherboard/Opteron
8000/). Supermicro Corporation. Archived (https://web.archive.org/web/20100527212322/http://
www.supermicro.com/Aplus/motherboard/Opteron8000/) from the original on May 27, 2010.
Retrieved June 20, 2010.
29. "Tyan Product Matrix" (http://www.supermicro.com/products/motherboard/Core/index.cfm#136
6). MiTEC International Corporation. Archived (https://web.archive.org/web/20100606190740/h
ttp://www.supermicro.com/products/motherboard/Core/index.cfm#1366) from the original on
June 6, 2010. Retrieved June 21, 2010.
30. "From the AMI Archives: AMIBIOS 8 and the Transition to EFI" (https://web.archive.org/web/20
211025233343/https://www.ami.com/tech-blog/from-the-ami-archives-amibios-8-and-the-transiti
on-to-efi/). American Megatrends. September 8, 2017. Archived from the original (https://www.a
mi.com/tech-blog/from-the-ami-archives-amibios-8-and-the-transition-to-efi/) on October 25,
2021. Retrieved October 25, 2021.
31. "Intel is Continuing the Yamhill Project?" (https://www.neowin.net/news/intel-is-continuing-the-y
amhill-project/). Neowin. Archived (https://web.archive.org/web/20220605151028/https://www.n
eowin.net/news/intel-is-continuing-the-yamhill-project/) from the original on June 5, 2022.
Retrieved June 5, 2022.
32. "Craig Barrett confirms 64 bit address extensions for Xeon. And Prescott" (https://archive.toda
y/20130112014446/http://www.theinquirer.net/inquirer/news/1042795/craig-barrett-confirms-bit-
address-extensions-xeon-and-prescott). The Inquirer. February 17, 2004. Archived from the
original (https://www.theinquirer.net/inquirer/news/1042795/craig-barrett-confirms-bit-address-e
xtensions-xeon-and-prescott) on January 12, 2013. Retrieved August 20, 2017.
33. " "A Roundup of 64-Bit Computing", from internetnews.com" (https://web.archive.org/web/2012
0925003349/http://www.internetnews.com/ent-news/article.php/3518781). Archived from the
original (http://www.internetnews.com/ent-news/article.php/3518781) on September 25, 2012.
Retrieved September 18, 2006.
34. Lapedus, Mark (February 6, 2004). "Intel to demo 'CT' 64-bit processor line at IDF" (https://ww
w.edn.com/intel-to-demo-ct-64-bit-processor-line-at-idf/). EDN. AspenCore Media. Archived (htt
ps://web.archive.org/web/20210525031727/https://www.edn.com/intel-to-demo-ct-64-bit-proces
sor-line-at-idf/) from the original on May 25, 2021. Retrieved May 25, 2021.
35. "Intel 64 Architecture" (http://www.intel.com/technology/intel64/index.htm). Intel. Archived (http
s://web.archive.org/web/20110629214538/http://www.intel.com/technology/intel64/index.htm)
from the original on June 29, 2011. Retrieved June 29, 2007.
36. "Intel Publishes "X86-S" Specification For 64-bit Only Architecture" (https://www.phoronix.com/
news/Intel-X86-S-64-bit-Only). www.phoronix.com.
37. "Envisioning a Simplified Intel Architecture for the Future" (https://www.intel.com/content/www/
us/en/developer/articles/technical/envisioning-future-simplified-architecture.html). Intel.

23 of 32 31/07/2024, 15:42
x86-64 - Wikipedia https://en.wikipedia.org/wiki/X86-64

38. "VIA to launch new processor architecture in 1Q08" (http://www.digitimes.com/news/a2007072

5PD206.html) (subscription required). DigiTimes. July 25, 2007. Archived (https://web.archive.o
rg/web/20081203201340/http://www.digitimes.com/news/a20070725PD206.html) from the
original on December 3, 2008. Retrieved July 25, 2007.
39. Stokes, Jon (January 23, 2008). "Isaiah revealed: VIA's new low-power architecture" (https://ar
stechnica.com/articles/paedia/cpu/via-cpu-isaiah.ars). Ars Technica. Archived (https://web.archi
ve.org/web/20080127095807/http://arstechnica.com/articles/paedia/cpu/via-cpu-isaiah.ars)
from the original on January 27, 2008. Retrieved January 24, 2008.
40. "VIA Launches VIA Nano Processor Family" (http://www.viatech.com/en/2008/05/via-launches-
via-nano-processor-family/) (Press release). VIA. May 29, 2008. Archived (https://web.archiv
e.org/web/20190203072901/https://www.viatech.com/en/2008/05/via-launches-via-nano-proces
sor-family/) from the original on February 3, 2019. Retrieved May 25, 2017.
41. "VIA Isaiah Architecture Introduction" (https://web.archive.org/web/20080907181213/http://ww
w.via.com.tw/en/downloads/presentations/processors/pb_via-isaiah_080124.pdf) (PDF). VIA.
January 23, 2008. Archived from the original (http://www.via.com.tw/en/downloads/presentation
s/processors/pb_via-isaiah_080124.pdf) (PDF) on September 7, 2008. Retrieved July 31,
2013.
42. Weimer, Florian (July 10, 2020). "New x86-64 micro-architecture levels" (https://lists.llvm.org/pi
permail/llvm-dev/2020-July/143289.html). llvm-dev (Mailing list). Archived (https://web.archive.o
rg/web/20210414100705/https://lists.llvm.org/pipermail/llvm-dev/2020-July/143289.html) from
the original on April 14, 2021. Retrieved March 11, 2021.
43. Weimer, Florian (January 5, 2021). "Building Red Hat Enterprise Linux 9 for the x86-64-v2
microarchitecture level" (https://developers.redhat.com/blog/2021/01/05/building-red-hat-enterp
rise-linux-9-for-the-x86-64-v2-microarchitecture-level). Red Hat developer blog. Archived (http
s://web.archive.org/web/20220220155150/https://developers.redhat.com/blog/2021/01/05/buildi
ng-red-hat-enterprise-linux-9-for-the-x86-64-v2-microarchitecture-level) from the original on
February 20, 2022. Retrieved March 22, 2022.
44. "System V Application Binary Interface Low Level System Information" (https://gitlab.com/x86-p
sABIs/x86-64-ABI/-/blob/master/x86-64-ABI/low-level-sys-info.tex). x86-64 psABI repo. January
29, 2021. Archived (https://web.archive.org/web/20210202215134/https://gitlab.com/x86-psABI
s/x86-64-ABI/-/blob/master/x86-64-ABI/low-level-sys-info.tex) from the original on February 2,
2021. Retrieved March 11, 2021 – via GitLab.
45. "QEMU version 7.2.0 released - QEMU" (https://www.qemu.org/2022/12/14/qemu-7-2-0/).
www.qemu.org. Archived (https://web.archive.org/web/20221221220214/https://www.qemu.or
g/2022/12/14/qemu-7-2-0/) from the original on December 21, 2022. Retrieved January 9,
2023.
46. "ChangeLog/7.2 - QEMU" (https://wiki.qemu.org/ChangeLog/7.2#TCG). wiki.qemu.org.
Archived (https://web.archive.org/web/20230109194106/https://wiki.qemu.org/ChangeLog/7.2#
TCG) from the original on January 9, 2023. Retrieved January 9, 2023.
47. Wasson, Scott (March 23, 2005). "64-bit computing in theory and practice" (http://techreport.co
m/articles.x/8131/1). The Tech Report. Archived (https://web.archive.org/web/2011031200430
4/http://techreport.com/articles.x/8131/1) from the original on March 12, 2011. Retrieved
March 22, 2011.
48. "Discussion on Stack Overflow" (https://stackoverflow.com/questions/66416287/in-x86-64-doe
s-a-32-bit-cmov-clear-the-top-bits-if-the-condition-is-false/66416462#comment117465925_664
16462). March 2021. Archived (https://web.archive.org/web/20230111050417/https://stackoverf
low.com/questions/66416287/in-x86-64-does-a-32-bit-cmov-clear-the-top-bits-if-the-condition-i
s-false/66416462#comment117465925_66416462) from the original on January 11, 2023.
Retrieved March 2, 2021.

24 of 32 31/07/2024, 15:42
x86-64 - Wikipedia https://en.wikipedia.org/wiki/X86-64

49. "Intel 64 and IA-32 Architectures Software Developer's Manual Volume 2 (2A, 2B & 2C):
Instruction Set Reference, A–Z" (http://www.intel.com/content/dam/www/public/us/en/document
s/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-32538
3.pdf) (PDF). Intel. September 2013. pp. 4–397. Archived (https://web.archive.org/web/201310
20144800/http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-ar
chitectures-software-developer-instruction-set-reference-manual-325383.pdf) (PDF) from the
original on October 20, 2013. Retrieved January 21, 2014.
50. "Intel 64 and IA-32 Architectures Software Developer's Manual Volume 2 (2A, 2B & 2C):
Instruction Set Reference, A-Z" (http://www.intel.com/content/dam/www/public/us/en/document
s/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-32538
3.pdf) (PDF). Intel. September 2013. pp. 4–400. Archived (https://web.archive.org/web/201310
20144800/http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-ar
chitectures-software-developer-instruction-set-reference-manual-325383.pdf) (PDF) from the
original on October 20, 2013. Retrieved January 21, 2014.
51. "How retiring segmentation in AMD64 long mode broke VMware" (http://www.pagetable.com/?p
=25). Pagetable.com. November 9, 2006. Archived (https://web.archive.org/web/20110718104
331/http://www.pagetable.com/?p=25) from the original on July 18, 2011. Retrieved May 2,
2010.
52. "VMware and CPU Virtualization Technology" (http://download3.vmware.com/vmworld/2005/pa
c346.pdf) (PDF). VMware. Archived (https://web.archive.org/web/20110717231306/http://downl
oad3.vmware.com/vmworld/2005/pac346.pdf) (PDF) from the original on July 17, 2011.
Retrieved September 8, 2010.
53. "Linux-Kernel Archive: [PATCH 2/5] KVM: svm: Disallow EFER.LMSLE on hardware that
doesn't support it" (https://lkml.indiana.edu/hypermail/linux/kernel/2209.2/00025.html).
lkml.indiana.edu. Retrieved November 3, 2023.
54. "AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System
Instructions" (https://support.amd.com/TechDocs/24594.pdf) (PDF). AMD. May 2018. p. 419.
Archived (https://web.archive.org/web/20180820123419/https://support.amd.com/TechDocs/24
594.pdf) (PDF) from the original on August 20, 2018. Retrieved August 2, 2018.
55. "Intel 64 and IA-32 Architectures Software Developer's Manual Volume 2 (2A, 2B & 2C):
Instruction Set Reference, A-Z" (http://www.intel.com/content/dam/www/public/us/en/document
s/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-32538
3.pdf) (PDF). Intel. September 2014. pp. 4–412. Archived (https://web.archive.org/web/201501
13223656/http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-ar
chitectures-software-developer-instruction-set-reference-manual-325383.pdf) (PDF) from the
original on January 13, 2015. Retrieved December 28, 2014.
56. Hadi Brais, The Significance of the x86 LFENCE Instruction (https://hadibrais.wordpress.com/2
018/05/14/the-significance-of-the-x86-lfence-instruction/), 14 May 2018. Archived (https://web.a
rchive.org/web/20230610045406/https://hadibrais.wordpress.com/2018/05/14/the-significance-
of-the-x86-lfence-instruction/) on 10 Jun 2023.
57. "Live Migration with AMD-V™ Extended Migration Technology" (http://developer.amd.com/word
press/media/2012/10/43781-3.00-PUB_Live-Virtual-Machine-Migration-on-AMD-processors.pd
f) (PDF). developer.amd.com. Archived (https://web.archive.org/web/20221206025751/http://de
veloper.amd.com/wordpress/media/2012/10/43781-3.00-PUB_Live-Virtual-Machine-Migration-o
n-AMD-processors.pdf) (PDF) from the original on December 6, 2022. Retrieved June 30,
2022.

25 of 32 31/07/2024, 15:42
x86-64 - Wikipedia https://en.wikipedia.org/wiki/X86-64

58. Maged M. Michael. "Practical Lock-Free and Wait-Free LL/SC/VL Implementations Using 64-
Bit CAS" (http://www.research.ibm.com/people/m/michael/disc-2004.pdf) (PDF). IBM. Archived
(https://web.archive.org/web/20130502033436/http://www.research.ibm.com/people/m/michael/
disc-2004.pdf) (PDF) from the original on May 2, 2013. Retrieved January 21, 2014.
59. darwou (August 20, 2004). "Why is the virtual address space 4GB anyway?" (https://blogs.msd
n.microsoft.com/oldnewthing/20040817-00/?p=38153#comment-204583). The Old New Thing.
Microsoft. Archived (https://web.archive.org/web/20170326140218/https://blogs.msdn.microsof
t.com/oldnewthing/20040817-00/?p=38153#comment-204583) from the original on March 26,
2017. Retrieved March 25, 2017.
60. "System Requirements—Windows 8.1" (http://windows.microsoft.com/en-us/windows-8/syste
m-requirements). Archived (https://web.archive.org/web/20140428223434/http://windows.micro
soft.com/en-us/windows-8/system-requirements) from the original on April 28, 2014. Retrieved
April 27, 2014. "To install a 64-bit OS on a 64-bit PC, your processor needs to support
CMPXCHG16b, PrefetchW, and LAHF/SAHF."
61. Petkov, Borislav (August 10, 2009). "Re: [PATCH v2] x86: clear incorrectly forced
X86_FEATURE_LAHF_LM flag" (https://lkml.org/lkml/2009/8/10/159). Linux kernel mailing list.
Archived (https://web.archive.org/web/20230111050420/https://lkml.org/lkml/2009/8/10/159)
from the original on January 11, 2023. Retrieved June 30, 2022.
62. "Revision Guide for AMD Athlon 64 and AMD Opteron Processors" (http://support.amd.com/us/
Processor_TechDocs/25759.pdf) (PDF). AMD. Archived (https://web.archive.org/web/2009082
4002650/http://support.amd.com/us/Processor_TechDocs/25759.pdf) (PDF) from the original
on August 24, 2009. Retrieved July 18, 2009.
63. "Product Change Notification 105224 - 01" (https://web.archive.org/web/20051117160702/htt
p://developer.intel.com/design/pcn/Processors/D0105224.pdf) (PDF). Intel. Archived from the
original (http://developer.intel.com/design/pcn/Processors/D0105224.pdf) (PDF) on November
17, 2005.
64. "Intel® Pentium® D Processor 800 Sequence and Intel® Pentium® Processor Extreme Edition
840 Specification Update" (https://www.intel.com/Assets/PDF/specupdate/306832.pdf) (PDF).
Archived (https://web.archive.org/web/20210518130540/https://www.intel.com/assets/pdf/spec
update/306832.pdf) (PDF) from the original on May 18, 2021. Retrieved June 30, 2022.
65. "Intel Xeon 2.8 GHz - NE80551KG0724MM / BX80551KG2800HA" (https://www.cpu-world.co
m/CPUs/Xeon/Intel-Xeon%202.8%20GHz%20-%20NE80551KG0724MM%20(BX80551KG280
0HA).html). CPU-World. Archived (https://web.archive.org/web/20200628213257/http://www.cp
u-world.com/CPUs/Xeon/Intel-Xeon%202.8%20GHz%20-%20NE80551KG0724MM%20(BX80
551KG2800HA).html) from the original on June 28, 2020. Retrieved June 30, 2022.
66. Smith, Tony (August 23, 2005). "Intel tweaks EM64T for full AMD64 compatibility" (https://ww
w.theregister.com/2005/08/23/intel_fixes_em64t/). The Register. Archived (https://web.archiv
e.org/web/20220630200453/https://www.theregister.com/2005/08/23/intel_fixes_em64t/) from
the original on June 30, 2022. Retrieved June 30, 2022.
67. "Product Change Notification 105271 – 00" (https://web.archive.org/web/20051117162258/htt
p://developer.intel.com/design/pcn/Processors/D0105271.pdf) (PDF). Intel. Archived from the
original (http://developer.intel.com/design/pcn/Processors/D0105271.pdf) (PDF) on November
17, 2005.
68. 0F47h debuted in the B0 stepping of Pentium D on October 21,[63][64] but 0F48h which also
supports LAHF/SAHF launched on October 10 in the dual-core Xeon.[65][a]

26 of 32 31/07/2024, 15:42
x86-64 - Wikipedia https://en.wikipedia.org/wiki/X86-64

69. "Product Change Notification 104101 – 00" (https://web.archive.org/web/20040716131656/htt

p://developer.intel.com/design/pcn/Processors/D0104101.pdf) (PDF). Intel. Archived from the
original (http://developer.intel.com/design/pcn/Processors/D0104101.pdf) (PDF) on July 16,
2004.
70. "64-bit Intel® Xeon™ Processor MP with up to 8MB L3 Cache Datasheet" (https://www.intel.co
m/content/dam/www/public/us/en/documents/datasheets/64-bit-xeon-mp-8mb-l3-cache-datash
eet.pdf) (PDF). Archived (https://web.archive.org/web/20221117025116/https://www.intel.com/c
ontent/dam/www/public/us/en/documents/datasheets/64-bit-xeon-mp-8mb-l3-cache-datashee
t.pdf) (PDF) from the original on November 17, 2022. Retrieved November 17, 2022.
71. "Justin Boggs's at Microsoft PDC 2008" (https://zbook.org/read/70903_justin-boggs-isv-engine
ering-developer-relations-manager.html). p. 5. Archived (https://web.archive.org/web/20221117
025143/https://zbook.org/read/70903_justin-boggs-isv-engineering-developer-relations-manag
er.html) from the original on November 17, 2022. Retrieved November 17, 2022.
72. Waldecker, Brian. "AMD Opteron Multicore Processors" (https://www.nersc.gov/assets/Upload
s/AMDMultiCoreCrayNersc020110.pdf) (PDF). p. 13. Archived (https://web.archive.org/web/20
221213095258/https://www.nersc.gov/assets/Uploads/AMDMultiCoreCrayNersc020110.pdf)
(PDF) from the original on December 13, 2022. Retrieved November 17, 2022.
73. "Intel® Xeon® Processor 7500 Series Datasheet, Volume 2" (https://www.intel.com/content/da
m/www/public/us/en/documents/datasheets/xeon-processor-7500-series-vol-2-datasheet.pdf)
(PDF). Archived (https://web.archive.org/web/20221117025118/https://www.intel.com/content/d
am/www/public/us/en/documents/datasheets/xeon-processor-7500-series-vol-2-datasheet.pdf)
(PDF) from the original on November 17, 2022. Retrieved November 17, 2022.
74. "Intel 64 and IA-32 Architectures Software Developer's Manual" (https://web.archive.org/web/2
0190514124207/https://www.intel.com/content/www/us/en/architecture-and-technology/64-ia-3
2-architectures-software-developer-manual-325462.html). September 2014. p. 2-21. Archived
from the original (http://www.intel.com/content/www/us/en/architecture-and-technology/64-ia-3
2-architectures-software-developer-manual-325462.html) on May 14, 2019. "Intel 64
architecture increases the linear address space for software to 64 bits and supports physical
address space up to 46 bits."
75. Logan, Tom (November 14, 2011). "Intel Core i7-3960X Review" (https://overclock3d.net/review
s/cpu_mainboard/intel_core_i7-3960x_review/2). Archived (https://web.archive.org/web/201603
28235235/http://overclock3d.net/reviews/cpu_mainboard/intel_core_i7-3960x_review/2) from
the original on March 28, 2016. Retrieved July 1, 2022.
76. Ye, Huaisheng. "Introduction to 5-Level Paging in 3rd Gen Intel Xeon Scalable Processors with
Linux" (https://lenovopress.lenovo.com/lp1468.pdf) (PDF). Lenovo. Archived (https://web.archiv
e.org/web/20220526220222/https://lenovopress.lenovo.com/lp1468.pdf) (PDF) from the
original on May 26, 2022. Retrieved July 1, 2022.
77. Kennedy, Patrick (November 10, 2022). "AMD EPYC Genoa Gaps Intel Xeon in Stunning
Fashion" (https://www.servethehome.com/amd-epyc-genoa-gaps-intel-xeon-in-stunning-fashio
n/2/). ServeTheHome. p. 2. Archived (https://web.archive.org/web/20221117025115/https://ww
w.servethehome.com/amd-epyc-genoa-gaps-intel-xeon-in-stunning-fashion/2/) from the original
on November 17, 2022. Retrieved November 17, 2022.
78. "Statistics | TOP500 Supercomputer Sites" (http://www.top500.org/statistics). Top500.org.
Archived (https://web.archive.org/web/20140319023302/http://www.top500.org/statistics/) from
the original on March 19, 2014. Retrieved March 22, 2014.
79. "Sublist Generator | TOP500 Supercomputer Sites" (https://www.top500.org/statistics/sublist/).
www.top500.org. Archived (https://web.archive.org/web/20181207200508/https://www.top500.o
rg/statistics/sublist/) from the original on December 7, 2018. Retrieved December 6, 2018.

27 of 32 31/07/2024, 15:42
x86-64 - Wikipedia https://en.wikipedia.org/wiki/X86-64

80. "Intel® Xeon PhiTM Coprocessor Instruction Set Architecture Reference Manual" (https://softw
are.intel.com/sites/default/files/forum/278102/327364001en.pdf) (PDF). Intel. September 7,
2012. section B.2 Intel Xeon Phi coprocessor 64 bit Mode Limitations. Archived (https://web.arc
hive.org/web/20140521050107/https://software.intel.com/sites/default/files/forum/278102/3273
64001en.pdf) (PDF) from the original on May 21, 2014. Retrieved May 21, 2014.
81. "Intel Powers the World's Fastest Supercomputer, Reveals New and Future High Performance
Computing Technologies" (http://newsroom.intel.com/community/intel_newsroom/blog/2013/0
6/17/intel-powers-the-worlds-fastest-supercomputer-reveals-new-and-future-high-performance-
computing-technologies). Archived (https://web.archive.org/web/20130622162239/http://newsr
oom.intel.com/community/intel_newsroom/blog/2013/06/17/intel-powers-the-worlds-fastest-sup
ercomputer-reveals-new-and-future-high-performance-computing-technologies) from the
original on June 22, 2013. Retrieved June 21, 2013.
82. "cvs commit: src/sys/amd64/amd64 genassym.c src/sys/amd64/include asm.h atomic.h
bootinfo.h coredump.h cpufunc.h elf.h endian.h exec.h float.h fpu.h frame.h globaldata.h
ieeefp.h limits.h lock.h md_var.h param.h pcb.h pcb_ext.h pmap.h proc.h profile.h psl.h ..." (htt
p://leaf.dragonflybsd.org/mailarchive/commits/2004-02/msg00011.html) Archived (https://web.a
rchive.org/web/20081204123450/http://leaf.dragonflybsd.org/mailarchive/commits/2004-02/msg
00011.html) from the original on December 4, 2008. Retrieved May 3, 2009.
83. "AMD64 port" (http://leaf.dragonflybsd.org/mailarchive/users/2007-07/msg00016.html).
Archived (https://web.archive.org/web/20100518104312/http://leaf.dragonflybsd.org/mailarchiv
e/users/2007-07/msg00016.html) from the original on May 18, 2010. Retrieved May 3, 2009.
84. "DragonFlyBSD: GoogleSoC2008" (http://www.dragonflybsd.org/docs/developer/GoogleSoC20
08/). Archived (https://web.archive.org/web/20090427115711/http://www.dragonflybsd.org/doc
s/developer/GoogleSoC2008/) from the original on April 27, 2009. Retrieved May 3, 2009.
85. "Summer of Code accepted students" (http://leaf.dragonflybsd.org/mailarchive/users/2009-04/
msg00091.html). Archived (https://web.archive.org/web/20100904021545/http://leaf.dragonflyb
sd.org/mailarchive/users/2009-04/msg00091.html) from the original on September 4, 2010.
Retrieved May 3, 2009.
86. "DragonFlyBSD: release24" (http://www.dragonflybsd.org/release24/). Archived (https://web.arc
hive.org/web/20090923152727/http://www.dragonflybsd.org/release24/) from the original on
September 23, 2009. Retrieved May 3, 2009.
87. "Tutorial for entering protected and long mode from DOS" (https://web.archive.org/web/201702
22181811/http://www.turboirc.com/asm/). Archived from the original (http://www.turboirc.com/as
m) on February 22, 2017. Retrieved July 6, 2008.
88. Andi Kleen (June 26, 2001). "Porting Linux to x86-64" (https://web.archive.org/web/201009100
14057/http://www.x86-64.org/pipermail/announce/2001-June/000020.html). Archived from the
original (http://www.x86-64.org/pipermail/announce/2001-June/000020.html) on September 10,
2010. "Status: The kernel, compiler, tool chain work. The kernel boots and work on simulator
and is used for porting of userland and running programs"
89. Andi Kleen. "Andi Kleen's Page" (http://www.halobates.de/). Archived (https://web.archive.org/
web/20091207131536/http://www.halobates.de/) from the original on December 7, 2009.
Retrieved August 21, 2009. "This was the original paper describing the Linux x86-64 kernel
port back when x86-64 was only available on simulators."
90. "Arch64 FAQ" (https://wiki.archlinux.org/index.php/Arch64_FAQ). April 23, 2012. Archived (http
s://web.archive.org/web/20120514030334/https://wiki.archlinux.org/index.php/Arch64_FAQ)
from the original on May 14, 2012. Retrieved May 11, 2012. "You can either use the multilib
packages or a i686 chroot."

28 of 32 31/07/2024, 15:42
x86-64 - Wikipedia https://en.wikipedia.org/wiki/X86-64

91. Thorsten Leemhuis (September 13, 2011). "Kernel Log: x32 ABI gets around 64-bit drawbacks"
(https://web.archive.org/web/20111028081253/http://www.h-online.com/open/features/Kernel-L
og-x32-ABI-gets-around-64-bit-drawbacks-1342061.html). www.h-online.com. Archived from
the original (http://www.h-online.com/open/features/Kernel-Log-x32-ABI-gets-around-64-bit-dra
wbacks-1342061.html) on October 28, 2011. Retrieved November 1, 2011.
92. "x32 - a native 32-bit ABI for x86-64" (http://linuxplumbersconf.org/2011/ocw/sessions/531).
linuxplumbersconf.org. Archived (https://web.archive.org/web/20120505022446/http://www.linu
xplumbersconf.org/2011/ocw/sessions/531) from the original on May 5, 2012. Retrieved
November 1, 2011.
93. "x32-abi" (https://sites.google.com/site/x32abi/). Google Sites. Archived (https://web.archive.or
g/web/20111030054600/http://sites.google.com/site/x32abi/) from the original on October 30,
2011. Retrieved November 1, 2011.
94. "AMD64 Port" (http://www.debian.org/ports/amd64/). debian.org. Archived (https://web.archiv
e.org/web/20190926060654/https://www.debian.org/ports/amd64/) from the original on
September 26, 2019. Retrieved October 29, 2011.
95. "5-level paging" (https://docs.kernel.org/arch/x86/x86_64/5level-paging.html). kernel.org.
Retrieved February 7, 2024.
96. "Apple – Mac OS X Xcode 2.4 Release Notes: Compiler Tools" (https://web.archive.org/web/20
090422045532/http://developer.apple.com/releasenotes/DeveloperTools/RN-CompilerTools/ind
ex.html). Apple Inc. April 11, 2007. Archived from the original (https://developer.apple.com/rele
asenotes/DeveloperTools/RN-CompilerTools/index.html) on April 22, 2009. Retrieved
November 19, 2012.
97. "Apple – Mac OS X Leopard – Technology - 64-bit" (https://web.archive.org/web/200901120550
17/http://www.apple.com/macosx/technology/64bit.html). Apple Inc. Archived from the original
(https://www.apple.com/macosx/technology/64bit.html) on January 12, 2009. Retrieved
November 19, 2012.
98. "Mac OS X v10.6: Macs that use the 64-bit kernel" (http://support.apple.com/kb/HT3770).
Apple Inc. Archived (https://web.archive.org/web/20090831113241/http://support.apple.com/kb/
HT3770) from the original on August 31, 2009. Retrieved November 29, 2012.
99. John Siracusa. "Mac OS X 10.6 Snow Leopard: the Ars Technica review" (https://arstechnica.c
om/apple/reviews/2009/08/mac-os-x-10-6.ars/5). Ars Technica LLC. Archived (https://web.archi
ve.org/web/20091009161632/http://arstechnica.com/apple/reviews/2009/08/mac-os-x-10-6.ar
s/5) from the original on October 9, 2009. Retrieved June 20, 2010.
100. "Mac OS X Technology" (https://web.archive.org/web/20110328170107/http://www.apple.com/
macosx/technology/#sixtyfourbit). Apple Inc. Archived from the original (https://www.apple.com/
macosx/technology/#sixtyfourbit) on March 28, 2011. Retrieved November 19, 2012.
101. Schmid, J; Thomases, K; Ramey, J; Czekalla, U; Mathieu, B; Abhiram, R (September 10,
2019). "So We Don't Have a Solution for Catalina...Yet" (https://www.codeweavers.com/blog/jsc
hmid/2019/9/10/so-we-dont-have-a-solution-for-catalinayet). CodeWeavers Blog. Archived (http
s://web.archive.org/web/20210929085817/https://www.codeweavers.com/blog/jschmid/201
9/9/10/so-we-dont-have-a-solution-for-catalinayet) from the original on September 29, 2021.
Retrieved September 29, 2021.
102. Thomases, Ken (December 11, 2019). "win32 on macOS" (https://www.winehq.org/pipermail/wi
ne-devel/2019-December/156602.html). WineHQ. Archived (https://web.archive.org/web/20201
111190220/https://www.winehq.org/pipermail/wine-devel/2019-December/156602.html) from
the original on November 11, 2020. Retrieved September 29, 2021.

29 of 32 31/07/2024, 15:42
x86-64 - Wikipedia https://en.wikipedia.org/wiki/X86-64

103. "Microsoft Raises the Speed Limit with the Availability of 64-Bit Editions of Windows Server
2003 and Windows XP Professional" (https://news.microsoft.com/2005/04/25/microsoft-raises-t
he-speed-limit-with-the-availability-of-64-bit-editions-of-windows-server-2003-and-windows-xp-
professional/#sm.0000kw91cdgntf2kwp82ed9a9yn4e). Microsoft News Center (Press release).
April 25, 2005. Retrieved January 29, 2024.
104. "A description of the x64-based versions of Windows Server 2003 and of Windows XP
Professional x64 Edition" (https://web.archive.org/web/20160420135711/https://support.micros
oft.com/en-gb/kb/888733). Microsoft Support. Archived from the original (https://support.micros
oft.com/en-gb/kb/888733) on April 20, 2016. Retrieved August 14, 2016.
105. "Windows Server 2003 SP1 Administration Tools Pack" (https://web.archive.org/web/20160827
033240/http://www.microsoft.com/en-us/download/details.aspx?id=3725). Microsoft Download
Center. Archived from the original (https://www.microsoft.com/en-us/download/details.aspx?id=
3725) on August 27, 2016. Retrieved August 14, 2016.
106. "/LARGEADDRESSAWARE (Handle Large Addresses)" (https://learn.microsoft.com/en-us/cpp/
build/reference/largeaddressaware-handle-large-addresses?view=msvc-170). Visual Studio
2022 Documentation – MSVC Linker Reference – MSVC Linker Options. Microsoft. Archived (h
ttps://web.archive.org/web/20221221152408/https://learn.microsoft.com/en-us/cpp/build/referen
ce/largeaddressaware-handle-large-addresses?view=msvc-170) from the original on
December 21, 2022. Retrieved December 21, 2022. "The /LARGEADDRESSAWARE option
tells the linker that the application can handle addresses larger than 2 gigabytes."
107. Matt Pietrek (May 2006). "Everything You Need To Know To Start Programming 64-Bit
Windows Systems" (https://learn.microsoft.com/en-us/archive/msdn-magazine/2006/may/x64-s
tarting-out-in-64-bit-windows-systems-with-visual-c). Microsoft. Retrieved April 18, 2023.
108. Chris St. Amand (January 2006). "Making the Move to x64" (https://learn.microsoft.com/en-us/p
revious-versions/technet-magazine/cc161043(v=msdn.10)). Microsoft. Retrieved April 18,
2023.
109. "Behind Windows x86-64's 44-bit Virtual Memory Addressing Limit" (http://www.alex-ionescu.co
m/?p=50). Archived (https://web.archive.org/web/20081223145800/http://www.alex-ionescu.co
m/?p=50) from the original on December 23, 2008. Retrieved July 2, 2009.
110. "64-bit programming for Game Developers" (https://learn.microsoft.com/en-us/windows/win32/d
xtecharts/sixty-four-bit-programming-for-game-developers#porting-applications-to-64-bit-platfor
ms). Retrieved April 18, 2023.
111. "Memory Limits for Windows and Windows Server Releases" (https://learn.microsoft.com/en-u
s/windows/win32/memory/memory-limits-for-windows-releases). Microsoft. Retrieved April 18,
2023.
112. Kingsley-Hughes, Adrian (August 23, 2010). "AMD says goodbye to 3DNow! instruction set" (ht
tps://www.zdnet.com/article/amd-says-goodbye-to-3dnow-instruction-set/). ZDNet. Archived (htt
ps://web.archive.org/web/20230108040037/https://www.zdnet.com/article/amd-says-goodbye-t
o-3dnow-instruction-set/) from the original on January 8, 2023. Retrieved January 8, 2023.
113. "General Porting Guidelines" (https://learn.microsoft.com/en-us/windows/win32/winprog64/gen
eral-porting-guidelines). Programming Guide for 64-bit Windows. Microsoft Docs. Retrieved
April 18, 2023.
114. "Driver history for Microsoft SQL Server" (https://learn.microsoft.com/en-us/sql/connect/connec
t-history?view=sql-server-ver16). Microsoft Docs. Retrieved April 18, 2023.
115. "Microsoft OLE DB Provider for Jet and Jet ODBC driver are available in 32-bit versions only"
(https://learn.microsoft.com/en-US/office/troubleshoot/access/jet-odbc-driver-available-32-bit-v
ersion). Office Access. Microsoft Docs. KB957570. Retrieved April 18, 2023.

30 of 32 31/07/2024, 15:42
x86-64 - Wikipedia https://en.wikipedia.org/wiki/X86-64

116. Anand Lal Shimpi (May 21, 2013). "The Xbox One: Hardware Analysis & Comparison to
PlayStation 4" (http://www.anandtech.com/show/6972/xbox-one-hardware-compared-to-playsta
tion-4/2). Anandtech. Archived (https://web.archive.org/web/20130607031844/http://www.anan
dtech.com/show/6972/xbox-one-hardware-compared-to-playstation-4/2) from the original on
June 7, 2013. Retrieved May 22, 2013.
117. "The Tech Spec Test: Xbox One Vs. PlayStation 4" (http://www.gameinformer.com/b/news/archi
ve/2013/05/21/the-tech-spec-test-xbox-one-vs-playstation-4.aspx). Game Informer. May 21,
2013. Archived (https://web.archive.org/web/20130607180640/http://www.gameinformer.com/b/
news/archive/2013/05/21/the-tech-spec-test-xbox-one-vs-playstation-4.aspx) from the original
on June 7, 2013. Retrieved May 22, 2013.
118. "What to expect from Sony 'PlayStation 5' launch in November" (https://indianexpress.com/artic
le/technology/gaming/sony-playstation-5-might-launch-on-november-13-6577207/). The Indian
Express. August 31, 2020. Archived (https://web.archive.org/web/20200919053244/https://india
nexpress.com/article/technology/gaming/sony-playstation-5-might-launch-on-november-13-657
7207/) from the original on September 19, 2020. Retrieved September 14, 2020.
119. Cutress, Dr Ian. "Hot Chips 2020 Live Blog: Microsoft Xbox Series X System Architecture
(6:00pm PT)" (https://www.anandtech.com/show/15994/hot-chips-2020-live-blog-microsoft-xbo
x-series-x-system-architecture-600pm-pt). www.anandtech.com. Archived (https://web.archiv
e.org/web/20200917190502/https://www.anandtech.com/show/15994/hot-chips-2020-live-blog-
microsoft-xbox-series-x-system-architecture-600pm-pt) from the original on September 17,
2020. Retrieved September 14, 2020.
120. Hollister, Sean (November 12, 2021). "Steam Deck: Five big things we learned from Valve's
developer summit" (https://www.theverge.com/22779252/steam-deck-things-we-learned-from-v
alve-developer-summit). The Verge. Archived (https://web.archive.org/web/20220207230831/ht
tps://www.theverge.com/22779252/steam-deck-things-we-learned-from-valve-developer-summi
t) from the original on February 7, 2022. Retrieved November 12, 2021.
121. "ProcessorArchitecture Fields" (http://msdn.microsoft.com/en-us/library/microsoft.build.utilitie
s.processorarchitecture_fields.aspx). Archived (https://web.archive.org/web/20150428190214/h
ttps://msdn.microsoft.com/en-us/library/microsoft.build.utilities.processorarchitecture_fields.asp
x) from the original on April 28, 2015. Retrieved September 4, 2013.
122. "An example file from Linux 3.7.8 kernel source tree displaying the usage of the term x86_64"
(https://web.archive.org/web/20050923210216/http://lxr.linux.no/#linux+v3.7.8/arch/x86/configs/
x86_64_defconfig). Archived from the original (http://lxr.linux.no/#linux+v3.7.8/arch/x86/configs/
x86_64_defconfig) on September 23, 2005. Retrieved February 17, 2013.
123. US 6877084 (https://worldwide.espacenet.com/textdoc?DB=EPODOC&IDX=US6877084)
124. US 6889312 (https://worldwide.espacenet.com/textdoc?DB=EPODOC&IDX=US6889312)
125. US 6732258 (https://worldwide.espacenet.com/textdoc?DB=EPODOC&IDX=US6732258)
126. "Patent Cross License Agreement Between AMD and Intel" (https://web.archive.org/web/20070
621084244/http://contracts.corporate.findlaw.com/agreements/amd/intel.license.2001.01.01.ht
ml). January 1, 2001. Archived from the original (http://contracts.corporate.findlaw.com/agreem
ents/amd/intel.license.2001.01.01.html) on June 21, 2007. Retrieved August 23, 2009.
127. "AMD Intel Settlement Agreement" (https://www.sec.gov/Archives/edgar/data/2488/000119312
509236705/dex101.htm). Archived (https://web.archive.org/web/20170707043343/https://ww
w.sec.gov/Archives/edgar/data/2488/000119312509236705/dex101.htm) from the original on
July 7, 2017. Retrieved September 18, 2017.

31 of 32 31/07/2024, 15:42
x86-64 - Wikipedia https://en.wikipedia.org/wiki/X86-64

128. Stephen Shankland and Jonathan E. Skillings (November 12, 2009). "Intel to pay AMD $1.25
billion in antitrust settlement" (https://web.archive.org/web/20121108032512/http://news.cnet.co
m/8301-1001_3-10396188-92.html). CNET. Archived from the original (http://news.cnet.com/83
01-1001_3-10396188-92.html) on November 8, 2012. Retrieved April 24, 2012.
129. Smith, Ryan (November 12, 2009). "AMD and Intel Settle Their Differences: AMD Gets To Go
Fabless" (https://web.archive.org/web/20100513042947/http://www.anandtech.com/show/287
3). AnandTech. Archived from the original (http://www.anandtech.com/show/2873) on May 13,
2010.

External links
▪ AMD Developer Guides, Manuals & ISA Documents (https://developer.amd.com/resources/dev
eloper-guides-manuals/)
▪ x86-64: Extending the x86 architecture to 64-bits (http://www.stanford.edu/class/ee380/Abstract
s/O00927.html) – technical talk by the architect of AMD64 (video archive (https://web.archive.or
g/web/20100813052749/http://stanford-online.stanford.edu/courses/ee380/000927-ee380-10
0.asx)), and second talk by the same speaker (http://www.stanford.edu/class/ee380/Abstracts/0
40107.html) (video archive (https://web.archive.org/web/20100813100133/http://stanford-onlin
e.stanford.edu/courses/ee380/040107-ee380-100.asx))
▪ AMD's "Enhanced Virus Protection" (https://web.archive.org/web/20060623073619/http://ww
w.xbitlabs.com/news/other/display/20041227094638.html)
▪ Intel tweaks EM64T for full AMD64 compatibility (https://www.theregister.co.uk/2005/08/23/intel
_fixes_em64t/)
▪ Analyst: Intel Reverse-Engineered AMD64 (http://www.extremetech.com/extreme/56018-analys
t-intel-reverseengineered-amd64)
▪ Early report of differences between Intel IA32e and AMD64 (https://marc.info/?l=linux-kernel&m
=107766481408468&w=2)
▪ Porting to 64-bit GNU/Linux Systems (http://gcc.gnu.org/pub/gcc/summit/2003/Porting%20t
o%2064%20bit.pdf), by Andreas Jaeger from GCC Summit 2003. An excellent paper
explaining almost all practical aspects for a transition from 32-bit to 64-bit.
▪ Intel 64 Architecture (http://www.intel.com/technology/intel64/index.htm)
▪ Intel Software Network: "64 bits" (https://web.archive.org/web/20110403005033/http://software.i
ntel.com/en-us/articles/all-about-64-bits/)
▪ TurboIRC.COM tutorials, including examples of how to of enter protected and long mode the
raw way from DOS (https://web.archive.org/web/20170222181811/http://www.turboirc.com/as
m/)
▪ Seven Steps of Migrating a Program to a 64-bit System (https://web.archive.org/web/20100123
010204/http://software.intel.com/en-us/articles/seven-steps-of-migrating-a-program-to-a-64-bit-
system/)
▪ Memory Limits for Windows Releases (http://msdn.microsoft.com/en-us/library/aa366778%28V
S.85%29.aspx)

Retrieved from "https://en.wikipedia.org/w/index.php?title=X86-64&oldid=1237056292"

32 of 32 31/07/2024, 15:42