APL1581

DUAL INPUT LOW DROPOUT REGULATOR

Features General Description

• Adjustable or Fixed Output The APL1581 series of high performance positive volt-
• 520mV typ. Dropout at 5A in Dual Power age regulators are designed for use in applications re-
Voltage Mode quiring very low dropout voltage at 5Amp.

• Remote Sense Pin Available

The superior dropout characteristics result in reducing
heat dissipation compared to regular LDOs. The APL1581
• 2% Accuracy Over Temperature Range
also provides excellent regulation over line, load, and tem-
• Built-In Over-Temperature Protection
perature variations.
• Built-In Current Limit Current limit is trimmed to ensure specified output cur-
• 5 Pin TO-263 and TO-252, SOP-8P, TO-252-4 rent and controlled short-circuit current. On-chip thermal
Packages limiting provides protection against any combination of
• Lead Free and Green Devices Available overload tha t would create excessi ve junction
(RoHS Compliant) temperature.
The APL1581 is available in both the through-hole and
surface mount versions of the industry standard 5-Pin
Applications TO-263 and TO-252, SOP-8P, TO-252-4 power packages.

• Microprocessor Supplies
• Chip Set Supplies
• VGA Card Power
• LCD Monitor Power

Ordering and Marking Information

APL1581 Package Code
G5 : TO-263-5 U5 :TO-252-5 KA : SOP-8P
U4 : TO-252-4
Assembly Material Temperature Range
C : 0 to 70 oC
Handling Code Handling Code
TR : Tape & Reel
Temperature Range
Voltage Code :
Package Code 15 : 1.5V 18 : 1.8V
25 : 2.5V Blank : Adjustable Version
Voltage Code Assembly Material
G : Halogen and Lead Free Device

15
APL1581-15 G5/U5/U4 : APL1581 XXXXX - Date Code
XXXXX

APL1581
APL1581-15 KA : XXXXX XXXXX - Date Code

Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise
customers to obtain the latest version of relevant information to verify before placing orders.

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Rev. B.8 - Jan., 2012
APL1581

Pin Configuration

5 VIN VIN
4
4 VCNTL 3 VCNTL
TAB is VOUT 3 TAB is VOUT
VOUT
2 ADJ
2 ADJ (or GND)
1 VSENSE
1 VSENSE

Front View of TO-263-5 Front View of TO-252-4

5 VIN VSENSE 1 8 VOUT

4 VCNTL ADJ (or GND) 2 7 VOUT
TAB is VOUT 3 VOUT
VCNTL 3 6 VOUT
2 ADJ(or GND)
VIN 4 5 VOUT
1 VSENSE

Front View of TO-252-5 SOP-8P (Top View)

NC = No internal connection

= Thermal Pad
(connected to VOUT plane for better heat
dissipation)
Pin 5~8 must be connected together by a shortest
wide track or plane.

Absolute Maximum Ratings (Note 1, 2)

Symbol Parameter Rating Unit

VIN Input Voltage 7 V

VCNTL Control Voltage 7 V

PD Power Dissipation Internally Limited W

TJ Junction Temperature 150 °C

TSTG Storage Temperature Range -65 to +150 °C

TSDR Maximum Lead Soldering Temperature, 10 Seconds 260 °C

Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are
stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recom-
mended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
Note 2 : The maximum allowable power dissipation at any TA (ambient temperature) is calculated using: PD (max) = (TJ – TA) / θJA; TJ
= 125°C. Exceeding the maximum allowable power dissipation will result in excessive die temperature.

Thermal Characteristics
Symbol Parameter Typical Value Unit

Junction-to-Ambient Resistance in free air (Note 3)

TO-263-5 (Toplayer plane size : 15mm x 15 mm) 28
θJA
o
C/W
TO-252-4/TO-252-5 (Toplayer plane size : 10mm x 10 mm) 42
SOP-8P (Toplayer plane size : 10mm x 10 mm) 68

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Rev. B.8 - Jan., 2012
APL1581

Thermal Characteristics (Cont.)

Symbol Parameter Typical Value Unit
(Note 4)
Junction-to-Case Resistance
θJC
o
TO-263-5 4 C/W
TO-252-4/TO-252-5 5

Note 3 : θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. The sizes of the
rectangular plane, where the devices are mounted, are shown in the table.
Note 4: The case temperature is measured on the TAB of the device mounted on the test board described in Note 3 except the
package TO-220-5. The case temperature of the TO-220-5 is measured on the bottom of the case directly below the die.

Electrical Characteristics
Unless otherwise noted , these specifications apply over CIN=10µF, CCNTL=1µF, COUT=10µF, and TA=0 to 70°C. Typical values refer to
TA=25°C. VOUT=VSENSE.

APL1581
Symbol Parameter Test Conditions Unit
Min. Typ. Max.
Reference Voltage VCNTL=2.75~5.5V, VIN=2.05~5.5V,
VREF 1.225 1.250 1.275 V
APL1581 IO =10mA~5A, VADJ=0V
Output Voltage (IO =0~5A for fixed versions)
APL1581-15 VCNTL=3~5.5V , VIN=2.3~5.5V 1.470 1.500 1.530
VOUT V
APL1581-18 VCNTL=3.3~5.5V , VIN=2.6~5.5V 1.764 1.800 1.836
APL1581-25 VCNTL=4~5.5V , VIN=3.3~5.5V 2.450 2.500 2.550
Line Regulation (IO =0A for fixed versions)
APL1581 VCNTL=2.75~5.5V, VIN=1.75~5.5V,
IO =10mA, VADJ=0V
REGLINE - - 3 mV
APL1581-15 VCNTL=3~5.5V, VIN=2.3~5.5V
APL1581-18 VCNTL=3.3~5.5V, VIN=2.6~5.5V
APL1581-25 VCNTL=4~5.5V, VIN=3~5.5V
Load Regulation (Note 5) (IO =0~5A for fixed versions)
APL1581 VCNTL=2.75V, VIN=2.1V, VADJ =0V,
IO =10mA~5A
REGLOAD - - 5 mV
APL1581-15 VCNTL=3V, VIN=2.35V
APL1581-18 VCNTL=3.3V, VIN=2.65V
APL1581-25 VCNTL=4V, VIN=3.35V
Dropout Voltage (Note 6) IO =5A for all versions
APL1581 VIN=2.05V, VADJ =0V
VCNTL-VOUT APL1581-15 VIN=2.3V - 1.20 1.35 V
APL1581-18 VIN=2.6V
APL1581-25 VIN=3.3V
Dropout Voltage (Note 6) IO =5A for all versions
APL1581 VCNTL=2.75V, VADJ =0V
VIN-VOUT APL1581-15 VCNTL=3V - 0.52 0.75 V
APL1581-18 VCNTL=3.3V
APL1581-25 VCNTL=4V
ILIMIT Current Limit VCNTL-VOUT=1.5V, VIN-VOUT=0.6V 5 - - A
(Note7)
Minimum Load Current
ILMIN - 0.8 10 mA
APL1581 VCNTL=5V, VIN=3.3V, VADJ =0V
REGTHERMAL Thermal Regulation 30ms Pulse - 0.01 - %/W
Power Supply Ripple Rejection VRIPPLE=1VPP at 120Hz, IO=5A
APL1581 VCNTL=5V, VIN=5V, VADJ =0V
PSRR APL1581-15 VCNTL=5.25V, VIN=5.25V 60 70 - dB
APL1581-18 VCNTL=5.55V, VIN=5.55V
APL1581-25 VCNTL=6.25V, VIN=6.25V

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Rev. B.8 - Jan., 2012
APL1581

Electrical Characteristics (Cont.)

Unless otherwise noted , these specifications apply over CIN = 10µF, CCNTL = 1µF, COUT = 10µF, and TA = 0 to 70°C. Typical values refer
to TA = 25°C. VOUT = VSENSE.

APL1581
Symbol Parameter Test Conditions Unit
Min. Typ. Max.
VCNTL-VOUT=1.5V, VIN-VOUT=0.8V,
ICNTL CNTL Pin Current - 45 120 mA
IO =5A
Ground Pin Current
APL1581-15 VCNTL =3V, VIN =2.3V
IGND - 8 13 mA
APL1581-18 VCNTL =3.3V, VIN =2.6V
APL1581-25 VCNTL =4V, VIN =3.3V
Adjust Pin Current
IADJ - 50 120 µA
APL1581 VCNTL=2.75V, VIN=2.05V , VADJ =0V
Note 5 : Low duty cycle pulse test with Kelvin connections are required to maintain data accuracy .
Note 6 : Dropout voltage is defined as the minimum difference between VIN and VOUT required to maintain 1% VOUT regulation.
Note 7 : Minimum load current is defined as the minimum current required at the output to maintain VOUT regulation.

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Rev. B.8 - Jan., 2012
APL1581

Typical Operating Characteristics

Reference Voltage vs. Junction Temperature Adjust Pin Current vs. Junction Temperature
1.275 80
1.270 70
1.265

Adjust Pin Current (µA)

Reference Voltage (V)

60
1.260
1.255 50

1.250 40
1.245 30
1.240
20
1.235
1.230 10

1.225 0
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
Junction Temperature (°C) Junction Temperature (°C)

Minimum Load Current vs. Junction Temperature VIN-VOUT Dropout Voltage vs. Output Current
1.2 700
TJ=125oC
VIN-VOUT Dropout Voltage (mV)

600
Minimum Load Current (mA)

1.0
VCNTL-VOUT=10.75V
500
0.8 TJ=25oC
400
VCNTL-VOUT=1.45V
0.6
300
0.4 TJ=-50oC
200
0.2 100

0.0 0
-50 -25 0 25 50 75 100 125 150 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
Junction Temperature (°C) Output Current (A)

Short-Circuit Current vs. Junction Temperature VCONTROL-VOUT Dropout Voltage vs. Output Current
14 1.4
VIN=5.0V TJ=-50oC
VCNTL-VOUT Dropout Voltage (V)

12 1.3 TJ=0oC
Short-Circuit Current (A)

10 1.2

8 VIN=3.3V 1.1

6 1.0 TJ=25oC

4 0.9
TJ=125oC
2 0.8

0 0.7
-50 -25 0 25 50 75 100 125 150 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
Junction Temperature (°C) Output Current (A)

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Rev. B.8 - Jan., 2012
APL1581

Typical Operating Characteristics (Cont.)

Control Pin Current vs. Output Current Control Pin Current vs. Output Current

VIN-V OUT=0.6V VIN-V OUT=0.8V

160 80
TJ=125oC TJ=-50oC
140 70

60 TJ=0oC
120
VCNTL Pin Current (mA)

VCNTL Pin Current (mA)

TJ=25oC
100 TJ=25oC 50

40 TJ=75oC
80

60 TJ=0oC 30

40 TJ=-50oC 20
TJ=125oC
20 10
TJ=75oC
0 0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
Output Current (A) Output Current (A)

Control Pin Current vs. Output Current Control Pin Current vs. Output Current
VIN-V OUT=1.0V VIN-V OUT=4.25V
80 70
TJ=-50oC
70 60 TJ=-50oC
TJ=0oC
VCNTL Pin Current (mA)

60 TJ=0oC
50
VCNTL Pin Current (mA)

TJ=25oC
50 TJ=25oC
40
40 TJ=75oC
TJ=75oC
30
30
20
20
10 TJ=125oC
10 TJ=125oC

0 0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
Output Current (A) Output Current (A)

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Rev. B.8 - Jan., 2012
APL1581

Pin Description

PIN
FUNCTION
NAME I/O
Positive side of the reference voltage, which allows remote sensing to obtain excellent load
VSENSE I
regulation.
Negative side of the reference voltage, which allows to use resistor divider to set an expect
ADJ O output voltage. A small bypass capacitor can be connected from this pin to ground to improve
PSRR performance.

GND O For fixed voltage devices, this is the bottom of the resistor divider that sets the output voltage.
Output pin of the regulator, which connects to the TAB. A minimum of 10µF capacitor must be
VOUT O
connected from this pin to ground to ensure the stability.
Supply pin of the control circuitry, which must be always higher than VOUT for the device to
VCNTL I
regulate. (See electrical characteristics)
Power input pin of the regulator, which must be always higher than VOUT for the device to
VIN I
regulate. (See electrical characteristics)

Block Diagram

VIN VOUT

VCNTL

Current Limit VSENSE

Thermal Voltage
Protection Regulation ADJ/GND

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Rev. B.8 - Jan., 2012
APL1581

Typical Application Circuit

(1) Adjustable Output Voltage Device

VIN VIN VOUT VOUT

+3.3V APL1581 +2.5V/5A
(Adj.)
VCNTL VCNTL VSENSE
+5V ADJ R1
VREF 120
CCNTL CIN COUT
10µF 100µF 470µF
R2
120
GND GND

* VOUT = VREF ( 1+ R2 / R1 ) + IADJ x R2

where VREF =1.25V (typical)
IADJ=50µA (typical)
* R1 is typically in range of 100Ω to 125Ω to satisfy the minimum load current requirement.

(2) Fixed Output Voltage Device

VIN VIN VOUT VOUT

+3.3V +2.5V/5A
APL1581-25
VCNTL VCNTL VSENSE
+5V GND
CCNTL CIN COUT
10µF 100µF 470µF

GND GND

(3) With Enable Control Application

VIN VIN VOUT VOUT

+3.3V APL1581 +2.5V/5A
Q1 (Adj.)
VCNTL VCNTL VSENSE
+5V 10k R1
ADJ VREF 120
CCNTL CIN COUT
Q2
Enable 10µF 100µF 470µF
R2
10k 120
GND GND
Q1 : APM2301A
Q2 : APM2300A

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Rev. B.8 - Jan., 2012
APL1581

Application Information

General The recommended R1 is in range of 100Ω to125Ω to

satisfy the minimum load current requirement. Proper
The APL1581 (adjustable or fixed) regulator is a 5 termi-
nal device designed specifically to provide extremely low sizes of R2 and R1 are also concerned for power
dissipation.
dropout voltages comparable to the PNP type without the
disadvantage of the extra power dissipation due to the
base current associated with PNP regulators. This is done VIN VIN VOUT VOUT

by bringing out the control pin of the regulator that pro- APL1581
vides the base current to the power NPN and connecting
VCNTL VCNTL VSENSE
it to a voltage that is greater than the voltage present at
ADJ VREF R1
the VIN pin. This flexibility makes APL1581 ideal for appli-
cations where dual inputs are available, such as a com-
puter motherboard with an ATX power supply that pro- IADJ=50µA R2
vides 5V and 3.3V to the board.
APL1581 is equipped with a 1.25V reference, precision
and fast voltage regulations, on-chip current and thermal
Figure 1. Setting Output Voltage
limits, and remote sensing capability to reduce system
total cost. Grounding and Output Sensing
APL1581 is available in SOP-8P, TO-252-5, and TO-263- The APL1581 allows true Kelvin sensing for both the high
5 packages to meet different power dissipation and low side of the load. Figure 2 shows the device con-
applications. nected to take advantage of the remote sense feature.
Output Voltage Setting The SENSE pin and the top of the resistor divider are
connected to the top of the load; the bottom of the resistor
See Figure 1 Adjustable APL1581 develops a 1.25V ref-
divider is connected to the bottom of the load. Typically,
erence voltage between the VSENSE pin and the ADJ pin.
the load is a microprocessor and parasitic resistance RP
Placing a resistor between these two terminals causes a
is made up of the PC traces and /or connector resistance
constant current to flow through R1 and down through R2
between the regulator and the processor. RP is now con-
to set the overall output voltage. In general, R1 is chosen
nected inside the regulation loop of the APL1581 and for
so that this current is the specified minimum load current
reasonable values of RP the load regulation at the load
of 10mA. The current out of the ADJ pin is small, typically
will be negligible. Voltage drops due to RP are not
50µA and itadds to the current from R1. Because IADJ is
eliminated; they will add to the dropout voltage of the regu-
very small, it needs to be considered only when very pre-
lator regardless of whether they are inside or outside the
cise output voltage setting is required. For best regulation,
regulation loop.
the top of the resistor divider should be connected di-
rectly to the SENSE pin. The adjustable APL1581 can be VOUT
programmable to any voltages in the range of 1.25V to VIN VIN VOUT

5.5V according to the following formula: APL1581

VCNTL VCNTL VSENSE
R2 ADJ R1 Load
VOUT = VREF x (1+ ) + IADJ x R2
R1

where Adjustable R2
Device
VREF = 1.25V (typical)
IADJ = 50µA (typical)
RP

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Rev. B.8 - Jan., 2012
APL1581

Application Information (Cont.)

Grounding and Output Sensing (Cont.) The output capacitors are also used to reduce the slew
rate of load current and help the APL1581 to minimize
VOUT variations of the output voltage, improving transient
VIN VIN VOUT
response. For this purpose, the low-ESR capacitors are
APL1581 recommended.
VCNTL VCNTL VSENSE
GND Load Input Capacitors

The input capacitors of VCNTL and VIN pins are not re-
quired for stability but for supplying surge currents during
Fixed Voltage
large load transients, and this will prevent the input rail
Device
RP from drooping and improve the performance of the
APL1581. Because parasitic inductors from voltage
Figure 2. Remote Voltage Sensing
sources or other bulk capacitors to the VCNTL and VIN
pins will limit the slew rate of the surge currents during
Stability and Output Capacitors large load transients, resulting in voltage drop at VIN and
The circuit design of using the APL1581 series requires VCNTL pins.
an output capacitor as part of the device frequency A capacitor of 1µF (ceramic chip capacitor) or greater
compensation. The following chart shows a stable re- (aluminum electrolytic capacitor) is recommended and
gion to select output capacitor for APL1581. This region connected near VCNTL pin. For VIN pin, an aluminum
above the curve indicates minimum required ESR and electrolytic capacitor (>33µF) is recommended. It is not
capacitance to maintain stability. However, the output ca- necessary to use low-ESR capacitors. More capacitance
pacitor should have an ESR less than 1Ω. reduces the variations of the input voltage at VIN pin.

100 Layout and Thermal Consideration

The APL1581 series have internal power and thermal

80
limiting (TJ=150oC typical) circuitry designed to protect
ESR (mΩ)

Stable Region the device under overload conditions. However, maximum

60
junction temperature ratings should not be exceeded
40 under continuous normal load conditions. Careful con-
sideration must be given to all sources of thermal resis-
20
tance from junction to ambient, including junction-to-case,
0 case-to-heat sink interface, and heat sink resistance itself.
1 10 100 1000 See Figure 3, the SOP-8P is a cost-effective package
Capacitance(µF) featuring a small size as a standard SOP-8 and a bottom
thermal pad to minimize the thermal resistance of the
A low-ESR solid tantalum and aluminum electrolytic ca- package, being applicable to high current applications.
pacitor (ESR<1Ω) works extremely well and provides good The thermal pad is soldered to the top VOUT plane which
transient response and stability over temperature. Ultra- may be connected to internal or bottom VOUT plane by
low-ESR capacitors, such as ceramic chip capacitors, may vias to reduce the heat sink thermal resistance. Therefore,
promote unstable or under-damped transient response, the printed circuit board (PCB) forms a heat sink and
but proper ceramic chip capacitors placed near loads can dissipates heat into ambient air.
be used as decoupling capacitors.

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Rev. B.8 - Jan., 2012
APL1581

Application Information (Cont.)

Layout and Thermal Consideration (Cont.)

Top layer
VOUT plane
for Heat Dissipation
(Larger area is better)

COUT

8 7 6 5
Load
Vias

Vias

1 2 3 4

Soldering area
(140mil x 110mil)
for bottom pad CCNTL CIN

Figure 3. Recommended SOP-8P Layout

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Rev. B.8 - Jan., 2012
APL1581

Package Information
TO-263-5
A

E c2 E1

L1

D1
D
H

b e c

SEE VIEW A
0

GAUGE PLANE SEATING PLANE

L

A1
0.25

VIEW A

S TO-263-5
Y
M MILLIMETERS INCHES
B
O
L MIN. MAX. MIN. MAX.
A 4.06 4.83 0.160 0.190

A1 0.00 0.25 0.000 0.010

b 0.51 0.99 0.020 0.039

c 0.38 0.74 0.015 0.029

c2 1.14 1.65 0.045 0.065

D 8.38 9.65 0.330 0.380

D1 6.00 9.00 0.236 0.354

E 9.65 11.43 0.380 0.450

E1 6.22 9.00 0.245 0.354

e 1.70 BSC 0.067 BSC

H 14.61 15.88 0.575 0.625

L 1.78 2.79 0.070 0.110

L1 1.68 0.066

0 0o 8 o
0o 8o

Note : Follow JEDEC TO-263 BB.

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Rev. B.8 - Jan., 2012
APL1581

Package Information
TO-252-5
E A
b3 c2 E1

L3

D1
D

H
c
b e
SEE VIEW A
0

GAUGE PLANE SEATING PLANE

L

A1
0.25

VIEW A

S TO-252-5
Y
M MILLIMETERS INCHES
B
O
L MIN. MAX. MIN. MAX.
A 2.18 2.39 0.086 0.094
A1 0.13 0.005
b 0.50 0.89 0.020 0.035
b3 4.32 5.46 0.170 0.215
c 0.46 0.61 0.018 0.024
c2 0.46 0.89 0.018 0.035
D 5.33 6.22 0.210 0.245
D1 4.57 6.00 0.180 0.236
E 6.35 6.73 0.250 0.265
E1 3.81 6.00 0.150 0.236
e 1.27 BSC 0.050 BSC
H 9.40 10.41 0.370 0.410
L 1.40 1.78 0.055 0.070
L3 0.89 2.03 0.035 0.080
0 0° 8° 0° 8°

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Rev. B.8 - Jan., 2012
APL1581

Package Information
TO-252-4
E A
b3 c2 E1

L3

D1
D

H
L4

c
b e
SEE VIEW A 0

GAUGE PLANE SEATING PLANE

L

A1
0.25

VIEW A

S TO-252-4
Y
M MILLIMETERS INCHES
B
O
L MIN. MAX. MIN. MAX.
A 2.18 2.39 0.086 0.094
A1 0.13 0.005
b 0.50 0.71 0.020 0.028
b3 4.32 5.46 0.170 0.215
c 0.46 0.61 0.018 0.024
c2 0.46 0.89 0.018 0.035
D 5.33 6.22 0.210 0.245
D1 4.57 6.00 0.180 0.236
E 6.35 6.73 0.250 0.265
E1 3.81 6.00 0.150 0.236
e 1.27 BSC 0.050 BSC
H 9.40 10.41 0.370 0.410
L 1.40 1.78 0.055 0.070
L3 0.89 2.03 0.035 0.080
L4 1.02 0.040
0 0° 8° 0° 8°

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Rev. B.8 - Jan., 2012
APL1581

Package Information
SOP-8P
-T- SEATING PLANE < 4 mils

SEE VIEW A

D1
E2
THERMAL
E1

E
PAD

h X 45o
e b c
A2

0.25
A1

GAUGE PLANE
SEATING PLANE
L
θ

VIEW A

S SOP-8P
Y
M MILLIMETERS INCHES
B
O
L MIN. MAX. MIN. MAX.
A 1.60 0.063
A1 0.00 0.15 0.000 0.006
A2 1.25 0.049
b 0.31 0.51 0.012 0.020
c 0.17 0.25 0.007 0.010
D 4.80 5.00 0.189 0.197
D1 2.50 3.50 0.098 0.138
E 5.80 6.20 0.228 0.244
E1 3.80 4.00 0.150 0.157
E2 2.00 3.00 0.079 0.118
e 1.27 BSC 0.050 BSC
h 0.25 0.50 0.010 0.020
L 0.40 1.27 0.016 0.050
θ 0oC 8o C 0o C 8o C

Note : 1. Followed from JEDEC MS-012 BA.

2. Dimension "D" does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion or gate burrs shall not exceed 6 mil per side .
3. Dimension "E" does not include inter-lead flash or protrusions.
Inter-lead flash and protrusions shall not exceed 10 mil per side.

Copyright  ANPEC Electronics Corp. 15 www.anpec.com.tw

Rev. B.8 - Jan., 2012
APL1581

Carrier Tape & Reel Dimensions

OD0 P0 P2 P1 A

E1
F

W
B0

K0 A0 OD1 B A
B
SECTION A-A

T
SECTION B-B

d
H
A

T1

Application A H T1 C d D W E1 F
16.4+2.00 13.0+0.50
330.0±2.00 50 MIN. 1.5 MIN. 20.2 MIN. 16.0±0.30 1.75±0.10 7.50±0.05
-0.00 -0.20
TO-252-4 P0 P1 P2 D0 D1 T A0 B0 K0
1.5+0.10 0.6+0.00
4.0±0.10 8.0±0.10 2.0±0.05 1.5 MIN. 6.80±0.20 10.40±0.20 2.50±0.20
-0.00 -0.40
Application A H T1 C d D W E1 F
16.4+2.00 13.0+0.50
330.0±2.00 50 MIN. 1.5 MIN. 20.2 MIN. 16.0±0.30 1.75±0.10 7.50±0.05
-0.00 -0.20
TO-252-5 P0 P1 P2 D0 D1 T A0 B0 K0
1.5+0.10 0.6+0.00
4.0±0.10 8.0±0.10 2.0±0.05 1.5 MIN. 6.80±0.20 10.40±0.20 2.50±0.20
-0.00 -0.40
Application A H T1 C d D W E1 F
24.4+2.00 13.0+0.50
330.0±2.00 50 MIN. 1.5 MIN. 20.2 MIN. 24.0±0.30 1.75±0.10 11.5±0.10
-0.00 -0.20
TO-263-5 P0 P1 P2 D0 D1 T A0 B0 K0
1.5+0.10 0.6+0.00
4.0±0.10 16.0±0.10 2.0±0.10 1.5 MIN. 10.8±0.20 16.1±0.20 5.2±0.20
-0.00 -0.40
Application A H T1 C d D W E1 F
12.4+2.00 13.0+0.50
330.0±2.00 50 MIN. 1.5 MIN. 20.2 MIN. 12.0±0.30 1.75±0.10 5.5±0.05
-0.00 -0.20
SOP-8P P0 P1 P2 D0 D1 T A0 B0 K0
1.5+0.10 0.6+0.00
4.0±0.10 8.0±0.10 2.0±0.05 1.5 MIN. 6.40±0.20 5.20±0.20 2.10±0.20
-0.00 -0.40

(mm)

Copyright  ANPEC Electronics Corp. 16 www.anpec.com.tw

Rev. B.8 - Jan., 2012
APL1581

Devices Per Unit

Package Type Unit Devices Per Reel
TO-252-4 Type & Reel 2500
TO-252-5 Type & Reel 2500
TO-263-5 Type & Reel 800
SOP-8P Type & Reel 2500

Taping Direction Information

TO-252-4

USER DIRECTION OF FEED

TO-252-5

USER DIRECTION OF FEED

Copyright  ANPEC Electronics Corp. 17 www.anpec.com.tw

Rev. B.8 - Jan., 2012
APL1581

Taping Direction Information

TO-263-5

USER DIRECTION OF FEED

SOP-8P

USER DIRECTION OF FEED

Copyright  ANPEC Electronics Corp. 18 www.anpec.com.tw

Rev. B.8 - Jan., 2012
APL1581

Classification Reflow Profiles

Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly
Preheat & Soak
100 °C 150 °C
Temperature min (Tsmin)
150 °C 200 °C
Temperature max (Tsmax)
60-120 seconds 60-120 seconds
Time (Tsmin to Tsmax) (ts)

Average ramp-up rate

3 °C/second max. 3°C/second max.
(Tsmax to TP)
Liquidous temperature (TL) 183 °C 217 °C
Time at liquidous (tL) 60-150 seconds 60-150 seconds
Peak package body Temperature
See Classification Temp in table 1 See Classification Temp in table 2
(Tp)*
Time (tP)** within 5°C of the specified
20** seconds 30** seconds
classification temperature (Tc)
Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max.

Time 25°C to peak temperature 6 minutes max. 8 minutes max.

* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.

Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)

3 3
Package Volume mm Volume mm
Thickness <350 ≥350
<2.5 mm 235 °C 220 °C
≥2.5 mm 220 °C 220 °C
Table 2. Pb-free Process – Classification Temperatures (Tc)
3 3 3
Package Volume mm Volume mm Volume mm
Thickness <350 350-2000 >2000
<1.6 mm 260 °C 260 °C 260 °C
1.6 mm – 2.5 mm 260 °C 250 °C 245 °C
≥2.5 mm 250 °C 245 °C 245 °C

Reliability Test Program

Test item Method Description
SOLDERABILITY JESD-22, B102 5 Sec, 245°C
HOLT JESD-22, A108 1000 Hrs, Bias @ Tj=125°C
PCT JESD-22, A102 168 Hrs, 100%RH, 2atm, 121°C
TCT JESD-22, A104 500 Cycles, -65°C~150°C
HBM MIL-STD-883-3015.7 VHBM≧2KV
MM JESD-22, A115 VMM≧200V
Latch-Up JESD 78 10ms, 1tr≧100mA

Copyright  ANPEC Electronics Corp. 19 www.anpec.com.tw

Rev. B.8 - Jan., 2012
APL1581

Customer Service

Anpec Electronics Corp.

Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050

Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838

Copyright  ANPEC Electronics Corp. 20 www.anpec.com.tw

Rev. B.8 - Jan., 2012