NXP Semiconductors Document Number: P2010EC

Data Sheet: Technical Data Rev. 3, 03/2016

P2010
P2010 QorIQ Integrated
Processor Hardware WB-TePBGA–689
31 mm × 31 mm
Specifications

The following list provides an overview of the P2010 feature • Programmable interrupt controller (PIC) compliant with
set: OpenPIC standard
• Single high-performance Power Architecture e500 cores. • Two four-channel DMA controllers
• 36-bit physical addressing • Two I2C controllers, DUART, timers
– Double-precision floating-point support • Enhanced local bus controller (eLBC)
– 32-Kbyte L1 instruction cache and 32-Kbyte L1 data • 16 general-purpose I/O signals
cache for each core • Operating junction temperature
– 800-MHz to 1.33-GHz clock frequency • 31 × 31 mm 689-pin WB-TePBGA II (wire bond
• 512 Kbyte L2 cache with ECC. Also configurable as temperature-enhanced plastic BGA)
SRAM and stashing memory.
• Three 10/100/1000 Mbps enhanced three-speed Ethernet
controllers (eTSECs)
– TCP/IP acceleration, quality of service, and
classification capabilities
– IEEE Std 1588™ support
– Lossless flow control
– R/G/MII, R/TBI, SGMII
• High-speed interfaces supporting various multiplexing
options:
– Four SerDes to 3.125 GHz multiplexed across
controllers
– Three PCI Express interfaces
– Two Serial RapidIO interfaces
– Two SGMII interfaces
• High-Speed USB controller (USB 2.0)
– Host and device support
– Enhanced host controller interface (EHCI)
– ULPI interface to PHY
• Enhanced secure digital host controller (SD/MMC)
Enhanced Serial peripheral interface (eSPI)
• Integrated security engine
– Protocol support includes SNOW, ARC4, 3DES, AES,
RSA/ECC, RNG, single-pass SSL/TLS, Kasumi
– XOR acceleration
• 64-bit DDR2/DDR3 SDRAM memory controller with
ECC support

NXP reserves the right to change the detail specifications as may be required to permit improvements in the design of
its products.

© 2011-2016 NXP B.V.

 Table of Contents
1 Pinout Assignments and Reset States . . . . . . . . . . . . . . . . . . .4 2.13 Enhanced Secure Digital Host Controller (eSDHC) . . 77
1.1 Ball Layout Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2.14 Programmable Interrupt Controller . . . . . . . . . . . . . . . 79
1.2 Pinout List by Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 2.15 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
2 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 2.16 I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
2.1 Overall DC Electrical Characteristics . . . . . . . . . . . . . .29 2.17 GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
2.2 Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 2.18 High-Speed Serial Interfaces (HSSI) . . . . . . . . . . . . . . 86
2.3 Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .34 2.19 PCI Express. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
2.4 Input Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 2.20 Serial RapidIO (SRIO) . . . . . . . . . . . . . . . . . . . . . . . . . 97
2.5 RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . .39 3 Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
2.6 Power-on Ramp Rate . . . . . . . . . . . . . . . . . . . . . . . . . .40 3.1 Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . . 101
2.7 DDR2 and DDR3 SDRAM . . . . . . . . . . . . . . . . . . . . . .40 3.2 Temperature Diode . . . . . . . . . . . . . . . . . . . . . . . . . . 102
2.8 eSPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 4 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
2.9 DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 4.1 Package Parameters for the P2020 WB-TePBGA . . . 102
2.10 Ethernet: Enhanced Three-Speed Ethernet (eTSEC), 4.2 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . 104
MII Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 5 Product Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
2.11 USB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 6 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
2.12 Enhanced Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . .70

P2010 QorIQ Integrated Processor Hardware Specifications, Rev. 3

2 NXP Semiconductors
Figure 1 shows the major functional units within the device.

P2010 e500 Core

512-Kbyte
L2
Cache 32-Kbyte 32-Kbyte
Power I-Cache D-Cache
Management

Security e500 64-/32-Bit

Enhanced Acceleration Coherency DDR2/DDR3
Local Bus OpenPIC with XOR SD/MMC
Module SDRAM
Acceleration Controller

Performance DMA DMA

Monitor USB
DUART Host/Device
Gigabit
2x I2C Ethernet SRIO/ SRIO/
eSPI ULPI PEX PEX
RIO Msg Unit/
PEX

SGMII
SerDes
SGMII

Figure 1. P2010 Block Diagram

P2010 QorIQ Integrated Processor Hardware Specifications, Rev. 3

NXP Semiconductors 3
Pinout Assignments and Reset States

1 Pinout Assignments and Reset States

1.1 Ball Layout Diagrams
Figure 2 shows the top view of the P2010 689-pin BGA ball map diagram.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29

VSS GVDD MDQ MDQ MDQ MDQ MDM MDQS MDQS MDQ MDQ LCS LSYNC_ LSYNC_ LCLK LAD LCS LAD LAD LGPL LA LA LA GPIO GPIO USB_D USB_D USB_ VSS
A [47] [43] [60] [56] [7] [7] [7] [63] [59] [1] IN OUT [1] [14] [7] [5] [2] [2] [21] [17] [28] [9] [10] [1] [2] DIR A

MDQS MDQS MDQ MDQ VSS MDQ MDQ GVDD MDQ MDQ GVDD LGPL LGPL VSS LCLK LAD LAD LAD LDP LAD LA LA LA BVDD USB_D USB_ VSS USB_D USB_
B [5] [5] [46] [42] [61] [57] [62] [58] [0] [4] [0] [10] [6] [0] [1] [3] [16] [26] [29] [4] NXT [5] STP B
USB_
MDQ MDM MDQ MDQ MDQ VSS GVDD VSS GVDD MDIC VSS BVDD LGPL BVDD LAD BVDD VSS LGPL LAD LA BVDD LA VSS USB_D USB_D CVDD USB_D
C [40] [5] [41] [52] [48] [0] [1] [15] LALE [5] [7] [18] [30] [6] [0] [7]
PWR- C
FAULT

MDQ MDQ GVDD MCK MCK MDQS MDQS MDQ MDQ LGPL LA LWE LCS LAD LCS VSS LAD BVDD LAD LCS LCS VSS LA GPIO VSS USB_D USB_ SPI_ SPI_
D [44] [45] [2] [2] [6] [6] [55] [50] [3] [22] [1] [6] [11] [5] [12] [4] [0] [3] [31] [11] [3] CLK CS0 CLK D

MDQ MDQ MDQ MDQ MDQ MDQ MDQ LAD LAD LA NC NC Temp_ Temp_ LDP LCS LAD LA LA GPIO GPIO SPI_ VSS SPI_
E VSS GVDD LBCTL CVDD CVDD E
[39] [34] [35] [53] [49] [54] [51] [9] [13] [20] [8] [7] Cathode Anode [0] [2] [1] [25] [23] [13] [15] CS1 CS3

AVDD_ SPI_ SDHC_ SDHC_ SPI_ SPI_

MODT MDQ MDQS MDQS MCK MCK MDM MDIC LCS LWE NC AVDD_ LA LAD LA LA GPIO GPIO GPIO
F [3] [38] [4] [4] [5] [5]
VSS
[6]
GVDD
[1] [4] [0] CORE Resv[26] VSS
[27] [8] [24] [19] [8] [12] [14] MOSI CMD DAT MISO F
[12] LBIU CS2
[0] [1]
UART_ SDHC_ SDHC_ IIC1_ SDHC_ SDHC_
MDM MCS MDQ MDQ VSS NC VSS GVDD BVDD VSS
G [4] [3] [33] [32] [1] SIN DAT DAT SCL DAT CLK G
[1] [2] [3] [0]

MODT MDQ MDQ MODT UART_ IIC2_ IIC2_ IIC1_ UART_

H GVDD VSS CTS VSS SIN H
[0] [37] [36] [1] SCL SDA SDA
[1] [0]

MCS MCS MODT MA MCS VSS

SEE DETAIL A SEE DETAIL B VSS
UART_ UART_ UART_ UART_ UART_
J [2] [0] MCAS [2] [13] [1] RTS SOUT SOUT UDE0 CTS RTS J
[1] [1] [0] [0] [0]

GVDD VSS MBA MA GVDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD OVDD VSS IRQ IRQ Resv[25] IRQ
K MRAS MWE [0] [10] RTC [1] [6] [2] K
CVDD CVDD
VSS GVDD GVDD GVDD MBA MA VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD IRQ OVDD IRQ IRQ
L [1] [0] [0] [4] _VSEL _VSEL [5] L
[1] [0]

MA MA MA BVDD LVDD BVDD

M [2] [1]
VSS VSS
[3]
VSS VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD MDVAL Resv.[24] VSS _VSEL _VSEL M
_VSEL
[1] [0]

MA VSS GVDD MA MAPAR_ GV VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD GPIO IRQ MSRCID OV VSS IRQ_
N [4] [6] DD [3] [3] [4] DD
OUT
N
ERR

MA MA MA GVDD VSS NC VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD VSS OVDD MSRCID MSRCID MSRCID GPIO
P [5] [8] [7] [13] [3] [2] [0] [2] P

MA GVDD VSS MA MAPAR_ VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD GPIO GPIO GPIO MSRCID GPIO GPIO
R [9] [11] OUT
MVREF [5] [7] [1] [1] [0] [6] R
DMA1 DMA1 DMA2
MCK MCK MA MBA MA VSS VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD CLK_ VSS
T [3] [3] [14] [2] [12] OUT
TDI _DDONE _DACK _DACK T
[0] [0] [0]

MCK MCK GVDD MA MCKE MCKE VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD HRESET OVDD TRIG GPIO
U [0] [0] [15] [0] [2] _REQ
ASLEEP TMS
_OUT [4] U

MCKE MCKE MECC VSS GVDD MECC VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD AVDD_ CKSTP VSS
V [1] [3] [3] [7] PLAT OUT0
TRST TDO TCK V
DMA2
MECC VSS GVDD VSS MDQ NC VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD NC SCAN_
W [2] [27] [9] SRESET HRESET [15] MODE
_DREQ SYSCLK W
[0]
TSEC2 DMA1 DMA2
MECC GVDD VSS MDQ MDQ VSS VSS AVDD_ VDD VDD VSS NC NC NC VSS VDD VDD VDD LVDD VSS OVDD NC
Y [6] [31] [26] DDR [2] [3] [4] _TXD [14] _DREQ _DDONE Y
[0] [0] [0]
TSEC2 TSEC2
MDQS GVDD GVDD MDM GVDD VSS GVDD VSS TSEC2 TEST CKSTP
AA [8] [8] _TX _TXD
_TX_EN
MCP0
_SEL IN0 AA
_CLK [2]

MDQS MECC MDQS MDQS MDQ

SEE DETAIL C SEE DETAIL D TSEC2 TSEC2 TSEC2 TSEC2
TRIG Resv.[23]
AB GVDD _TXD _TXD _RXD _RXD AB
[8] [4] [3] [3] [30] _IN
[5] [4] [6] [3]
TSEC2 TSEC2
MDM MECC VSS MDQ MCK MCK VSS VSS LVDD VSS LVDD LVDD VSS
AC [3] [1] [25] [4] [4] DDRCLK _RXD _RX AC
[5] _CLK
SD_ SD_ TSEC1 TSEC1 TSEC1 TSEC1 TSEC2 TSEC2 TSEC2 TSEC2
MECC MECC MDQ MCK MCK AVDD_ SD_PLL EC_ TSEC2
AD VSS GVDD VSS GVDD VSS XVSS TXA_P XVDD SDAVSS XVDD TXA_P XVSS _RXD _TXD _TXD _TXD _RXD _RXD _RXD AD
[5] [0] [24] [1] [1] SRDS _TPA MDC _CRS _RX_DV
[0] [3] [1] [6] [5] [0] [4] [7] [2]
SD_ SD_ SD_ SD_ TSEC_ TSEC1 TSEC1 TSEC1 TSEC1 TSEC2
MDQ MDQ GVDD MDQ MDQ MDQ MDM MDQ VSS NC XVDD XVSS SD_PLL XVSS XVDD 1588_ALARM _TXD LVDD TSEC2 TSEC2 TSEC2
AE [18] [19] [29] [15] [14] [1] [9] [5] TXA_N TXA_P
_TPD
TXA_P TXF_N _RXD _RXD _TXD _TXD
_COL _RX_ER _TX_ER
AE
[0] [1] [2] [3] _OUT [4] [2] [4] [1] [7]
SD_ SD_ SD_ TSEC1 EC_ TSEC2 TSEC2 TSEC2 TSEC2
MDQ MDQ MDQ GVDD MDQ MDQS MDQS MDQ MDQ NC XVSS XVSS XVDD SD_REF XVDD XVSS IMP_CAL VSS LVDD TSEC1 LVDD
AF [23] [22] [28] [10] [1] [1] [8] [13] [6]
TXB_N
_CLK
TXE_N _TXD
_TX_ER
GTX_CLK- _TXD _TXD _RXD _RXD AF
[1] [2] _TX [7] 125 [6] [1] [0] [1]
SD_ TSEC_ TSEC_ TSEC_ TSEC1 TSEC1 TSEC1 TSEC2 TSEC2
MDQS MDQS VSS MDQ VSS GVDD VSS GVDD MDQ XVSS IMP_CAL SVSS SVSS SVSS SD_REF SV SVSS SVSS SVSS 1588_TRIG 1588_CLK 1588_CLK _RXD VSS VSS
AG [2] [2] [11] [12] _CLK
DD _GTX _RX _GTX _TXD AG
_RX _IN[2] _IN _OUT [7] _CLK _CLK _CLK [3]
SD_ SD_ SD_ SD_ TSEC_ TSEC_ TSEC1 TSEC1 TSEC1
AH
MDM MDQ MDQ MDQ MDQ MDQ MDM MDQ MDQ VSS SVSS RXA_P SVDD RXB_P SVSS RXE_P SVDD RXF_P SVSS 1588_TRIG 1588_PULSE _RXD TSEC1 TSEC1 _RXD
TSEC1 LVDD _TXD LVDD AH
[2] [17] [16] [20] [2] [6] [0] [1] [5] _RX_ER _TX_EN _COL
[0] [1] [2] [3] _IN[1] _OUT [6] [0] [2]
SD_ SD_ SD_ SD_ TSEC_ TSEC_ TSEC1 TSEC1 TSEC1 TSEC1 TSEC1 TSEC1
AJ VSS GVDD MDQ MDQ MDQ MDQS MDQS MDQ MDQ VSS SVDD RXA_N SVSS RXB_N SVDD RXE_N SVSS RXF_N SVDD 1588_ALARM EC_ 1588_PULSE _RXD _TX _TXD _RX_DV _CRS _RXD VSS AJ
[21] [3] [7] [0] [0] [0] [4] MDIO
[0] [1] [2] [3] _OUT _OUT [5] _CLK [3] [3]

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29

Figure 2. P2010 Top View Ballmap

P2010 QorIQ Integrated Processor Hardware Specifications, Rev. 3

4 NXP Semiconductors
 Pinout Assignments and Reset States

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

VSS GVDD MDQ MDQ MDQ MDQ MDM MDQS MDQS MDQ MDQ LCS LSYNC_ LSYNC_ LCLK
A [47] [43] [60] [56] [7] [7] [7] [63] [59] [1] IN OUT [1]

MDQS MDQS MDQ MDQ VSS MDQ MDQ GVDD MDQ MDQ GVDD LGPL LGPL VSS LCLK
B [5] [5] [46] [42] [61] [57] [62] [58] [0] [4] [0]

MDQ MDM MDQ MDQ MDQ VSS GVDD VSS GVDD MDIC VSS BVDD LGPL BVDD LAD
C [40] [5] [41] [52] [48] [0] [1] [15]

MDQ MDQ GVDD MCK MCK MDQS MDQS MDQ MDQ LGPL LA LWE LCS LAD LCS
D [44] [45] [2] [2] [6] [6] [55] [50] [3] [22] [1] [6] [11] [5]

MDQ MDQ VSS MDQ MDQ MDQ GVDD MDQ MDQ LAD LAD LA NC NC Temp_
E [39] [34] [35] [53] [49] [54] [51] [9] [13] [20] [8] [7] Cathode

AVDD_
MODT MDQ MDQS MDQS MCK MCK VSS MDM GVDD MDIC LCS LWE NC AVDD_
F [3] [38] [4] [4] [5] [5] [6] [1] [4] [0] [12] LBIU
CORE
[0]

MDM MCS MDQ MDQ VSS NC VSS GVDD

G [4] [3] [33] [32] [1]

MODT GVDD VSS MDQ MDQ MODT

H [0] [37] [36] [1]

MCS MCS MODT MA MCS VSS

J [2] [0]
MCAS [2] [13] [1]

GVDD VSS MBA MA GVDD VDD VDD VDD VDD VDD VDD
K MRAS MWE [0] [10]

VSS GVDD GVDD GVDD MBA MA VDD VSS VSS VSS VSS VSS
L [1] [0]

MA MA VSS VSS MA VSS VDD VSS VSS VSS VSS VSS

M [2] [1] [3]

MA VSS GVDD MA MAPAR_ GVDD VDD VSS VSS VSS VSS VSS
N [4] [6] ERR

MA MA MA GVDD VSS NC VDD VSS VSS VSS VSS VSS

P [5] [8] [7] [13]

MA GVDD VSS MA MAPAR_ VDD VSS VSS VSS VSS VSS

R [9] [11] MVREF
OUT

DETAIL A
Figure 3. P2010 Ball Map—Detail A

P2010 QorIQ Integrated Processor Hardware Specifications, Rev. 3

NXP Semiconductors 5
Pinout Assignments and Reset States

16 17 18 19 20 21 22 23 24 25 26 27 28 29

LAD LCS LAD LAD LGPL LA LA LA GPIO GPIO USB_D USB_D USB_ VSS
[14] [7] [5] [2] [2] [21] [17] [28] [9] [10] [1] [2] DIR
A

LAD LAD LAD LDP LAD LA LA LA BVDD USB_D USB_ VSS USB_D USB_
[10] [6] [0] [1] [3] [16] [26] [29] [4] NXT [5] STP
B

USB_
BVDD VSS LGPL LAD LA BVDD LA VSS USB_D USB_D CVDD USB_D PWR-
LALE [5] [7] [18] [30] [6] [0] [7]
C
FAULT

LAD LAD LCS LCS LA GPIO USB_D USB_ SPI_ SPI_

VSS BVDD VSS VSS D
[12] [4] [0] [3] [31] [11] [3] CLK CS0 CLK

Temp_ LDP LCS LAD LA LA GPIO GPIO SPI_ VSS SPI_

LBCTL CVDD CVDD E
Anode [0] [2] [1] [25] [23] [13] [15] CS1 CS3

SPI_ SDHC_ SDHC_ SPI_ SPI_

Resv[26] VSS LA LAD LA LA GPIO GPIO GPIO
[27] [8] [24] [19] [8] [12] [14] MOSI CMD DAT MISO CS2 F
[1]
UART_ SDHC_ SDHC_ SDHC_
IIC1_ SDHC_
BVDD VSS SIN DAT DAT DAT G
SCL CLK
[1] [2] [3] [0]
UART_ IIC2_ IIC2_ IIC1_ UART_
CTS VSS SIN H
SCL SDA SDA
[1] [0]
UART_ UART_ UART_ UART_ UART_
VSS RTS SOUT SOUT UDE0 CTS RTS J
[1] [1] [0] [0] [0]

VDD VDD VDD VDD VDD OVDD VSS IRQ IRQ Resv[25] IRQ
RTC [1] [6] [2] K

CVDD CVDD
VSS VSS VSS VSS VDD IRQ OVDD IRQ IRQ
[0] [4] _VSEL _VSEL [5] L
[1] [0]
BVDD LVDD BVDD
VSS VSS VSS VSS VDD MDVAL Resv[25] VSS _VSEL _VSEL M
_VSEL
[1] [0]

VSS VSS VSS VSS VDD GPIO IRQ MSRCID OVDD VSS IRQ_
[3] [3] [4]
N
OUT

VSS VSS VSS VSS VDD VSS OVDD MSRCID MSRCID MSRCID GPIO
[3] [2] [0] [2]
P

VSS VSS VSS VSS VDD GPIO GPIO GPIO MSRCID GPIO GPIO
[5] [7] [1] [1] [0] [6]
R

DETAIL B
Figure 4. P2010 Ball Map—Detail B

P2010 QorIQ Integrated Processor Hardware Specifications, Rev. 3

6 NXP Semiconductors
 Pinout Assignments and Reset States

DETAIL C

MCK MCK MA MBA MA VSS VDD VSS VSS VSS VSS VSS
T [3] [3] [14] [2] [12]

MCK MCK GVDD MA MCKE MCKE VDD VSS VSS VSS VSS VSS
U [0] [0] [15] [0] [2]

MCKE MCKE MECC VSS GVDD MECC VDD VSS VSS VSS VSS VSS
V [1] [3] [3] [7]

MECC VSS GVDD VSS MDQ NC VDD VSS VSS VSS VSS VSS
W [2] [27] [9]

MECC GVDD VSS MDQ MDQ VSS VSS AVDD_ VDD VDD VSS NC NC
Y [6] [31] [26] DDR [2] [3]

MDQS GVDD GVDD MDM GVDD VSS GVDD

AA [8] [8]

MDQS MECC MDQS MDQS MDQ GVDD

AB [8] [4] [3] [3] [30]

MDM MECC VSS MDQ MCK MCK VSS

AC [3] [1] [25] [4] [4] DDRCLK

SD_
MECC MECC VSS MDQ GVDD VSS MCK MCK GVDD VSS XVSS XVDD AVDD_
AD [5] [0] [24] [1] [1]
TXA_P SDAVSS
SRDS
[0]
SD_ SD_
MDQ MDQ GVDD MDQ MDQ MDQ MDM MDQ VSS NC XVDD XVSS SD_PLL
AE TXA_N TXA_P
[18] [19] [29] [15] [14] [1] [9] [5] _TPD
[0] [1]
SD_
MDQ MDQ MDQ GVDD MDQ MDQS MDQS MDQ MDQ NC XVSS XVSS TXB_N XVDD SD_REF
AF [23] [22] [28] [10] [1] [1] [8] [13] [6]
[1] _CLK
SD_
MDQS MDQS VSS MDQ VSS GVDD VSS GVDD MDQ XVSS SVSS SVSS SVSS SD_REF
AG IMP_CAL
[2] [2] [11] [12] _CLK
_RX
SD_ SD_
MDM MDQ MDQ MDQ MDQ MDQ MDM MDQ MDQ VSS SVSS RXA_P SVDD RXB_P SVSS
AH [2] [17] [16] [20] [2] [6] [0] [1] [5]
[0] [1]
SD_ SD_
VSS GVDD MDQ MDQ MDQ MDQS MDQS MDQ MDQ VSS SVDD SVSS SVDD
AJ [21] [3] [7] [0] [0] [0] [4]
RXA_N RXB_N
[0] [1]

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Figure 5. P2010 Ball Map—Detail C

P2010 QorIQ Integrated Processor Hardware Specifications, Rev. 3

NXP Semiconductors 7
Pinout Assignments and Reset States

DETAIL D

DMA1 DMA1 DMA2

VSS VSS VSS VSS VDD CLK_ VSS
TDI _DDONE _DACK _DACK T
OUT
[0] [0] [0]

VSS VSS VSS VSS VDD HRESET OVDD TRIG GPIO

ASLEEP TMS [4] U
_REQ _OUT

VSS VSS VSS VSS VDD AVDD_ CKSTP VSS

PLAT
TRST TDO TCK V
OUT0

DMA2
VSS VSS VSS VSS VDD NC SCAN_
SRESET HRESET [15] _DREQ SYSCLK W
MODE [0]
TSEC2 DMA1 DMA2
NC VSS VDD VDD VDD LVDD VSS OVDD NC
[4] _TXD [14] _DREQ _DDONE Y
[0] [0] [0]
TSEC2 TSEC2
VSS TSEC2 TEST CKSTP
_TX _TXD MCP0 AA
_TX_EN _SEL IN0
_CLK [2]
TSEC2 TSEC2 TSEC2 TSEC2
TRIG Resv[23]
_TXD _TXD _RXD _RXD AB
_IN
[5] [4] [6] [3]
TSEC2 TSEC2
VSS LVDD VSS LVDD _RXD LVDD VSS _RX AC
[5] _CLK
SD_ TSEC1 TSEC1 TSEC1 TSEC1 TSEC2 TSEC2 TSEC2
SD_PLL EC_ TSEC2 TSEC2
XVDD TXA_P XVSS _RXD _TXD _TXD _TXD _RXD _RXD _RXD AD
_TPA MDC _CRS _RX_DV
[3] [1] [6] [5] [0] [4] [7] [2]
SD_ SD_ TSEC_ TSEC1 TSEC1 TSEC1 TSEC1 TSEC2
XVSS XVDD 1588_ALARM _TXD LVDD TSEC2 TSEC2 TSEC2
TXA_P TXF_N _RXD _RXD _TXD _TXD AE
[2] [3] _COL _RX_ER _TX_ER
_OUT [4] [2] [4] [1] [7]
SD_ SD_ TSEC1 EC_ TSEC2 TSEC2 TSEC2 TSEC2
XVDD XVSS TSEC1
TXE_N IMP_CAL VSS LVDD _TXD GTX_CLK- LVDD _TXD _TXD _RXD _RXD AF
[2] _TX_ER
_TX [7] 125 [6] [1] [0] [1]
TSEC_ TSEC_ TSEC_ TSEC1 TSEC1 TSEC1 TSEC2 TSEC2
SVDD SVSS SVSS SVSS 1588_TRIG 1588_CLK 1588_CLK _RXD VSS _GTX _RX VSS _GTX _TXD AG
_IN[2] _IN _OUT [7] _CLK _CLK _CLK [3]
SD_ SD_ TSEC_ TSEC_ TSEC1 TSEC1 TSEC1
TSEC1 TSEC1 TSEC1
RXE_P SVDD RXF_P SVSS 1588_TRIG1588_PULSE _RXD _RXD LVDD _TXD LVDD AH
_RX_ER _TX_EN _COL
[2] [3] _IN[1] _OUT [6] [0] [2]
SD_ SD_ TSEC_ TSEC_ TSEC1 TSEC1 TSEC1 TSEC1
RXE_N SVSS RXF_N SVDD 1588_ALARM EC_ 1588_PULSE _RXD _TX _TXD
TSEC1 TSEC1
_RXD VSS AJ
MDIO _RX_DV _CRS
[2] [3] _OUT _OUT [5] _CLK [3] [3]

16 17 18 19 20 21 22 23 24 25 26 27 28 29
Figure 6. P2010 Ball Map—Detail D

P2010 QorIQ Integrated Processor Hardware Specifications, Rev. 3

8 NXP Semiconductors
 Pinout Assignments and Reset States

1.2 Pinout List by Bus

Table 1 provides the pinout listing for the device.
Table 1. P2010 Pinout Listing 1

Power
Signal Signal Name Package Pin Number Pin Type Notes
Supply

DDR SDRAM Memory Interface

MDQ00 Data AJ8 IO GVDD —

MDQ01 Data AH8 IO GVDD —

MDQ02 Data AH5 IO GVDD —

MDQ03 Data AJ4 IO GVDD —

MDQ04 Data AJ9 IO GVDD —

MDQ05 Data AH9 IO GVDD —

MDQ06 Data AH6 IO GVDD —

MDQ07 Data AJ5 IO GVDD —

MDQ08 Data AF8 IO GVDD —

MDQ09 Data AE8 IO GVDD —

MDQ10 Data AF5 IO GVDD —

MDQ11 Data AG4 IO GVDD —

MDQ12 Data AG9 IO GVDD —

MDQ13 Data AF9 IO GVDD —

MDQ14 Data AE6 IO GVDD —

MDQ15 Data AE5 IO GVDD —

MDQ16 Data AH3 IO GVDD —

MDQ17 Data AH2 IO GVDD —

MDQ18 Data AE1 IO GVDD —

MDQ19 Data AE2 IO GVDD —

MDQ20 Data AH4 IO GVDD —

MDQ21 Data AJ3 IO GVDD —

MDQ22 Data AF2 IO GVDD —

MDQ23 Data AF1 IO GVDD —

MDQ24 Data AD4 IO GVDD —

MDQ25 Data AC4 IO GVDD —

MDQ26 Data Y5 IO GVDD —

MDQ27 Data W5 IO GVDD —

MDQ28 Data AF3 IO GVDD —

P2010 QorIQ Integrated Processor Hardware Specifications, Rev. 3

NXP Semiconductors 9
Pinout Assignments and Reset States

Table 1. P2010 Pinout Listing (continued)1

Power
Signal Signal Name Package Pin Number Pin Type Notes
Supply

MDQ29 Data AE4 IO GVDD —

MDQ30 Data AB5 IO GVDD —

MDQ31 Data Y4 IO GVDD —

MDQ32 Data G4 IO GVDD —

MDQ33 Data G3 IO GVDD —

MDQ34 Data E2 IO GVDD —

MDQ35 Data E4 IO GVDD —

MDQ36 Data H5 IO GVDD —

MDQ37 Data H4 IO GVDD —

MDQ38 Data F2 IO GVDD —

MDQ39 Data E1 IO GVDD —

MDQ40 Data C1 IO GVDD —

MDQ41 Data C3 IO GVDD —

MDQ42 Data B4 IO GVDD —

MDQ43 Data A4 IO GVDD —

MDQ44 Data D1 IO GVDD —

MDQ45 Data D2 IO GVDD —

MDQ46 Data B3 IO GVDD —

MDQ47 Data A3 IO GVDD —

MDQ48 Data C5 IO GVDD —

MDQ49 Data E6 IO GVDD —

MDQ50 Data D9 IO GVDD —

MDQ51 Data E9 IO GVDD —

MDQ52 Data C4 IO GVDD —

MDQ53 Data E5 IO GVDD —

MDQ54 Data E8 IO GVDD —

MDQ55 Data D8 IO GVDD —

MDQ56 Data A6 IO GVDD —

MDQ57 Data B7 IO GVDD —

MDQ58 Data B10 IO GVDD —

MDQ59 Data A11 IO GVDD —

MDQ60 Data A5 IO GVDD —

P2010 QorIQ Integrated Processor Hardware Specifications, Rev. 3

10 NXP Semiconductors
 Pinout Assignments and Reset States

Table 1. P2010 Pinout Listing (continued)1

Power
Signal Signal Name Package Pin Number Pin Type Notes
Supply

MDQ61 Data B6 IO GVDD —

MDQ62 Data B9 IO GVDD —

MDQ63 Data A10 IO GVDD —

MECC[00] Error Correcting Code AD2 IO GVDD 36

MECC[01] Error Correcting Code AC2 IO GVDD 36

MECC[02] Error Correcting Code W1 IO GVDD 36

MECC[03] Error Correcting Code V3 IO GVDD 36

MECC[04] Error Correcting Code AB2 IO GVDD 36

MECC[05] Error Correcting Code AD1 IO GVDD 36

MECC[06] Error Correcting Code Y1 IO GVDD 36

MECC[07] Error Correcting Code V6 IO GVDD 36

MAPAR_ERR Address Parity Error N5 I GVDD 37

MAPAR_OUT Address Parity Error R5 O GVDD —

MDM[00] Data Mask AH7 O GVDD —

MDM[01] Data Mask AE7 O GVDD —

MDM[02] Data Mask AH1 O GVDD —

MDM[03] Data Mask AC1 O GVDD —

MDM[04] Data Mask G1 O GVDD —

MDM[05] Data Mask C2 O GVDD —

MDM[06] Data Mask F8 O GVDD —

MDM[07] Data Mask A7 O GVDD —

MDM[08] Data Mask AA4 O GVDD —

MDQS[00] Data Strobe AJ6 IO GVDD —

MDQS[01] Data Strobe AF6 IO GVDD —

MDQS[02] Data Strobe AG2 IO GVDD —

MDQS[03] Data Strobe AB3 IO GVDD —

MDQS[04] Data Strobe F3 IO GVDD —

MDQS[05] Data Strobe B2 IO GVDD —

MDQS[06] Data Strobe D7 IO GVDD —

MDQS[07] Data Strobe A9 IO GVDD —

MDQS[08] Data Strobe AA1 IO GVDD —

MDQS[00] Data Strobe AJ7 IO GVDD —

P2010 QorIQ Integrated Processor Hardware Specifications, Rev. 3

NXP Semiconductors 11
Pinout Assignments and Reset States

Table 1. P2010 Pinout Listing (continued)1

Power
Signal Signal Name Package Pin Number Pin Type Notes
Supply

MDQS[01] Data Strobe AF7 IO GVDD —

MDQS[02] Data Strobe AG1 IO GVDD —

MDQS[03] Data Strobe AB4 IO GVDD —

MDQS[04] Data Strobe F4 IO GVDD —

MDQS[05] Data Strobe B1 IO GVDD —

MDQS[06] Data Strobe D6 IO GVDD —

MDQS[07] Data Strobe A8 IO GVDD —

MDQS[08] Data Strobe AB1 IO GVDD —

MBA[00] Bank Select K5 O GVDD —

MBA[01] Bank Select L5 O GVDD —

MBA[02] Bank Select T4 O GVDD —

MA[00] Address L6 O GVDD —

MA[01] Address M2 O GVDD —

MA[02] Address M1 O GVDD —

MA[03] Address M5 O GVDD —

MA[04] Address N1 O GVDD —

MA[05] Address P1 O GVDD —

MA[06] Address N4 O GVDD —

MA[07] Address P3 O GVDD —

MA[08] Address P2 O GVDD —

MA[09] Address R1 O GVDD —

MA[10] Address K6 O GVDD —

MA[11] Address R4 O GVDD —

MA[12] Address T5 O GVDD —

MA[13] Address J5 O GVDD —

MA[14] Address T3 O GVDD —

MA[15] Address U4 O GVDD —

MWE Write Enable K2 O GVDD —

MRAS Row Address Strobe K1 O GVDD —

MCAS Column Address Strobe J3 O GVDD —

MCS[00] Chip Select J2 O GVDD —

MCS[01] Chip Select J6 O GVDD —

P2010 QorIQ Integrated Processor Hardware Specifications, Rev. 3

12 NXP Semiconductors
 Pinout Assignments and Reset States

Table 1. P2010 Pinout Listing (continued)1

Power
Signal Signal Name Package Pin Number Pin Type Notes
Supply

MCS[02] Chip Select J1 O GVDD —

MCS[03] Chip Select G2 O GVDD —

MCKE[00] Clock Enable U5 O GVDD 9

MCKE[01] Clock Enable V1 O GVDD 9

MCKE[02] Clock Enable U6 O GVDD 9

MCKE[03] Clock Enable V2 O GVDD 9

MCK[00] Clock U2 O GVDD 32

MCK[01] Clock AD8 O GVDD 32

MCK[02] Clock D4 O GVDD 32

MCK[03] Clock T2 O GVDD 32

MCK[04] Clock AC6 O GVDD 32

MCK[05] Clock F5 O GVDD 32

MCK[00] Clock Complements U1 O GVDD 32

MCK[01] Clock Complements AD7 O GVDD 32

MCK[02] Clock Complements D5 O GVDD 32

MCK[03] Clock Complements T1 O GVDD 32

MCK[04] Clock Complements AC5 O GVDD 32

MCK[05] Clock Complements F6 O GVDD 32

MODT[00] On Die Termination H1 O GVDD —

MODT[01] On Die Termination H6 O GVDD —

MODT[02] On Die Termination J4 O GVDD —

MODT[03] On Die Termination F1 O GVDD —

MDIC[00] Driver Impedance C10 IO GVDD 18

Calibration

MDIC[01] Driver Impedance F10 IO GVDD 18

Calibration

SerDes

SD_TX[03] Transmit Data (positive) AD18 O XVDD —

SD_TX[02] Transmit Data (positive) AE17 O XVDD —

SD_TX[01] Transmit Data (positive) AE13 O XVDD —

SD_TX[00] Transmit Data (positive) AD12 O XVDD —

SD_TX[03] Transmit Data (negative) AE18 O XVDD —

SD_TX[02] Transmit Data (negative) AF17 O XVDD —

P2010 QorIQ Integrated Processor Hardware Specifications, Rev. 3

NXP Semiconductors 13
Pinout Assignments and Reset States

Table 1. P2010 Pinout Listing (continued)1

Power
Signal Signal Name Package Pin Number Pin Type Notes
Supply

SD_TX[01] Transmit Data (negative) AF13 O XVDD —

SD_TX[00] Transmit Data (negative) AE12 O XVDD —

SD_RX[03] Receive Data (positive) AH18 I XVDD —

SD_RX[02] Receive Data (positive) AH16 I XVDD —

SD_RX[01] Receive Data (positive) AH14 I XVDD —

SD_RX[00] Receive Data (positive) AH12 I XVDD —

SD_RX[03] Receive Data (negative) AJ18 I XVDD —

SD_RX[02] Receive Data (negative) AJ16 I XVDD —

SD_RX[01] Receive Data (negative) AJ14 I XVDD —

SD_RX[00] Receive Data (negative) AJ12 I XVDD —

SD_REF_CLK PLL Reference Clock AG15 I XVDD —

SD_REF_CLK PLL Reference Clock AF15 I XVDD —

Complement

Enhanced Local Bus Controller Interface

LAD[00] Muxed Data/Address B18 IO BVDD 4, 23

LAD[01] Muxed Data/Address E20 IO BVDD 4, 23

LAD[02] Muxed Data/Address A19 IO BVDD 4, 23

LAD[03] Muxed Data/Address B20 IO BVDD 4, 23

LAD[04] Muxed Data/Address D19 IO BVDD 4, 23

LAD[05] Muxed Data/Address A18 IO BVDD 4, 23

LAD[06] Muxed Data/Address B17 IO BVDD 4, 23

LAD[07] Muxed Data/Address C20 IO BVDD 4, 23

LAD[08] Muxed Data/Address F19 IO BVDD 4, 23

LAD[09] Muxed Data/Address E10 IO BVDD 4, 23

LAD[10] Muxed Data/Address B16 IO BVDD 4, 23

LAD[11] Muxed Data/Address D14 IO BVDD 4, 23

LAD[12] Muxed Data/Address D17 IO BVDD 4, 23

LAD[13] Muxed Data/Address E11 IO BVDD 4, 23

LAD[14] Muxed Data/Address A16 IO BVDD 4, 23

LAD[15] Muxed Data/Address C15 IO BVDD 4, 23

LDP[00] Data Parity E18 IO BVDD —

LDP[01] Data Parity B19 IO BVDD —

P2010 QorIQ Integrated Processor Hardware Specifications, Rev. 3

14 NXP Semiconductors
 Pinout Assignments and Reset States

Table 1. P2010 Pinout Listing (continued)1

Power
Signal Signal Name Package Pin Number Pin Type Notes
Supply

LA[16] Address B21 O BVDD 7

LA[17] Address A22 O BVDD 15

LA[18] Address C21 O BVDD 4,7

LA[19] Address F21 O BVDD 4,7

LA[20] Address E12 O BVDD 4,7,21

LA[21] Address A21 O BVDD 4,7,21

LA[22] Address D11 O BVDD 4,7,21

LA[23] Address E22 O BVDD 4,7

LA[24] Address F20 O BVDD 4,7

LA[25] Address E21 O BVDD 7

LA[26] Address B22 O BVDD 4,7

LA[27] Address F18 O BVDD 7,25

LA[28] Address A23 O BVDD 4,7

LA[29] Address B23 O BVDD 5,7

LA[30] Address C23 O BVDD 5,7

LA[31] Address D23 O BVDD 5,7

LCS[00] Chip Selects D20 O BVDD 8

LCS[01] Chip Selects A12 O BVDD 8

LCS[02] Chip Selects E19 O BVDD 8

LCS[03] Chip Selects D21 O BVDD 8

LCS[04] Chip Selects F11 O BVDD 8

LCS[05]/DMA2_DREQ[01] Chip Selects D15 O BVDD 8

LCS[06]/DMA2_DACK[01] Chip Selects D13 O BVDD 8

LCS[07]/DMA2_DDONE[01] Chip Selects A17 O BVDD 8

LWE[00]/LBS[00] Write Enable F12 O BVDD 7

LWE[01]/LBS[01] Write Enable D12 O BVDD 4, 7

LBCTL Buffer Control E17 O BVDD 6

LALE Address Latch Enable C17 O BVDD 6

LGPL[00]/LFCLE UPM General Purpose Line B12 O BVDD 4

0/Flash Command Latch
Enable

LGPL[01]/LFALE UPM General Purpose Line C13 O BVDD 4

1/Flash Addr Latch Enable

P2010 QorIQ Integrated Processor Hardware Specifications, Rev. 3

NXP Semiconductors 15
Pinout Assignments and Reset States

Table 1. P2010 Pinout Listing (continued)1

Power
Signal Signal Name Package Pin Number Pin Type Notes
Supply

LGPL[02]/LOE/LFRE UPM General Purpose Line A20 O BVDD 6

2/Output Enable/ Flash
Read Enable

LGPL[03]/LFWP UPM General Purpose Line D10 O BVDD 4

3/Flash Write Protect

LGPL[04]/LGTA/LFRB/ UPM General Purpose Line B13 O BVDD 34

LUPWAIT/LPBSE 4/Txn Termination/
Wait/Flash Ready-Busy

LGPL[05] UPM General Purpose Line C19 O BVDD 4

5/Addr mux
LCLK[00] Local Bus Clock B15 O BVDD —

LCLK[01] Local Bus Clock A15 O BVDD —

LSYNC_IN Local Bus DLL A13 I BVDD —

Synchronization

LSYNC_OUT Local Bus DLL A14 O BVDD —

Synchronization

DMA

DMA1_DREQ DMA1 Channel 0 Request Y28 I OVDD —

DMA2_DREQ DMA2 Channel 0 Request W28 I OVDD —

DMA1_DACK DMA1 Channel 0 T28 O OVDD 15

Acknowledge

DMA2_DACK DMA2 Channel 0 T29 O OVDD 4, 7

Acknowledge

DMA1_DDONE DMA1 Channel 0 Done T26 O OVDD 7,21

DMA2_DDONE DMA2 Channel 0 Done Y29 O OVDD 4, 7

Programmable Interrupt Controller

UDE0 Unconditional Debug Event J27 I OVDD —

Proc 0

MCP0 Machine Check Processor 0 AA27 I OVDD —

IRQ[00] External Interrupts L24 I OVDD —

IRQ[01] External Interrupts K26 I OVDD —

IRQ[02] External Interrupts K29 I OVDD —

IRQ[03] External Interrupts N25 I OVDD —

IRQ[04] External Interrupts L26 I OVDD —

IRQ[05] External Interrupts L29 I OVDD —

IRQ[06] External Interrupts K27 I OVDD —

P2010 QorIQ Integrated Processor Hardware Specifications, Rev. 3

16 NXP Semiconductors
 Pinout Assignments and Reset States

Table 1. P2010 Pinout Listing (continued)1

Power
Signal Signal Name Package Pin Number Pin Type Notes
Supply

IRQ_OUT Interrupt Output N29 O OVDD 2, 3

Voltage Select

LVDD_VSEL Voltage Select M28 I OVDD 22

BVDD_VSEL[00] Voltage Select M29 I OVDD 22

BVDD_VSEL[01] Voltage Select M27 I OVDD 22

CVDD_VSEL[00] Voltage Select L28 I OVDD 22

CVDD_VSEL[01] Voltage Select L27 I OVDD 22

1588

TSEC_1588_CLK_IN Clock In AG21 I LVDD —

TSEC_1588_TRIG_IN1 Trigger In 1 AH20 I LVDD —

TSEC_1588_TRIG_IN2 Trigger In 2 AG20 I LVDD —

TSEC_1588_ALARM_OUT01 Trigger Out 1 AE20 O LVDD 4, 7

TSEC_1588_ALARM_OUT02 Trigger Out 2 AJ20 O LVDD 4, 7

TSEC_1588_CLK_OUT Clock Out AG22 O LVDD 24

TSEC_1588_PULSE_OUT[01] Pulse Out 1 AH21 O LVDD 24

TSEC_1588_PULSE_OUT[02] Pulse Out 2 AJ22 O LVDD 24

Ethernet Management Interface

EC_MDC Management Data Clock AD20 O LVDD 4, 7

EC_MDIO Management Data In/Out AJ21 IO LVDD —

Gigabit Ethernet Reference Clock

EC_GTX_CLK125 Reference Clock AF24 I LVDD 20

Three Speed Ethernet Controller 1

TSEC1_TXD[07]/ Transmit Data AF22 O LVDD 4, 7

TSEC3_TXD[03]
TSEC1_TXD[06]/ Transmit Data AD22 O LVDD 4, 7
TSEC3_TXD[02]
TSEC1_TXD[05]/ Transmit Data AD23 O LVDD 4, 7
TSEC3_TXD[01]

TSEC1_TXD[04]/ Transmit Data AE21 O LVDD 4, 7

TSEC3_TXD[00]

TSEC1_TXD[03] Transmit Data AJ25 O LVDD 4, 7

TSEC1_TXD[02] Transmit Data AH28 O LVDD 4, 7

TSEC1_TXD[01] Transmit Data AE25 O LVDD 4, 7

P2010 QorIQ Integrated Processor Hardware Specifications, Rev. 3

NXP Semiconductors 17
Pinout Assignments and Reset States

Table 1. P2010 Pinout Listing (continued)1

Power
Signal Signal Name Package Pin Number Pin Type Notes
Supply

TSEC1_TXD[00] Transmit Data AD24 O LVDD 4, 7

TSEC1_TX_EN Transmit Enable AH24 O LVDD 16

TSEC1_TX_ER Transmit Error AF23 O LVDD 4,7

TSEC1_TX_CLK Transmit Clock AJ24 I LVDD —

TSEC1_GTX_CLK Transmit Clock Out AG25 O LVDD —

TSEC1_CRS/TSEC3_RX_DV Carrier Sense AJ27 IO LVDD —

TSEC1_COL/TSEC3_RX_CLK Collision Detect AH26 I LVDD —

TSEC1_RXD[07]/ Receive Data AG23 I LVDD —

TSEC3_RXD[03]

TSEC1_RXD[06]/ Receive Data AH22 I LVDD —

TSEC3_RXD[02]

TSEC1_RXD[05]/ Receive Data AJ23 I LVDD —

TSEC3_RXD[01]
TSEC1_RXD[04]/ Receive Data AE24 I LVDD —
TSEC3_RXD[00]

TSEC1_RXD[03] Receive Data AJ28 I LVDD —

TSEC1_RXD[02] Receive Data AE22 I LVDD —

TSEC1_RXD[01] Receive Data AD21 I LVDD —

TSEC1_RXD[00] Receive Data AH25 I LVDD —

TSEC1_RX_DV Receive Data Valid AJ26 I LVDD —

TSEC1_RX_ER Receive Error AH23 I LVDD —

TSEC1_RX_CLK Receive Clock AG26 I LVDD —

Three Speed Ethernet Controller 2

TSEC2_TXD[07] Transmit Data AE26 O LVDD 4,7

TSEC2_TXD[06] Transmit Data AF26 O LVDD 15

TSEC2_TXD[05]/ Transmit Data AB24 O LVDD 4,7,

TSEC3_TX_EN 16

TSEC2_TXD[04]/ Transmit Data AB25 O LVDD 4,7

TSEC3_GTX_CLK

TSEC2_TXD[03] Transmit Data AG29 O LVDD 4,7

TSEC2_TXD[02] Transmit Data AA25 O LVDD 4,7

TSEC2_TXD[01] Transmit Data AF27 O LVDD 4,7

17

TSEC2_TXD[00] Transmit Data Y24 O LVDD 4,7

TSEC2_TX_EN Transmit Enable AA26 O LVDD 16

P2010 QorIQ Integrated Processor Hardware Specifications, Rev. 3

18 NXP Semiconductors
 Pinout Assignments and Reset States

Table 1. P2010 Pinout Listing (continued)1

Power
Signal Signal Name Package Pin Number Pin Type Notes
Supply

TSEC2_TX_ER Transmit Error AE29 O LVDD 4,7

TSEC2_TX_CLK Transmit Clock In AA24 I LVDD —

TSEC2_GTX_CLK Transmit Clock Out AG28 O LVDD —

TSEC2_CRS/TSEC3_RX_ER Carrier Sense AD25 IO LVDD —

TSEC2_COL/TSEC3_TX_CLK Collision Detect AE27 I LVDD —

TSEC2_RXD[07] Receive Data AD27 I LVDD —

TSEC2_RXD[06] Receive Data AB26 I LVDD —

TSEC2_RXD[05] Receive Data AC26 I LVDD —

TSEC2_RXD[04] Receive Data AD26 I LVDD —

TSEC2_RXD[03] Receive Data AB27 I LVDD —

TSEC2_RXD[02] Receive Data AD28 I LVDD —

TSEC2_RXD[01] Receive Data AF29 I LVDD —

TSEC2_RXD[00] Receive Data AF28 I LVDD —

TSEC2_RX_DV Receive Data Valid AD29 I LVDD —

TSEC2_RX_ER Receive Error AE28 I LVDD —

TSEC2_RX_CLK Transmit Clock In AC29 I LVDD —

DUART

UART0_SOUT Transmit Data J26 O OVDD 21

UART1_SOUT Transmit Data J25 O OVDD —

UART0_SIN Receive Data H29 I OVDD —

UART1_SIN Receive Data G24 I OVDD —

UART0_CTS Clear to Send J28 I OVDD —

UART1_CTS Clear to Send H24 I OVDD —

UART0_RTS Ready to Send J29 O OVDD 4

UART1_RTS Ready to Send J24 O OVDD 4

I2C

IIC1_SDA Serial Data H28 IO OVDD 3,14

IIC1_SCL Serial Clock G27 IO OVDD 3,14

IIC2_SDA Serial Data H26 IO OVDD 3,14

IIC2_SCL Serial Clock H25 IO OVDD 3,14

eSDHC

P2010 QorIQ Integrated Processor Hardware Specifications, Rev. 3

NXP Semiconductors 19
Pinout Assignments and Reset States

Table 1. P2010 Pinout Listing (continued)1

Power
Signal Signal Name Package Pin Number Pin Type Notes
Supply

SDHC_DATA[00] Data G28 IO CVDD —

SDHC_DATA[01] Data F27 IO CVDD —

SDHC_DATA[02] Data G25 IO CVDD —

SDHC_DATA[03] Data G26 IO CVDD —

SDHC_CMD Command/Response F26 IO CVDD —

SDHC_CLK Host to Card Clock G29 IO CVDD —

eSPI

SPI_MISO Master In Slave Out F28 I CVDD —

SPI_MOSI Master Out Slave In F25 IO CVDD —

SPI_CS[00]/SDHC_DATA[04] eSPI chip select D28 IO CVDD —

SPI_CS[01]/SDHC_DATA[05] eSPI chip select E26 IO CVDD —

SPI_CS[02]/SDHC_DATA[06] eSPI chip select F29 IO CVDD —

SPI_CS[03]/SDHC_DATA[07] eSPI chip select E29 IO CVDD —

SPI_CLK eSPI clock D29 O CVDD —

USB

USB_NXT USB Next data B26 I CVDD —

USB_DIR USB Data Direction A28 I CVDD —

USB_STP USB Stop B29 O CVDD 15

USB_PWRFAULT Power Fault C29 I CVDD —

USB_CLK USB Bus Clock D27 I CVDD —

USB_D[07] USB Data Bits C28 I/O CVDD —

USB_D[06] USB Data Bits C25 I/O CVDD —

USB_D[05] USB Data Bits B28 I/O CVDD —

USB_D[04] USB Data Bits B25 I/O CVDD —

USB_D[03] USB Data Bits D26 I/O CVDD —

USB_D[02] USB Data Bits A27 I/O CVDD —

USB_D[01] USB Data Bits A26 I/O CVDD —

USB_D[00] USB Data Bits C26 I/O CVDD —

General-Purpose Input/Output

GPIO[00]/IRQ[07] General-Purpose Input/ R28 IO OVDD —

Output

P2010 QorIQ Integrated Processor Hardware Specifications, Rev. 3

20 NXP Semiconductors
 Pinout Assignments and Reset States

Table 1. P2010 Pinout Listing (continued)1

Power
Signal Signal Name Package Pin Number Pin Type Notes
Supply

GPIO[01]/IRQ[08] General-Purpose Input/ R26 IO OVDD —

Output

GPIO[02]/IRQ[09] General-Purpose Input/ P29 IO OVDD —

Output

GPIO[03]/IRQ[10] General-Purpose Input/ N24 IO OVDD —

Output
GPIO[04]/IRQ[11] General-Purpose Input/ U29 IO OVDD —
Output

GPIO[05] General-Purpose Input/ R24 IO OVDD —

Output

GPIO[06] General-Purpose Input/ R29 IO OVDD —

Output
GPIO[07] General-Purpose Input/ R25 IO OVDD —
Output

GPIO[08]/SDHC_CD General-Purpose Input/ F22 IO BVDD 31

Output

GPIO[09]/SDHC_WP General-Purpose Input/ A24 IO BVDD —

Output
GPIO[10]/USB_PCTL0 General-Purpose Input/ A25 IO BVDD —
Output

GPIO[11]/USB_PCTL1 General-Purpose Input/ D24 IO BVDD —

Output

GPIO[12] General-Purpose Input/ F23 IO BVDD —

Output
GPIO[13] General-Purpose Input/ E23 IO BVDD —
Output

GPIO[14] General-Purpose Input/ F24 IO BVDD —

Output

GPIO[15] General-Purpose Input/ E24 IO BVDD —

Output

System Control

HRESET Hard Reset W25 I OVDD —

HRESET_REQ Reset Request U24 O OVDD 15

SRESET Soft Reset W24 I OVDD —

CKSTP_IN0 Checkstop In AA29 I OVDD 2

CKSTP_OUT[00] Checkstop Out V25 O OVDD 2, 3

Debug

P2010 QorIQ Integrated Processor Hardware Specifications, Rev. 3

NXP Semiconductors 21
Pinout Assignments and Reset States

Table 1. P2010 Pinout Listing (continued)1

Power
Signal Signal Name Package Pin Number Pin Type Notes
Supply

TRIG_IN Trigger In AB28 I OVDD —

TRIG_OUT Trigger Out U28 O OVDD 7

MSRCID[00] Debug Source ID 0 P28 O OVDD 4

MSRCID[01] Debug Source ID 1 R27 O OVDD 21

MSRCID[02] Debug Source ID 2 P27 O OVDD 15

MSRCID[03] Debug Source ID 3 P26 O OVDD 15

MSRCID[04] Debug Source ID 4 N26 O OVDD 21

MDVAL Debug Data Valid M24 O OVDD 15

Clocks

CLK_OUT Clock Out T24 O OVDD —

RTC Real Time Clock K24 I OVDD —

DDRCLK DDR Clock AC9 I OVDD 19

SYSCLK System Clock W29 I OVDD —

DFT

SCAN_MODE Scan Mode W27 I OVDD 33

TEST_SEL Test Select AA28 I OVDD 30

JTAG

TCK Test Clock V29 I OVDD —

TDI Test Data In T25 I OVDD 10

TDO Test Data Out V28 O OVDD 9

TMS Test Mode Select U26 I OVDD 10

TRST Test Reset V26 I OVDD 10

Power Management

ASLEEP Asleep U25 O OVDD 7, 11,

15

No Connect

NC1 No Connection AE10 NC OVDD —

NC2 No Connection AF10 NC OVDD —

NC3 No Connection E13 NC OVDD —

NC4 No Connection E14 NC OVDD —

NC5 No Connection W6 NC OVDD —

P2010 QorIQ Integrated Processor Hardware Specifications, Rev. 3

22 NXP Semiconductors
 Pinout Assignments and Reset States

Table 1. P2010 Pinout Listing (continued)1

Power
Signal Signal Name Package Pin Number Pin Type Notes
Supply

NC6 No Connection Y14 NC OVDD —

NC7 No Connection Y15 NC OVDD —

NC8 No Connection Y16 NC OVDD —

NC9 No Connection G6 NC OVDD —

NC12 No Connection F13 NC — —

NC13 No Connection P6 NC — —

NC14 No Connection Y27 NC — —

NC15 No Connection W26 NC — —

Reserve

Reserve23 Reserved AB29 Pull up OVDD —

4.7K

Reserve24 Reserved M25 Pull up OVDD —

4.7K

Reserve25 Reserved K28 Pull up OVDD —

4.7K

Reserve26 Reserved F16 Pull up VDD —

4.7K

Power and Ground Signals

AGND_SRDS SerDes PLL GND AD15 — — —

AVDD_CORE0 Core PLL0 Supply F15 — AVDD_core0 13, 26

AVDD_DDR DDR PLL Supply Y10 — AVDD_DDR 13

AVDD_LBIU Local Bus PLL Supply F14 — AVDD_LBIU 13

AVDD_PLAT Platform PLL Supply V24 — AVDD_PLAT 13

AVDD_SRDS SerDes PLL Supply AD14 — AVDD_SRDS 13

BVDD Local Bus, GPIO Supply B24 — BVDD —

BVDD Local Bus, GPIO Supply C12 — BVDD —

BVDD Local Bus, GPIO Supply C14 — BVDD —

BVDD Local Bus, GPIO Supply C16 — BVDD —

BVDD Local Bus, GPIO Supply C22 — BVDD —

BVDD Local Bus, GPIO Supply D18 — BVDD —

BVDD Local Bus, GPIO Supply G20 — BVDD —

CVDD SPI, eSDHC, USB Supply C27 — CVDD —

CVDD SPI, eSDHC, USB Supply E25 — CVDD —

P2010 QorIQ Integrated Processor Hardware Specifications, Rev. 3

NXP Semiconductors 23
Pinout Assignments and Reset States

Table 1. P2010 Pinout Listing (continued)1

Power
Signal Signal Name Package Pin Number Pin Type Notes
Supply

CVDD SPI, eSDHC, USB Supply E27 — CVDD —

GVDD DDR Supply A2 — GVDD —

GVDD DDR Supply B8 — GVDD —

GVDD DDR Supply B11 — GVDD —

GVDD DDR Supply C7 — GVDD —

GVDD DDR Supply C9 — GVDD —

GVDD DDR Supply D3 — GVDD —

GVDD DDR Supply E7 — GVDD —

GVDD DDR Supply F9 — GVDD —

GVDD DDR Supply G10 — GVDD —

GVDD DDR Supply H2 — GVDD —

GVDD DDR Supply K3 — GVDD —

GVDD DDR Supply K7 — GVDD —

GVDD DDR Supply L2 — GVDD —

GVDD DDR Supply L3 — GVDD —

GVDD DDR Supply L4 — GVDD —

GVDD DDR Supply N3 — GVDD —

GVDD DDR Supply N6 — GVDD —

GVDD DDR Supply P4 — GVDD —

GVDD DDR Supply R2 — GVDD —

GVDD DDR Supply U3 — GVDD —

GVDD DDR Supply V5 — GVDD —

GVDD DDR Supply W3 — GVDD —

GVDD DDR Supply Y2 — GVDD —

GVDD DDR Supply AA2 — GVDD —

GVDD DDR Supply AA3 — GVDD —

GVDD DDR Supply AA5 — GVDD —

GVDD DDR Supply AA7 — GVDD —

GVDD DDR Supply AB6 — GVDD —

GVDD DDR Supply AD5 — GVDD —

GVDD DDR Supply AD9 — GVDD —

GVDD DDR Supply AE3 — GVDD —

P2010 QorIQ Integrated Processor Hardware Specifications, Rev. 3

24 NXP Semiconductors
 Pinout Assignments and Reset States

Table 1. P2010 Pinout Listing (continued)1

Power
Signal Signal Name Package Pin Number Pin Type Notes
Supply

GVDD DDR Supply AF4 — GVDD —

GVDD DDR Supply AG6 — GVDD —

GVDD DDR Supply AG8 — GVDD —

GVDD DDR Supply AJ2 — GVDD —

LVDD TSEC I/O Supply Y23 — LVDD —

LVDD TSEC I/O Supply AC21 — LVDD —

LVDD TSEC I/O Supply AC25 — LVDD —

LVDD TSEC I/O Supply AC27 — LVDD —

LVDD TSEC I/O Supply AE23 — LVDD —

LVDD TSEC I/O Supply AF21 — LVDD —

LVDD TSEC I/O Supply AF25 — LVDD —

LVDD TSEC I/O Supply AH27 — LVDD —

LVDD TSEC I/O Supply AH29 — LVDD —

SVDD_SRDS SerDes Core Logic Supply AG16 — SVDD_SRDS —

SVDD_SRDS SerDes Core Logic Supply AH13 — SVDD_SRDS —

SVDD_SRDS SerDes Core Logic Supply AH17 — SVDD_SRDS —

SVDD_SRDS SerDes Core Logic Supply AJ11 — SVDD_SRDS —

SVDD_SRDS SerDes Core Logic Supply AJ15 — SVDD_SRDS —

SVDD_SRDS SerDes Core Logic Supply AJ19 — SVDD_SRDS —

SGND_SRDS SerDes Core Logic GND AG12 — — —

SGND_SRDS SerDes Core Logic GND AG13 — — —

SGND_SRDS SerDes Core Logic GND AG14 — — —

SGND_SRDS SerDes Core Logic GND AG17 — — —

SGND_SRDS SerDes Core Logic GND AG18 — — —

SGND_SRDS SerDes Core Logic GND AG19 — — —

SGND_SRDS SerDes Core Logic GND AH11 — — —

SGND_SRDS SerDes Core Logic GND AH15 — — —

SGND_SRDS SerDes Core Logic GND AH19 — — —

SGND_SRDS SerDes Core Logic GND AJ13 — — —

SGND_SRDS SerDes Core Logic GND AJ17 — — —

XVDD_SRDS SerDes Transceiver Supply AD13 — XVDD_SRDS —

XVDD_SRDS SerDes Transceiver Supply AD17 — XVDD_SRDS —

P2010 QorIQ Integrated Processor Hardware Specifications, Rev. 3

NXP Semiconductors 25
Pinout Assignments and Reset States

Table 1. P2010 Pinout Listing (continued)1

Power
Signal Signal Name Package Pin Number Pin Type Notes
Supply

XVDD_SRDS SerDes Transceiver Supply AE11 — XVDD_SRDS —

XVDD_SRDS SerDes Transceiver Supply AE19 — XVDD_SRDS —

XVDD_SRDS SerDes Transceiver Supply AF14 — XVDD_SRDS —

XVDD_SRDS SerDes Transceiver Supply AF16 — XVDD_SRDS —

XGND_SRDS SerDes Transceiver GND AD11 — — —

XGND_SRDS SerDes Transceiver GND AD19 — — —

XGND_SRDS SerDes Transceiver GND AE14 — — —

XGND_SRDS SerDes Transceiver GND AE16 — — —

XGND_SRDS SerDes Transceiver GND AF11 — — —

XGND_SRDS SerDes Transceiver GND AF12 — — —

XGND_SRDS SerDes Transceiver GND AF18 — — —

XGND_SRDS SerDes Transceiver GND AG10 — — —

OVDD General I/O Supply K23 — — —

OVDD General I/O Supply L25 — — —

OVDD General I/O Supply N27 — — —

OVDD General I/O Supply P25 — — —

OVDD General I/O Supply U27 — — —

OVDD General I/O Supply Y26 — — —

VDD Core Supply K11, K13, K15, K17, K19, L10, — — —

K10, K12, K14, K16, L20, K18,
K20, N10, N20, M10, M20,
R10, R20, P10, P20, U10,
U20, T10, T20, W10, V10,
V20, W20, Y11,Y12, Y19, Y18,
Y20

P2010 QorIQ Integrated Processor Hardware Specifications, Rev. 3

26 NXP Semiconductors
 Pinout Assignments and Reset States

Table 1. P2010 Pinout Listing (continued)1

Power
Signal Signal Name Package Pin Number Pin Type Notes
Supply

GND Ground A1, A29, B5, B14, B27, C6, — — —

C8, C11, C18, C24, D16, D22,
D25, E3, E28, F7, G5, G9,
G21, H3, H27, J7, J23,
K4,F17, L12,L14, L16, L18,
M11, K25, L1, L11, L13, L15,
L17, L19, M3, M4, M6, M19,
M12, M13, M14, M15, M16,
M17, M18, P11, M26, N2, N11,
N12, N13, N14, N15, N16,
N17, N18, N19, N28, P5, P19,
P12, P13, P14, P15, P16, P17,
P18, T11, P24, R3, R11, R12,
R13, R14, R15, R16, R17,
R18, R19, T6, T19, T12, T13,
T14, T15, T16, T17, T18, V11,
T27, U11, U12, U13, U14,
U15, U16, U17, U18, U19, V4,
V19, V12, V13, V14, V15, V16,
V17, V18, W12, V27, W2, W4,
W11, W13, W14, W15, W16,
W17, W19, Y3, Y6, Y7, W18,
Y13, Y17, Y25, AA6, AA23,
AC3, AC10, AC20, AC24,
AC28, AD3, AD6, AE9, AF20,
AG3, AG5, AG7, AG24, AG27,
AJ1, AJ29, AH10, AJ10, AD10

Analog

SD_IMP_CAL_RX SerDes Rx Impedance AG11 I XVDD 27

Calibration
SD_IMP_CAL_TX SerDes Tx Impedance AF19 I XVDD 27
Calibration
SD_PLL_TPA SerDes PLL Test Point AD16 O XVDD 12
Analog
SD_PLL_TPD SerDes PLL Test Point AE15 O XVDD 12
Digital
MVREF SSTL_1.5/1.8 Reference R6 — GVDD ÷ 2 —
Voltage
Temp_Anode Temp_Anode E16 I Internal 35
Diode

Temp_Cathode Temp_Cathode E15 O Internal 35

Diode

P2010 QorIQ Integrated Processor Hardware Specifications, Rev. 3

NXP Semiconductors 27
Pinout Assignments and Reset States

Table 1. P2010 Pinout Listing (continued)1

Power
Signal Signal Name Package Pin Number Pin Type Notes
Supply

Note:
1. All multiplexed signals are listed only once and do not reoccur.
2. It is recommended that a weak pull-up resistor (2–10 KΩ) be placed on this pin to OVDD.
3. Open drain signal. GPIO pins may be programmed to operate as open-drain outputs.
4. This pin is a reset configuration pin. It has a weak internal pull-up P-FET which is enabled only when the processor is in the
reset state. This pull-up is designed such that it can be overpowered by an external 4.7-kΩ pull-down resistor. If the signal is
intended to be high after reset and if there is any device on the net which might pull down the value of the net at reset, a pullup
or active driver is needed.
5. The value of LA[29:31] during reset sets the CCB clock to SYSCLK PLL ratio. These pins require 4.7-kΩ pull-up or pull-down
resistors.
6. The value of LALE, LGPL[02], LBCTL at reset set the e500 core0 clocks to CCB Clock PLL ratios. These pins require 4.7-kΩ
pull-up or pull-down resistors.
7. Functionally, this pin is an output, but structurally it is an I/O because it either samples configuration input during reset or
because it has other manufacturing test functions. This pin is therefore described as an I/O for boundary scan.
8. If this pin is configured for local bus controller use, pull up with 2–10 KΩ resistor to BVDD to ensure there is no random chip
select assertion due to possible noise or other causes.
9. This output is actively driven during reset rather than being three-stated during reset.
10. These JTAG pins have weak internal pull-up P-FETs that are always enabled.
11. If this pin is connected to a device that pulls down during reset, an external pull-up is required to drive this pin to a high state
during reset.
12. Do not connect.
13. Independent supply derived from board VDD.
14. It is recommended that a pull-up resistor (~1 kΩ) be placed on this pin to OVDD.
15. The following pins must NOT be pulled down during power-on reset: DMA1_DACK[00], LA[17], USB_STP, TSEC2_TXD[06],
HRESET_REQ, MSRCID[2:3], MDVAL, ASLEEP.
16. TSEC2_TXD[05] is a POR configuration pin for eSDHC card-detect (cfg_sdhc_cd_pol_sel), and it also has an alternate
function of TSEC3_TX_EN. When eTSEC1 or eTSEC2 or eTSEC3 are used as parallel interfaces, the TSECx_TX_EN pins
require an external 4.7-k pull-down resistor to prevent PHY from seeing a valid Transmit Enable before it is actively driven.
However, the pull-down resistor on TSEC3_TX_EN causes the eSDHC card-detect (cfg_sdhc_cd_sel) to be inverted; the
inversion should be overridden from the SDHCDCR[CD_INV] debug control register. If the device is configured to boot from
the eSDHC interface, the SDHC_CD should be inverted on the board.
17. TSEC2_TXD[01] is used as cfg_dram_type. It must be valid at power up.
18. For DDR2 MDIC[00] is grounded through an 18.2-Ω (full-strength mode) or 36.4-Ω (half-strength mode) precision 1% resistor
and MDIC[01] is connected to GVDD through an 18.2-Ω (full-strength mode) or 36.4-Ω (half-strength mode) precision 1%
resistor. These pins are used for automatic calibration of the DDR IOs. The calibration resistor value for DDR3 must be 20-Ω
(full-strength mode), or 40.2-Ω (half-strength mode).

P2010 QorIQ Integrated Processor Hardware Specifications, Rev. 3

28 NXP Semiconductors
 Electrical Characteristics

Table 1. P2010 Pinout Listing (continued)1

Power
Signal Signal Name Package Pin Number Pin Type Notes
Supply

19. DDRCLK input is only required when the P2010 DDR controller is running in asynchronous mode. See Section 4.2.2, “Clock
Signals”, Section 4.4.3.2, “DDR PLL Ratio” and Table 4-10, “DDR Complex Clock PLL Ratio,” in the P2020 QorIQ Integrated
Communications Host Processor Family Reference Manual
20. EC_GTX_CLK125 is a 125-MHz input clock shared among all eTSEC ports in the following modes: GMII, TBI, RGMII and
RTBI. If none of the eTSEC ports is operating in these modes, the EC_GTX_CLK125 input can be tied off to GND. The
EC_GTX_CLK125 signal high level is nominally LVDD.
21. These POR configuration inputs may be used in the future to control functionality. It is advised that boards are built with the
ability to pulldown these pins.LA[20:22], UART_SOUT[00], MSRCID[01], MSRCID[04], and DMA1_DDONE[00] are reserved
for future reset configuration.
22. Incorrect settings can lead to irreversible device damage.
23. The value of LAD[0:15] during reset sets the upper 16 bits of the GPPORCR as a user option setting.
24. Used to set the DDR clock PLL settings; requires a 4.7-kΩ pull-up or pull-down resistor.
25. Used to determine CPU boot configuration; requires a 4.7-kΩ pull-up or pull-down resistor.
26. Pin must be the same voltage as VDD.
27. SD_IMP_CAL_RX is grounded through an 200-Ω precision ±1% resistor and SD_IMP_CAL_TX is grounded through an
100-Ω precision ±1% resistor.
30. Requires a pull down with 100~1K to GND
31. 100K pull down needed if this signal is used as a CD pin for SD cards. The pull down is not needed for MMC cards.
32. All unused MCK pins must be disabled via DDRCLKDR register.
33. This pin requires a 1 kΩ pull up to OVDD.
34. For systems that boot from local bus (GPCM)-controlled NOR flash or (FCM)-controlled NAND flash, a pullup on LGPL4 is
required.
35. These pins may be connected to a thermal diode monitoring device such as the ADT7461A. If a thermal diode monitoring
device is not connected, these pins may be connected to test point or left as a no connect.
36. This pin, if not used, must be pulled high or low via individual 2–10 kΩ resistor.
37. This pin must be pulled high or low via a 2–10 kΩ resistor.

2 Electrical Characteristics
This section provides the AC and DC electrical specifications for the device. The device is currently targeted to these
specifications. Some of these specifications are independent of the I/O cell, but are included for a more complete reference.
These are not purely I/O buffer design specifications.

2.1 Overall DC Electrical Characteristics

This section covers the DC ratings, conditions, and other characteristics.

P2010 QorIQ Integrated Processor Hardware Specifications, Rev. 3

NXP Semiconductors 29
Electrical Characteristics

2.1.1 Absolute Maximum Ratings

Table 2 provides the absolute maximum ratings.
Table 2. Absolute Maximum Ratings1

Parameter Symbol Max Value Unit Notes

Core and platform supply voltage VDD –0.3 to 1.1 V —

PLL supply voltage AVDD_CORE0 –0.3 to 1.1 V 2

AVDD_DDR,
AVDD_LBIU,
AVDD_PLAT,
AVDD_SRDS

Core power supply for SerDes transceivers SVDD_SRDS –0.3 to 1.1 V —

Pad power supply for SerDes transceivers XVDD_SRDS –0.3 to 1.1 V —

DDR2/3 DRAM I/O voltage GVDD –0.3 to 1.98 V —

–0.3 to 1.65

Three-speed Ethernet I/O, MII management voltage LVDD(eTSEC) –0.3 to 3.63 V —

–0.3 to 2.75

DUART, system control and power management, I2C, GPIOx8, OVDD –0.3 to 3.63 V 3
and JTAG I/O voltage

USB, eSPI, eSDHC CVDD –0.3 to 3.63 V 3

–0.3 to 2.75
–0.3 to 1.98

Enhanced local bus I/O voltage and GPIOx8 voltage BVDD –0.3 to 3.63 V 3
–0.3 to 2.75
–0.3 to 1.98

Input voltage DDR2/DDR3 DRAM signals MVIN –0.3 to (GVDD + 0.3) V 3

DDR2/DDR3 DRAM reference MVREF –0.3 to (GVDD/2 + 0.3) V 3

Three-speed Ethernet signals LVIN –0.3 to (LVDD + 0.3) V 3, 4

Enhanced local bus signals BVIN –0.3 to (BVDD + 0.3) V —

DUART, SYSCLK, system control and power OVIN –0.3 to (OVDD + 0.3) V 3
management, I2C, and JTAG signals

SerDes XVIN –0.3 to (XVDD + 0.3) V —

Storage temperature range TSTG –55 to 150 °C —

Notes:
1. Functional operating conditions are given in Table 3. Absolute maximum ratings are stress ratings only, and functional
operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent
damage to the device.
2. AVDD is measured at the input to the filter and not at the pin of the device.
3. Caution: (B,M,L,O,C, X)VIN must not exceed (B,G,L,O, C,X)VDD by more than 0.3 V. This limit may be exceeded for a
maximum of 20 ms during power-on reset and power-down sequences.
4. (M,L,O)VIN and MVREF may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 7.

P2010 QorIQ Integrated Processor Hardware Specifications, Rev. 3

30 NXP Semiconductors
 Electrical Characteristics

2.1.2 Recommended Operating Conditions

Table 3 provides the recommended operating conditions for this device. Note that the values in Table 3 are the recommended
and tested operating conditions. Proper device operation outside these conditions is not guaranteed.
Table 3. Recommended Operating Conditions

Recommended
Parameter Symbol Unit Notes
Value

Core and platform supply voltage VDD 1.05 ± 50 mV V 1

PLL supply voltage AVDD_CORE0 1.05 ± 50 mV V —

AVDD_CORE1
AVDD_DDR,
AVDD_LBIU,
AVDD_PLAT,
AVDD_SRDS
Core power supply for SerDes transceivers SVDD _SRDS 1.05 ± 50 mV V —

Pad power supply for SerDes transceivers and PCI Express XVDD_SRDS 1.05 ± 50 mV V —

DDR2 DRAM I/O voltage GVDD 1.8 V ± 100 mV V —

DDR3 DRAM I/O voltage GVDD 1.5 V ± 75 mV V —

Three-speed Ethernet I/O voltage (eTSEC) LVDD 3.3 V ± 165 mV V —

2.5 V ± 125 mV

DUART, system control and power management, I2C, GPIOx8, and OVDD 3.3 V ± 165 mV V —
JTAG I/O voltage

Enhanced local bus I/O and GPIOx8 voltage BVDD 3.3 V ± 165 mV V —
2.5 V ± 125 mV
1.8 V ± 90 mV

USB, eSPI, eSDHC I/O voltage CVDD 3.3 V ± 165 mV V 4

2.5 V ± 125 mV
1.8 V ± 90 mV

Input voltage DDR2/3 DRAM signals MVIN GND to GVDD V —

DDR2 DRAM reference MVREF GVDD/2 V —

DDR3 DRAM reference MVREF GVDD/2 V —

Three-speed Ethernet signals LVIN GND to LVDD V —

Enhanced local bus signals BVIN GND to BVDD V —

DUART, SYSCLK, system control and power OVIN GND to OVDD V —

management, I2C, and JTAG signals

USB, eSPI, eSDHC CVIN GND to CVDD V —

SerDes signals XVIN GND to XVDD V —

P2010 QorIQ Integrated Processor Hardware Specifications, Rev. 3

NXP Semiconductors 31
Electrical Characteristics

Table 3. Recommended Operating Conditions (continued)

Recommended
Parameter Symbol Unit Notes
Value

Operating Commercial TA TA= 0 (min) to °C 3

Temperature TJ TJ= 125 (max)
range
Industrial TA TA= –40 (min) to °C 3
TJ TJ= 125 (max)
Notes:
1. Caution: (B,M,L,O,C, X)VIN must not exceed (B,G,L,O, C,X)VDD by more than 0.3 V. This limit may be exceeded for a
maximum of 20 ms during power-on reset and power-down sequences.
2. Caution: Until VDD reaches its recommended operating voltage, if L/C/B/G/OVDD exceeds VDD extra current may be drawn
by the device.
3. Minimum temperature is specified with TA; maximum temperature is specified with TJ.
4. CVDD for eSDHC is limited for 3.3, 2.5, and 1.8 V

Figure 7 shows the undershoot and overshoot voltages at the interfaces of the device.

B/C/G/L/X/OVDD + 20%
B/C/G/L/X/OVDD + 5%
VIH B/C/G/L/X/OVDD

GND
GND – 0.3
VIL
GND – 0.7
Not to Exceed 10%
of tCLOCK1
Note:
1. tCLOCK refers to the clock period associated with the respective interface:
For I2C and JTAG, tCLOCK references SYSCLK.
For DDR, tCLOCK references MCLK.
For eTSEC, tCLOCK references EC_GTX_CLK125.
For eLBC, tCLOCK references LCLK.
For SerDes XVDD, tCLOCK references SD_REF_CLK.

Figure 7. Overshoot/Undershoot Voltage for BVDD/CVDD/GVDD/LVDD/XVDD/OVDD

The core voltage must always be provided at nominal 1.05 V (see Table 3 for actual recommended core voltage.) Voltage to the
processor interface I/Os are provided through separate sets of supply pins and must be provided at the voltages shown in Table 3.
The input voltage threshold scales with respect to the associated I/O supply voltage. OVDD and LVDD based receivers are simple
CMOS I/O circuits and satisfy appropriate LVCMOS type specifications. The SDRAM interface uses a differential receiver
referenced the externally supplied MVREF signal (nominally set to GVDD ÷ 2). The DDR DQS receivers cannot be operated in
single-ended fashion. The complement signal must be properly driven and cannot be grounded.

P2010 QorIQ Integrated Processor Hardware Specifications, Rev. 3

32 NXP Semiconductors
 Electrical Characteristics

2.1.3 Output Driver Characteristics

Table 4 provides information on the characteristics of the output driver strengths. The values are preliminary estimates.
Table 4. Output Drive Capability

Output Impedance Supply

Driver Type Notes
(Ω) Voltage

Enhanced local bus interface, GPIO[0:7] 45 BVDD = 3.3 V —

45 BVDD = 2.5 V
45 BVDD = 1.8 V
DDR2 signal (programmable) 18 (full-strength mode) GVDD = 1.8 V 1
36 (half-strength mode)

DDR 3 signal (programmable) 20 (full-strength mode) GVDD = 1.5 V 1

40 (half-strength mode)

eTSEC signals 45 LVDD = 2.5/3.3 V —

DUART, system control, JTAG 45 OVDD = 3.3 V —

I2C 45 OVDD = 3.3 V —

USB, eSPI, eSDHC 45 CVDD = 3.3 V —

CVDD = 2.5 V
CVDD = 1.8 V

Note:
1. The drive strength of the DDR2/3 interface in half-strength mode is at TJ = 105 °C and at GVDD (min).

2.2 Power Sequencing

The device. requires its power rails to be applied in a specific sequence in order to ensure proper device operation. These
requirements are as follows for power up:
1. VDD, AVDD, BVDD, LVDD, CVDD, OVDD, SVDD_SRDS, and XVDD_SRDS
2. GVDD
All supplies must be at their stable values within 50 ms.
Items on the same line have no ordering requirement with respect to one another. Items on separate lines must be ordered
sequentially such that voltage rails on a previous step must reach 90% of their value before the voltage rails on the current step
reach 10% of theirs.

NOTE
While VDD is ramping, current may be supplied from VDD through the device to GVDD.
Nevertheless, GVDD from an external supply should follow the sequencing described
above.
From a system standpoint, if any of the I/O power supplies ramp prior to the VDD core
supply, the I/Os associated with that I/O supply may drive a logic one or zero during power
up, and extra current may be drawn by the device.

WARNING
Only 100,000 POR cycles are permitted per lifetime of a device.

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2.3 Power Characteristics

The estimated typical core power consumption for the core complex bus (CCB) versus the core frequency for this family of
QorIQ devices is shown in Table 5.
Table 5. P2010 Core Power Consumption

Core Frequency Platform VDD Junction Power

Power Mode Notes
(MHz) Frequency (MHz) (V) Temperature (°C) (W)

Thermal 800 400 1.05 125 4.7 1, 2

Maximum 5.7 1, 3

Thermal 1000 500 1.05 125 4.9 1, 2

Maximum 6.0 1, 3

Thermal 1200 600 1.05 125 5.1 1, 2

Maximum 6.3 1, 3

Thermal 1333 667 1.05 125 5.4 1, 2

Maximum 6.7 1, 3

Notes:
1. These values specify the power consumption at nominal voltage and apply to all valid processor bus frequencies and
configurations. The values do not include power dissipation for I/O supplies.
2. Thermal power is the maximum power measured at nominal core voltage (VDD_Core_n) and maximum operating junction
temperature (see Table 3) while running the Dhrystone 2.1 benchmark and achieving 2.3 Dhrystone MIPs/MHz.
3. Maximum power is the maximum power measured at nominal core voltage (VDD) and maximum operating junction
temperature (see Table 3) while running a test which includes an entirely L1-cache-resident, contrived sequence of
instructions which keep all the execution units busy at with one core at 100% efficiency and a typical workload on platform
interfaces.
4. This table includes power numbers for the VDD and AVDD_n rails

2.3.1 I/O DC Power Supply Recommendation

Table 6 provides estimated I/O power numbers for each block: DDR, PCI Express, eLBC, eTSEC, serial RapidIO, SGMII,
eSDHC, USB, eSPI, DUART, I2C and GPIO.
Table 6. I/O Power Supply Estimated Values

Interface Parameter Symbol Typical Maximum Unit Notes

DDR2 400 MHz data rate GVDD (1.8 V) 0.7 1.0 W 1, 2, 3

533 MHz data rate GVDD (1.8 V) 0.9 1.25 W 1, 2, 3
667 MHz data rate GVDD (1.8 V) 1.1 1.6 W 1, 2, 3
DDR3 667 MHz data rate GVDD (1.5 V) 0.7 1.1 W 1, 2, 3
800 MHz data rate GVDD (1.5 V) 0.8 1.2 W 1, 2, 3, 4
PCI Express ×1, 2.5 G-baud XVDD (1.05 V) 0.15 0.15 W 1, 2, 3
×2, 2.5 G-baud XVDD (1.05 V) 0.21 0.21 W 1, 2, 3
×4, 2.5 G-baud XVDD (1.05 V) 0.32 0.32 W 1, 2, 3

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Table 6. I/O Power Supply Estimated Values (continued)

Interface Parameter Symbol Typical Maximum Unit Notes

Serial RapidIO ×1, 2.5 G-baud XVDD (1.05 V) 0.18 0.18 W 1, 2, 3

×4, 2.5 G-baud XVDD (1.05 V) 0.39 0.39 W 1, 2, 3
SGMII ×1, 1.25G-baud XVDD (1.05 V) 0.1 0.2 W 1, 2, 3
eLBC 16-bit, 75 MHz BVDD (1.8 V) 0.05 0.09 W 1, 2, 3
BVDD (2.5 V) 0.08 0.13 W 1, 2, 3
BVDD (3.3 V) 0.11 0.20 W 1, 2, 3
eTSEC MII, GMII, RGMII, RTBI, LVDD (2.5 V) 0.07 0.15 W 1, 2, 3, 5
RMII, TBI, 1588
MII, GMII, TBI, RMII, LVDD (3.3 V) 0.11 0.20 W 1, 2, 3, 5
1588
eSDHC — CVDD (3.3 V) 0.03 0.04 W 1, 2, 3
CVDD (2.5 V) 0.02 0.03 W 1, 2, 3
CVDD (1.8 V) 0.01 0.02 W 1, 2, 3
USB — CVDD (3.3 V) 0.05 0.06 W 1, 2, 3
CVDD (2.5 V) 0.04 0.05 W 1, 2, 3
CVDD (1.8 V) 0.02 0.03 W 1, 2, 3
eSPI — CVDD (3.3 V) 0.03 0.04 W 1, 2, 3
CVDD (2.5 V) 0.02 0.03 W 1, 2, 3
CVDD (1.8 V) 0.01 0.02 W 1, 2, 3
I2C — OVDD (3.3 V) 0.01 0.02 W 1, 2, 3
DUART — OVDD (3.3 V) 0.01 0.02 W 1, 2, 3
GPIO [0:7] ×8 OVDD (3.3 V) 0.01 0.02 W 1, 2, 3, 6
GPIO [8:15] ×8 BVDD (1.8 V) 0.01 0.02 W 1, 2, 3, 6
BVDD (2.5 V) 0.01 0.02 W 1, 2, 3, 6
BVDD (3.3 V) 0.01 0.02 W 1, 2, 3, 6
Notes:
1.The maximum value is dependent on actual use case such as what application, external components used, environmental
conditions such as temperature voltage and frequency. This is not intended to be the maximum guaranteed current.
Depending on use case different result is expected.
2. The typical value are estimates based on simulations at nominal recommended core voltage (VDD) and assuming 65 C
junction temperature.
3. The maximum value are estimates based on simulations at nominal recommended core voltage (VDD) and assuming 105 C
junction temperature.
4. 800 Mbps data rate only supported on DDR3.
5. The current values are per each eTSEC used.
6. GPIO ×8 support on OVDD and ×8 on BVDD rail supply.

2.4 Input Clocks

This section discusses the parameters for the input clocks.

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2.4.1 System Clock Timing

Table 7 provides the system clock (SYSCLK) DC specifications for the device.
Table 7. SYSCLK DC Electrical Characteristics (OVDD = 3.3 V ± 165 mV)

Parameter Symbol Min Typical Max Unit Notes

High-level input voltage VIH 2.0 — — V 1

Low-level input voltage VIL — — 0.8 V 1
Input capacitance CIN — 7 15 pf —
Input current (VIN= 0 V or VIN = VDD) IIN — — ±50 μA 2
Note:
1. The max VIH, and min VIL values can be found in Table 3
2. The symbol VIN, in this case, represents the OVIN symbol referenced in Table 3

Table 8 provides the system clock (SYSCLK) AC timing specifications for the device.

Table 8. SYSCLK AC Timing Specifications

At recommended operating conditions (see Table 3) with OVDD = 3.3 V ± 165 mV.

Parameter/Condition Symbol Min Typ Max Unit Notes

SYSCLK frequency fSYSCLK 64.00 — 100 MHz 1, 2

SYSCLK cycle time tSYSCLK 10 — 15.6 ns 1, 2

SYSCLK duty cycle tKHK/tSYSCLK 40 — 60 % 2

SYSCLK slew rate — 1 — 4 V/ns 3

SYSCLK peak period jitter — — — ±150 ps —

SYSCLK jitter phase noise at –56 dBc — — — 500 KHz 4

AC input swing limits at 3.3 V OVDD ΔVAC 1.9 — — V —

Notes:
1. Caution: The CCB_clk to SYSCLK ratio and e500 core to CCB_clk ratio settings must be chosen such that the resulting
SYSCLK frequency, e500 core frequency, and CCB_clk frequency do not exceed their respective maximum or minimum
operating frequencies.
2. Measured at the rising edge and/or the falling edge at OVDD ÷ 2.
3. Slew rate as measured from ±0.3 ΔVAC at center of peak-to-peak voltage at clock input.
4. Phase noise is calculated as FFT of TIE jitter.

2.4.2 SYSCLK and Spread Spectrum Source Recommendations

Spread spectrum clock sources are an increasingly popular way to control electromagnetic interference emissions (EMI) by
spreading the emitted noise to a wider spectrum and reducing the peak noise magnitude in order to meet industry and
government requirements. These clock sources intentionally add long-term jitter in order to diffuse the EMI spectral content.
The jitter specification given in Table 8 considers short-term (cycle-to-cycle) jitter only and the clock generator’s cycle-to-cycle
output jitter should meet the device input cycle-to-cycle jitter requirement. Frequency modulation and spread are separate

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concerns, and the device is compatible with spread spectrum sources if the recommendations listed in Table 9 are observed.
Table 9. SYSCLK Spread Spectrum Clock Source Recommendations
At recommended operating conditions. See Table 3.

Parameter Min Max Unit Notes

Frequency modulation — 60 kHz —

Frequency spread — 1.0 % 1, 2

Note:
1. SYSCLK frequencies resulting from frequency spreading, and the resulting core and VCO frequencies, must meet the
minimum and maximum specifications given in Table 8.
2. Maximum spread spectrum frequency may not result in exceeding any maximum operating frequency of the device

CAUTION
The processor’s minimum and maximum SYSCLK, core, and VCO frequencies must not
be exceeded regardless of the type of clock source. Therefore, systems in which the
processor is operated at its maximum rated e500 core frequency should avoid violating the
stated limits by using down-spreading only.

2.4.3 Real Time Clock Timing

The RTC input is sampled by the platform clock (CCB clock). The output of the sampling latch is then used as an input to the
counters of the PIC and the TimeBase unit of the e500. There is no jitter specification. The minimum pulse width of the RTC
signal must be greater than 2× the period of the CCB clock. That is, minimum clock high time is 2 × tCCB, and minimum clock
low time is 2 × tCCB. There is no minimum RTC frequency; RTC may be grounded if not needed.

2.4.4 eTSEC Gigabit Reference Clock Timing

Table 10 provides the eTSEC gigabit reference clocks DC electrical characteristics for RGMII, GMII at LVDD = 2.5 V.
Table 10. eTSEC Gigabit Reference Clock DC Electrical Characteristics RGMII, GMII at LVDD = 2.5 V

Parameter Symbol Min Max Unit Notes

High-level input voltage VIH 1.70 — V 1

Low-level input voltage VIL — 0.70 V 1

Input current (VIN = 0 V or VIN = VDD) IIN — ±40 μA 2

Note:
1. The max VIH, and min VIL values can be found in Table 3.
2. The symbol VIN, in this case, represents the OVIN symbol referenced in Table 3.

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Table 11 provides the eTSEC gigabit reference clocks DC electrical characteristics for GMII LVDD = 3.3 V.
Table 11. eTSEC Gigabit Reference Clock DC Electrical Characteristics GMII LVDD = 3.3 V

Parameter Symbol Min Max Unit Notes

High-level input voltage VIH 1.90 — V 1

Low-level input voltage VIL — 0.90 V 1
Input current (VIN = 0 or VIN = VDD) IIN — ±40 μA 2
Note:
1. The max VIH, and min VIL values can be found in Table 3.
2. The symbol VIN, in this case, represents the OVIN symbol referenced in Table 3.

Table 12 provides the eTSEC gigabit reference clocks (EC_GTX_CLK125) AC timing specifications for the device.
Table 12. EC_GTX_CLK125 AC Timing Specifications

Parameter/Condition Symbol Min Typical Max Unit Notes

EC_GTX_CLK125 frequency tG125 125 - 100 125 125 + 100 MHz —

ppm ppm

EC_GTX_CLK125 cycle time tG125 — 8 — ns —

EC_GTX_CLK rise and fall time tG125R/tG125F — — ns 1

LVDD = 2.5 V 0.75
LVDD = 3.3 V 1.0

EC_GTX_CLK125 duty cycle tG125H/tG125 — % 2

GMII, TBI 45 55
1000Base-T for RGMII, RTBI 47 53

EC_GTX_CLK125 jitter — — — ±150 ps 2

Notes:
1. Rise and fall times for EC_GTX_CLK125 are measured from 0.5 and 2.0 V for LVDD = 2.5 V, and from 0.6 and 2.7 V for
LVDD = 3.3 V.
2. EC_GTX_CLK125 is used to generate the GTX clock for the eTSEC transmitter with 2% degradation. EC_GTX_CLK125 duty
cycle can be loosened from 47%/53% as long as the PHY device can tolerate the duty cycle generated by the eTSEC
GTX_CLK. See Section 2.10.2.5, “RGMII and RTBI AC Timing Specifications,” for duty cycle for 10Base-T and 100Base-T
reference clock.

2.4.5 DDR Clock Timing

Table 7 provides the system clock (DDRCLK) DC specifications for the device.
Table 13. DDRCLK DC Electrical Characteristics (OVDD = 3.3 V ± 165 mV)

Parameter Symbol Min Typical Max Unit Notes

High-level input voltage VIH 2.0 — OVDD + 0.3 V —

Low-level input voltage VIL –0.3 — 0.8 V —
Input capacitance CIN — 7 15 pf —
Input current (VIN = 0 V or VIN = VDD) IIN — — ±50 μA 1
Note:
1. The symbol VIN, in this case, represents the OVIN symbol referenced in Table 2 and Table 3.

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Table 14 provides the DDR clock (DDRCLK) AC timing specifications for the device.
Table 14. DDRCLK AC Timing Specifications
At recommended operating conditions with OVDD of 3.3 V ± 5%.

Parameter/Condition Symbol Min Typical Max Unit Notes

DDRCLK frequency fDDRCLK 66.7 — 100 MHz 1, 2

DDRCLK cycle time tDDRCLK 10 — 15 ns 1, 2

DDRCLK duty cycle tKHK/tDDRCLK 40 — 60 % 2

DDRCLK slew rate — 1 — 4 V/ns 3

DDRCLK peak period jitter — — — ±150 ps —

DDRCLK jitter phase noise at –56 dBc — — — 500 KHz 4

AC Input Swing Limits at 3.3 V OVDD ΔVAC 1.9 — — V —

Notes:
1. Caution: The DDR complex clock to DDRCLK ratio settings must be chosen such that the resulting DDR complex clock
frequency does not exceed the maximum or minimum operating frequencies.
2. Measured at the rising edge and/or the falling edge at OVDD ÷ 2.
3. Slew rate as measured from ±0.3 ΔVAC at center of peak to peak voltage at clock input.
4. Phase noise is calculated as FFT of TIE jitter.

2.4.6 Other Input Clocks

For information on the input clocks of other functional blocks of the platform such as SerDes and eTSEC, see their specific
sections in this document.

2.5 RESET Initialization

This section describes the AC electrical specifications for the RESET initialization timing requirements of the device. Table 15
provides the RESET initialization AC timing specifications.
Table 15. RESET Initialization Timing Specifications

Parameter Min Max Unit Notes

Required assertion time of HREST 100 — μs —

Minimum assertion time for SRESET 3 — SYSCLKs 1

PLL input setup time with stable SYSCLK before HRESET negation 100 — μs —

Input setup time for POR configurations (other than PLL configuration) 4 — SYSCLKs 1
with respect to negation of HRESET
Input hold time for all POR configurations (including PLL configuration) 2 — SYSCLKs 1
with respect to negation of HRESET

Maximum valid-to-high impedance time for actively driven POR — 5 SYSCLKs 1, 2

configurations with respect to negation of HRESET

Note:
1. SYSCLK is the primary clock input for the device.
2. HRESET should have a rise time of no more than one SYSCLK cycle.

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Table 16 provides the PLL lock times.

Table 16. PLL Lock Times

Parameter Min Max Unit Notes

Core PLL lock times — 100 μs —

Platform PLL lock time — 100 μs —

DDR PLL lock times — 100 μs —

Enhanced local bus PLL — 100 μs —

2.6 Power-on Ramp Rate

This section describes the AC electrical specifications for the power-on ramp rate requirements. Controlling the maximum
Power-On Ramp Rate is required to avoid falsely triggering the ESD circuitry. Table 17 provides the power supply ramp rate
specifications.
Table 17. Power Supply Ramp Rate

Parameter Min Max Unit Notes

Required ramp rate for all voltage supplies (including OVDD/CVDD/ — 36000 Volts/Sec 1, 2
GVDD/BVDD/SVDD/LVDD, All VDD supplies, MVREF and all AVDD supplies.)

Note:
1. Ramp rate is specified as a linear ramp from 10 to 90%. If non-linear (e.g. exponential), the maximum rate of change from
200 to 500 mV is the most critical as this range might falsely trigger the ESD circuitry.
2. Over full recommended operating temperature range Table 3.

2.7 DDR2 and DDR3 SDRAM

This section describes the DC and AC electrical specifications for the DDR SDRAM interface of the device. DDR2 and DDR3
share the same AC timing specifications. Note that DDR2 SDRAM is GVDD(typ) = 1.8 V and DDR3 SDRAM is
GVDD(typ) = 1.5 V.

2.7.1 DDR2 and DDR3 SDRAM Interface DC Electrical Characteristics

Table 18 provides the recommended operating conditions for the DDR SDRAM controller when interfacing to DDR2 SDRAM.
Table 18. DDR2 SDRAM DC Electrical Characteristics for GVDD(typ) = 1.8 V1
1

Parameter Symbol Min Max Unit Notes

I/O reference voltage MVREF 0.49 × GVDD 0.51 × GVDD V 2, 3, 4

Input high voltage VIH MVREF + 0.125 — V 5

Input low voltage VIL — MVREF – 0.125 V 5

Output high current (VOUT = 1.370 V) IOH — –13.4 mA 6

Output low current (VOUT = 0.330 V) IOL 13.4 — mA 6

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Table 18. DDR2 SDRAM DC Electrical Characteristics for GVDD(typ) = 1.8 V1

Parameter Symbol Min Max Unit Notes

Output leakage current IOZ –50 50 μA 7

Notes:
1. GVDD is expected to be within 50 mV of the DRAM GVDD at all times. The DRAM’s and memory controller’s voltage supply
may or may not be from the same source.
2. MVREF is expected to be equal to 0.5 × GVDD and to track GVDD DC variations as measured at the receiver. Peak-to-peak
noise on MVREF may not exceed the MVREF DC level by more than ±1% of GVDD (for example, ±18 mV).
3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be
equal to MVREF. This rail should track variations in the DC level of MVREF.
4. The voltage regulator for MVREFn must be able to supply up to 1500 μA.
5. Input capacitance load for DQ, DQS, and DQS are available in the IBIS models.
6. Refer to the IBIS model for the complete output IV curve characteristics.
7. Output leakage is measured with all outputs disabled, 0 V ≤ VOUT ≤ GVDD.

Table 19 provides the recommended operating conditions for the DDR SDRAM controller when interfacing to DDR3 SDRAM.
Table 19. DDR3 SDRAM Interface DC Electrical Characteristics for GVDD(typ) = 1.5 V1

Parameter/Condition Symbol Min Max Unit Note

I/O reference voltage MVREF 0.49 × GVDD 0.51 × GVDD V 2, 3, 4

Input high voltage VIH MVREF + 0.100 GVDD V 5

Input low voltage VIL GND MVREF – 0.100 V 5

I/O leakage current IOZ –50 50 μA 6

Notes:
1. GVDD is expected to be within 50 mV of the DRAM’s voltage supply at all times. The DRAM’s and memory controller’s voltage
supply may or may not be from the same source.
2. MVREF is expected to be equal to 0.5 × GVDD and to track GVDD DC variations as measured at the receiver. Peak-to-peak
noise on MVREF may not exceed the MVREF DC level by more than ±1% of GVDD (for example, ±15 mV).
3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made, and it is expected to be
equal to MVREFn with a min value of MVREFn – 0.04 and a max value of MVREFn + 0.04. VTT should track variations in the
DC level of MVREFn.
4. The voltage regulator for MVREFn must be able to supply up to125 μA current.
5. Input capacitance load for DQ, DQS, and DQS are available in the IBIS models.
6. Output leakage is measured with all outputs disabled, 0 V ≤ VOUT ≤ GVDD.

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Table 20 provides the DDR Controller interface capacitance for DDR2 and DDR3.
Table 20. DDR2 DDR3 SDRAM Capacitance for GVDD(typ) = 1.8 V and 1.5 V

Parameter/Condition Symbol Min Max Unit Notes

Input/output capacitance: DQ, DQS, DQS CIO 6 8 pF 1, 2

Delta input/output capacitance: DQ, DQS, DQS CDIO — 0.5 pF 1, 2

Note:
1. This parameter is sampled. GVDD = 1.8 V ± 0.1 V (for DDR2), f = 1 MHz, TA = 25 °C, VOUT = GVDD ÷ 2, VOUT
(peak-to-peak) = 0.2 V.
2. This parameter is sampled. GVDD = 1.5 V ± 0.075 V (for DDR3), f = 1 MHz, TA = 25 °C, VOUT = GVDD ÷ 2, VOUT
(peak-to-peak) = 0.150 V.

Table 21 provides the current draw characteristics for MVREF.

Table 21. Current Draw Characteristics for MVREF

Parameter/Condition Symbol Min Max Unit Note

Current draw for DDR2 SDRAM for MVREF MVREF — 1500 μA 1

Current draw for DDR3 SDRAM for MVREF MVREF — 1250 μA 1

Note:
1. The voltage regulator for MVREF must be able to supply up to 1500 μA current.

2.7.2 DDR2 and DDR3 SDRAM Interface AC Timing Specifications

This section provides the AC timing specifications for the DDR SDRAM controller interface. The DDR controller supports both
DDR2 and DDR3 memories. Note that the required GVDD(typ) voltage is 1.8 V or 1.5 V when interfacing to DDR2 or DDR3
SDRAM respectively.

2.7.2.1 DDR2 and DDR3 SDRAM Interface Input AC Timing Specifications

Table 22, Table 23, and Table 24 provide the input AC timing specifications for the DDR controller.
Table 22. DDR2 SDRAM Input AC Timing Specifications for 1.8-V Interface
At recommended operating conditions (see Table 3).

Parameter Symbol Min Max Unit Notes

AC input low voltage > 533 Mbps data rate VILAC — MVREF – 0.20 V —

≤ 533 Mbps data rate — MVREF – 0.25 —

AC input high voltage > 533 Mbps data rate VIHAC MVREF + 0.20 — V —

≤ 533 Mbps data rate MVREF + 0.25 — —

Table 23. DDR3 SDRAM Input AC Timing Specifications for 1.5-V Interface
At recommended operating conditions (see Table 3).

Parameter Symbol Min Max Unit Notes

AC input low voltage VIL — MVREF – 0.175 V —

AC input high voltage VIH MVREF + 0.175 — V —

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Table 24. DDR2 and DDR3 SDRAM Interface Input AC Timing Specifications
At recommended operating conditions (see Table 3).

Parameter/Condition Symbol Min Max Unit Notes

Controller Skew for MDQS—MDQ/MECC tCISKEW — — ps 1, 2

800 Mbps data rate –350 350 ps 1, 2
667 Mbps data rate –390 390 ps 1, 2
533 Mbps data rate –450 450 ps 1, 2
400 Mbps data rate –515 515 ps 1, 2

Tolerated Skew for MDQS—MDQ/MECC tDISKEW — — ps 1, 2

800 Mbps data rate –275 275 ps 1, 2
667 Mbps data rate –360 360 ps 1, 2
533 Mbps data rate –488 488 ps 1, 2
400 Mbps data rate –735 735 ps 1, 2

Notes:
1. tCISKEW represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that
is captured with MDQS[n]. This must be subtracted from the total timing budget.
2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called tDISKEW.This can be
determined by the following equation: tDISKEW = ± (T ÷ 4 – abs(tCISKEW)) where T is the clock period and abs(tCISKEW) is the
absolute value of tCISKEW.

Figure 8 shows the DDR2 and DDR3 SDRAM interface input timing diagram.

MCK[n]

MCK[n]
tMCK

MDQS[n]

tDISKEW

MDQ[x] D0 D1
tDISKEW
tDISKEW

Figure 8. DDR2 and DDR3 SDRAM Interface Input Timing Diagram

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2.7.2.2 DDR2 and DDR3 SDRAM Interface Output AC Timing Specifications

Table 25 contains the output AC timing targets for the DDR SDRAM interface.
Table 25. DDR2 and DDR3 SDRAM Output AC Timing Specifications
At recommended operating conditions (see Table 3).

Parameter Symbol1 Min Max Unit Notes

MCK[n] cycle time tMCK 2.5 5 ns 2

ADDR/CMD output setup with respect to MCK tDDKHAS ns

800 Mbps data rate 0.767 — 3, 7
667 Mbps data rate .950 — 3
533 Mbps data rate 1.33 — 3, 4
400 Mbps data rate 1.8 — 3, 4

ADDR/CMD output hold with respect to MCK tDDKHAX ns

800 Mbps data rate 0.767 — 3, 7
667 Mbps data rate .950 — 3
533 Mbps data rate 1.33 — 3, 4
400 Mbps data rate 1.8 — 3, 4

MCS[n] output setup with respect to MCK tDDKHCS ns

800 Mbps data rate 0.767 — 3, 7
667 Mbps data rate .950 — 3
533 Mbps data rate 1.33 — 3, 4
400 Mbps data rate 1.8 — 3, 4

MCS[n] output hold with respect to MCK tDDKHCX ns

800 Mbps data rate 0.767 — 3, 7
667 Mbps data rate .950 — 3
533 Mbps data rate 1.33 — 3, 4
400 Mbps data rate 1.8 — 3, 4

MCK to MDQS Skew tDDKHMH ns

800 Mbps data rate –0.525 0.525 5, 7
667 Mbps data rate –0.600 0.600 5
533 Mbps data rate –0.600 0.600 4, 5
400 Mbps data rate –0.600 0.600 4, 5

MDQ/MECC/MDM output setup with respect tDDKHDS, ps

to MDQS tDDKLDS
800 Mbps data rate 225 — 6, 7
667 Mbps data rate 300 — 6
533 Mbps data rate 388 — 4, 6
400 Mbps data rate 550 — 4, 6

MDQ/MECC/MDM output hold with respect to tDDKHDX, ps

MDQS tDDKLDX
800 Mbps data rate 225 — 6, 7
667 Mbps data rate 300 — 6
533 Mbps data rate 388 — 4, 6
400 Mbps data rate 550 — 4,6

MDQS preamble tDDKHMP 0.9 × tMCK — ns —

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Table 25. DDR2 and DDR3 SDRAM Output AC Timing Specifications (continued)
At recommended operating conditions (see Table 3).

Parameter Symbol1 Min Max Unit Notes

MDQS postamble tDDKHME 0.4 × tMCK 0.6 × tMCK ns —

Notes:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. Output hold time can be read as DDR timing
(DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example,
tDDKHAS symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes from the high (H) state until outputs
(A) are setup (S) or output valid time. Also, tDDKLDX symbolizes DDR timing (DD) for the time tMCK memory clock reference
(K) goes low (L) until data outputs (D) are invalid (X) or data output hold time.
2. All MCK/MCK and MDQS/MDQS referenced measurements are made from the crossing of the two signals.
3. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MECC/MDM/MDQS.
4. Note that minimum data rate for DDR3 is 667 MHz.
5. tDDKHMH follows the symbol conventions described in note 1. For example, tDDKHMH describes the DDR timing (DD) from the
rising edge of the MCK[n] clock (KH) until the MDQS signal is valid (MH). tDDKHMH can be modified through control of the
MDQS override bits (called WR_DATA_DELAY) in the TIMING_CFG_2 register. This is typically set to the same delay as in
DDR_SDRAM_CLK_CNTL[CLK_ADJUST]. The timing parameters listed in the table assume that these two parameters
have been set to the same adjustment value. See the P2010 QorIQ Reference Manual for a description and understanding
of the timing modifications enabled by use of these bits.
6. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC
(MECC), or data mask (MDM). The data strobe must be centered inside of the data eye at the pins of the microprocessor.
7. DDR3 only.

NOTE
For the ADDR/CMD setup and hold specifications in Table 25, it is assumed that the clock
control register is set to adjust the memory clocks by ½ applied cycle.
Figure 9 shows the DDR2 and DDR3 SDRAM output timing for the MCK to MDQS skew measurement (tDDKHMH).

MCK[n]

MCK[n]
tMCK

tDDKHMHmax)

MDQS

tDDKHMH(min)

MDQS

Figure 9. Timing Diagram for tDDKHMH

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Figure 10 shows the DDR SDRAM output timing diagram.

MCK[n]
MCK[n]
tMCK

tDDKHAS, tDDKHCS
tDDKHAX, tDDKHCX

ADDR/CMD Write A0 NOOP

tDDKHMP
tDDKHMH

MDQS[n]
tDDKHME
tDDKHDS
tDDKLDS

MDQ[x] D0 D1
tDDKLDX
tDDKHDX
Figure 10. DDR2 and DD3 SDRAM Output Timing Diagram

Figure 11 provides the AC test load for the DDR bus.

Output Z0 = 50 Ω GVDD/2
RL = 50 Ω

Figure 11. DDR AC Test Load

2.8 eSPI
This section describes the DC and AC electrical specifications for the eSPI.

2.8.1 eSPI DC Electrical Characteristics

Table 26 provides the DC electrical characteristics for the eSPI interface operating at CVDD = 3.3 V.
Table 26. SPI DC Electrical Characteristics (3.3 V)

Parameter Symbol Min Max Unit Note

High-level input voltage VIH 2 — V 1

Low-level input voltage VIL — 0.8 V 1

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Table 26. SPI DC Electrical Characteristics (3.3 V) (continued)

Parameter Symbol Min Max Unit Note

Input current (VIN = 0 V or VIN = CVDD) IIN — ±70 μA 2

High-level output voltage VOH 2.4 — V —
(CVDD = min, IOH = –2 mA)
Low-level output voltage VOL — 0.4 V —
(CVDD = min, IOL = 2 mA)
Note:
1. The min VILand max VIH values are based on the respective min and max CVIN values found in Table 3.
2. The symbol VIN, in this case, represents the CVIN symbol referenced in Section 2.1.2, “Recommended Operating Conditions.”

Table 27 provides the DC electrical characteristics for the eSPI interface operating at CVDD = 2.5 V.
Table 27. SPI DC Electrical Characteristics (2.5 V)

Parameter Symbol Min Max Unit Note

High-level input voltage VIH 1.7 — V 1

Low-level input voltage VIL — 0.7 V 1
Input current (VIN = 0 V or VIN = CVDD) IIN — ±70 μA 2
High-level output voltage (CVDD = min, IOH = –1 mA) VOH 2.0 — V —
Low-level output voltage (CVDD = min, IOL = 1 mA) VOL — 0.4 V —
Note:
1. The min VILand max VIH values are based on the respective min and max CVIN values found in Table 3.
2. The symbol VIN, in this case, represents the CVIN symbol referenced in Section 2.1.2, “Recommended Operating Conditions.”

Table 28 provides the DC electrical characteristics for the eSPI interface operating at CVDD = 1.8 V.
Table 28. SPI DC Electrical Characteristics (1.8 V)

Parameter Symbol Min Max Unit Note

High-level input voltage VIH 1.25 — V 1

Low-level input voltage VIL — 0.6 V 1
Input current (VIN = 0 V or VIN = CVDD) IIN — ±70 μA 2
High-level output voltage (CVDD = min, IOH = –0.5 mA) VOH 1.35 — V —
Low-level output voltage (CVDD = min, IOL = 0.5 mA) VOL — 0.4 V —
Note:
1. The min VILand max VIH values are based on the respective min and max CVIN values found in Table 3.
2. The symbol VIN, in this case, represents the CVIN symbol referenced in Section 2.1.2, “Recommended Operating Conditions”

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2.8.2 eSPI AC Timing Specifications

Table 29 provides the eSPI input and output AC timing specifications.

Table 29. eSPI AC Timing Specifications1

Characteristic Symbol Min Max Unit Note

SPI_MOSI output—Master data (internal clock) hold time tNIKHOX 0.5 — ns 1, 2, 3

tNIKHOX 3.0 —

SPI_MOSI output—Master data (internal clock) delay tNIKHOV — 6.0 ns 1, 2, 3

tNIKHOV 10

SPI_CS outputs—Master data (internal clock) hold time tNIKHOX2 0 — ns 1, 2

SPI_CS outputs—Master data (internal clock) delay tNIKHOV2 — 6.0 ns 1, 2

SPI inputs—Master data (internal clock) input setup time tNIIVKH 5.75 — ns 4

SPI inputs—Master data (internal clock) input hold time tNIIXKH 0 — ns 4

Notes:
1. Output specifications are measured from the 50% level of the CLK to the 50% level of the signal. Timings are measured at
the pin.
2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tNIKHOV symbolizes the NMSI
outputs internal timing (NI) for the time tSPI memory clock reference (K) goes from the high state (H) until outputs (O) are
valid (V).
3. The greater of the two output timings for tNIKHOX and tNIKHOV are used when the SPCOM[RxDelay] bit of eSPI Command
Register is set. For example, the tNIKHOX is 3.0ns and tNIKHOV is 10ns if SPCOM[RxDelay] is set.
4. For Windbond Flash dual-output mode both SPI_MOSI and SPI_MISO are inputs.

Figure 12 provides the AC test load for the eSPI.

Output Z0 = 50 Ω CDVDD/2
RL = 50 Ω

Figure 12. eSPI AC Test Load

Figure 13 represents the AC timing from Table 29. Note that although the specifications generally reference the rising edge of
the clock, these AC timing diagrams also apply when the falling edge is the active edge.

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Figure 13 shows the eSPI timing in master mode (internal clock).

SPICLK (output)
tNIIXKH
tNIIVKH
Input Signals:
SPIMISO
(See Note)
tNIKHOV tNIKHOX
Output Signals:
SPIMOSI
(See Note)

tNIKHOV2 tNIKHOX2
Output Signals:
SPI_CS[0:3]
(See Note)
Note: The clock edge is selectable on eSPI.

Figure 13. eSPI AC Timing in Master Mode (Internal Clock) Diagram

2.9 DUART
This section describes the DC and AC electrical specifications for the DUART interface of the device.

2.9.1 DUART DC Electrical Characteristics

Table 30 provides the DC electrical characteristics for the DUART interface.
Table 30. DUART DC Electrical Characteristics

Parameter Symbol Min Max Unit Note

High-level input voltage VIH 2 — V 1

Low-level input voltage VIL — 0.8 V 1

Input current (OVIN = GND or OVIN = OVDD) IIN — ±40 μA 2

High-level output voltage (OVDD = min, IOH = –2 mA) VOH 2.4 — V —

Low-level output voltage (OVDD = min, IOL = 2mA) VOL — 0.4 V —

Note:
1. The min VILand max VIH values are based on the respective min and max OVIN values found in Table 3.
2. The symbol OVIN represents the input voltage of the supply. It is referenced in Table 2 and Table 3.

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2.9.2 DUART AC Electrical Specifications

Table 31 provides the AC timing parameters for the DUART interface.
Table 31. DUART AC Timing Specifications

Parameter Value Unit Notes

Minimum baud rate CCB clock/1,048,576 baud 1

Maximum baud rate CCB clock/16 baud 1, 2

Notes:
1. CCB clock refers to the platform clock.
2. The actual attainable baud rate is limited by the latency of interrupt processing.

2.10 Ethernet: Enhanced Three-Speed Ethernet (eTSEC),

MII Management
This section provides the AC and DC electrical characteristics for enhanced three-speed Ethernet controller, and MII
management.

2.10.1 Enhanced Three-Speed Ethernet Controller (eTSEC)

(10/100/1000 Mbps)— GMII/SGMII/MII/TBI/RGMII/RTBI/RMII
Electrical Characteristics
The electrical characteristics specified here apply to the following interfaces:
• All gigabit media independent interface (GMII)
• Serial gigabit media independent interface (SGMII)
• Media independent interface (MII)
• Ten-bit interface (TBI)
• Reduced gigabit media independent interface (RGMII)
• Reduced ten-bit interface (RTBI)
• Reduced media independent interface (RMII) signals except management data input/output (MDIO) and management
data clock (MDC).
The RGMII and RTBI interfaces are defined for 2.5 V, while the GMII, MII, RMII, and TBI interfaces can be operated at 3.3
or 2.5 V. Whether the GMII, MII, or TBI interface is operated at 3.3 or 2.5 V, the timing is compliant with IEEE Std 802.3™.
The interfaces conform to specifications, as follows:
• SGMII interfaces conform (with exceptions) to the Serial Gigabit Media-Independent Interface (SGMII) Specification,
Version 1.8.
• RGMII and RTBI interfaces conform to the Reduced Gigabit Media-Independent Interface (RGMII) Specification,
Version 1.3 (12/10/2000).
• The RMII interface conforms to the RMII Consortium RMII Specification, Version 1.2 (3/20/1998).
The electrical characteristics for MDIO and MDC are specified in Section 2.10.7, “Ethernet Management Interface Electrical
Characteristics.”

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2.10.1.1 IEEE 1588, GMII, MII, TBI, RGMII, RMII, and RTBI DC Electrical
Characteristics
All GMII, MII, TBI, RGMII, RMII, and RTBI drivers and receivers comply with the DC parametric attributes specified in
Table 32 and Table 33. The RGMII and RTBI signals are based on a 2.5-V CMOS interface voltage as defined by JEDEC
EIA/JESD8-5.
Table 32. IEEE 1588, GMII, MII, RMII, and TBI DC Electrical Characteristics at LVDD = 3.3 V

Parameter Symbol Min Max Unit Notes

Output high voltage (LVDD = min, IOH = –4.0 mA) VOH 2.40 — V —

Output low voltage (LVDD = min, IOL = 4.0 mA) VOL — 0.40 V —

Input high voltage (IEEE 1588, MII, RMII and TBI) VIH 2.0 — V —

Input high voltage (GMII) VIH 1.90 — V —

Input low voltage VIL — 0.90 V —

Input high current (VIN = LVDD) IIH — 40 μA 1

Input low current (VIN = GND) IIL –40 — μA 1

Note:
1. The symbol VIN, in this case, represents the LVIN symbols referenced in Table 2 and Table 3.

Table 33. IEEE 1588, GMII, MII, RMII, RGMII, RTBI, and TBI DC Electrical Characteristics at LVDD = 2.5 V

Parameters Symbol Min Max Unit Notes

Output high voltage (LVDD = min, IOH = –1.0 mA) VOH 2.00 — V —
Output low voltage (LVDD = min, IOL = 1.0 mA) VOL — 0.40 V —
Input high voltage VIH 1.70 — V —
Input low voltage VIL — 0.70 V —
Input high current (VIN = LVDD) IIH — 40 μA —
Input low current (VIN = GND) IIL –40 — μA 1
Note:
1. The symbol VIN, in this case, represents the LVIN symbols referenced in Table 2 and Table 3.

2.10.2 GMII,MII, TBI, RGMII, RMII, and RTBI AC Timing Specifications

The AC timing specifications for GMII, MII, TBI, RGMII, RMII, and RTBI are presented in this section.

2.10.2.1 GMII AC Timing Specifications

This section describes the GMII transmit and receive AC timing specifications.

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2.10.2.1.1 GMII Transmit AC Timing Specifications

Table 34 provides the GMII transmit AC timing specifications.
Table 34. GMII Transmit AC Timing Specifications

Parameter Symbol Min Typ Max Unit Note

GTX_CLK clock period tGTX — 8.0 — ns —

GMII data TXD[7:0], TX_ER, TX_EN setup time tGTKHDV 2.5 — — ns —

GTX_CLK to GMII data TXD[7:0], TX_ER, TX_EN delay tGTKHDX 0.5 — 5.5 ns 1

GTX_CLK data clock rise time (20%–80%) tGTXR — — 1.0 ns —

GTX_CLK data clock fall time (80%–20%) tGTXF — — 1.0 ns —

Note:
1. Data valid minimum setup time, tgtkhdv, is a function of clock and maximum hold time (min setup = cycle time – max delay).

Figure 14 shows the GMII transmit AC timing diagram.

tGTX tGTXR

GTX_CLK

tGTXH tGTXF
TXD[7:0]
TX_EN
TX_ER
tGTKHDX
tGTKHDV

Figure 14. GMII Transmit AC Timing Diagram

2.10.2.1.2 GMII Receive AC Timing Specifications

Table 35 provides the GMII receive AC timing specifications.
Table 35. GMII Receive AC Timing Specifications

Parameter Symbol Min Typ Max Unit Note

RX_CLK clock period tGRX 7.5 — — ns 1
RX_CLK duty cycle tGRXH/tGRX 35 — 65 % 2
RXD[7:0], RX_DV, RX_ER setup time to RX_CLK tGRDVKH 2.0 — — ns —
RXD[7:0], RX_DV, RX_ER hold time to RX_CLK tGRDXKH 0 — — ns —
RX_CLK clock rise (20%–80%) tGRXR — — 1.0 ns 2
RX_CLK clock fall time (80%–20%) tGRXF — — 1.0 ns 2
Note:
1. The frequency of RX_CLK should not exceed frequency of gigabit Ethernet reference clock by more than 300 ppm.
2. System/board must be designed to ensure the input requirement to the device is achieved. Proper device operation is
guaranteed for inputs meeting this requirement by design, simulation, characterization, or functional testing.

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Figure 15 provides the AC test load for eTSEC.

Output Z0 = 50 Ω LVDD/2
RL = 50 Ω

Figure 15. eTSEC AC Test Load

Figure 16 shows the GMII receive AC timing diagram.

tGRX tGRXR

RX_CLK

tGRXH tGRXF
RXD[7:0]
RX_DV
RX_ER
tGRDXKH
tGRDVKH

Figure 16. GMII Receive AC Timing Diagram

2.10.2.2 MII AC Timing Specifications

This section describes the MII transmit and receive AC timing specifications.

2.10.2.2.1 MII Transmit AC Timing Specifications

Table 36 provides the MII transmit AC timing specifications.
Table 36. MII Transmit AC Timing Specifications

Parameter Symbol Min Typ Max Unit

TX_CLK clock period 10 Mbps tMTX — 400 — ns

TX_CLK clock period 100 Mbps tMTX — 40 — ns

TX_CLK duty cycle tMTXH/tMTX 35 — 65 %

TX_CLK to MII data TXD[3:0], TX_ER, TX_EN delay tMTKHDX 1 5 15 ns

TX_CLK data clock rise (20%–80%) tMTXR 1.0 — 4.0 ns

TX_CLK data clock fall (80%–20%) tMTXF 1.0 — 4.0 ns

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Figure 17 shows the MII transmit AC timing diagram.

tMTX tMTXR

TX_CLK

tMTXH tMTXF
TXD[3:0]
TX_EN
TX_ER
tMTKHDX

Figure 17. MII Transmit AC Timing Diagram

2.10.2.2.2 MII Receive AC Timing Specifications

Table 37 provides the MII receive AC timing specifications.
Table 37. MII Receive AC Timing Specifications

Parameter/Condition Symbol Min Typ Max Unit Note

RX_CLK clock period 10 Mbps tMRX — 400 — ns 1

RX_CLK clock period 100 Mbps tMRX — 40 — ns 1

RX_CLK duty cycle tMRXH/tMRX 35 — 65 % 2

RXD[3:0], RX_DV, RX_ER setup time to RX_CLK tMRDVKH 10.0 — — ns —

RXD[3:0], RX_DV, RX_ER hold time to RX_CLK tMRDXKH 10.0 — — ns —

RX_CLK clock rise (20%–80%) tMRXR 1.0 — 4.0 ns 2

RX_CLK clock fall time (80%–20%) tMRXF 1.0 — 4.0 ns 2

Note:
1. The frequency of RX_CLK should not exceed the frequency of TX_CLK by more than 300 ppm.
2. System/board must be designed to ensure the input requirement to the device is achieved. Proper device operation is
guaranteed for inputs meeting this requirement by design, simulation, characterization, or functional testing.

Figure 18 provides the AC test load for eTSEC.

Output Z0 = 50 Ω LVDD/2
RL = 50 Ω

Figure 18. eTSEC AC Test Load

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Figure 19 shows the MII receive AC timing diagram.

tMRX tMRXR

RX_CLK

tMRXH tMRXF
RXD[3:0]
RX_DV Valid Data
RX_ER
tMRDVKH
tMRDXKL
Figure 19. MII Receive AC Timing Diagram

2.10.2.3 TBI AC Timing Specifications

This section describes the TBI transmit and receive AC timing specifications.

2.10.2.3.1 TBI Transmit AC Timing Specifications

Table 38 provides the TBI transmit AC timing specifications.
Table 38. TBI Transmit AC Timing Specifications

Parameter Symbol Min Typ Max Unit Note

GTX_CLK clock period tGTX — 8.0 — ns —

TCG[9:0] setup time GTX_CLK going high tTTKHDV 2.0 — — ns —

GTX_CLK to TCG[9:0] delay time tTTKHDX 1.0 — 5.0 ns 1

GTX_CLK rise (20%–80%) tTTXZ 0.7 — 1.0 ns —

GTX_CLK fall time (80%–20%) tTTXF 0.7 — 1.0 ns —

Note:
1. Data valid tTTKHDV to GTX_CLK minimum setup time is a function of clock and maximum hold time
(min setup = cycle time – max delay).

Figure 20 shows the TBI transmit AC timing diagram.

tTTX tTTXR

GTX_CLK
tTTXH
tTTXF
tTTXF

TCG[9:0]

tTTKHDV tTTXR
tTTKHDX

Figure 20. TBI Transmit AC Timing Diagram

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2.10.2.3.2 TBI Receive AC Timing Specifications

Table 39 provides the TBI receive AC timing specifications.
Table 39. TBI Receive AC Timing Specifications

Parameter/Condition Symbol Min Typ Max Unit Note

TSECn_RX_CLK[0:1] clock period tTRX — 16.0 — ns 1

TSECn_RX_CLK[0:1] skew tSKTRX 7.5 — 8.5 ns —

TSECn_RX_CLK[0:1] duty cycle tTRXH/tTRX 40 — 60 % 2

RCG[9:0] setup time to rising PMA_RX_CLK tTRDVKH 2.5 — — ns —

RCG[9:0] hold time to rising PMA_RX_CLK tTRDXKH 1.5 — — ns —

TSECn_RX_CLK[0:1] clock rise time (20%–80%) tTRXR 0.7 — 2.4 ns 2

TSECn_RX_CLK[0:1] clock fall time (80%–20%) tTRXF 0.7 — 2.4 ns 2

Note:
1. The frequency of RX_CLK should not exceed the frequency of TX_CLK by more than 300 ppm.
2. System/board must be designed to ensure the input requirement to the device is achieved. Proper device operation is
guaranteed for inputs meeting this requirement by design, simulation, characterization, or functional testing.

Figure 21 shows the TBI receive AC timing diagram.

tTRX tTRXR

TSECn_RX_CLK1

tTRXH tTRXF

RCG[9:0] Valid Data Valid Data

tTRDVKH
tSKTRX tTRDXKH

TSECn_RX_CLK0

tTRXH tTRDXKH
tTRDVKH

Figure 21. TBI Receive AC Timing Diagram

2.10.2.4 TBI Single-Clock Mode AC Specifications

When the eTSEC is configured for TBI modes, all clocks are supplied from external sources to the relevant eTSEC interface.
In single-clock TBI mode, when a 125-MHz TBI receive clock is supplied on the TSECn pin (no receive clock is used in this
mode, whereas for the dual-clock mode this is the PMA1 receive clock). The 125-MHz transmit clock is applied in all TBI
modes.

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A summary of the single-clock TBI mode AC specifications for receive is shown in Table 40.
Table 40. TBI Single-Clock Mode Receive AC Timing Specifications

Parameter/Condition Symbol Min Typ Max Unit Note

RX_CLK clock period tTRR 7.5 8.0 8.5 ns 1

RX_CLK duty cycle tTRRH 40 50 60 % 2
Rise time RX_CLK (20%–80%) tTRRR — — 1.0 ns —
Fall time RX_CLK (80%–20%) tTRRF — — 1.0 ns —
RCG[9:0] setup time to RX_CLK rising edge tTRRDV 2.0 — — ns 2
RCG[9:0] hold time to RX_CLK rising edge tTRRDX 1.0 — — ns 2
Note:
1. The frequency of RX_CLK should not exceed the frequency of TX_CLK by more than 300 ppm.
2. System/board must be designed to ensure the input requirement to the device is achieved. Proper device operation is
guaranteed for inputs meeting this requirement by design, simulation, characterization, or functional testing.

A timing diagram for TBI receive appears in Figure 22.

.

tTRR tTRRR

RX_CLK

tTRRH tTRRF

RCG[9:0] Valid Data

tTRRDV tTRRDX
Figure 22. TBI Single-Clock Mode Receive AC Timing Diagram

2.10.2.5 RGMII and RTBI AC Timing Specifications

Table 41 presents the RGMII and RTBI AC timing specifications.
Table 41. RGMII and RTBI AC Timing Specifications

Parameter Symbol Min Typ Max Unit Note

Data to clock output skew (at transmitter) tSKRGT_TX –500 0 500 ps 5

Data to clock input skew (at receiver) tSKRGT_RX 1.0 — 2.8 ns 1

Clock period duration tRGT 7.2 8.0 8.8 ns 2

Duty cycle for 10BASE-T and 100BASE-TX tRGTH/tRGT 40 50 60 % 2, 3

Duty cycle for Gigabit tRGTH/tRGT 45 50 55 % —

Rise time (20%–80%) tRGTR — — 0.75 ns 4

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Table 41. RGMII and RTBI AC Timing Specifications (continued)

Parameter Symbol Min Typ Max Unit Note

Fall time (20%–80%) tRGTF — — 0.75 ns 4

Notes:
1. This implies that PC board design requires clocks to be routed such that an additional trace delay of greater than
1.5 ns is added to the associated clock signal.
2. For 10 and 100 Mbps, tRGT scales to 400 ns ± 40 ns and 40 ns ± 4 ns, respectively.
3. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domain
as long as the minimum duty cycle is not violated and stretching occurs for no more than three tRGT of the lowest
speed transitioned between.
4. System/board must be designed to ensure the input requirement to the device is achieved. Proper device operation
is guaranteed for inputs meeting this requirement by design, simulation, characterization, or functional testing.
5. The frequency of RX_CLK should not exceed the frequency of gigabit Ethernet reference clock by more than 300
ppm.

Figure 23 shows the RGMII and RTBI AC timing and multiplexing diagrams.

tRGT
tRGTH
GTX_CLK
(At MAC, output)
tSKRGT_TX tSKRGT_TX
TXD[8:5][3:0] TXD[8:5]
TXD[3:0] TXD[7:4]
TXD[7:4][3:0]
(At MAC, output)

TX_CTL TXD[4] TXD[9]

(At MAC, output) TXEN TXERR
PHY equivalent to tSKRGT_RX PHY equivalent to tSKRGT_RX

TX_CLK
(At PHY, input)

tRGT
tRGTH
RX_CLK
(At PHY, output)

RXD[8:5][3:0] RXD[8:5]
RXD[7:4][3:0] RXD[3:0] RXD[7:4]
(At PHY, output) PHY equivalent to tSKRGT_TX PHY equivalent to tSKRGT_TX

RX_CTL RXD[4] RXD[9]

RXDV RXERR
(At PHY, output)
tSKRGT_RX tSKRGT_RX
RX_CLK
(At MAC, input)

Figure 23. RGMII and RTBI AC Timing and Multiplexing Diagrams

2.10.2.6 RMII AC Timing Specifications

This section describes the RMII transmit and receive AC timing specifications.

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2.10.2.6.1 RMII Transmit AC Timing Specifications

The RMII transmit AC timing specifications are in Table 42.
Table 42. RMII Transmit AC Timing Specifications

Parameter/Condition Symbol Min Typ Max Unit

TSECn_TX_CLK (reference clock) clock period tRMT 15.0 20.0 25.0 ns

TSECn_TX_CLK duty cycle tRMTH 35 50 65 %

Rise time TSECn_TX_CLK (20%–80%) tRMTR 1.0 — 2.0 ns

Fall time TSECn_TX_CLK (80%–20%) tRMTF 1.0 — 2.0 ns

TSECn_TX_CLK to RMII data TXD[1:0], TX_EN delay tRMTDX 2.0 — 10.0 ns

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Figure 24 shows the RMII transmit AC timing diagram.

tRMT tRMTR

TSECn_TX_CLK
(reference clock)
tRMTH tRMTF
TXD[1:0]
TX_EN
TX_ER
tRMTDX
Figure 24. RMII Transmit AC Timing Diagram

2.10.2.6.2 RMII Receive AC Timing Specifications

Table 43 lists the RMII receive AC timing specifications.
Table 43. RMII Receive AC Timing Specifications

Parameter Symbol Min Typ Max Unit Note

TSECn_TX_CLK (reference clock) clock period tRMR 15.0 20.0 25.0 ns —

TSECn_TX_CLK duty cycle tRMRH 35 50 65 % 1

Rise time TSECn_TX_CLK (20%–80%) tRMRR 1.0 — 4.0 ns 1

Fall time TSECn_TX_CLK (80%–20%) tRMRF 1.0 — 4.0 ns 1

RXD[1:0], CRS_DV, RX_ER setup time to TSECn_TX_CLK tRMRDV 4.0 — — ns —

rising edge

RXD[1:0], CRS_DV, RX_ER hold time to TSECn_TX_CLK tRMRDX 2.0 — — ns —

rising edge
Note:
1. System/board must be designed to ensure the input requirement to the device is achieved. Proper device operation is
guaranteed for inputs meeting this requirement by design, simulation, characterization, or functional testing.

Figure 25 provides the AC test load for eTSEC.

Output Z0 = 50 Ω LVDD/2
RL = 50 Ω

Figure 25. eTSEC AC Test Load

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Figure 26 shows the RMII receive AC timing diagram.

tRMR tRMRR

TSECn_TX_CLK

tRMRH tRMRF
RXD[1:0]
CRS_DV Valid Data
RX_ER
tRMRDV
tRMRDX

Figure 26. RMII Receive AC Timing Diagram

2.10.3 SGMII Interface Electrical Characteristics

Each SGMII port features a 4-wire AC-Coupled serial link from the SerDes interface of device, as shown in Figure 27, where
CTX is the external (on board) AC-Coupled capacitor. Each output pin of the SerDes transmitter differential pair features 50-Ω
output impedance. Each input of the SerDes receiver differential pair features 50-Ω on-die termination to SGND_SRDS2
(xcorevss). The reference circuit of the SerDes transmitter and receiver is shown in Figure 57.

2.10.3.1 DC Requirements for SGMII SD_REF_CLK and SD_REF_CLK

The characteristics and DC requirements of the separate SerDes reference clock are described in Section 2.18.2.3, “DC Level
Requirement for SerDes Reference Clocks.”

2.10.3.2 AC Requirements for SGMII SD_REF_CLK and SD_REF_CLK

Note that the SGMII clock requirements for SD_REF_CLK and SD_REF_CLK are intended to be used within the clocking
guidelines specified by Section 2.18.3, “AC Requirements for PCI Express SerDes Reference Clocks.”

2.10.4 SGMII Transmitter Electrical Characteristics

2.10.4.1 SGMII Transmit DC Timing Specifications

Table 44 and Table 45 describe the SGMII SerDes transmitter and receiver AC-Coupled DC electrical characteristics.
Transmitter DC characteristics are measured at the transmitter outputs (SD_TX[n] and SD_TX[n]) as shown in Figure 28.
Table 44. SGMII DC Transmitter Electrical Characteristics

Parameter Symbol Min Typ Max Unit Notes

Output high voltage VOH — — XVDD_SRDS-Typ/2 + mV 1

|VOD|-max/2
Output low voltage VOL XVDD_SRDS-Typ/2 – — — mV 1
|VOD|-max/2

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Table 44. SGMII DC Transmitter Electrical Characteristics (continued)

Parameter Symbol Min Typ Max Unit Notes

Output differential |VOD| 342 525 756 mV Equalization setting: 1.0×

voltage2, 3, 4
313 481 693 Equalization setting: 1.09×
(XVDD-Typ at 1.05V)
285 437 630 Equalization setting: 1.2×

257 394 568 Equalization setting: 1.33×

228 350 504 Equalization setting: 1.5×

200 307 442 Equalization setting: 1.71×

171 262 378 Equalization setting: 2.0×

Output impedance RO 40 50 60 Ω —
(single-ended)
Note:
1. This does not align to DC-coupled SGMII. XVDD_SRDS2-Typ= 1.05 V.
2. |VOD| = |VSDn_TXn – VSDn_TXn|. |VOD| is also referred to as output differential peak voltage. VTX-DIFFp-p = 2 × |VOD|.
3. The |VOD| value shown in the table assumes the following transmit equalization setting in the TXEQ0/1 (for SerDes lanes 0
and 1) or TXEQ2/3 (for SerDes lanes 2 and 3) bit field of device’s SerDes Control Register:
• The MSB (bit 0) of the above bit field is cleared (selecting the full VDD-DIFF-p-p amplitude – power up default).
• The LSB (bit [1:3]) of the above bit field is set based on the equalization setting shown in table.
4. The |VOD| value shown in the Typ column is based on the condition of XVDD_SRDS-Typ = 1.05 V, no common mode offset
variation (VOS = 500 mV), SerDes transmitter is terminated with 100-Ω differential load between SD_TX[n] and SD_TX[n].

50 Ω SD_TX CTX SD_RX

50 Ω
Transmitter Receiver

50 Ω

CTX
SD_TX SD_RXm 50 Ω
P2010 SGMII
SerDes Interface SD_RX CTX SD_TXm 50 Ω

50 Ω
Receiver Transmitter

50 Ω
CTX
50 Ω SD_RX SD_TXm

Figure 27. 4-Wire AC-Coupled SGMII Serial Link Connection Example

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P2010 SGMII
SerDes Interface

50 Ω SD_TXn
50 Ω

Transmitter Vos VOD

50 Ω
50 Ω
SD_TXn

Figure 28. SGMII Transmitter DC Measurement Circuit

2.10.4.2 SGMII DC Receiver Timing Specification

Table 45 lists the SGMII DC receiver electrical characteristics. Source synchronous clocking is not supported. Clock is
recovered from the data.
Table 45. SGMII DC Receiver Electrical Characteristics

Parameter Symbol Min Typ Max Unit Notes

DC Input voltage range — N/A — 1

Input differential voltage LSTS = 001 VRX_DIFFp-p 100 — 1200 mV 2, 3

LSTS = 100 175 —

Loss of signal threshold LSTS = 001 VLOS 30 — 100 mV 3, 4

LSTS = 100 65 — 175

Receiver differential input impedance ZRX_DIFF 80 — 120 Ω —

Note:
1. Input must be externally AC-coupled.
2. VRX_DIFFp-p is also referred to as peak-to-peak input differential voltage.
3. The LSTS shown in the table refers to the LSTS2 or LSTS3 bit field of device’s SerDes Control Register SRDSCR4.
4. The concept of this parameter is equivalent to the Electrical Idle Detect Threshold parameter in PCI Express. Refer to PCI
Express Differential Receiver (Rx) Input Specifications section for further explanation.

2.10.5 SGMII AC Timing Specifications

This section discusses the AC timing specifications for the SGMII interface.

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2.10.5.1 SGMII Transmit AC Timing Specifications

Table 46 provides the SGMII transmit AC timing specifications. A source synchronous clock is not supported. The AC timing
specifications do not include RefClk jitter.
Table 46. SGMII Transmit AC Timing Specifications
At recommended operating conditions with XVDD_SRDS2 = 1.1 V ± 5%.

Parameter Symbol Min Typ Max Unit Notes

Deterministic Jitter JD — — 0.17 UI p-p —

Total Jitter JT — — 0.35 UI p-p 1

Unit Interval UI 799.92 800 800.08 ps 2

AC coupling capacitor CTX 10 100 200 nF 3

Notes:
1. See Figure 30 for single frequency sinusoidal jitter limits.
2. Each UI is 800 ps ± 100 ppm.
3. The external AC coupling capacitor is required. It is recommended that it be placed near the device transmitter outputs.

2.10.6 SGMII AC Measurement Details

Transmitter and receiver AC characteristics are measured at the transmitter outputs (SD_TX[n] and SD_TX[n]) or at the
receiver inputs (SD_RX[n] and SD_RX[n]) as depicted in Figure 29, respectively.

D+ Package
Pin
C = CTX
TX
Silicon
+ Package
C = CTX
D– Package
Pin R = 50 Ω R = 50 Ω

Figure 29. SGMII AC Test/Measurement Load

2.10.6.1 SGMII Receiver AC Timing Specification

Table 47 provides the SGMII receiver AC timing specifications. The AC timing specifications do not include RefClk jitter.
Table 47. SGMII Receive AC Timing Specifications
At recommended operating conditions with XVDD_SRDS2 = 1.1 V ± 5%.

Parameter Symbol Min Typ Max Unit Notes

Deterministic Jitter Tolerance JD 0.37 — — UI p-p 1, 2

Combined Deterministic and Random Jitter Tolerance JDR 0.55 — — UI p-p 1, 2
Total Jitter Tolerance JT 0.65 — — UI p-p 1, 2
Bit Error Ratio BER — — 10-12 — —

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Table 47. SGMII Receive AC Timing Specifications (continued)

At recommended operating conditions with XVDD_SRDS2 = 1.1 V ± 5%.

Parameter Symbol Min Typ Max Unit Notes

Unit Interval UI 799.92 800.00 800.08 ps 3

Notes:
1. Measured at receiver.
3. Refer to RapidIO™ 1×/4× LP Serial Physical Layer Specification for interpretation of jitter specifications.
2. Each UI is 800 ps ± 100 ppm.

The sinusoidal jitter in the total jitter tolerance may have any amplitude and frequency in the unshaded region of Figure 30.

8.5 UI p-p

Sinusoidal
Jitter
Amplitude

0.10 UI p-p

22.1 kHz Frequency 1.875 MHz 20 MHz

Figure 30. Single Frequency Sinusoidal Jitter Limits

2.10.7 Ethernet Management Interface Electrical Characteristics

The electrical characteristics specified here apply to MII management interface signals MDIO (management data input/output)
and MDC (management data clock). The electrical characteristics for GMII, RGMII, RMII, TBI, and RTBI are specified in
“Section 2.10.1, “Enhanced Three-Speed Ethernet Controller (eTSEC) (10/100/1000 Mbps)—
GMII/SGMII/MII/TBI/RGMII/RTBI/RMII Electrical Characteristics.”

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2.10.7.1 MII Management DC Electrical Characteristics

The MDC and MDIO are defined to operate at a supply voltage of 3.3 V or 2.5 V. The DC electrical characteristics for MDIO
and MDC are provided in Table 48 and Table 49. Table 48 provides the electrical characteristics at 3.3 V.
Table 48. MII Management DC Electrical Characteristics (LVDD = 3.3 V)

Parameter Symbol Min Max Unit Notes

Input high voltage VIH 2.0 — V 1

Input low voltage VIL — 0.90 V 1

Input high current (LVDD = Max, VIN = 2.1 V) IIH — 40 μA 2

Input low current (LVDD = Max, VIN = 0.5 V) IIL –40 — μA —

Output high voltage (LVDD = Min, IOH = –1.0 mA) VOH 2.10 — V —

Output low voltage (LVDD = Min, IOL = 1.0 mA) VOL — 0.50 V —

Note:
1. The min VILand max VIH values are based on the respective min and max LVIN values found in Table 3.
2. The symbol VIN, in this case, represents the LVIN symbol referenced in Table 2.

Table 49 shows the electrical characteristics at 2.5 V.

Table 49. MII Management DC Electrical Characteristics (LVDD = 2.5 V)

Parameters Symbol Min Max Unit Notes

Input high voltage VIH 1.70 — V 1

Input low voltage VIL — 0.70 V 1

Input high current (VIN = LVDD) IIH — 40 μA 2

Input low current (VIN = GND) IIL –40 — μA —

Output high voltage (LVDD = Min, IOH = –1.0 mA) VOH 2.00 — V —

Output low voltage (LVDD = Min, IOL = 1.0 mA) VOL — 0.40 V —

Note:
1. The min VILand max VIH values are based on the respective min and max LVIN values found in Table 3.
2. The symbol VIN, in this case, represents the LVIN symbol referenced in Table 2.

2.10.7.2 MII Management AC Electrical Specifications

Table 50 provides the MII management AC timing specifications.
Table 50. MII Management AC Timing Specifications

Parameter/Condition Symbol Min Typ Max Unit Notes

MDC frequency fMDC — 2.5 — MHz 1

MDC period tMDC — 400 — ns —

MDC clock pulse width high tMDCH 160 — — ns —

MDC to MDIO valid tMDKHDV 2 × (tplb_clk × 8) — — ns 2

MDC to MDIO delay tMDKHDX (16 × tplb_clk) – 3 — (16 × tplb_clk) + 3 ns 2, 3, 4

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Table 50. MII Management AC Timing Specifications (continued)

Parameter/Condition Symbol Min Typ Max Unit Notes

MDIO to MDC setup time tMDDVKH 5 — — ns —

MDIO to MDC hold time tMDDXKH 0 — — ns —

MDC rise time tMDCR — — 10 ns —

MDC fall time tMDHF — — 10 ns —

Notes:
1. This parameter is dependent on the system clock speed. (The maximum frequency is the maximum platform frequency
divided by 64.)
2. tplb_clk is the platform (CCB) clock.
3. This parameter is dependent on the platform clock frequency. The delay is equal to 16 platform clock periods ±3 ns. For
example, with a platform clock of 333 MHz, the min/max delay is 48 ns ± 3 ns. Similarly, if the platform clock is 400 MHz, the
min/max delay is 40 ns ± 3 ns).
4. MDC to MDIO Data valid tMDKHDV is a function of clock period and max delay time (tMDKHDX).
(Min setup = cycle time – max delay)

Figure 31 shows the MII management interface timing diagram.

tMDC tMDCR

MDC

tMDCH tMDCF

MDIO
(Input)
tMDDVKH
tMDDXKH
MDIO
(Output)

tMDKHDX
Figure 31. MII Management Interface Timing Diagram

2.10.8 eTSEC IEEE Std 1588 AC Specifications

Table 51 provides the IEEE 1588 AC timing specifications.
Table 51. eTSEC IEEE 1588 AC Timing Specifications

Parameter/Condition Symbol Min Typ Max Unit Notes

TSEC_1588_CLK clock period tT1588CLK 3.3 — TRX_CLK × 7 ns 1, 2

TSEC_1588_CLK duty cycle tT1588CLKH/ 40 50 60 % 3

tT1588CLK

TSEC_1588_CLK peak-to-peak jitter tT1588CLKINJ — — 250 ps —

Rise time eTSEC_1588_CLK (20%–80%) tT1588CLKINR 1.0 — 2.0 ns —

Fall time eTSEC_1588_CLK (80%–20%) tT1588CLKINF 1.0 — 2.0 ns —

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Table 51. eTSEC IEEE 1588 AC Timing Specifications (continued)

Parameter/Condition Symbol Min Typ Max Unit Notes

TSEC_1588_CLK_OUT clock period tT1588CLKOUT 2 × tT1588CLK — — ns —

TSEC_1588_CLK_OUT duty cycle tT1588CLKOTH/ 30 50 70 % —

tT1588CLKOUT

TSEC_1588_PULSE_OUT tT1588OV 0.5 — 3.0 ns —

TSEC_1588_TRIG_IN pulse width tT1588TRIGH 2 × tT1588CLK_MAX — — ns 2

Notes:
1.TRX_CLK is the maximum clock period of eTSEC receiving clock selected by TMR_CTRL[CKSEL]. See the P2010QorIQ
Integrated Processor Reference Manual, for a description of TMR_CTRL registers.
2. The maximum value of tT1588CLK is not only defined by the value of TRX_CLK, but also defined by the recovered clock. For
example, for 10/100/1000 Mbps modes, the maximum value of tT1588CLK will be 2800, 280, and 56 ns, respectively.
3. It needs to be at least two times the clock period of the clock selected by TMR_CTRL[CKSEL]. See the P2010 QorIQ
Integrated Processor Reference Manual, for a description of TMR_CTRL registers.

Figure 32 shows the data and command output AC timing diagram.

tT1588CLKOUT
tT1588CLKOUTH

TSEC_1588_CLK_OUT

tT1588OV

TSEC_1588_PULSE_OUT
TSEC_1588_TRIG_OUT

Note: eTSEC IEEE 1588 Output AC timing: The output delay is counted starting at the rising edge if
tT1588CLKOUT is noninverting. Otherwise, it is counted starting at the falling edge.
Figure 32. eTSEC IEEE 1588 Input AC Timing

Figure 33 shows the data and command input AC timing diagram.

tT1588CLK
tT1588CLKH

TSEC_1588_CLK

TSEC_1588_TRIG_IN

tT1588TRIGH

Figure 33. eTSEC IEEE 1588 Input AC Timing

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2.11 USB
This section provides the AC and DC electrical specifications for the USB interface of the device.

2.11.1 USB DC Electrical Characteristics

Table 52, Table 53, and Table 54 provides the DC electrical characteristics for the USB interface.
Table 52. USB DC Electrical Characteristics (CVDD = 3.3 V)

Parameter Symbol Min Max Unit Notes

High-level input voltage1 VIH 2.0 — V 1

Low-level input voltage VIL — 0.8 V 1

Input current (VIN = 0 V or VIN = CVDD) IIN — ±70 μA 2

High-level output voltage (CVDD = min, IOH = –2 mA) VOH 2.8 — V 3

Low-level output voltage (CVDD = min, IOL = 2 mA) VOL — 0.3 V —

Notes:
1. The min VILand max VIH values are based on the respective min and max CVIN values found in Table 3.
2. The symbol VIN, in this case, represents the CVIN symbol referenced in Section 2.1.2, “Recommended Operating
Conditions.”
3. Not applicable for open drain signals

Table 53. USB DC Electrical Characteristics (CVDD = 2.5 V)

Parameter Symbol Min Max Unit Notes

High-level input voltage1 VIH 1.7 — V 1

Low-level input voltage VIL — 0.7 V 1

Input current (VIN = 0 V or VIN = CVDD) IIN — ±70 μA 2

High-level output voltage (CVDD = min, IOH = –1 mA) VOH 2.0 — V 3

Low-level output voltage (CVDD = min, IOL = 1mA) VOL — 0.4 V —

Notes:
1. The min VILand max VIH values are based on the respective min and max CVIN values found in Table 3.
2. The symbol VIN, in this case, represents the CVIN symbol referenced in Section 2.1.2, “Recommended Operating
Conditions.”
3. Not applicable for open drain signals

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Table 54. USB DC Electrical Characteristics (CVDD = 1.8V)

Parameter Symbol Min Max Unit Notes

High-level input voltage1 VIH 1.25 — V 1

Low-level input voltage VIL — 0.6 V 1

Input current (VIN = 0 V or VIN = CVDD) IIN — ±70 μA 2

High-level output voltage (CVDD = min, IOH = –0.5 mA) VOH 1.35 — V 3

Low-level output voltage (CVDD = min, IOL = 0.5 mA) VOL — 0.4 V —

Notes:
1. The min VILand max VIH values are based on the respective min and max CVIN values found in Table 3.
2. The symbol VIN, in this case, represents the CVIN symbol referenced in Section 2.1.2, “Recommended Operating
Conditions.”
3. Not applicable for open drain signals.

2.11.2 USB AC Electrical Specifications

Table 55 describes the general timing parameters of the USB interface of the device.
Table 55. USB General Timing Parameters6 (ULPI Mode Only)

Parameter Symbol1 Min Max Unit Note

USB clock cycle time tUSCK 15 — ns 2, 3, 4, 5

Input setup to USB clock—all inputs tUSIVKH 4 — ns 2, 3, 4, 5

Input hold to USB clock—all inputs tUSIXKH 1 — ns 2, 3, 4, 5

USB clock to output valid—all outputs tUSKHOV — 7 ns 2, 3, 4, 5

Output hold from USB clock—all outputs tUSKHOX 2 — ns 2, 3, 4, 5

Notes:
1. The symbols for timing specifications follow the pattern of t(First two letters of functional block)(signal)(state) (reference)(state) for inputs
and t(First two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tUSIXKH symbolizes USB timing (US)
for the input (I) to go invalid (X) with respect to the time the USB clock reference (K) goes high (H). Also, tUSKHOX symbolizes
USB timing (US) for the USB clock reference (K) to go high (H) with respect to the output (O) going invalid (X) or output hold
time.
2. All timings are in reference to USB clock.
3. All signals are measured from CVDD ÷ 2 of the rising edge of the USB clock to 0.4 × CVDD of the signal in question for 3.3 V
signaling levels.
4. Input timings are measured at the pin.
5. For active/float timing measurements, the high impedance or off state is defined to be when the total current delivered
through the component pin is less than or equal to that of the leakage current specification.
6. When switching the data pins from outputs to inputs using the USB_DIR pin, the output timings is violated on that cycle
because the output buffers are tristated asynchronously. This should not be a problem, because the PHY should not be
functionally looking at these signals on that cycle as per ULPI specifications.

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Figure 34 and Figure 35 provide the AC test load and signals for the USB, respectively.

Output Z0 = 50 Ω CVDD/2
RL = 50 Ω

Figure 34. USB AC Test Load

USB_CLK
tUSIXKH
tUSIVKH
Input Signals

tUSKHOV tUSKHOX
Output Signals:

Figure 35. USB Signals

Table 56 provides the USB clock input (USB_CLK_IN) AC timing specifications.

Table 56. USB_CLK_IN AC Timing Specifications

Parameter Condition Symbol Min Typ Max Unit

Frequency range Steady state fUSB_CLK_IN 59.97 60 60.03 MHz

Clock frequency tolerance — tCLK_TOL –0.05 0 0.05 %
Reference clock duty cycle Measured at 1.6 V tCLK_DUTY 40 50 60 %
Total input jitter/time Peak-to-peak value measured with a second-order, tCLK_PJ — — 200 ps
interval error high-pass filter of 500-kHz bandwidth

2.12 Enhanced Local Bus

This section describes the DC and AC electrical specifications for the enhanced local bus interface.

2.12.1 Enhanced Local Bus DC Electrical Characteristics

Table 57 provides the DC electrical characteristics for the enhanced local bus interface operating at BVDD = 3.3 V DC.
Table 57. Enhanced Local Bus DC Electrical Characteristics (3.3 V DC)
For recommended operating conditions, see Table 3.

Parameter Symbol Min Max Unit Note

High-level input voltage VIH 2 — V 1

Low-level input voltage VIL — 0.8 V 1

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Table 57. Enhanced Local Bus DC Electrical Characteristics (3.3 V DC) (continued)
For recommended operating conditions, see Table 3.

Parameter Symbol Min Max Unit Note

Input current (VIN1 = 0 V or VIN = BVDD) IIN — ±40 μA 2

High-level output voltage (BVDD = min, IOH = –2 mA) VOH 2.4 — V —

Low-level output voltage (BVDD = min, IOL = 2 mA) VOL — 0.4 V —

Note:
1. The min VILand max VIH values are based on the respective min and max BVIN values found in Table 3.
2. The symbol VIN, in this case, represents the BVIN symbol referenced in Section 2.1.2, “Recommended Operating Conditions.”

Table 58 provides the DC electrical characteristics for the enhanced local bus interface operating at BVDD = 2.5 V DC.
Table 58. Enhanced Local Bus DC Electrical Characteristics (2.5 V DC)
For recommended operating conditions, see Table 3

Parameter Symbol Min Max Unit Note

High-level input voltage VIH 1.70 — V 1

Low-level input voltage VIL — 0.7 V 1

Input current (VIN = 0 V or VIN = BVDD) IIN — ±40 μA 2

High-level output voltage (BVDD = min, IOH = –1 mA) VOH 2.0 — V —

Low-level output voltage (BVDD = min, IOL = 1 mA) VOL — 0.4 V —

Note:
1. The min VILand max VIH values are based on the respective min and max BVIN values found in Table 3.
2. The symbol VIN, in this case, represents the BVIN symbol referenced in Section 2.1.2, “Recommended Operating Conditions.”

Table 59 provides the DC electrical characteristics for the enhanced local bus interface operating at BVDD = 1.8 V DC.
Table 59. Enhanced Local Bus DC Electrical Characteristics (1.8 V DC)
For recommended operating conditions, see Table 3

Parameter Symbol Min Max Unit Note

High-level input voltage VIH 1.25 — V 1

Low-level input voltage VIL — 0.6 V 1

Input current (VIN = 0 V or VIN = BVDD) IIN — ±40 μA 2

High-level output voltage (BVDD = min, IOH = –0.5 mA) VOH 1.35 — V —

Low-level output voltage (BVDD = min, IOL = 0.5 mA) VOL — 0.4 V —

Note:
1. The min VILand max VIH values are based on the respective min and max BVIN values found in Table 3.
2. The symbol VIN, in this case, represents the BVIN symbol referenced in Section 2.1.2, “Recommended Operating Conditions.”

2.12.2 Enhanced Local Bus AC Electrical Specifications

This section describes the AC timing specifications for the enhanced local bus interface.

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2.12.2.1 Test Condition

Figure 36 provides the AC test load for the enhanced local bus.
Figure 36. Enhanced Local Bus AC Test Load

Output Z0 = 50 Ω BVDD/2
RL = 50 Ω

2.12.2.2 Local Bus AC Timing Specifications for PLL Enable Mode

For PLL enable mode, all timings are relative to the rising edge of LSYNC_IN.
Table 60 describes the general timing parameters of the enhanced local bus interface.
Table 60. Enhanced Local Bus Timing Specifications (BVDD = 3.3 V, 2.5 V, and 1.8 V)—PLL Enabled Mode1

Parameter Symbol Min Max Unit Notes

Local bus cycle time tLBK 6.67 12 ns —

Local bus duty cycle tLBKH/tLBK 45 55 % —
LCLK[n] skew to LCLK[m] or LSYNC_OUT tLBKSKEW — 150 ps 2
Input setup tLBIVKH 2 — ns —
Input hold tLBIXKH 0.55 — ns —
Output delay tLBKHOV — 3.8 ns —
(Except LALE)
Output hold tLBKHOX 0.7 — ns —
(Except LALE)
Local bus clock to output high impedance for tLBKHOZ — 3.8 ns 3
LAD/LDP
LALE output negation to LAD/LDP output tLBONOT 1 — eLBC controller 4
transition (LATCH hold time) (LBCR[AHD] = 0) clock cycle
(=1 platform clock
1/2 cycles)
(LBCR[AHD] = 1)
Note:
1. All signals are measured from BVDD ÷ 2 of the rising edge of LSYNC_IN to BVDD ÷ 2 of the signal in question.
2. Skew measured between different LCLK signals at BVDD ÷ 2.
3. For purposes of active/float timing measurements, the high impedance or off state is defined to be when the total current
delivered through the component pin is less than or equal to the leakage current specification.
4. tLBONOT is a measurement of the minimum time between the negation of LALE and any change in LAD. tLBONOT is determined
by LBCR[AHD]. The unit is the eLBC controller clock cycle. The eLBC controller clock refers to the internal clock that runs the
local bus controller, not the external LCLK. LCLK cycle = eLBC controller clock cycle × LCRR[CLKDIV]. After power on reset,
LBCR[AHD] defaults to 0 and eLBC runs at maximum hold time.

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Figure 37 shows the AC timing diagram for PLL-enabled mode.

LSYNC_IN
tLBIXKH
tLBIVKH

Input Signals

tLBKHOV tLBKHOX

Output Signal
(Except LALE)

LAD
(address phase)

tLBONOT

LALE
tLBKHOZ

LAD/LDP
(data phase)

Figure 37. Local Bus AC Timing Diagram (PLL Enabled)

Figure 37 applies to all three controllers that eLBC supports: GPCM, UPM, and FCM.
For input signals, the AC timing data is used directly for all three controllers.

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For output signals, each type of controller provides its own unique method to control the signal timing. The final signal delay
value for output signals is the programmed delay plus the AC timing delay. For example, for GPCM, LCS can be programmed
to delay by tacs (0, ¼, ½, 1, 1 + ¼, 1 + ½, 2, 3 cycles), so the final delay is tacs + tLBKHOV.
Figure 38 shows how the AC timing diagram applies to GPCM. The same principle applies to UPM and FCM.

LSYNC_IN

taddr taddr

LAD[0:31] address read data address write data

tLBONOT tLBONOT
LALE

tarcs + tLBKHOV tawcs + tLBKHOV

LCS_B
tLBKHOX

LGPL2/LOE_B taoe + tLBKHOV

twen
trc tawe+ tLBKHOV
LWE_B
toen
twc

LBCTL

read write
1 taddr is programmable and determined by LCRR[EADC] and ORx[EAD].
2 t
arcs, tawcs, taoe , trc, toen, tawe, twc, twen are determined by ORx. See the P2010reference manual.

Figure 38. GPCM Output Timing Diagram (PLL Enabled)

2.12.2.3 Local Bus AC Timing Specifications for PLL Bypass Mode

All output signal timings are relative to the falling edge of any LCLKs. The external circuit must use the rising edge of the
LCLKs to latch the data.
All input timings except LGTA/LUPWAIT/LFRB are relative to the rising edge of LCLKs. LGTA/LUPWAIT/LFRB are
relative to the falling edge of LCLKs.
Table 61 describes the timing specifications of the local bus interface.

Table 61. Enhanced Local Bus Timing Specifications (BVDD = 3.3 V, 2.5 V, and 1.8 V)-PLL Bypassed
For recommended operating conditions, see Table 3

Parameter Symbol1 Min Max Unit Notes

Local bus cycle time tLBK 12 — ns —

Local bus duty cycle tLBKH/tLBK 45 55 % —
LCLK[n] skew to LCLK[m] tLBKSKEW — 150 ps 2
Input setup tLBIVKH 6 — ns —
(except LGTA/LUPWAIT/LFRB)

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Table 61. Enhanced Local Bus Timing Specifications (BVDD = 3.3 V, 2.5 V, and 1.8 V)-PLL Bypassed
(continued)

Parameter Symbol1 Min Max Unit Notes

Input hold tLBIXKH 1 — ns —

(except LGTA/LUPWAIT/LFRB)
Input setup tLBIVKL 6 — ns —
(for LGTA/LUPWAIT/LFRB)
Input hold tLBIXKL 1 — ns —
(for LGTA/LUPWAIT/LFRB)
Output delay tLBKLOV — 1.5 ns —
(Except LALE)
Output hold tLBKLOX –3.5 — ns 3
(Except LALE)
Local bus clock to output high impedance for tLBKLOZ — 2 ns 4
LAD/LDP
LALE output negation to LAD/LDP output tLBONOT 1 — eLBC controller 5
transition (LATCH hold time) (LBCR[AHD] = 0) clock cycle
(= 1 platform
1/2 clock cycles)
(LBCR[AHD] = 1)
Note:
1. All signals are measured from BVDD/2 of rising/falling edge of LCLK to BVDD/2 of the signal in question.
2. Skew measured between different LCLK signals at BVDD/2.
3. Output hold is negative. This means that output transition happens earlier than the falling edge of LCLK.
4. For purposes of active/float timing measurements, the high impedance or off state is defined to be when the total current
delivered through the component pin is less than or equal to the leakage current specification.
5. tLBONOT is a measurement of the minimum time between the negation of LALE and any change in LAD. tLBONOT is determined
by LBCR[AHD]. The unit is the eLBC controller clock cycle, which is the internal clock that runs the local bus controller, not the
external LCLK. LCLK cycle = eLBC controller clock cycle × LCRR[CLKDIV]. After power on reset, LBCR[AHD] defaults to 0 and
eLBC runs at maximum hold time.

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Figure 39 shows the enhanced local bus signals in PLL-bypass mode.

LCLK[m]
tLBIXKH
tLBIVKH
Input Signals
(Except LGTA/LUPWAIT/LFRB)
tLBIVKL

Input Signal
(LGTA/LUPWAIT/LFRB)
tLBIXKL
tLBKLOV tLBKLOX

Output Signals
(Except LALE)

LAD
(address phase)

tLBONOT

LALE

tLBKLOZ

LAD/LDP
(data phase)

Figure 39. Enhanced Local Bus Signals (PLL Bypass Mode)

Figure 39 applies to all three controllers that eLBC supports: GPCM, UPM, and FCM.
For input signals, the AC timing data is used directly for all three controllers.
For output signals, each type of controller provides its own unique method to control the signal timing. The final signal delay
value for output signals is the programmed delay plus the AC timing delay. For example, for GPCM, LCS can be programmed
to delay by tacs (0, ¼, ½, 1, 1 + ¼, 1 + ½, 2, 3 cycles), so the final delay is tacs + tLBKHOV.

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Figure 40 shows how the AC timing diagram applies to GPCM. The same principle applies to UPM and FCM.

LCLK

taddr taddr

LAD[0:31] address read data address write data

tLBONOT tLBONOT

LALE

tarcs + tLBKLOV tawcs + tLBKLOV

LCS_B
tLBKLOX

LGPL2/LOE_B taoe + tLBKLOV

twen
trc tawe + tLBKLOV
LWE_B
toen
twc

LBCTL

read write

1
taddr is programmable and determined by LCRR[EADC] and ORx[EAD].
2
tarcs, tawcs, taoe, trc, toen, tawe, twc, twen are determined by ORx. See the P2010reference manual.

Figure 40. GPCM Output Timing Diagram

2.13 Enhanced Secure Digital Host Controller (eSDHC)

This section describes the DC and AC electrical specifications for the eSDHC (SDIO) interface.

2.13.1 eSDHC DC Electrical Characteristics

Table 62 provides the DC electrical characteristics for the eSDHC (SDIO) interface.
Table 62. eSDHC Interface DC Electrical Characteristics (CVDD = 3.3 V)

Parameter Symbol Condition Min Max Unit Note

Input high voltage VIH — 0.625 × CVDD — V 1

Input low voltage VIL — — 0.25 × CVDD V 1

Output high voltage VOH IOH = –100 uA at 0.75 × CVDD — V —

OVDDmin

Output low voltage VOL IOL = 100uA at — 0.125 × CVDD V —

OVDDmin

Output high voltage VOH IOH = –100 uA CVDD-0.2 — V 2

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Table 62. eSDHC Interface DC Electrical Characteristics (continued)(CVDD = 3.3 V)

Parameter Symbol Condition Min Max Unit Note

Output low voltage VOL IOL = 2 mA — 0.3 V 2

Input leakage current IIN — –70 70 uA —

Note:
1. Note that the min VILand max VIH values are based on the respective min and max OVIN values found in Table 3
2. Open drain mode for MMC cards only.

2.13.2 eSDHC AC Timing Specifications

This section describes the AC electrical specifications for the eSDHC (SDIO) interface. Table 63 provides the eSDHC AC
timing specifications for full speed mode as defined in Figure 41 and Figure 42.
Table 63. eSDHC AC Timing Specifications

Parameter Symbol1 Min Max Unit Notes

SD_CLK clock frequency fSHSCK 0 MHz 2, 3

SD Full-speed/High-speed mode 25/50
MMC Full-speed/High-speed mode 20/52

SD_CLK clock low time—Full-speed mode/High-speed mode tSHSCKL 10/7 — ns 3

SD_CLK clock high time—Full-speed mode/High-speed mode tSHSCKH 10/7 — ns 3

SD_CLK clock rise and fall times tSHSCKR/ — 3 ns 3

tSHSCKF

Input setup times: SD_CMD, SD_DATX, SD_CD to SD_CLK tSHSIVKH 3.7 — ns 3, 4, 5

Input hold times: SD_CMD, SD_DATX, SD_CD to SD_CLK tSHSIXKH 2.5 — ns 3

Output delay time: SD_CLK to SD_CMD, SD_DATx valid tSHSKHOV –3 3 ns 3, 5

Notes:
1. The symbols used for timing specifications herein follow the pattern of t(first three letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first three letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tFHSKHOV
symbolizes eSDHC high speed mode device timing (SHS) clock reference (K) going to the high (H) state, with respect to the
output (O) reaching the invalid state (X) or output hold time. Note that, in general, the clock reference symbol representation
is based on five letters representing the clock of a particular functional. For rise and fall times, the latter convention is used
with the appropriate letter: R (rise) or F (fall).
2. In full speed mode, clock frequency value can be 0–25 MHz for a SD/SDIO card and 0–20 MHz for a MMC card. In high speed
mode, clock frequency value can be 0–50 MHz for a SD/SDIO card and 0–52 MHz for a MMC card.
3. CCARD ≤ 10 pF, (1 card), and CL = CBUS + CHOST + CCARD ≤ 40 pF
4. To satisfy setup timing, one way board routing delay between Host and Card, on SD_CLK, SD_CMD, and SD_DATx should
not exceed 0.65ns.
5. The parameter values apply to both full speed and high speed modes.

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This figure provides the eSDHC clock input timing diagram.

eSDCH
VM VM VM
External Clock
operational mode tSHSCKL tSHSCKH

tSHSCK
tSHSCKR tSHSCKF
VM = Midpoint Voltage (CVDD/2)
Figure 41. eSDHC Clock Input Timing Diagram

This figure provides the data and command input/output timing diagram.

VM VM VM VM
SD_CK
External Clock
tSHSIVKH tSHSIXKH

SD_DAT/CMD
Inputs

SD_DAT/CMD
Outputs

tSHSKHOV
VM = Midpoint Voltage (CVDD/2)

Figure 42. eSDHC Data and Command Input/Output Timing Diagram Referenced to Clock

2.14 Programmable Interrupt Controller

In IRQ edge trigger mode, when an external interrupt signal is asserted (according to the programmed polarity), it must remain
the assertion for at least 3 system clocks (SYSCLK periods).

2.14.1 PIC DC Electrical Characteristics

Table 66 provides the DC electrical characteristics for the PIC interface.
Table 64. PIC DC Electrical Characteristics

Parameter Symbol 1 Min Max Unit Note

High-level input voltage VIH 2 — V 1

Low-level input voltage VIL — 0.8 V 1
Input current (OVIN = 0 V or OVIN = OVDD) IIN — ±40 μA 2
High-level output voltage (OVDD = min, IOH = –2 mA) VOH 2.4 — V —
Low-level output voltage (OVDD = min, IOL = 2 mA) VOL — 0.4 V —
Notes:
1. Note that the min VILand max VIH values are based on the respective min and max OVIN values found in Table 3.
2. Note that the symbol OVIN represents the input voltage of the supply. It is referenced in Table 3.

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2.14.2 PIC AC Electrical Characteristics

Table 65 shows the PIC AC timing specifications.
Table 65. PIC Input AC Timing Specifications

Parameter Symbol Min Max Unit Notes

PIC inputs—minimum pulse width tPIWID 3 — SYSCLK 1

Note:
1. PIC inputs and outputs are asynchronous to any visible clock. PIC outputs must be synchronized before use by any external
synchronous logic. PIC inputs are required to be valid for at least tPIWID ns to ensure proper operation when working in
edge-triggered mode.

2.15 JTAG
This section discusses the JTAG interface.

2.15.1 JTAG DC Electrical Characteristics

Table 66 provides the DC electrical characteristics for the JTAG interface.
Table 66. JTAG DC Electrical Characteristics

Parameter Symbol 1 Min Max Unit Note

High-level input voltage VIH 2 — V 1

Low-level input voltage VIL — 0.8 V 1
Input current IIN — ±40 μA 2
(VIN1 = 0 V or VIN = OVDD)
High-level output voltage VOH 2.4 — V —
(OVDD = min, IOH = –2 mA)
Low-level output voltage VOL — 0.4 V —
(OVDD = min, IOL = 2 mA)
Notes:
1. Note that the min VILand max VIH values are based on the respective min and max OVIN values found in Table 3.
2. Note that the symbol VIN, in this case, represents the OVIN symbol found in Table 3.

2.15.2 JTAG AC Electrical Specifications

This section describes the AC electrical specifications for the IEEE Std 1149.1™ (JTAG) interface of the device.
This table provides the JTAG AC timing specifications as defined in Figure 44 through Figure 46.
Table 67. JTAG AC Timing Specifications (Independent of SYSCLK)
At recommended operating conditions (see Table 3).

Parameter Symbol1 Min Max Unit Notes

JTAG external clock frequency of operation fJTG 0 33.3 MHz —

JTAG external clock cycle time t JTG 30 — ns —

JTAG external clock pulse width measured at OVDD/2 tJTKHKL 15 — ns —

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Table 67. JTAG AC Timing Specifications (Independent of SYSCLK) (continued)

At recommended operating conditions (see Table 3).

Parameter Symbol1 Min Max Unit Notes

JTAG external clock rise and fall times tJTGR & tJTGF 0 2 ns —

TRST assert time tTRST 25 — ns 2

Input setup times tJTDVKH 4 — ns —

Input hold times tJTDXKH 10 — ns —

Output valid times tJTKLDV 0 10 ns 3

Output hold times tJTKLDX 0 — ns 3

Notes:
1. The symbols used for timing specifications follow the pattern t(first two letters of functional block)(signal)(state)(reference)(state) for inputs
and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tJTDVKH symbolizes JTAG device timing
(JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the tJTG clock reference (K) going
to the high (H) state or setup time. Also, tJTDXKH symbolizes JTAG timing (JT) with respect to the time data input signals (D)
reaching the invalid state (X) relative to the tJTG clock reference (K) going to the high (H) state. Note that in general, the clock
reference symbol representation is based on three letters representing the clock of a particular functional. For rise and fall
times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
2. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
3. All outputs are measured from the midpoint voltage of the falling/rising edge of tTCLK to the midpoint of the signal in question.
The output timings are measured at the pins. All output timings assume a purely resistive 50-Ω load. Time-of-flight delays
must be added for trace lengths, vias, and connectors in the system.

Figure 43 provides the AC test load for TDO and the boundary-scan outputs.

Output Z0 = 50 Ω OVDD/2
RL = 50 Ω

Figure 43. AC Test Load for the JTAG Interface

Figure 44 provides the JTAG clock input timing diagram.

JTAG
VM VM VM
External Clock

tJTKHKL tJTGR
tJTG tJTGF

VM = Midpoint Voltage (OVDD/2)

Figure 44. JTAG Clock Input Timing Diagram

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Figure 45 provides the TRST timing diagram.

TRST VM VM

tTRST

VM = Midpoint Voltage (OVDD/2)

Figure 45. TRST Timing Diagram

Figure 46 provides the boundary-scan timing diagram.

JTAG
External Clock VM VM
tJTDVKH
tJTDXKH
Boundary Input
Data Inputs Data Valid
tJTKLDV
tJTKLDX
Boundary
Output Data Valid
Data Outputs

VM = Midpoint Voltage (OVDD/2)

Figure 46. Boundary-Scan Timing Diagram

2.16 I2C
This section describes the DC and AC electrical characteristics for the I2C interfaces of the device.

2.16.1 I2C DC Electrical Characteristics

Table 68 provides the DC electrical characteristics for the I2C interfaces.
Table 68. I2C DC Electrical Characteristics

Parameter Symbol Min Max Unit Notes

Input high voltage level VIH 2 — V 1

Input low voltage level VIL — 0.8 V 1

Output Low voltage (OVDD = min, IOL = 2 mA) VOL 0 0.4 V 2

Pulse width of spikes which must be suppressed tI2KHKL 0 50 ns 3

by the input filter

Input current each I/O pin (input voltage is II –40 40 μA 4

between 0.1 × OVDD and 0.9 × OVDD(max)

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Table 68. I2C DC Electrical Characteristics (continued)

Parameter Symbol Min Max Unit Notes

Capacitance for each I/O pin CI — 10 pF —

Notes:
1. Note that the min VILand max VIH values are based on the respective min and max OVIN values found in Table 3.
2. Output voltage (open drain or open collector) condition = 3 mA sink current.
3. See the P2020 QorIQ Integrated Communications Host Processor Family Reference Manual for information on the digital
filter used.
4. I/O pins obstruct the SDA and SCL lines if OVDD is switched off.

2.16.2 I2C AC Electrical Specifications

Table 69 provides the AC timing parameters for the I2C interfaces.
Table 69. I2C AC Electrical Specifications
At recommended operating conditions with OVDD of 3.3 V ± 5%. All values refer to VIH (min) and VIL (max) levels (see Table 68).

Parameter Symbol1 Min Max Unit Note

SCL clock frequency fI2C 0 400 kHz4 2

Low period of the SCL clock tI2CL 1.3 — μs —

High period of the SCL clock tI2CH 0.6 — μs —

Setup time for a repeated START tI2SVKH 0.6 — μs —

condition

Hold time (repeated) START condition tI2SXKL 0.6 — μs —

(after this period, the first clock pulse is
generated)

Data setup time tI2DVKH 100 — ns —

Data input hold time: tI2DXKL μs 3

CBUS compatible masters — —
I2C bus devices 0 —

Data output delay time tI2OVKL — 0.9 μs 4

Set-up time for STOP condition tI2PVKH 0.6 — μs —

Bus free time between a STOP and tI2KHDX 1.3 — μs —

START condition
Noise margin at the LOW level for each VNL 0.1 × OVDD — V —
connected device (including hysteresis)
Noise margin at the HIGH level for each VNH 0.2 × OVDD — V —
connected device (including hysteresis)

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Table 69. I2C AC Electrical Specifications (continued)

At recommended operating conditions with OVDD of 3.3 V ± 5%. All values refer to VIH (min) and VIL (max) levels (see Table 68).

Parameter Symbol1 Min Max Unit Note

Capacitive load for each bus line Cb — 400 pF —

Note:
1. The symbols used for timing specifications herein follow the pattern t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tI2DVKH symbolizes I2C timing (I2)
with respect to the time data input signals (D) reaching the valid state (V) relative to the tI2C clock reference (K) going to the
high (H) state or setup time. Also, tI2SXKL symbolizes I2C timing (I2) for the time that the data with respect to the START
condition (S) went invalid (X) relative to the tI2C clock reference (K) going to the low (L) state or hold time. Also, tI2PVKH
symbolizes I2C timing (I2) for the time that the data with respect to the STOP condition (P) reaches the valid state (V) relative
to the tI2C clock reference (K) going to the high (H) state or setup time.
2. The requirements for I2C frequency calculation must be followed. Refer to NXP application note AN2919, “Determining the
I2C Frequency Divider Ratio for SCL.”
3. As a transmitter, the device provides a delay time of at least 300 ns for the SDA signal (referred to as the VIHmin of the SCL
signal) to bridge the undefined region of the falling edge of SCL to avoid unintended generation of a START or STOP
condition. When the device acts as the I2C bus master while transmitting, it drives both SCL and SDA. As long as the load
on SCL and SDA are balanced, the device does not generate an unintended START or STOP condition. Therefore, the 300
ns SDA output delay time is not a concern. If under some rare condition, the 300 ns SDA output delay time is required for the
device as transmitter, application note AN2919, referred to in note 2 above, is recommended.
4. The maximum tI2OVKL must be met only if the device does not stretch the LOW period (tI2CL) of the SCL signal.

Figure 47 provides the AC test load for the I2C.

Output Z0 = 50 Ω OVDD/2
RL = 50 Ω

Figure 47. I2C AC Test Load

Figure 48 shows the AC timing diagram for the I2C bus.

SDA
tI2DVKH tI2KHKL tI2KHDX
tI2CL tI2SXKL

SCL
tI2SXKL tI2CH tI2SVKH tI2PVKH
tI2DXKL,tI2OVKL
S Sr P S

Figure 48. I2C Bus AC Timing Diagram

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2.17 GPIO
This section describes the DC and AC electrical specifications for the GPOUT and GPIN interface of the device.

2.17.1 GPIO DC Electrical Characteristics

Table 70 provides the DC electrical characteristics for the GPIO interface.
Table 70. PIO[0:7] DC Electrical Characteristics (3.3 V)

Parameter Symbol Min Max Unit Notes

High-level input voltage VIH 2 — V 1, 2

Low-level input voltage VIL — 0.8 V 1, 2

1
Input current (VIN = 0 V or VIN = VDD) IIN — ±40 μA —

High-level output voltage (OVDD = min, IOH = –2 mA) VOH 2.4 — V —

Low-level output voltage (OVDD = min, IOL = 2mA) VOL — 0.4 V —

Note:
1. The min VILand max VIH values are based on the min and max OVIN respective values found in Table 2.
2. The symbol OVIN represents the input voltage of the supply. It is referenced in Table 2.

Table 71. GPIO[8:15] DC Electrical Characteristics (3.3 V)

Parameter Symbol Min Max Unit Notes

High-level input voltage VIH 2 — V 1, 2

Low-level input voltage VIL — 0.8 V 1, 2

1
Input current (VIN = 0 V or VIN = VDD) IIN — ±40 μA —

High-level output voltage (BVDD = min, IOH = –2 mA) VOH 2.4 — V —

Low-level output voltage (BVDD = min, IOL = 2mA) VOL — 0.4 V —

Note:
1. The min VILand max VIH values are based on the min and max OVIN respective values found in Table 2.
2. The symbol OVIN represents the input voltage of the supply. It is referenced in Table 2.

Table 72. GPIO[8:15] DC Electrical Characteristics (2.5 V)

Parameter Symbol Min Max Unit Notes

High-level input voltage VIH 1.7 — V 1, 2

Low-level input voltage VIL — 0.7 V 1, 2

Input current (VIN1 = 0 V or VIN = VDD) IIN — ±40 μA —

High-level output voltage (BVDD = mn, IOH = –1 mA) VOH 1.7 — V —

Low-level output voltage (BVDD = min, IOL = 1 mA) VOL — 0.7 V —

Note:
1. The min VILand max VIH values are based on the min and max OVIN respective values found in Table 2.
2. The symbol OVIN represents the input voltage of the supply. It is referenced in Table 2.

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Table 73. GPIO[8:15] DC Electrical Characteristics (1.8 V)

Parameter Symbol Min Max Unit Notes

High-level input voltage VIH 1.2 — V 1, 2

Low-level input voltage VIL — 0.6 V 1, 2

Input current (VIN1 = 0 V or VIN = VDD) IIN — ±40 μA —

High-level output voltage (BVDD = mn, IOH = –0.5 mA) VOH 1.35 — V —

Low-level output voltage (BVDD = min, IOL = 0.5 mA) VOL — 0.4 V —

Note:
1.The min VILand max VIH values are based on the min and max OVIN respective values found in Table 2.
2. The symbol OVIN represents the input voltage of the supply. It is referenced in Table 2.

2.17.2 GPIO AC Electrical Specifications

Table 74 provides the GPIO input and output AC timing specifications.
Table 74. GPIO Input and Output AC Timing Specifications1

Characteristic Symbol 2 Min Unit Notes

GPIO inputs—minimum pulse width tPIWID 1.5 × plat ÷ 2 ns 1

Notes:
1. GPIO inputs and outputs are asynchronous to any visible clock. GPIO outputs must be synchronized before use by any
external synchronous logic. GPIO inputs are required to be valid for at least tPIWID ns to ensure proper operation.

Figure 49 provides the AC test load for the GPIO.

Output Z0 = 50 Ω OVDD/2
RL = 50 Ω

Figure 49. GPIO AC Test Load

2.18 High-Speed Serial Interfaces (HSSI)

The device features one Serializer/Deserializer (SerDes) interfaces to be used for high-speed serial interconnect applications.
The SerDes interface can be used for PCI Express SGMII and/or Serial RapidIO data transfers.
This section describes the common portion of SerDes DC electrical specifications, which is the DC requirement for SerDes
Reference Clocks. The SerDes data lane’s transmitter and receiver reference circuits are also shown.

2.18.1 Signal Terms Definition

The SerDes utilizes differential signaling to transfer data across the serial link. This section defines terms used in the description
and specification of differential signals.

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Figure 50 shows how the signals are defined. For illustration purposes, only one SerDes lane is used for description. Figure 50
shows the waveform for either a transmitter output (SD_TX and SD_TX) or a receiver input (SD_RX and SD_RX). Each signal
swings between A Volts and B Volts where A > B.

SD_TX or
SD_RX
A Volts

Vcm = (A + B)÷2
SD_TX or
SD_RX
B Volts

Differential Swing, VID or VOD = A – B

Differential Peak Voltage, VDIFFp = |A – B|

Differential Peak-Peak Voltage, VDIFFpp = 2 × VDIFFp (not shown)

Figure 50. Differential Voltage Definitions for Transmitter or Receiver

Using this waveform, the definitions are as follows. To simplify the illustration, the following definitions assume that the
SerDes transmitter and receiver operate in a fully symmetrical differential signaling environment:
Single-Ended Swing
The transmitter output signals and the receiver input signals SD_TX, SD_TX, SD_RX and SD_RX
each have a peak-to-peak swing of A – B Volts. This is also referred as each signal wire’s
Single-Ended Swing.
Differential Output Voltage, VOD (or Differential Output Swing)
The Differential Output Voltage (or Swing) of the transmitter, VOD, is defined as the difference of
the two complimentary output voltages: VSDn_TX – VSDn_TX. The VOD value can be either positive
or negative.
Differential Input Voltage, VID (or Differential Input Swing)
The Differential Input Voltage (or Swing) of the receiver, VID, is defined as the difference of the
two complimentary input voltages: VSDn_RX – VSDn_RX. The VID value can be either positive or
negative.
Differential Peak Voltage, VDIFFp
The peak value of the differential transmitter output signal or the differential receiver input signal
is defined as Differential Peak Voltage, VDIFFp = |A – B| Volts.
Differential Peak-to-Peak, VDIFFp-p
Since the differential output signal of the transmitter and the differential input signal of the receiver
each range from A – B to –(A – B) Volts, the peak-to-peak value of the differential transmitter
output signal or the differential receiver input signal is defined as Differential Peak-to-Peak
Voltage, VDIFFp-p = 2 × VDIFFp = 2 × |(A - B)| Volts, which is twice of differential swing in
amplitude, or twice of the differential peak. For example, the output differential peak-peak voltage
can also be calculated as VTX-DIFFp-p = 2 × |VOD|.
Differential Waveform
The differential waveform is constructed by subtracting the inverting signal (SD_TX, for example)
from the non-inverting signal (SD_TX, for example) within a differential pair. There is only one
signal trace curve in a differential waveform. The voltage represented in the differential waveform
is not referenced to ground. Refer to Figure 50 as an example for differential waveform.

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Common Mode Voltage, Vcm

The Common Mode Voltage is equal to one half of the sum of the voltages between each conductor
of a balanced interchange circuit and ground. In this example, for SerDes output,
Vcm_out = (VSDn_TX + VSDn_TX) ÷ 2 = (A + B) ÷ 2, which is the arithmetic mean of the two
complimentary output voltages within a differential pair. In a system, the common mode voltage
may often differ from one component’s output to the other’s input. It may be different between the
receiver input and driver output circuits within the same component. It is also referred to as the DC
offset on some occasions.
To illustrate these definitions using real values, consider the case of a current mode logic (CML) transmitter that has a common
mode voltage of 2.25 V and each of its outputs, TD and TD, has a swing that goes between 2.5 V and 2.0 V. Using these values,
the peak-to-peak voltage swing of each signal (TD or TD) is 500 mV p-p, which is referred to as the single-ended swing for
each signal. In this example, because the differential signaling environment is fully symmetrical, the transmitter output’s
differential swing (VOD) has the same amplitude as each signal’s single-ended swing. The differential output signal ranges
between 500 mV and –500 mV. In other words, VOD is 500 mV in one phase and –500 mV in the other phase. The peak
differential voltage (VDIFFp) is 500 mV. The peak-to-peak differential voltage (VDIFFp-p) is 1000 mV p-p.

2.18.2 SerDes Reference Clocks

The SerDes reference clock inputs are applied to an internal PLL whose output creates the clock used by the corresponding
SerDes lanes. The SerDes reference clocks inputs are SD_REF_CLK and SD_REF_CLK for PCI Express and Serial RapidIO,
or SD_REF_CLK and SD_REF_CLK for the SGMII interface respectively.
The following sections describe the SerDes reference clock requirements and some application information.

2.18.2.1 SerDes Spread Spectrum Clock Source Recommendations

SD_REF_CLK/SD_REF_CLK are designed to work with spread spectrum clock for PCI Express protocol only with the
spreading specification defined in Table 75. When using spread spectrum clocking for PCI Express, both ends of the link
partners should use the same reference clock. For best results, a source without significant unintended modulation should be
used.
The spread spectrum clocking cannot be used if the same SerDes reference clock is shared with other non-spread spectrum
supported protocols. For example, if the spread spectrum clocking is desired on a SerDes reference clock for PCI Express and
the same reference clock is used for any other protocol such as SGMII/SRIO due to the SerDes lane usage mapping option,
spread spectrum clocking cannot be used at all.
Table 75. SerDes Spread Spectrum Clock Source Recommendations
At recommended operating conditions. See Table 3.

Parameter Min Max Unit Notes

Frequency modulation 30 33 kHz —

Frequency spread +0 –0.5 % 1

Note:
1. Only down spreading is allowed.

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2.18.2.2 SerDes Reference Clock Receiver Characteristics

Figure 51 shows a receiver reference diagram of the SerDes reference clocks.

50 Ω

SD_REF_CLK

Input
Amp
SD_REF_CLK

50 Ω

Figure 51. Receiver of SerDes Reference Clocks

The characteristics are as follows:

• The supply voltage requirements for XVDD_SRDS2 are specified in Table 2 and Table 3.
• The SerDes reference clock receiver reference circuit structure is as follows:
— The SD_REF_CLK and SD_REF_CLK are internally AC-coupled differential inputs as shown in Figure 51. Each
differential clock input (SD_REF_CLK or SD_REF_CLK) has on-chip 50-Ω termination to SGND_SRDSn
(xcorevss) followed by on-chip AC-coupling.
— The external reference clock driver must be able to drive this termination.
— The SerDes reference clock input can be either differential or single-ended. Refer to the Differential Mode and
Single-ended Mode description below for further detailed requirements.
• The maximum average current requirement that also determines the common mode voltage range is the following:
— When the SerDes reference clock differential inputs are DC coupled externally with the clock driver chip, the
maximum average current allowed for each input pin is 8 mA. In this case, the exact common mode input voltage
is not critical as long as it is within the range allowed by the maximum average current of 8 mA (refer to the
following bullet for more detail), because the input is AC-coupled on-chip.
— This current limitation sets the maximum common mode input voltage to be less than 0.4 V (0.4 V/50 = 8 mA)
while the minimum common mode input level is 0.1 V above SGND_SRDSn (xcorevss). For example, a clock
with a 50/50 duty cycle can be produced by a clock driver with output driven by its current source from 0 mA to
16 mA (0–0.8 V), such that each phase of the differential input has a single-ended swing from 0 V to 800 mV with
the common mode voltage at 400 mV.
— If the device driving the SD_REF_CLK and SD_REF_CLK inputs cannot drive 50 Ω to SGND_SRDSn
(xcorevss) DC, or it exceeds the maximum input current limitations, then it must be AC-coupled off-chip.
• The input amplitude requirement is as follows:
— This requirement is described in detail in the following sections.

2.18.2.3 DC Level Requirement for SerDes Reference Clocks

The DC level requirement for the device SerDes reference clock inputs is different depending on the signaling mode used to
connect the clock driver chip and SerDes reference clock inputs as described below:
• Differential Mode
— The input amplitude of the differential clock must be between 400 mV and 1600 mV differential peak-peak (or
between 200 mV and 800 mV differential peak). In other words, each signal wire of the differential pair must have

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a single-ended swing less than 800 mV and greater than 200 mV. This requirement is the same for both external
DC-coupled or AC-coupled connection.
— For external DC-coupled connection, as described in Section 2.18.2.2, “SerDes Reference Clock Receiver
Characteristics,” the maximum average current requirements sets the requirement for average voltage (common
mode voltage) to be between 100 mV and 400 mV. Figure 52 shows the SerDes reference clock input requirement
for DC-coupled connection scheme.
200 mV < Input Amplitude or Differential Peak < 800 mV
SD_REF_CLK
Vmax < 800 mV

100 mV < Vcm < 400 mV

SD_REF_CLK
Vmin >0V
Figure 52. Differential Reference Clock Input DC Requirements (External DC-Coupled)

— For external AC-coupled connection, there is no common mode voltage requirement for the clock driver. Since
the external AC-coupling capacitor blocks the DC level, the clock driver and the SerDes reference clock receiver
operate in different command mode voltages. The SerDes reference clock receiver in this connection scheme has
its common mode voltage set to SGND_SRDSn. Each signal wire of the differential inputs is allowed to swing
below and above the command mode voltage (SGND_SRDSn). Figure 53 shows the SerDes reference clock input
requirement for AC-coupled connection scheme.
—

200 mV < Input Amplitude or Differential Peak < 800 mV

SD_REF_CLK
Vmax < Vcm + 400 mV

Vcm

SD_REF_CLK Vmin > Vcm – 400

Figure 53. Differential Reference Clock Input DC Requirements (External AC-Coupled)

• Single-ended Mode
— The reference clock can also be single-ended. The SD_REF_CLK input amplitude (single-ended swing) must be
between 400 mV and 800 mV peak-peak (from VMIN to VMAX) with SD_REF_CLK either left unconnected or
tied to ground.
— The SD_REF_CLK input average voltage must be between 200 and 400 mV. Figure 54 shows the SerDes
reference clock input requirement for single-ended signaling mode.
— To meet the input amplitude requirement, the reference clock inputs might need to be DC or AC-coupled
externally. For the best noise performance, the reference of the clock could be DC or AC-coupled into the unused
phase (SD_REF_CLK) through the same source impedance as the clock input (SD_REF_CLK) in use.

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400 mV < SD_REF_CLK Input Amplitude < 800 mV

SD_REF_CLK

0V

SD_REF_CLK
Figure 54. Single-Ended Reference Clock Input DC Requirements

2.18.3 AC Requirements for PCI Express SerDes Reference Clocks

Table 76 lists AC requirements for the PCI Express, SGMII, and SRIO SerDes reference clocks to be guaranteed by the
customer’s application design.
Table 76. SD_REF_CLK and SD_REF_CLK Input Clock Requirements

Parameter Symbol Min Typical Max Unit Notes

SD_REF_CLK/ SD_REF_CLK frequency range tCLK_REF — 100/125 — MHz 1

SD_REF_CLK/ SD_REF_CLK clock frequency tolerance tCLK_TOL –350 — +350 ppm —

SD_REF_CLK/ SD_REF_CLK reference clock duty cycle tCLK_DUTY 40 50 60 % 7

SD_REF_CLK/ SD_REF_CLK max deterministic tCLK_DJ — — 42 ps 6

peak-peak Jitter @ 10-6 BER

SD_REF_CLK/ SD_REF_CLK total reference clock jitter @ tCLK_TJ — — 86 ps 2, 6

10-6 BER (Peak-to-peak jitter at refClk input)

SD_REF_CLK/SD_REF_CLK rising/falling edge rate tCLKRR/tCLKFR 1 — 4 V/ns 3, 6

Differential input high voltage VIH 200 — — mV 3

Differential input low voltage VIL — — –200 mV 3

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Table 76. SD_REF_CLK and SD_REF_CLK Input Clock Requirements (continued)

Parameter Symbol Min Typical Max Unit Notes

Rising edge rate (SD_REF_CLK) to falling edge rate Rise-Fall Matching — — 20 % 4, 5, 6

(SD_REF_CLK) matching

Notes:
1. Caution: Only 100 and 125 have been tested. In-between values do not work correctly with the rest of the system.
2. Limits from PCI Express CEM Rev 2.0
3. Measured from –200 mV to +200 mV on the differential waveform (derived from SD_REF_CLK minus SD_REF_CLK). The
signal must be monotonic through the measurement region for rise and fall time. The 400 mV measurement window is
centered on the differential zero crossing. See Figure 55.
4. Measurement taken from single-ended waveform.
5. Matching applies to rising edge for SD_REF_CLK and falling edge rate for SD_REF_CLK. It is measured using a 200 mV
window centered on the median cross point where SD_REF_CLK rising meets SD_REF_CLK falling. The median cross point
is used to calculate the voltage thresholds that the oscilloscope uses for the edge rate calculations. The rise edge rate of
SD_REF_CLK must be compared to the fall edge rate of SD_REF_CLK, the maximum allowed difference should not exceed
20% of the slowest edge rate. See Figure 56.
6. System/board must be designed to ensure the input requirement to the device is achieved. Proper device operation is
guaranteed for inputs meeting this requirement by design, simulation, characterization, or functional testing.
7. Measurement taken from the differential waveform.

Figure 55 shows the differential measurement points for rise and fall time.

Rise Edge Rate Fall Edge Rate

VIH = +200 mV
0.0 V
VIL = –200 mV
SD_REF_CLK –
SD_REF_CLK

Figure 55. Differential Measurement Points for Rise and Fall Time

Figure 56 shows the single-ended measurement points for rise and fall time matching.

Figure 56. Single-Ended Measurement Points for Rise and Fall Time Matching

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2.18.4 SerDes Transmitter and Receiver Reference Circuits

Figure 57 shows the reference circuits for SerDes data lane’s transmitter and receiver.

SD_TXn SD_RXn

50 Ω

50 Ω
Transmitter Receiver

50 Ω

SD_TXn SD_RXn 50 Ω

Figure 57. SerDes Transmitter and Receiver Reference Circuits

The DC and AC specification of SerDes data lanes are defined in each interface protocol section below (PCI Express, Serial
Rapid IO or SGMII) in this document based on the application usage:
• Section 2.10.3, “SGMII Interface Electrical Characteristics”
• Section 2.19, “PCI Express”
• Section 2.20, “Serial RapidIO (SRIO)”
Note that external AC Coupling capacitor is required for the above three serial transmission protocols per the protocol’s standard
requirements.

2.18.5 Clocking Dependencies

The ports on the two ends of a link must transmit data at a rate that is within 600 parts per million (ppm) of each other at all
times. This is specified to allow bit rate clock sources with a ± 300 ppm tolerance.

2.19 PCI Express

This section describes the DC and AC electrical specifications for the PCI Express bus of the P2010.

2.19.1 PCI Express DC Requirements for SD_REF_CLK and SD_REF_CLK

For more information, see Section 2.18.2.3, “DC Level Requirement for SerDes Reference Clocks.”

2.19.2 PCI Express DC Physical Layer Specifications

This section contains the DC specifications for the physical layer of PCI Express on this device.

2.19.2.1 PCI Express DC Physical Layer Transmitter Specifications

Table 77 defines the PCI Express (2.5 Gb/s) DC specifications for the differential output at all transmitters (TXs). The
parameters are specified at the component pins.

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Table 77. PCI Express (2.5Gb/s) Differential Transmitter (TX) Output DC Specifications

Parameter Symbol Min Typical Max Units Comments

Differential Peak-to-Peak VTX-DIFFp-p 800 1000 1200 mV VTX-DIFFp-p = 2 ÷ |VTX-D+ – VTX-D–| See Note 1.
Output Voltage

De-emphasized Differential VTX-DE-RATIO 3.0 3.5 4.0 dB Ratio of the VTX-DIFFp-p of the second and
Output Voltage (Ratio) following bits after a transition divided by the
VTX-DIFFp-p of the first bit after a transition. See
Note 1.

DC Differential TX ZTX-DIFF-DC 80 100 120 Ω TX DC Differential mode low impedance

Impedance

Transmitter DC Impedance ZTX-DC 40 50 60 Ω Required TX D+ as well as D– DC impedance

during all states

Note:
1. Specified at the measurement point into a timing and voltage compliance test load as shown in Figure 58 and measured over
any 250 consecutive Tx UIs.

Table 79 defines the PCI Express (2.5 Gb/s) AC specifications for the differential output at all transmitters (TXs). The
parameters are specified at the component pins. The AC timing specifications do not include RefClk jitter.

2.19.2.2 PCI Express DC Physical Layer Receiver Specifications

Table 78 defines the DC specifications for the PCI Express (2.5 Gb/s) differential input at all receivers (RXs). The parameters
are specified at the component pins.
Table 78. PCI Express (2.5 Gb/s) Differential Receiver (RX) Input DC Specifications

Parameter Symbol Min Typical Max Units Comments

Differential Input VRX-DIFFp-p 175 — 1200 mV VRX-DIFFp-p = 2 × |VRX-D+ – VRX-D–-|

Peak-to-Peak See Note 1.
Voltage

DC Differential ZRX-DIFF-DC 80 100 120 Ω RX DC Differential mode impedance. See

Input Impedance Note 2

DC Input ZRX-DC 40 50 60 Ω Required RX D+ as well as D– DC Impedance

Impedance (50 ± 20% tolerance). See Notes 1 and 2.

Powered Down ZRX-HIGH-IMP-DC 50 — — kΩ Required RX D+ as well as D– DC Impedance

DC Input when the Receiver terminations do not have
Impedance power. See Note 3.

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Table 78. PCI Express (2.5 Gb/s) Differential Receiver (RX) Input DC Specifications (continued)

Parameter Symbol Min Typical Max Units Comments

Electrical Idle VRX-IDLE-DET-DIF 65 — 175 mV VRX-IDLE-DET-DIFFp-p = 2 × |VRX-D+ –VRX-D–|

Detect Threshold Fp-p Measured at the package pins of the Receiver

Notes:
1. Specified at the measurement point and measured over any 250 consecutive UIs. The test load in Figure 58 must be used as
the Rx device when taking measurements. If the clocks to the Rx and Tx are not derived from the same reference clock, the
Tx UI recovered from 3500 consecutive UI must be used as a reference for the eye diagram.
2. Impedance during all LTSSM states. When transitioning from a fundamental reset to detect (the initial state of the LTSSM)
there is a 5 ms transition time before receiver termination values must be met on all unconfigured lanes of a port.
3. The Rx DC common mode impedance that exists when no power is present or fundamental reset is asserted. This helps
ensure that the receiver detect circuit does not falsely assume a receiver is powered on when it is not. This term must be
measured at 300 mV above the Rx ground.

2.19.3 PCI Express AC Physical Layer Specifications

This section contains the DC specifications for the physical layer of PCI Express on this device.

2.19.3.1 PCI Express AC Physical Layer Transmitter Specifications

This section discusses the PCI Express AC physical layer transmitter specification for 2.5 Gb/s.
Table 79 defines the PCI Express (2.5 Gb/s) AC specifications for the differential output at all transmitters (TXs). The
parameters are specified at the component pins. The AC timing specifications do not include RefClk jitter.
Table 79. PCI Express (2.5Gb/s) Differential Transmitter (TX) Output AC Specifications

Parameter Symbol Min Typical Max Units Comments

Unit Interval UI 399.88 400.00 400.12 ps Each UI is 400 ps ± 300 ppm. UI does not account for
spread spectrum clock dictated variations. See Note 1.

Minimum TX TTX-EYE 0.70 — — UI The maximum transmitter jitter can be derived as

Eye Width TTX-MAX-JITTER = 1 – TTX-EYE = 0.3 UI.
See Notes 2 and 3.

Maximum time TTX-EYE-MEDIAN- — — 0.15 UI Jitter is defined as the measurement variation of the
between the to-MAX-JITTER crossing points (VTX-DIFFp-p = 0 V) in relation to a recovered
jitter median TX UI. A recovered TX UI is calculated over 3500
and maximum consecutive unit intervals of sample data. Jitter is
deviation from measured using all edges of the 250 consecutive UI in the
the median. center of the 3500 UI used for calculating the TX UI. See
Notes 2 and 3.

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Table 79. PCI Express (2.5Gb/s) Differential Transmitter (TX) Output AC Specifications (continued)

Parameter Symbol Min Typical Max Units Comments

AC Coupling CTX 75 — 200 nF All transmitters are AC coupled. The AC coupling is

Capacitor required either within the media or within the transmitting
component itself. See Note 4.

Notes:
1. No test load is necessarily associated with this value.
2. Specified at the measurement point into a timing and voltage compliance test load as shown in Figure 58 and measured over
any 250 consecutive Tx UIs.
3. A TTX-EYE = 0.70 UI provides for a total sum of deterministic and random jitter budget of TTX-JITTER-MAX = 0.30 UI for the
Transmitter collected over any 250 consecutive Tx UIs. The TTX-EYE-MEDIAN-to-MAX-JITTER median is less than half of the total
Tx jitter budget collected over any 250 consecutive Tx UIs. It must be noted that the median is not the same as the mean. The
jitter median describes the point in time where the number of jitter points on either side is approximately equal as opposed to
the averaged time value.
4.P2010 SerDes transmitter does not have CTX built-in. An external AC Coupling capacitor is required

2.19.3.2 Test and Measurement Load

The AC timing and voltage parameters must be verified at the measurement point. The package pins of the device must be
connected to the test/measurement load within 0.2 inches of that load, as shown in Figure 58.

NOTE
The allowance of the measurement point to be within 0.2 inches of the package pins is
meant to acknowledge that package/board routing may benefit from D+ and D– not being
exactly matched in length at the package pin boundary. If the vendor does not explicitly
state where the measurement point is located, the measurement point is assumed to be the
D+ and D– package pins.

D+ Package
Pin C = CTX

TX
Silicon
+ Package
C = CTX
D– Package
Pin R = 50 Ω R = 50 Ω

Figure 58. Test/Measurement Load

2.19.3.3 PCI Express AC Physical Layer Receiver Specifications

This section discusses the PCI Express AC physical layer receiver specifications for 2.5 Gb/s.

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Table 80 defines the AC specifications for the PCI Express (2.5 Gb/s) differential input at all receivers. The parameters are
specified at the component pins. The AC timing specifications do not include RefClk jitter.
Table 80. PCI Express (2.5 Gb/s) Differential Receiver (RX) Input AC Specifications

Parameter Symbol Min Typical Max Units Comments

Unit Interval UI 399.88 400.00 400.12 ps Each UI is 400 ps ± 300 ppm. UI does not account for
spread spectrum clock dictated variations. See Note
1.

Minimum Receiver TRX-EYE 0.4 — — UI The maximum interconnect media and transmitter
Eye Width jitter that can be tolerated by the receiver can be
derived as TRX-MAX-JITTER = 1 – TRX-EYE = 0.6 UI.
See Notes 2 and 3.

Maximum time TRX-EYE-ME — — 0.3 UI Jitter is defined as the measurement variation of the
between the jitter DIAN-to-MAX- crossing points (VRX-DIFFp-p = 0 V) in relation to a
median and JITTER recovered TX UI. A recovered TX UI is calculated over
maximum 3500 consecutive unit intervals of sample data. Jitter
deviation from the is measured using all edges of the 250 consecutive UI
median. in the center of the 3500 UI used for calculating the
TX UI. See Notes 2, 3 and 4.

Notes:
1. No test load is necessarily associated with this value.
2. Specified at the measurement point and measured over any 250 consecutive UIs. The test load in Figure 58 must be used as
the Rx device when taking measurements. If the clocks to the Rx and Tx are not derived from the same reference clock, the
Tx UI recovered from 3500 consecutive UI must be used as a reference for the eye diagram.
3. A TRX-EYE = 0.40 UI provides for a total sum of 0.60 UI deterministic and random jitter budget for the Transmitter and
interconnect collected any 250 consecutive UIs. The TRX-EYE-MEDIAN-to-MAX-JITTER specification ensures a jitter
distribution in which the median and the maximum deviation from the median is less than half of the total. UI jitter budget
collected over any 250 consecutive Tx UIs. It must be noted that the median is not the same as the mean. The jitter median
describes the point in time where the number of jitter points on either side is approximately equal as opposed to the averaged
time value. If the clocks to the Rx and Tx are not derived from the same reference clock, the Tx UI recovered from 3500
consecutive UI must be used as the reference for the eye diagram.
4. It is recommended that the recovered Tx UI is calculated using all edges in the 3500 consecutive UI interval with a fit algorithm
using a minimization merit function. Least squares and median deviation fits have worked well with experimental and
simulated data.

2.20 Serial RapidIO (SRIO)

This section describes the DC and AC electrical specifications for the RapidIO interface for the LP-Serial physical layer. The
electrical specifications cover both single and multiple-lane links. Two transmitters (short run and long run) and a single
receiver are specified for each of three baud rates, 1.25, 2.50, and 3.125 GBaud.
Two transmitter specifications allow for solutions ranging from simple board-to-board interconnect to driving two connectors
across a backplane. A single receiver specification is given that accepts signals from both the short run and long run transmitter
specifications.
The short run transmitter must be used mainly for chip-to-chip connections on either the same printed circuit board or across a
single connector. This covers the case where connections are made to a mezzanine (daughter) card. The minimum swings of the
short run specification reduce the overall power used by the transceivers.
The long run transmitter specifications use larger voltage swings that are capable of driving signals across backplanes. This
allows a user to drive signals across two connectors and a backplane. The specifications allow a distance of at least 50 cm at all
baud rates.

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All unit intervals are specified with a tolerance of ±100 ppm. The worst case frequency difference between any transmit and
receive clock is 200 ppm.

2.20.1 Signal Definitions

To ensure interoperability between drivers and receivers of different vendors and technologies, AC coupling at the receiver
input must be used.
LP-Serial links use differential signaling. This section defines terms used in the description and specification of differential
signals. Figure 59 shows how the signals are defined. The figures show waveforms for either a transmitter output (TD and TD)
or a receiver input (RD and RD). Each signal swings between A Volts and B Volts where A > B.

TD or RD
A Volts

TD or RD
B Volts

Differential Peak-Peak = 2*VDIFFp

Figure 59. Differential Peak-Peak Voltage of Transmitter or Receiver

Using these waveforms, the definitions are as follows:

• The transmitter output signals and the receiver input signals TD, TD, RD and RD each have a peak-to-peak swing of
A – B Volts.
• The differential output signal of the transmitter, VOD, is defined as VTD – VTD
• The differential input signal of the receiver, VID, is defined as VRD – VRD
• The differential output signal of the transmitter and the differential input signal of the receiver each range from A – B
to –(A – B) Volts
• The peak value of the differential transmitter output signal and the differential receiver input signal is A –B Volts.
• The peak-to-peak value of the differential transmitter output signal and the differential receiver input signal is
2 × (A – B) Volts.
To illustrate these definitions using real values, consider the case of a CML (Current Mode Logic) transmitter that has a common
mode voltage of 2.25 V and each of its outputs, TD and TD, has a swing that goes between 2.5 V and 2.0 V. Using these values,
the peak-to-peak voltage swing of the signals TD and TD is 500 mV p-p. The differential output signal ranges between 500 mV
and –500 mV. The peak differential voltage is 500 mV. The peak-to-peak differential voltage is 1000 mV p-p.

2.20.2 Equalization
With the use of high speed serial links, the interconnect media causes degradation of the signal at the receiver. Effects such as
Inter-Symbol Interference (ISI) or data dependent jitter are produced. This loss can be large enough to degrade the eye opening
at the receiver beyond what is allowed in the specification. To negate a portion of these effects, equalization can be used. The
most common equalization techniques that can be used are as follows:
• Pre-emphasis on the transmitter
• A passive high pass filter network placed at the receiver. This is often referred to as passive equalization.
• The use of active circuits in the receiver. This is often referred to as adaptive equalization.

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2.20.3 DC Requirements for Serial RapidIO

This section explains the DC requirements for the Serial RapidIO interface.

2.20.3.1 DC Requirements for Serial RapidIO SD_REF_CLK and SD_REF_CLK

The characteristics and DC requirements of the separate SerDes reference clocks of the Serial RapidIO interface are described
in Section 2.18.2.3, “DC Level Requirement for SerDes Reference Clocks.”

2.20.4 DC Serial RapidIO Timing Transmitter Specifications

LP-Serial transmitter electrical and timing specifications are stated in the text and tables of this section.
The differential return loss, S11, of the transmitter in each case is better than
• –10 dB for (Baud Frequency)/10 < Freq(f) < 625 MHz, and
• –10 dB + 10log(f/625 MHz) dB for 625 MHz ≤ Freq(f) ≤ Baud Frequency
The reference impedance for the differential return loss measurements is 100-Ω resistive. Differential return loss includes
contributions from on-chip circuitry, chip packaging and any off-chip components related to the driver. The output impedance
requirement applies to all valid output levels.
It is recommended that the 20%–80% rise/fall time of the transmitter, as measured at the transmitter output, have a minimum
value 60 ps in each case.
It is recommended that the timing skew at the output of an LP-Serial transmitter between the two signals that comprise a
differential pair not exceed 25 ps at 1.25 GBaud, 20 ps at 2.50 GBaud and 15 ps at 3.125 GBaud.
Table 81 defines the Transmitter DC specifications for the Serial RapidIO interface.
Table 81. SRIO Transmitter DC Timing Specifications—1.25 GBaud, 2.5 GBaud, 3.125 GBaud

Parameter Symbol Min Typical Max Unit Notes

Output Voltage, VO –0.40 — 2.30 V 1

Long Run Differential Output Voltage VDIFFPP 800 — 1600 mV p-p —

Short Run Differential Output Voltage VDIFFPP 500 — 1000 mV p-p —

Note:
1. Voltage relative to COMMON of either signal comprising a differential pair.

2.20.5 DC Serial RapidIO Receiver Specifications

LP-Serial receiver electrical and timing specifications are stated in the text and tables of this section.
Receiver input impedance results in a differential return loss better that 10 dB and a common mode return loss better than 6 dB
from 100 MHz to (0.8) × (Baud Frequency). This includes contributions from on-chip circuitry, the chip package and any
off-chip components related to the receiver. AC coupling components are included in this requirement. The reference
impedance for return loss measurements is 100-Ω resistive for differential return loss and 25-Ω resistive for common mode.
Table 82 defines the Receiver DC specifications for the Serial RapidIO interface.
Table 82. SRIO Receiver DC Timing Specifications—1.25 GBaud, 2.5 GBaud, 3.125 GBaud

Characteristic Symbol Min Typical Max Unit Notes

Differential Input Voltage VIN 200 — 1600 mV p-p Measured at receiver

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2.20.6 AC Requirements for Serial RapidIO

This section explains the AC requirements for the Serial RapidIO interface.

2.20.6.1 AC Requirements for Serial RapidIO SD_REF_CLK and SD_REF_CLK

Please note that the Serial RapidIO clock requirements for SD_REF_CLK and SD_REF_CLK are intended to be used within
the clocking guidelines specified by Section 2.18.3, “AC Requirements for PCI Express SerDes Reference Clocks.”

2.20.6.2 AC Requirements for Serial RapidIO Transmitter and Receiver

Table 83 defines the transmitter AC specifications for the Serial RapidIO interface. The AC timing specifications do not include
RefClk jitter.
Table 83. SRIO Transmitter AC Timing Specifications

Parameter Symbol Min Typical Max Unit

Deterministic Jitter JD — — 0.17 UI p-p

Total Jitter JT — — 0.35 UI p-p

Unit Interval: 1.25 GBaud UI 800–100ppm 800 800+100ppm ps

Unit Interval: 2.5 GBaud UI 400–100ppm 400 400+100ppm ps

Unit Interval: 3.125 GBaud UI 320–100ppm 320 320+100ppm ps

Table 84 defines the receiver AC specifications for the Serial RapidIO interface. The AC timing specifications do not include
RefClk jitter.
Table 84. SRIO Receiver AC Timing Specifications

Parameter Symbol Min Typical Max Unit Notes

Deterministic Jitter Tolerance JD 0.37 — — UI p-p Measured at

receiver

Combined Deterministic and Random JDR 0.55 — — UI p-p Measured at

Jitter Tolerance receiver

Total Jitter Tolerance1 JT 0.65 — — UI p-p Measured at

receiver

Bit Error Rate BER — — 10–12 — —

Unit Interval: 1.25 GBaud UI 800–100ppm 800 800+100ppm ps —

Unit Interval: 2.5 GBaud UI 400–100ppm 400 400+100ppm ps —

Unit Interval: 3.125 GBaud UI 320–100ppm 320 320+100ppm ps —

Note:
1. Total jitter is composed of three components: deterministic jitter, random jitter, and single frequency sinusoidal jitter. The
sinusoidal jitter may have any amplitude and frequency in the unshaded region of Figure 60. The sinusoidal jitter component
is included to ensure margin for low frequency jitter, wander, noise, crosstalk and other variable system effects.

P2010 QorIQ Integrated Processor Hardware Specifications, Rev. 3

NXP Semiconductors 101
Thermal

Figure 60 shows the single frequency sinusoidal jitter limits.

8.5 UI p-p

Sinusoidal
Jitter
Amplitude

0.10 UI p-p

22.1 kHz Frequency 1.875 MHz 20 MHz

Figure 60. Single Frequency Sinusoidal Jitter Limits

3 Thermal
This section describes the thermal specifications of the device.

3.1 Thermal Characteristics

Table 85 provides the package thermal characteristics.
Table 85. Package Thermal Characteristics

Characteristic JEDEC Board Symbol Value Unit Notes

Junction-to-ambient Natural Convection Single layer board (1s) RθJA 21 °C/W 1, 2

Junction-to-ambient Natural Convection Four layer board (2s2p) RθJA 14 °C/W 1, 2
Junction-to-ambient (at 200 ft/min) Single layer board (1s) RθJA 16 °C/W 1, 2
Junction-to-ambient (at 200 ft/min) Four layer board (2s2p) RθJA 12 °C/W 1, 2
Junction-to-board thermal — RθJB 7 °C/W 3

P2010 QorIQ Integrated Processor Hardware Specifications, Rev. 3

102 NXP Semiconductors
 Package Information

Table 85. Package Thermal Characteristics

Characteristic JEDEC Board Symbol Value Unit Notes

Junction-to-case thermal (Top) — RθJC 5 °C/W 4

Notes:
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance.
2. Per JEDEC JESD51-2 and JESD51-6 with the board (JESD51-9) horizontal.
3. Thermal resistance between the die and the printed-circuit board per JEDEC JESD51-8. Board temperature is measured on
the top surface of the board near the package.
4. Junction-to-case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is
used for the case temperature. Reported value includes the thermal resistance of the interface layer.

3.2 Temperature Diode

The device has a temperature diode on the microprocessor that can be used in conjunction with other system temperature
monitoring devices. These devices use the negative temperature coefficient of a diode operated at a constant current to
determine the temperature of the microprocessor and its environment.
The following are the specifications of the P2010 on-board temperature diode:
Operating range: 10 – 230 μA
Ideality factor over 13.5 – 220 μA; n = 1.011 +/- 0.008

4 Package Information
This section provides the package parameters and ordering information.

4.1 Package Parameters for the P2010 WB-TePBGA

The package parameters are provided in the following list. The package type is 31 mm × 31 mm, 689 plastic ball grid array
(WB-TePBGA).
Package outline 31 mm × 31 mm
Interconnects 689
Pitch 1.00 mm
Module height (typical) 2.0 mm to 2.46 mm (Maximum)
Solder Balls 3.5% Ag, 96.5% Sn
Ball diameter (typical) 0.60 mm

P2010 QorIQ Integrated Processor Hardware Specifications, Rev. 3

NXP Semiconductors 103
Package Information

Figure 61. P2010 Package

NOTES for Figure 61:

1. All dimensions are in millimeters.
2. Dimensioning and tolerancing per ASME Y14. 5M-1994.
3. Maximum solder ball diameter measured parallel to Datum A.
4. Datum A, the seating plane, is determined by the spherical crowns of the solder balls.
5. Parallelism measurement excludes any effect of mark on top surface of package.

P2010 QorIQ Integrated Processor Hardware Specifications, Rev. 3

104 NXP Semiconductors
 Product Documentation

4.2 Ordering Information

Table 86 provides the NXP part numbering nomenclature for the device. Note that the individual part numbers correspond to a
maximum processor core frequency. For available frequencies, contact your local NXP sales office. Each part number also
contains a revision code which refers to the die mask revision number.
Table 86. Part Numbering Nomenclature

p 2 02 or 01 0 x t e n c d r

Number of Qual Temperature Package CPU DDR Die

Generation Platform Derivative Encryption
Cores Status Range Type Frequency Speed Revision

P = 45nm 1–5 01 = Single 0–9 P= S = Std Temp E = SEC 2= H= F= A = Rev

core Prototype X = Ext. Temp Present TEPBGA2 800 MHz 667 MHz 1.0
02 = Dual N= N = SEC Pb free K= H= B = Rev
core Qual’d to Not Present 1000 MHz 800 MHz 2.0
Industrial M= C = Rev
Tier 1200 MHz 2.1
N=
1333 MHz

4.2.1 Part Marking

Parts are marked as in the example shown in Figure 62.

P2010xtencdr
core/platform MHZ
ATWLYYWW
CCCCC
*MMMMM YWWLAZ
TePBGA II
Notes:
ATWLYYWW is the traceability code.
CCCCC is the country code.
MMMMM is the mask number.
YWWLAZ is the assembly traceability code.
P2010xtencdr is the orderable part number. See Table 86 for details.

Figure 62. Part Marking for WB-TePBGA Device

5 Product Documentation
The following documents are required for a complete description of the device and are needed to design properly with the part:
• P2020 QorIQ Integrated Processor Reference Manual (document number P2020RM)
• e500 PowerPC Core Reference Manual (E500CORERM)

P2010 QorIQ Integrated Processor Hardware Specifications, Rev. 3

NXP Semiconductors 105
Revision History

6 Revision History
Table 87 provides a revision history for the this hardware specification.
Table 87. Document Revision History

Rev.
Date Substantive Change(s)
Number

3 03/2016 • In Table 1, note 15, changed “USB1_STP” to “USB_STP”.

• In Table 10, updated the high-level input voltage min and the low-level input voltage max and
added “RGMII, GMII at LVDD = 2.5 V” to the title.
• Added Table 11 for GMII LVDD = 3.3 V.
• In Table 12, added the frequency min and max formulas and added a row with jitter data.
2 08/2013 • In the features list, removed “(Tj) range: 0-125 °C and -40 °C-125 °C (industrial standard)” from
the “Operating junction temperature” bullet point.
• In the features list, changed the 36-bit physical addressing clock frequency from 1.2 GHz to 1.33
GHz.
• In Table 1, added overbar to the signal TEST_SEL.
• In Table 3, modified the recommended value for DDR2 and DDR3 DRAM reference input
voltages.
• In Table 5, added rows for core frequency = 1333.
• In Table 18 and Table 19, updated footnote 2.
• In Table 86, added CPU frequency N = 1333.

P2010 QorIQ Integrated Processor Hardware Specifications, Rev. 3

106 NXP Semiconductors
 Revision History

Table 87. Document Revision History (continued)

Rev.
Date Substantive Change(s)
Number

1 03/2012 • In Table 1, “P2010 Pinout Listing 1,” updated the text corresponding to footnote 16 from: “When
eTSEC1 and eTSEC2 are used as parallel interfaces, pins TSEC1_TX_EN and TSEC2_TX_EN
require an external 4.7-kΩ pull-down resistor to prevent PHY from seeing a valid Transmit
Enable before it is actively driven. TSEC2_TXD[05] is a POR configuration pin for eSDHC
card-detect (cfg_sdhc_cd_pol_sel) and also has an alternate function as TSEC3_TX_EN. When
using eTSEC3 as a parallel interface, the TSEC3_TX_EN requires a pull down. However,
because the pull-down resistor on TSEC2_TXD[05]/TSEC3_TX_EN signal causes the eSDHC
card-detect (cfg_sdhc_cd_pol_sel) to be inverted, the inversion must be overridden from the
SDHCDCR [CD_INV] debug control register.”
to:
“TSEC2_TXD[05] is a POR configuration pin for eSDHC card-detect (cfg_sdhc_cd_pol_sel),
and it also has an alternate function of TSEC3_TX_EN. When eTSEC1 or eTSEC2 or eTSEC3
are used as parallel interfaces, the TSECx_TX_EN pins require an external 4.7-k pull-down
resistor to prevent PHY from seeing a valid Transmit Enable before it is actively driven. However,
the pull-down resistor on TSEC3_TX_EN causes the eSDHC card-detect (cfg_sdhc_cd_sel) to
be inverted; the inversion should be overridden from the SDHCDCR[CD_INV] debug control
register. If the device is configured to boot from the eSDHC interface, the SDHC_CD should be
inverted on the board.”
• In Table 2, “Absolute Maximum Ratings1,” for DDR2/DDR3 DRAM signals and reference rows,
updated the value in the “Maximum” column from “–0.3 to (GVDD + 0.3)” to “–0.3 to (GVDD +
0.3)” and “–0.3 to (GVDD/2 + 0.3),” respectively.
• In Table 2, “Absolute Maximum Ratings1,” for the SerDes row, updated the value in the
“Maximum” column from “–0.3 to (OVDD + 0.3)” to “–0.3 to (XVDD + 0.3).”
• In Table 6, I/O Power Supply Estimated Values,” added “RMII” to the “Parameters” column for
the eTSEC row that corresponds to LVDD (2.5 V), and added “MII, GMII, TBI, RMII, and 1588”
to the “Parameters” column for the eTSEC row that corresponds to LVDD (3.3 V).
• In Section 2.10.1.1, “IEEE 1588, GMII, MII, TBI, RGMII, RMII, and RTBI DC Electrical
Characteristics,” Table 32, IEEE 1588, GMII, MII, RMII, and TBI DC Electrical Characteristics at
LVDD = 3.3 V,” and Table 33, “IEEE 1588, GMII, MII, RMII, RGMII, RTBI, and TBI DC Electrical
Characteristics at LVDD = 2.5 V,” added “IEEE 1588” to the title.
• In Table 32, IEEE 1588, GMII, MII, RMII, and TBI DC Electrical Characteristics at LVDD = 3.3 V,”
added “IEEE 1588” to the cell containing the “Input high voltage” parameter.
• In Table 43, “RMII Receive AC Timing Specifications,” updated the parameter “RXD[1:0],
CRS_DV, RX_ER setup time to TSECn_RX_CLK rising edge” to “RXD[1:0], CRS_DV, RX_ER
setup time to TSECn_TX_CLK rising edge,” and the parameter “RXD[1:0], CRS_DV, RX_ER
hold time to TSECn_RX_CLK rising edge” to “RXD[1:0], CRS_DV, RX_ER hold time to
TSECn_TX_CLK rising edge.”
• In Figure 26, “RMII Receive AC Timing Diagram,” changed “TSECn_RX_CLK” to
“TSECn_TX_CLK.”
• In Table 59, “Enhanced Local Bus DC Electrical Characteristics (1.8 V DC),” in the “Parameters”
column, changed “Low-level output voltage (BVDD = min, IOH = –0.5 mA)” to “Low-level output
voltage (BVDD = min, IOH = 0.5 mA).”
• In Table 62, “eSDHC Interface DC Electrical Characteristics (CVDD = 3.3 V),” changed the
minimum value of parameter “Input leakage current” from “–40” to “–70.”
• In Figure 42, “eSDHC Data and Command Input/Output Timing Diagram Referenced to Clock,”
changed “tHSIVKH” to “tSHSIVKH” and changed “tHSIXKH” to “tSHSIXKH.“
• In Table 67, “JTAG AC Timing Specifications (Independent of SYSCLK),” changed parameter
“JTAG external clock pulse width measured at 1.4 V” to “JTAG external clock pulse width
measured at OVDD/2.”

P2010 QorIQ Integrated Processor Hardware Specifications, Rev. 3

NXP Semiconductors 107
Revision History

Table 87. Document Revision History (continued)

Rev.
Date Substantive Change(s)
Number

1 03/2012 • In Table 76, “SD_REF_CLK and SD_REF_CLK Input Clock Requirements,” added the following
continued footnote to the table and added it to the “Notes” column of row “SD_REF_CLK/SD_REF_CLK
reference clock duty cycle”: “7. Measurement taken from the differential waveform.”
• In Table 76, “SD_REF_CLK and SD_REF_CLK Input Clock Requirements,” removed “(Measure
at 1.6 V)” from parameter “SD_REF_CLK/SD_REF_CLK reference clock duty cycle.”
• In Figure 59, “Differential Peak-Peak Voltage of Transmitter or Receiver,” changed “Differential
Peak-Peak = 2 ℜ× (A‚Ä” to “Differential Peak-Peak = 2*VDIFFp.”
• In Section 2.2, “Power Sequencing,” added the following warning: “Only 100,000 POR cycles
are permitted per lifetime of a device.”
• In Table 46, “SGMII Transmit AC Timing Specifications,” updated the minimum value for the AC
coupling capacitor parameter from 5 to 10.
• In Table 43, “RMII Receive AC Timing Specifications,” removed note from “TSECn_TX_CLK
(reference clock) clock period” row.
• In Table 59, “Enhanced Local Bus DC Electrical Characteristics (1.8 V DC),” changed parameter
from “Low-level output voltage (BVDD = min, IOH = 0.5 mA)” to “Low-level output voltage (BVDD
= min, IOL = 0.5 mA).”
• In Figure 42, “eSDHC Data and Command Input/Output Timing Diagram Referenced to Clock,”
updated text from “VM = Midpoint Voltage (OVDD/2)” to “VM = Midpoint Voltage (CVDD/2).”
• In Figure 41, “eSDHC Clock Input Timing Diagram,” updated the text from “VM = Midpoint
Voltage (OVDD/2)” to “VM = Midpoint Voltage (CVDD/2).”

0 04/2011 Initial public release

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108 NXP Semiconductors
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Document Number: P2010EC

Rev. 3
03/2016