MSSP MODULE
MSSP Module Silicon/Data Sheet Errata
The PICmicro® microcontrollers you have received all 1. Module: I2C™ (Slave Mode)
exhibit anomalous behavior in their Master SSP
(MSSP) modules, as described in this document. They In its current implementation, the module may fail
otherwise conform functionally to the descriptions to correctly recognize certain Repeated Start
provided in their respective Device Data Sheets and conditions. For this discussion, a Repeated Start is
Reference Manuals, as amended by silicon release defined as a Start condition presented to the bus
errata for particular devices. after an initial valid Start condition has been recog-
nized and the Start status bit (SSPSTAT<3>) has
Users are encouraged to review the latest Device Data been set and before a valid Stop condition is
Sheets and errata available for additional information received.
concerning an individual device. These documents
may be obtained directly from the Microchip corporate If a Repeated Start is not recognized, a loss of
web site, at www.microchip.com. synchronization between the Master and Slave
may occur; the condition may continue until the
These issues are expected to be resolved in future module is reset. A NACK condition, generated by
silicon revisions of the designated parts. the Slave for any reason, will not reset the module.
Silicon issues 1 and 2 affect all silicon revisions of the This failure has been observed only under two
following devices: circumstances:
• PIC16C717 • PIC18F2220 • A Repeated Start occurs within the frame of a
• PIC16C770 • PIC18F2320 data or address byte. The unexpected Start
• PIC16C771 • PIC18F242 condition may be erroneously interpreted as a
• PIC16C773 • PIC18F2439 data bit, provided that the required conditions
• PIC16C774 • PIC18F248 for setup and hold times are met.
• PIC16F737 • PIC18F252 • A Repeated Start condition occurs between two
• PIC16F747 • PIC18F2539 back-to-back slave address matches in the
• PIC16F767 • PIC18F258 same Slave, with the R/W bit set to Read (= 1)
• PIC16F777 • PIC18F4220 in both cases. (This circumstance is regarded
• PIC16F872 • PIC18F4320 as being unlikely in normal operation.)
• PIC16F873 • PIC18F442 Work around
• PIC16F873A • PIC18F4439 A time-out routine should be used to monitor the
• PIC16F874 • PIC18F448 module’s operation. The timer is enabled upon the
• PIC16F874A • PIC18F452 receipt of a valid Start condition; if a time-out
• PIC16F876 • PIC18F4539 occurs, the module is reset. The length of the time-
• PIC16F876A • PIC18F458 out period will vary from application to application
• PIC16F877 • PIC18F6520 and will need to be determined by the user.
• PIC16F877A • PIC18F6525 Two methods are suggested to reset the module:
• PIC17C752 • PIC17F6585
1. Change the mode of the module to something
• PIC17C756 • PIC18F6620 other than the desired mode by changing the set-
• PIC17C756A • PIC18F6621 tings of bits, SSPM3:SSPM0 (SSPCON1<3:0>);
• PIC17C762 • PIC18F6680 then, change the bits back to the desired
• PIC17C766 • PIC18F6720 configuration.
• PIC18C242 • PIC18F8520 2. Disable the module by clearing the SSPEN bit
• PIC18C252 • PIC18F8525 (SSPCON1<5>); then, re-enable the module
• PIC18C442 • PIC18F8585 by setting the bit.
• PIC18C452 • PIC18F8620 Other methods may be available.
• PIC18C601 • PIC18F8621
• PIC18C801 • PIC18F8680
• PIC18C658 • PIC18F8720
• PIC18C858
© 2006 Microchip Technology Inc. DS80131E-page 1
MSSP MODULE
Clarifications/Corrections to the Data 1. Module: MSSP (SPI Mode)
Sheets
The description of the operation of the CKE bit
Note: Items 1-3 apply to the Data Sheets for the (SSPSTAT<6>) is clarified. Please substitute the
following devices: description in Register 1, below, for all occurrences
of the existing text for the SSPSTAT register, bit 6
• PIC16C717/770/771 (DS41120B) (new text in bold).
• PIC16C773/774 (DS30275A)
Note: This text refers only to the operation of
• PIC16F872 (DS30221B)
the CKE bit in SPI mode; its operation
• PIC16F873/874/876/877 (DS30292C) in I2C mode is unchanged. For those
• PIC16F873A/874A/876A/877A data sheets that describe the SSPSTAT
(DS39582B) register in separate locations for SPI
• PIC17C752/756A/762/766 (DS30289B) and I2C modes, this description applies
• PIC18C242/252/442/452 (DS39026C) only to the register titled “SSPSTAT
• PIC18C601/801 (DS39541A) Register (SPI Mode)”.
• PIC18C658/858 (DS30475A)
• PIC18F242/252/442/452 (DS39564B) 2. Module: MSSP (SPI Slave Mode)
• PIC18F2220/2320/4220/4320 The description of the operation of SPI Slave
(DS39599C) mode is clarified as follows: the state of the clock
• PIC18F2439/2539/4439/4539 line (SCK) must match the polarity for the Idle state
(DS30485A) before enabling the module.
• PIC18F6520/6620/6720/8520/8620/ The subsection of the “MSSP Module” chapter,
8720 (DS39609B) entitled “Slave Mode” (Subsection 3.6 in the
• PIC18F6585/6680/8585/8680 majority of data sheets, Subsection 3.5 in others),
(DS30491C) is amended by adding the following paragraph to
the end of the existing text:
“Before enabling the module in SPI Slave mode,
the clock line must match the proper Idle state.
The clock line can be observed by reading the
SCK pin. The Idle state is determined by the CKP
bit (SSPCON1<4>) .”
REGISTER 1: SSPSTAT: MSSP STATUS REGISTER (EXCERPT)
bit 6 CKE: SPI Clock Edge Select bit
1 = Transmit occurs on transition from active to Idle clock state
0 = Transmit occurs on transition from Idle to active clock state
Note: Polarity of clock state is set by the CKP bit (SSPCON1<4>).
DS80131E-page 2 © 2006 Microchip Technology Inc.
MSSP MODULE
3. Module: MSSP (I2C Mode)
The table for the I2C Baud Rate Generator clock
rates is revised. Replace the I2C Clock Rate Table
with the following:
TABLE 1: I2C™ CLOCK RATE w/BRG
FSCL
FOSC FCY FCY * 2 BRG Value
(2 Rollovers of BRG)
40 MHz 10 MHz 20 MHz 18h 400 kHz(1)
40 MHz 10 MHz 20 MHz 1Fh 312.5 kHz
40 MHz 10 MHz 20 MHz 63h 100 kHz
16 MHz 4 MHz 8 MHz 09h 400 kHz(1)
16 MHz 4 MHz 8 MHz 0Ch 308 kHz
16 MHz 4 MHz 8 MHz 27h 100 kHz
4 MHz 1 MHz 2 MHz 02h 333 kHz(1)
4 MHz 1 MHz 2 MHz 09h 100 kHz
4 MHz 1 MHz 2 MHz 00h 1 MHz(1)
Note 1: The I2C™ interface does not conform to the 400 kHz I2C specification (which applies to rates greater than
100 kHz) in all details, but may be used with care where higher rates are required by the application.
© 2006 Microchip Technology Inc. DS80131E-page 3
MSSP MODULE
4. Module: MSSP (I2C Mode) SCL]) corresponding to the I2C pins must be set to
‘1’. If any TRIS bits (TRISx<7:0>) of the port con-
Note: Item 4 applies to the Data Sheets for the taining the I2C pins (PORTx [SDA, SCL]) are
following devices: changed in software during I2C communication
• PIC16C717/770/771 (DS41120B) using a Read-Modify-Write instruction (BSF, BCF),
• PIC16C773/774 (DS30275A) then the I2C mode may stop functioning properly
and I2C communication may suspend. Do not
• PIC16F872 (DS30221B)
change any of the TRISx bits (TRIS bits of the port
• PIC16F873/874/876/877 (DS30292C) containing the I2C pins) using the instruction BSF
• PIC16F873A/874A/876A/877A or BCF during I2C communication. If it is absolutely
(DS39582B) necessary to change the TRISx bits during
communication, the following method can be
The description of the I2C pins related to the TRIS
used:
bits is clarified. To ensure proper communication of
the I2C Slave mode, the TRIS bits (TRISx [SDA,
MOVF TRISC, W ; Example for a 40-pin part such as the PIC16F877A
IORLW 0x18 ; Ensures <4:3> bits are ‘11’
ANDLW B’11111001’ ; Sets <2:1> as output, but will not alter other bits
; User can use their own logic here, such as IORLW, XORLW and ANDLW
MOVWF TRISC
DS80131E-page 4 © 2006 Microchip Technology Inc.
MSSP MODULE
REVISION HISTORY
Revision A Document (7/2002):
Original version (I2C Slave Issue)
Revision B Document (1/2003):
Clarification of original issue to include Restart
conditions. Addition of data sheet clarification 1 (SPI
Mode, CKE bit).
Revision C Document (3/2003):
Addition of data sheet clarification 2 (SPI Slave Mode,
operation).
Revision D Document (9/2004):
Updated list of affected devices for silicon issue 1 (I2C
– Slave Mode) and 2 (MSSP – SPI, Slave Mode),
removed silicon issue 3 (I2C – Slave Mode) and added
data sheet clarifications 3 and 4 (MSSP – I2C Mode).
Revision E Document (7/2006):
Removed silicon issue 2 (MSSP – SPI, Slave Mode).
© 2006 Microchip Technology Inc. DS80131E-page 5
MSSP MODULE
NOTES:
DS80131E-page 6 © 2006 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
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mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
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© 2006 Microchip Technology Inc. DS80131E-page 7
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DS80131E-page 8 © 2006 Microchip Technology Inc.
