OPA3875

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Triple 2:1 High-Speed Video Multiplexer

1FEATURES DESCRIPTION
• 700MHz SMALL-SIGNAL BANDWIDTH
2

The OPA3875 offers a very wideband, 3-channel, 2:1

(AV = +2) multiplexer in a small SSOP-16 package. Using only
• 425MHz, 4VPP BANDWIDTH 11mA/ch, the OPA3875 provides three, gain of +2,
video amplifier channels with greater than 400MHz
• 0.1dB GAIN FLATNESS to 150MHz
large-signal bandwidth (4VPP). Gain accuracy and
• 4ns CHANNEL SWITCHING TIME switching glitch are improved over earlier solutions
• LOW SWITCHING GLITCH: 40mVPP using a new (patented) input stage switching
• 3100V/µs SLEW RATE approach. This technique uses current steering as the
input switch while maintaining an overall closed-loop
• 0.025%/0.025° DIFFERENTIAL GAIN, PHASE design. Gain matching between each of the
• HIGH GAIN ACCURACY: 2.0V/V ±0.4% 3-channel pairs is also significantly improved using
this technique (<0.2% gain mismatch). With greater
APPLICATIONS than 700MHz small-signal bandwidth at a gain of 2,
• RGB SWITCHING the OPA3875 gives a typical 0.1dB gain flatness to
greater than 150MHz.
• LCD PROJECTOR INPUT SELECT
• WORKSTATION GRAPHICS System power may be reduced using the chip enable
feature for the OPA3875. Taking the chip enable line
• TRIPLE ADC INPUT MUX
high powers down the OPA3875 to less than 900µA
• DROP-IN UPGRADE TO LT1675 total supply current. Muxing multiple OPA3875
+5V outputs together, then using the chip enable to select
which channels are active, increases the number of
possible inputs to the 3-channel outputs.
75W 75W Where a single channel of the OPA3875 is required,
RGB consider the OPA875.
Channel 0
75W OPA3875
SELECT ENABLE RED OUT GREEN OUT BLUE OUT

75W 75W
1 0 R0 G0 B0
OPA3875 RGB
(Patented) Out 0 0 R1 G1 B1
X 1 Off Off Off
75W

RGB
OPA3875 RELATED PRODUCTS
Channel 1 75W
75W DESCRIPTION
OPA875 Single-Channel OPA3875
OPA4872 Quad 510MHz 4:1 Multiplexer
75W
-5V EN
OPA3693 Triple 650MHz Video Buffer
Channel
Select

RGB Switching

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2 All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2006–2008, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
OPA3875
SBOS341D – DECEMBER 2006 – REVISED AUGUST 2008 ............................................................................................................................................ www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ORDERING INFORMATION (1)

SPECIFIED
PACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORT
PRODUCT PACKAGE-LEAD DESIGNATOR RANGE MARKING NUMBER MEDIA, QUANTITY
OPA3875IDBQ Rails, 75
OPA3875 SSOP-16 DBQ –45°C to +85°C OP3875
OPA3875IDBQR Tape and Reel, 2500

(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.

ABSOLUTE MAXIMUM RATINGS

Over operating temperature range, unless otherwise noted.
OPA3875 UNIT
Power Supply ±6.5 V
Internal Power Dissipation See Thermal Analysis
Input Voltage Range ±VS V
Storage Temperature Range –65 to +125 °C
Lead Temperature (soldering, 10s) +260 °C
Operating Junction Temperature +150 °C
Continuous Operating Junction Temperature +140 °C
ESD Rating:
Human Body Model (HBM) 2000 V
Charge Device Model (CDM) 1500 V
Machine Model (MM) 200 V

PIN CONFIGURATION

Top View SSOP

OPA3875

R0 1 16 V+

G0 2 x2 15 OUT_R

B0 3 x2 14 OUT_G

GND 4 x2 13 OUT_B

GND 5 12 V-

R1 6 11 V-

G1 7 10 SEL

B1 8 9 EN

SSOP-16

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ELECTRICAL CHARACTERISTICS: VS = ±5V

At G = +2, RL = 150Ω, unless otherwise noted.
OPA3875
MIN/MAX OVER
TYP TEMPERATURE
0°C to –40°C to MIN/ TEST
PARAMETER CONDITIONS +25°C +25°C (2) 70°C (3) +85°C (3) UNITS MAX LEVEL (1)
AC PERFORMANCE See Figure 1
Small-Signal Bandwidth VO = 200mVPP, RL = 150Ω 700 525 515 505 MHz min B
Large-Signal Bandwidth VO = 4VPP, RL = 150Ω 425 390 380 370 MHz min B
Bandwidth for 0.1dB Gain Flatness VO = 200mVPP 150 MHz typ C
Maximum Small-Signal Gain VO = 200mVPP, RL = 150Ω, f = 5MHz 2.0 2.02 2.03 2.05 V/V max B
Minimum Small-Signal Gain VO = 200mVPP, RL = 150Ω, f = 5MHz 2.0 1.98 1.97 1.95 V/V min B
SFDR 10MHz, VO = 2VPP, RL = 150Ω –68 –65 –64 –63 dBc max B
Input Voltage Noise f > 100kHz 6.7 7.0 7.2 7.4 nV/√Hz max B
Input Current Noise f > 100kHz 3.8 4.2 4.6 4.9 pA/√Hz max B
NTSC Differential Gain RL = 150Ω 0.025 % typ C
NTSC Differential Phase RL = 150Ω 0.025 ° typ C
Slew Rate VO = ±2V 3100 2800 2700 2600 V/µs min B
Rise Time and Fall Time VO = 0.5V Step 460 ps typ C
VO = 1.4V Step 600 ps typ C
CHANNEL-TO-CHANNEL PERFORMANCE
Gain Match Channel to Channel, RL = 150Ω ±0.05 ±0.25 ±0.3 ±0.35 % max A
All inputs, RL = 150Ω ±0.1 ±0.5 ±0.6 ±0.7 % max A
Output Offset Voltage Mismatch All three outputs ±3 ±9 ±10 ±12 mV max A
All Hostile Crosstalk f = 50MHz, RL = 150Ω –50 dB typ C
Channel-to-Channel Crosstalk f = 50MHz, RL = 150Ω –58 dB typ C
CHANNEL AND CHIP-SELECT PERFORMANCE
SEL (Channel Select) Swtiching Time RL = 150Ω 4 ns typ C
EN (Chip Select) Switching Time Turn On 9 ns typ C
Turn Off 60 ns typ C
SEL (Channel Select) Switching Glitch All Inputs to Ground, At Matched Load 40 mVPP typ C
EN (Chip-Select) Switching Glitch All Inputs to Ground, At Matched Load 15 mVPP typ C
All Hostile Disable Feedthrough 50MHz, Chip Disabled (EN = High) –68 dB typ C
Maximum Logic 0 EN, SEL 0.8 0.8 0.8 V max B
Minimum Logic 1 EN, SEL 2.0 2.0 2.0 V min B
EN Logic Input Current 0V to 4.5V 75 100 125 150 µA max A
SEL Logic Input Current 0V to 4.5V 160 200 250 300 µA max A
DC PERFORMANCE
Output Offset Voltage RIN = 0Ω, G = +2V/V ±2.5 ±14 ±15.8 ±17 mV max A
Average Output Offset Voltage Drift RIN = 0Ω, G = +2V/V ±50 ±50 µV/°C max B
Input Bias Current ±5 ±18 ±19.5 ±20.5 µA max A
Average Input Bias Current Drift ±40 ±40 nA/°C max B
Gain Error (from 2V/V) VO = ±2V 0.4 1.4 1.5 1.6 % max A
INPUT
Input Voltage Range ±2.8 V typ C
Input Resistance 1.75 MΩ typ C
Input Capacitance Channel Selected 0.9 pF typ C
Channel Deselected 0.9 pF typ C
Chip Disabled 0.9 pF typ C

(1) Test levels: (A) 100% tested at +25°C. Over temperature limits set by characterization and simulation. (B) Limits set by characterization
and simulation. (C) Typical value only for information.
(2) Junction temperature = ambient for +25°C tested specifications.
(3) Junction temperature = ambient at low temperature limit; junction temperature = ambient +36°C at high temperature limit for over
temperature specifications.

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ELECTRICAL CHARACTERISTICS: VS = ±5V (continued)

At G = +2, RL = 150Ω, unless otherwise noted.
OPA3875
MIN/MAX OVER
TYP TEMPERATURE
0°C to –40°C to MIN/ TEST
PARAMETER CONDITIONS +25°C +25°C (2) 70°C (3) +85°C (3) UNITS MAX LEVEL (1)
OUTPUT
Output Voltage Range ±3.5 ±3.4 ±3.35 ±3.3 V min A
Output Current VO = 0V, Linear Operation ±70 ±50 ±45 ±40 mA min A
Output Resistance Chip enabled 0.3 Ω typ C
Chip Disabled, Maximum 800 912 915 918 Ω max A
Chip Disabled, Minumum 800 688 685 682 Ω min A
Output Capacitance Chip Disabled 2 pF typ C
POWER SUPPLY
Specified Operating Voltage ±5 V typ C
Minimum Operating Voltage ±3.0 ±3.0 ±3.0 V min B
Maximum Operating Voltage ±6.3 ±6.3 ±6.3 V max A
Maximum Quiescent Current Chip Selected, VS = ±5V 33 34 35 36 mA max A
Minimum Quiescent Current Chip Selected, VS = ±5V 33 31 30 27 mA min A
Maximum Quiescent Current Chip Deselected 0.9 1.2 1.4 1.5 mA max A
Power-Supply Rejection Ratio (+PSRR) Input-Referred 56 50 48 47 dB min A
(–PSRR) Input-Referred 55 51 49 48 dB min A
THERMAL CHARACTERISTICS
Specified Operating Range D Package –40 to +85 °C typ C
Thermal Resistance θJA Junction-to-Ambient
DBQ SSOP-16 85 °C/W typ C

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TYPICAL CHARACTERISTICS: VS = ±5V

At G = +2 and RL = 150Ω, unless otherwise noted.

SMALL-SIGNAL FREQUENCY RESPONSE LARGE-SIGNAL FREQUENCY RESPONSE

7 0.3 8
Frequency Response RL = 150W
Left Scale 7
6 0.2 G = +2V/V

Normalized Gain Flatness (dB)

6
1 0.1 5
4

Gain (dB)
Gain (dB)

4 0 3
VO = 4VPP
Gain Flatness 2
3 Right Scale -0.1
1
VO = 1VPP
2 -0.2 0
VO = 500mVPP -1
1 RL = 150W -0.3 VO = 5VPP VO = 2VPP
-2
G = +2V/V
0 -0.4 -3
1M 10M 100M 1G 0 100 200 300 400 500 600 700 800 900 1000
Frequency (Hz) Frequency (100MHz/div)
Figure 1. Figure 2.

NONINVERTING PULSE RESPONSE ALL INPUT DISABLE FEEDTHROUGH vs FREQUENCY

0.5 2.5 -20
RL = 150W Input-Referred
0.4 G = +2V/V 2.0 -30
Large-Signal Output Voltage (V)
Small-Signal Output Voltage (V)

Large-Signal 4VPP EN = +5V

0.3 1.5 -40
Right Scale
0.2 1.0
-50
Isolation (dB)

0.1 Small-Signal 0.4VPP 0.5

Left Scale -60
0 0
-70
-0.1 -0.5
-80
-0.2 -1.0
-0.3 -1.5 -90

-0.4 -2.0 -100

100MHz Square-Wave Input
-0.5 -2.5 -110
Time (1ns/div) 1M 10M 100M 1G
Frequency (Hz)
Figure 3. Figure 4.

RECOMMENDED RS vs CAPACITIVE LOAD FREQUENCY RESPONSE vs CAPACITIVE LOAD

80 8
0.1dB Peaking Targeted
7
70 CL = 10pF
Gain to Capacitive Load (dB)

6
60 5
50 4
RS (W)

3
40 CL = 47pF
2
30 1 RS
CL = 100pF
20 0 75W x2
(1)
CL 1kW
-1
10 75W CL = 22pF
-2 NOTE: (1) 1kW is optional.

0 -3
1 10 100 1000 1 10 100 400
Capacitive Load (pF) Frequency (MHz)
Figure 5. Figure 6.

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TYPICAL CHARACTERISTICS: VS = ±5V (continued)

At G = +2 and RL = 150Ω, unless otherwise noted.

HARMONIC DISTORTION vs LOAD RESISTANCE HARMONIC DISTORTION vs SUPPLY VOLTAGE

-60 -40
VO = 2VPP VO = 2VPP
-45
f = 10MHz RL = 150W
-65 -50 f = 10MHz

Harmonic Distortion (dBc)

Harmonic Distortion (dBc)

2nd-Harmonic
-55
-70
-60
2nd-Harmonic
-65
-75
-70
-75
-80
-80
3rd-Harmonic 3rd-Harmonic
-85 -85
-90
dBc = dB Below Carrier dBc = dB Below Carrier
-90 -95
100 1k 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Resistance (W) Supply Voltage (±V)
Figure 7. Figure 8.

HARMONIC DISTORTION vs FREQUENCY HARMONIC DISTORTION vs OUTPUT VOLTAGE

-45 -50
VO = 2VPP RL = 150W
-50 -55
RL = 150W f = 10MHz
-55 -60
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)

-60 2nd-Harmonic
2nd-Harmonic -65
-65
-70
-70
-75
-75
3rd-Harmonic -80
-80 3rd-Harmonic
-85 -85

-90 -90
-95 -95
dBc = dB Below Carrier dBc = dB Below Carrier
-100 -100
1 10 100 0.5 1.5 2.5 3.5 4.5 5.5 6.5 7.0
Frequency (MHz) Output Voltage Swing (VPP)
Figure 9. Figure 10.

TWO-TONE, 3RD-ORDER INTERMODULATION SPURIOUS OUTPUT VOLTAGE AND CURRENT LIMITIATIONS

-50 5
RL = 100W 1W Internal
4
Third-Order Spurious Level (dBc)

Load Power at Matched 50W Load Power Limit

-60 dBc = dB Below Carrier 3
2
100W Load Line
-70 1
VOUT (V)

25W Load Line

50MHz 0
-80 -1
20MHz -2
10MHz 50W Load Line
-90 -3
-4 1W Internal
Power Limit
-100 -5
-6 -4 -2 0 2 4 6 8 10 -200 -150 -100 -50 0 50 100 150 200
Single-Tone Load Power (dBm) IO (mA)
Figure 11. Figure 12.

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TYPICAL CHARACTERISTICS: VS = ±5V (continued)

At G = +2 and RL = 150Ω, unless otherwise noted.

CHANNEL SWITCHING CHANNEL-TO-CHANNEL SWITCHING TIME

1.5 1.5
Output Voltage (V)

Output Voltage (V)

1.0 1.0
0.5 Output Voltage 0.5
0 0
-0.5 -0.5 Output Voltage
-1.0 3.5 -1.0 3.5
-1.5 3.0 -1.5 3.0

Channel Select (V)

Channel Select (V)

VSEL 2.5 VSEL 2.5
2.0 2.0
1.5 1.5
RL = 150W 1.0 1.0
VIN_Ch1 = 400MHz, 1VPP 0.5 VIN_Ch0 = +0.5VDC 0.5
VIN_Ch0 = 0VDC 0 VIN_Ch1 = -0.5VDC 0
-0.5 -0.5
Time (5ns/div) Time (5ns/div)
Figure 13. Figure 14.

CHANNEL SWITCHING GLITCH DISABLE/ENABLE TIME

40 1.5
Output Voltage (V)
Output Voltage (mV)

30 1.0 Output Voltage

At Matched Load 0.5
20 (0V input both channels)
0
10
-0.5
0 -1.0 3.5
-10 -1.5 3.0

Enable Voltage (V)

VEN 2.5
-20
Channel Select (V)

6 2.0
1.5
VSEL 4
1.0
2 0.5
VIN_Ch1 = 0V
0 VIN_Ch0 = 200MHz, 1VPP 0
-2 -0.5
Time (10ns/div) Time (20ns/div)
Figure 15. Figure 16.

DISABLE/ENABLE SWITCHING GLITCH CHANNEL-TO-CHANNEL CROSSTALK

20 -20
Output Voltage (V)

15 At Matched Load Input-Referred

10 -30
5
-40
0
Crosstalk (dB)

B0 Selected
-5 -50 B1 Driven
-10
-60
Enable Voltage (V)

6 R1 Selected
-70
VEN 4 R0 Driven
2 -80
0
-2 -90
Time (100ns/div) 1M 10M 100M 1G
Frequency (Hz)
Figure 17. Figure 18.

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TYPICAL CHARACTERISTICS: VS = ±5V (continued)

At G = +2 and RL = 150Ω, unless otherwise noted.

ALL HOSTILE AND ADJACENT-CHANNEL CROSSTALK vs

FREQUENCY CLOSED-LOOP OUTPUT IMPEDANCE vs FREQUENCY
0 10k
Input-Referred
-10
1k Disabled

Output Impedance (W)

-20
Crosstalk (dB)

-30 100
-40
Adjacent Channel Crosstalk
-50 10

-60
All Hostile Crosstalk 1
-70 Enabled

-80 0.1
1M 10M 100M 1G 100k 1M 10M 100M 1G
Frequency (Hz) Frequency (Hz)
Figure 19. Figure 20.

INPUT IMPEDANCE vs FREQUENCY PSRR vs FREQUENCY

10M 60
-PSRR
Power-Supply Rejection Ratio (dB)

50
1M +PSRR
Input Impedance (W)

40
100k
30
10k
20

1k 10

100 0
100k 1M 10M 100M 1G 100 1k 10k 100k 1M 10M 100M 1G
Frequency (Hz) Frequency (Hz)
Figure 21. Figure 22.

SUPPLY CURRENT vs TEMPERATURE TYPICAL DC DRIFT OVER TEMPERATURE

40 5.0 10
Output Offset Voltage (VOS)
38 4.5 Left Scale 9
Output Offset Voltage (mV)

36 4.0 8

Input Bias Current (mA)

Supply Current (mA)

34 3.5 7
32 3.0 6
30 2.5 5
28 2.0 4
26 1.5 Input Bias Current (IB) 3
Right Scale
24 1.0 2
22 0.5 1
20 0 0
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125
Ambient Temperature (°C) Ambient Temperature (°C)
Figure 23. Figure 24.

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TYPICAL CHARACTERISTICS: VS = ±5V (continued)

At G = +2 and RL = 150Ω, unless otherwise noted.

INPUT VOLTAGE AND CURRENT NOISE

100

Voltage Noise (nV/ÖHz)

Current noise (pA/ÖHz)
10 Voltage Noise (6.7nV/ÖHz)

Input Current Noise (3.8pA/ÖHz)

1
10 100 1k 10k 100k 1M 10M 100M
Frequency (Hz)
Figure 25.

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APPLICATIONS INFORMATION
that the 75Ω input matching impedance is set here by
2:1 HIGH-SPEED VIDEO MULTIPLEXER the parallel combination of 92Ω and 402Ω. In order
OPERATION not to disturb the sync, color burst, and blanking if
present, the inverting amplifiers are only switched on
The OPA3875 can be used as a triple 2:1 high-speed during active video.
video multiplexer, as illustrated in the front page
schematic for an RGB signal. Figure 26 shows a LOGO INSERTER
simplified version of the front page schematic in
which one output is shown with its input and output Figure 28 illustrates the principle of overlaying a
impedance matching resistors. picture in a picture. The picture comes through U1;
the signal to be overlayed comes through U2. Here
RGB VIDEO INVERTER we have a reference voltage of 0.714V in channel 2
indicating that we will highlight a section of the picture
Figure 27 illustrates an extension of the previously with white (for NTSC-related RGB video). How much
shown RGB switching circuit with a noninverting white comes through depends on the combination of
signal going through channel 1 and an inverted signal select 1 and select 2 pins as well as the series output
going through channel two. Here, the output resistance of each OPA3875. To match the 75Ω
impedance of the OPA3875 is set to 75Ω. Looking at output impedance of the video cable, the parallel
the input part of this circuit, we see that the RGB combination of the series output resistance (R and
signal is inverted with an OPA3693 fixed gain set in nR) needs to be 75Ω. The two select pins gives us 2
an inverting configuration with a reference voltage on bits of control. By selecting n = 2, you have the
the noninverting node. The reference voltage, set capability of a 0% highlight (full original video signal),
here at 0.714V, has a gain of 1 at the output of the 33% highlight, 66% highlight, and 100% highlight (all
OPA3691 as the input signal is AC-coupled (not white). By selecting n = 3, you have 0%, 25%, 75%,
represented here). This bias voltage is required to and 100% highlight capabilities, etc.
prevent the video from swinging negative. Note also

+5V

1/3 OPA3875

VIN_1 x1
75W

75W
VOUT

402W
VIN_2 x1
75W 402W

-5V EN
Channel
Select

Figure 26. Triple 2:1 High-Speed Video Multiplexer

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+5V

OPA3875

RIN x1
75W
92W ROUT

402W
GIN x1
402W
92W

75W
BIN x1
GOUT
92W 300W
402W
300W
1/3 402W
OPA3693 x1
VREF
300W 75W
BOUT
300W
1/3 402W
OPA3693 x1
VREF 402W
300W

300W
1/3
OPA3693 x1
VREF

Channel
VREF = 0.749V Select
-5V EN

Figure 27. RGB Video Inverter

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+5V

U1

OPA3875

RIN x1 RO
75W ROUT

402W
GIN x1
402W
75W

RO
BIN x1 GOUT
75W
402W

402W
x1

RO
BOUT
x1
402W

402W

x1

VREF

-5V EN

Select 1

Select 2 U2

OPA3875

x1 nRO

402W
x1
402W

nRO
x1

402W

402W
x1

nRO

x1
402W

402W

x1 VREF = 0.714V
RO || nRO = 75W
VREF

-5V EN

Figure 28. Logo Inserter

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ADC INPUT MUX

Figure 29 shows the OPA3875 used as a multiplexer in a high-speed data acquisition signal chain.

+5V

250W
OPA3875 +3.3V
VCC
VIN1 x1
250W
IN 1/2
250W VCM ADS5232
402W IN

402W
250W 250W

+3.3V
VCC
VIN2 x1
250W
IN 1/2
250W VCM ADS5232
402W IN

402W 250W 250W

+3.3V
VCC
VIN3 x1
250W
IN 1/2
250W VCM ADS5232
402W IN
VIN4 x1

402W
250W

VIN5 x1

VIN6 x1

-5V Channel EN
Select

Figure 29. ADC Input Multiplexer

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DESIGN-IN TOOLS problem have been suggested. When the primary

considerations are frequency response flatness,
pulse response fidelity, and/or distortion, the simplest
DEMONSTRATION FIXTURE and most effective solution is to isolate the capacitive
A printed circuit board (PCB) is available to assist in load from the feedback loop by inserting a series
the initial evaluation of circuit performance using the isolation resistor between the amplifier output and the
OPA3875. The fixture is offered free of charge as an capacitive load. This isolation resistor does not
unpopulated PCB, delivered with a user's guide. The eliminate the pole from the loop response, but rather
summary information for this fixture is shown in shifts it and adds a zero at a higher frequency. The
Table 1. additional zero acts to cancel the phase lag from the
capacitive load pole, thus increasing the phase
Table 1. OPA3875 Demonstration Fixture margin and improving stability.
LITERATURE The Typical Characteristics show the recommended
PRODUCT PACKAGE ORDERING NUMBER NUMBER RS versus capacitive load and the resulting frequency
OPA3875IDBQ SSOP-16 DEM-OPA-SSOP-3E SBOU043 response at the load; see Figure 5 and Figure 6,
respectively. Parasitic capacitive loads greater than
The demonstration fixture can be requested at the 2pF can begin to degrade the performance of the
Texas Instruments web site at (www.ti.com) through OPA3875. Long PCB traces, unmatched cables, and
the OPA3875 product folder. connections to multiple devices can easily cause this
value to be exceeded. Always consider this effect
carefully, and add the recommended series resistor
MACROMODELS AND APPLICATIONS as close as possible to the OPA3875 output pin (see
SUPPORT the Board Layout Guidelines section).

Computer simulation of circuit performance using DC ACCURACY

SPICE is often useful when analyzing the
performance of analog circuits and systems. This is The OPA3875 offers excellent DC signal accuracy.
particularly true for video and RF amplifier circuits Parameters that influence the output DC offset
where parasitic capacitance and inductance can have voltage are:
a major effect on circuit performance. A SPICE model • Output offset voltage
for the OPA875 is available through the Texas • Input bias current
Instruments web site at www.ti.com. Use three of • Gain error
these models to simulate the OPA3875. These
models do a good job of predicting small-signal AC • Power-supply rejection ratio
and transient performance under a wide variety of • Temperature
operating conditions. They do not do as well in Leaving both temperature and gain error parameters
predicting the harmonic distortion or dG/dP aside, the output offset voltage envelope can be
characteristics. These models do not attempt to described as shown in Equation 1:
distinguish between the package types in their
- PSRR+
small-signal AC performance nor do they predict VOSO_envelope = VOSO + (RS·Ib) x G ± |5 - (VS+)| x 10 20
channel-to-channel effects. - PSRR- - CMRR
± |-5 - (VS+)| x 10 20 + VCM x 10 20

OPERATING SUGGESTIONS (1)

With:
VOSO: Output offset voltage
DRIVING CAPACITIVE LOADS RS: Input resistance seen by R0, R1, G0, G1, B0,
One of the most demanding, yet very common load or B1.
conditions is capacitive loading. Often, the capacitive Ib: Input bias current
load is the input of an ADC—including additional G: Gain
external capacitance that may be recommended to
improve ADC linearity. A high-speed device such as VS+: Positive supply voltage
the OPA3875 can be very susceptible to decreased VS–: Negative supply voltage
stability and closed-loop response peaking when a PSRR+: Positive supply PSRR
capacitive load is placed directly on the output pin. PSRR–: Negative supply PSRR
When the device open-loop output resistance is
considered, this capacitive load introduces an
additional pole in the signal path that can decrease
the phase margin. Several external solutions to this
14 Submit Documentation Feedback Copyright © 2006–2008, Texas Instruments Incorporated

Product Folder Link(s): OPA3875

 OPA3875
www.ti.com ............................................................................................................................................ SBOS341D – DECEMBER 2006 – REVISED AUGUST 2008

Evaluating the front-page schematic, using a NOISE PERFORMANCE

worst-case, +25°C offset voltage, bias current and
The OPA3875 offers an excellent balance between
PSRR specifications and operating at ±6V, gives a
voltage and current noise terms to achieve low output
worst-case output equal to Equation 2:
noise. As long as the AC source impedance looking
- 50
20 out of the noninverting node is less than 100Ω, this
±14mV + 75W x ±18mA x 2 ± |5 - 6| x 10
current noise will not contribute significantly to the
- 51 total output noise. Figure 30 shows this device noise
20
± |-5 - (-6)| x 10 analysis model with all the noise terms included. In
this model, all noise terms are taken to be noise
= ±22.7mV (2) voltage or current density terms in either nV/√Hz or
pA/√Hz.
DISTORTION PERFORMANCE
+5V
The OPA3875 provides good distortion performance
into a 100Ω load on ±5V supplies. Relative to
en 1/3 OPA3875
alternative solutions, it provides exceptional
performance into lighter loads. Generally, until the x1
fundamental signal reaches very high frequency or
RS ib
power levels, the 2nd-harmonic dominates the
eo
distortion with a negligible 3rd-harmonic component.
eRS x1
Focusing then on the 2nd-harmonic, increasing the 402W
load impedance improves distortion directly. Also, 4kTRS
providing an additional supply decoupling capacitor 402W
(0.01µF) between the supply pins (for bipolar
operation) improves the 2nd-order distortion slightly
(3dB to 6dB).
-5V Channel EN
In most op amps, increasing the output voltage swing Select

increases harmonic distortion directly. The Typical

Characteristics show the 2nd-harmonic increasing at Figure 30. Noise Model
a little less than the expected 2X rate while the
3rd-harmonic increases at a little less than the The total output spot noise voltage can be computed
expected 3X rate. Where the test power doubles, the as the square root of the sum of all squared output
2nd-harmonic increases only by less than the noise voltage contributors. Equation 3 shows the
expected 6dB, whereas the 3rd-harmonic increases general form for the output noise voltage using the
by less than the expected 12dB. This also shows up terms shown in Figure 30.
in the two-tone, 3rd-order intermodulation spurious 2 2
(IM3) response curves. The 3rd-order spurious levels eo = 2 en + (ibRS) + 4kTRS
(3)
are extremely low at low output power levels. The
output stage continues to hold them low even as the Dividing this expression by the device gain (2V/V)
fundamental power reaches very high levels. As the gives the equivalent input-referred spot noise voltage
Typical Characteristics show, the spurious at the noninverting input as shown in Equation 4.
intermodulation powers do not increase as predicted en = 2 2
en + (ibRS) + 4kTRS
by a traditional intercept model. As the fundamental (4)
power level increases, the dynamic range does not
Evaluating these two equations for the OPA3875
decrease significantly. For two tones centered at
circuit and component values shown in Figure 26
20MHz, with 4dBm/tone into a matched 50Ω load
gives a total output spot noise voltage of 13.6nV/√Hz
(that is, 1VPP for each tone at the load, which requires
and a total equivalent input spot noise voltage of
4VPP for the overall 2-tone envelope at the output
6.8nV/√Hz. This total input-referred spot noise
pin), the Typical Characteristics show a 82dBc
voltage is higher than the 6.7nV/√Hz specification for
difference between the test-tone power and the
the mux voltage noise alone. This number reflects the
3rd-order intermodulation spurious levels.
noise added to the output by the bias current noise
times the source resistor.

Copyright © 2006–2008, Texas Instruments Incorporated Submit Documentation Feedback 15

Product Folder Link(s): OPA3875
OPA3875
SBOS341D – DECEMBER 2006 – REVISED AUGUST 2008 ............................................................................................................................................ www.ti.com

THERMAL ANALYSIS b) Minimize the distance (< 0.25") from the

power-supply pins to high frequency 0.1µF
Heatsinking or forced airflow may be required under decoupling capacitors. At the device pins, the
extreme operating conditions. Maximum desired ground and power plane layout should not be in close
junction temperature will set the maximum allowed proximity to the signal I/O pins. Avoid narrow power
internal power dissipation as discussed in this and ground traces to minimize inductance between
document. In no case should the maximum junction the pins and the decoupling capacitors. The
temperature be allowed to exceed +150°C. power-supply connections (on pins 9, 11, 13, and 15)
Operating junction temperature (TJ) is given by TA + should always be decoupled with these capacitors.
PD × θJA. The total internal power dissipation (PD) is An optional supply decoupling capacitor across the
the sum of quiescent power (PDQ) and additional two power supplies (for bipolar operation) will improve
power dissipated in the output stage (PDL) to deliver 2nd-harmonic distortion performance. Larger (2.2µF
load power. Quiescent power is simply the specified to 6.8µF) decoupling capacitors, effective at lower
no-load supply current times the total supply voltage frequency, should also be used on the main supply
across the part. PDL depends on the required output pins. These may be placed somewhat farther from
signal and load but, for a grounded resistive load, is the device and may be shared among several
at a maximum when the output is fixed at a voltage devices in the same area of the PCB.
equal to 1/2 of either supply voltage (for equal bipolar c) Careful selection and placement of external
supplies). Under this condition PDL = VS2/(4 × RL), components will preserve the high-frequency
where RL includes feedback network loading. performance of the OPA3875. Resistors should be
Note that it is the power in the output stage and not in a very low reactance type. Surface-mount resistors
the load that determines internal power dissipation. work best and allow a tighter overall layout. Metal-film
and carbon composition, axially leaded resistors can
As a worst-case example, compute the maximum TJ also provide good high-frequency performance.
using an OPA3875 in the circuit of Figure 26 Again, keep their leads and PCB trace length as short
operating at the maximum specified ambient as possible. Never use wirewound type resistors in a
temperature of +85°C with all three outputs driving a high-frequency application. Other network
grounded 100Ω load to +2.5V: components, such as noninverting input termination
2
PD = 10V ´ 36mA + 3(5 /4 ´ (100W || 804W)) = 571mW resistors, should also be placed close to the package.
Maximum TJ = +85°C + (0.57W ´ 85°C/W) = 133°C d) Connections to other wideband devices on the
board may be made with short direct traces or
This worst-case condition is approaching the through onboard transmission lines. For short
maximum +150°C junction temperature. Normally, connections, consider the trace and the input to the
this extreme case is not encountered. Careful next device as a lumped capacitive load. Relatively
attention to internal power dissipation is required. wide traces (50mils to 100mils) should be used,
preferably with ground and power planes opened up
BOARD LAYOUT GUIDELINES around them. Estimate the total capacitive load and
set RS from the plot of Figure 5. Low parasitic
Achieving optimum performance with a high
capacitive loads (< 5pF) may not need an RS
frequency amplifier such as the OPA3875 requires
because the OPA3875 is nominally compensated to
careful attention to board layout parasitics and
operate with a 2pF parasitic load. If a long trace is
external component types. Recommendations that
required, and the 6dB signal loss intrinsic to a
will optimize performance include:
doubly-terminated transmission line is acceptable,
a) Minimize parasitic capacitance to any AC implement a matched impedance transmission line
ground for all of the signal I/O pins. Parasitic using microstrip or stripline techniques (consult an
capacitance on the output pin can cause instability: ECL design handbook for microstrip and stripline
on the noninverting input, it can react with the source layout techniques). A 50Ω environment is normally
impedance to cause unintentional bandlimiting. To not necessary on board, and in fact, a higher
reduce unwanted capacitance, a window around the impedance environment will improve distortion as
signal I/O pins should be opened in all of the ground shown in the Distortion versus Load plots.
and power planes around those pins. Otherwise,
ground and power planes should be unbroken
elsewhere on the board.

16 Submit Documentation Feedback Copyright © 2006–2008, Texas Instruments Incorporated

Product Folder Link(s): OPA3875

 OPA3875
www.ti.com ............................................................................................................................................ SBOS341D – DECEMBER 2006 – REVISED AUGUST 2008

With a characteristic board trace impedance defined INPUT AND ESD PROTECTION
based on board material and trace dimensions, a
The OPA3875 is built using a very high-speed
matching series resistor into the trace from the output
complementary bipolar process. The internal junction
of the OPA3875 is used as well as a terminating
shunt resistor at the input of the destination device. breakdown voltages are relatively low for these very
small geometry devices. These breakdowns are
Remember also that the terminating impedance will
reflected in the Absolute Maximum Ratings table. All
be the parallel combination of the shunt resistor and
device pins have limited ESD protection using internal
the input impedance of the destination device; this
diodes to the power supplies as shown in Figure 31.
total effective impedance should be set to match the
trace impedance. The high output voltage and current
+VCC
capability of the OPA3875 allows multiple destination
devices to be handled as separate transmission lines,
each with their own series and shunt terminations. If
External Internal
the 6dB attenuation of a doubly-terminated Pin Circuitry
transmission line is unacceptable, a long trace can be
series-terminated at the source end only. Treat the
trace as a capacitive load in this case and set the -VCC
series resistor value as shown in Figure 5. This will
not preserve signal integrity as well as a Figure 31. Internal ESD Protection
doubly-terminated line. If the input impedance of the
destination device is low, there will be some signal
These diodes provide moderate protection to input
attenuation due to the voltage divider formed by the
overdrive voltages above the supplies as well. The
series output into the terminating impedance.
protection diodes can typically support 30mA
e) Socketing a high-speed part like the OPA3875 continuous current. Where higher currents are
is not recommended. The additional lead length and possible (for example, in systems with ±15V supply
pin-to-pin capacitance introduced by the socket can parts driving into the OPA3875), current-limiting
create an extremely troublesome parasitic network series resistors should be added into the two inputs.
which can make it almost impossible to achieve a Keep these resistor values as low as possible
smooth, stable frequency response. Best results are because high values degrade both noise performance
obtained by soldering the OPA3875 onto the board. and frequency response.

Copyright © 2006–2008, Texas Instruments Incorporated Submit Documentation Feedback 17

Product Folder Link(s): OPA3875
OPA3875
SBOS341D – DECEMBER 2006 – REVISED AUGUST 2008 ............................................................................................................................................ www.ti.com

Revision History

Changes from Revision C (September 2007) to Revision D .......................................................................................... Page

• Changed storage temperature range rating in Absolute Maximum Ratings table from –40°C to +125°C to –65°C to
+125°C ................................................................................................................................................................................... 2

Changes from Revision B (December 2006) to Revision C ........................................................................................... Page

• Changed the ordering number column in Table 1. .............................................................................................................. 14

18 Submit Documentation Feedback Copyright © 2006–2008, Texas Instruments Incorporated

Product Folder Link(s): OPA3875

 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

OPA3875IDBQ ACTIVE SSOP DBQ 16 75 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 OP3875

OPA3875IDBQR ACTIVE SSOP DBQ 16 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 OP3875

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 3-Jun-2022

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA3875IDBQR SSOP DBQ 16 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 3-Jun-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
OPA3875IDBQR SSOP DBQ 16 2500 356.0 356.0 35.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 3-Jun-2022

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
OPA3875IDBQ DBQ SSOP 16 75 506.6 8 3940 4.32

Pack Materials-Page 3
 PACKAGE OUTLINE
DBQ0016A SCALE 2.800
SSOP - 1.75 mm max height
SHRINK SMALL-OUTLINE PACKAGE

SEATING PLANE

.228-.244 TYP
[5.80-6.19] .004 [0.1] C
A PIN 1 ID AREA
14X .0250
[0.635]
16
1

2X
.189-.197
[4.81-5.00] .175
NOTE 3 [4.45]

8
9
16X .008-.012
B .150-.157 [0.21-0.30] .069 MAX
[3.81-3.98] [1.75]
NOTE 4 .007 [0.17] C A B

.005-.010 TYP
[0.13-0.25]

SEE DETAIL A

.010
[0.25]
GAGE PLANE

.004-.010
0 -8 [0.11-0.25]
.016-.035
[0.41-0.88] DETAIL A
(.041 ) TYPICAL
[1.04]

4214846/A 03/2014

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 inch, per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MO-137, variation AB.

www.ti.com
 EXAMPLE BOARD LAYOUT
DBQ0016A SSOP - 1.75 mm max height
SHRINK SMALL-OUTLINE PACKAGE

16X (.063)
[1.6] SEE
SYMM
DETAILS
1
16

16X (.016 )
[0.41]

14X (.0250 )
[0.635] 8 9

(.213)
[5.4]

LAND PATTERN EXAMPLE

SCALE:8X

SOLDER MASK SOLDER MASK

METAL METAL
OPENING OPENING

.002 MAX .002 MIN

[0.05] [0.05]
ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4214846/A 03/2014

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DBQ0016A SSOP - 1.75 mm max height
SHRINK SMALL-OUTLINE PACKAGE

16X (.063)
[1.6]
SYMM
1
16

16X (.016 )
[0.41]
SYMM

14X (.0250 )
[0.635] 8 9

(.213)
[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.127 MM] THICK STENCIL
SCALE:8X

4214846/A 03/2014

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
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