915723, 3:55 PM ‘Nuala Asie Design Interview Questions | vsiteshers visi4freshers dDesign DFT Verification CMOS Nvidia Asic Design Interview Questions sitreshers February 24,2022 Add Comment" Company Preparation 41. Complete the blanks in the following question with the appropriate answer. Given Base CPI(Cycles per instruction) = 1, clock frequency = F GHz, Miss rate for L2 cache =M%, access time of L2 cache = Ans Miss rate for L3=N%, access time for L3 cache=B ns Main memory access time = C ns We have two memory system: ‘System 1-with L3 cache only ‘System 2-with a L3 cache and L2 cache M 2 N A 5 B 40 c 100 ‘System will have higher performance gain.(1 for system 1 and 2 for system 2). ‘The performance ratio of the high performance system to the lower performance system (round off integer part) is 2. Complete the blanks in the following question with the appro} ‘A.system has X MB, Y way set associative cache with block size Z Bytes. Processor generates M bit addresses in dition to tag there are 2 valid bit, 1 replacement bit and 1 modified bi. A npe:iiwwwisareshers.com/2022/02hnvdia-ase-design-inerview-questions html an915723, 3:55 PM ‘Nuala Asie Design Interview Questions | vsiteshers Write With Confidence Check your grammar, spelling, and punctuation instantly with Grammarly M 64 ‘The size of the tag array is KBytes 3. Complete the blanks in the following question with the appropriate answer. Consider the following circuit of identical NMOS transistors connected as shown in the figure below. VDD=5V; VTH (transistor threshold voltage) = 2V, Vin = 4V. N2 vop 1 cr NB Vistreshers voo Vin a. Voltage at node N1 is . b. Voltage at node N2 is Vv. . Voltage at node N3 is v. 4. Complete the blanks in the following question with the appropriate answer. In a digital design, power gating is implemented for standard cells with efficiency of 80% and power gating is implemented for RAMS with efficiency of 90% Why this ad? @ Standard cell dynamic power = 300mW and RAMS Dynamic power = 150mW. com/2022/02/nvidia-asic-design-nterviow-questions him! ane915723, 3:55 PM ‘Nuala Asie Design Interview Questions | vsiteshers Standard cell leakage power = 100mW and RAMS Leakage Power = 50mW. 10% of the standard cells are always ON and not power gated When the design is power-gated, the dynamic power is mW and leakage power is 5. Complete the blanks in the following question with the appropriate answer. Ads by Ge Why this ad? @ mW, ‘The following circuit consists of two identical flops F1, F2, a combinational logic cloud, and 10 identical clock buffers, The relevant timing parameters are listed in the table below, The circuit has a maximum operating frequency of 500 MHZ. Setup time of flop = 0.2ns Hold time of flop = 0.0ns Talk-q of flop = 0.2ns A hitps hv. vsitrashers.com/2022/02!nvidia-asic-design-nterview-questions html ane915723, 3:55 PM ‘Nuala Asie Design Interview Questions | vsiteshers Delay of single clock buffer = 0.1ns Ted FL = ve [visiatceshers Teb Teb Based on the above data ,TPI ns. 6. Complete the blanks in the following question with the appropriate answer. (0->1 event can occur on signal "A" within the window 15ps to 7Sps. The signal “B" stays at logic "1" from Ops to 120ps. 150 event can occur on signal "C* 45ps to 65ps. The delay of the AND gate is 20ps. ‘The delay of the NOT gate is 10ps. A v1 B Visiafreshers c y2 A npe:iiwwwisareshers.com/2022/02Invdia-ase-design-inerviow-questions html ana915723, 3:55 PM ‘Nuala Asie Design Interview Questions | vsiteshers If the signal nets "Y1" and "Y2" are routed on adjacent tracks, a crosstalk event might occur on these nets in the window, psto ps. Why this ad? @ 7. Complete the blanks in the following question with the appropriate answer. ‘Two flip flops are placed far from each other with no combinational logic in between, The distance between the two flop is 60mm, data wire delay is 400psimm and clock wire delay is 200ps/mm. Setup time of the flops is 0.5ns and clock to q delay is 0.5 ns, The clock periad is Sns. We need to insert retiming flops in the data path to meet timing constraints RST RST FFL FF2 lk | clk ~ [isiaireshers | —> 200 ps/men A com/2022/02/nvidia-asic-design-nterviow-questions him! ein2915723, 3:55 PM ‘Nuala Asie Design Interview Questions | vsiteshers The minimum number of retiming flops required for above circuit to work as per given timing constraints is Ads by Google feedback | Why this ad? @ 8. Complete the blanks in the following question with the appropriate answer. Design operating point changes from to a > a > Fout Fin] gq bar ag Oba eax Ob vise] Input Frequency (Fin) KHz =25 ‘Output Frequency (KHz) A2. Complete the blanks in the following question with the appropriate answer. npe:iiwwwvisareshers.com/2022/02Invdia-ase-design-inerviow-questions hin] m2915723, 3:55 PM ‘Nuala Asie Design Interview Questions | vsiteshers CR NoT 15 20 AND 10 15 BUFFER 10 20 XOR 25 20 For t>0 output 2=0 for a duration of, ns, 13. Complete the blanks in the following question with the appropriate answer. traffic signal cycles from GREEN to YELLOW, YELLOW to RED and RED to GREEN. In each cycle, GREEN is turned on for "G" seconds, YELLOW is turned on for "Y" seconds and the RED is turned on for "R" seconds, (FSM). This traffic light has to be implemented using a finite state machine The only input to this FSM is a clock of "N" seconds period. Green "G" (in seconds)=12 Yellow "Y" (in seconds)=3 Red "R" (in seconds)=15 Clock Period N (in seconds}=3 The minimum number of fip flops required to implement this logic, 14. Complete the blanks in the following question with the appropriate answer. A digital logic is implemented in the fashion shown in the diagram. Inputs of the first xor gate are : (1, X). All the Xor-gates after this stage have inputs as : (output of previous stage, X). °N" Xor-gates are connected in series as per the diagram. A npe:iiwwwisareshers.com/2022/02Invdia-ase-design-inerviow-questions html anz915723, 3:55 PM ‘Nuala Asie Design Interview Questions | vsiteshers pynay ry) Nn x Visiafreshers = = Number of Xor gates connected in series (N)= 50 1) Output of Nth xorgate is 2) Output of " Note: If the answer is NOT(x) or inversion of x then mention it as either x’ or x ‘or xbar, xor-gate when passed through a not-gate is 15. Complete the blanks in the following question with the appropriate answer. Consider a rotating disk, with 1/4th of the disk painted black and white alternatively. There are two sensors A and B mounted close to the disk, but not touching the disk. Sensors A and B are 45 degrees apart as shown. The sensors output logic 1 when the color of the disk below it shall be white and logic 0 when it shall be black For eg: In the current position both the sensors output logic 1 Delay for Inverter (Td), Setup time (Tsu) and Clock to Q (Teq) are given in the below table Tsu (ns) os Teq (ns) 0s A hitps hv. vsitrashers.com/2022/02!nvidia-asic- design-nterview-questions him! oz915723, 3:55 PM ‘Nuala Asie Design Interview Questions | vsiteshers rotations per microsecond in clockwise direction answer as +100. 16. Complete the blanks in the following question with the appropriate answer. M takes X no. of days to complete one-fifth of the work, N takes Y no. of days to complete one-tenth of the same work and O takes Z no. of days to complete half the work. Hall of them work together for 4 days and M and © quit, how long will it take for N to complete the remaining work done. Y 6 12 N will complete the work in days. Note: Round the number to nearest Integer. For Ex: if the answer is 25.1 then enter 25, if the answer is 25.9 then enter 26. 17. Complete the blanks in the following question with the appropriate answer. ‘Aman can row A kmph in still water. If the river is flowing at a speed of B kmph, it takes him C minutes to row to a place and back. How far is the place? 8 (kmph) 3 C (minutes) 56 Parameters Note: Pis truncate to 2 decimal values, For example: if the answer is 3.452, enter 3.45 if the answer is 5, enter 5,00 Ifthe answer is 5.5, enter 5.50 Place is Km away. 18. Complete the blanks in the following question with the appropriate answer. How many zeroes are there at the end (Isb side), in the decimal expansion of 2021! (2021 factorial)? ‘The number of zeroes is: 19. Complete the blanks in the following question with the appropriate answer Eight ants are present, one at each vertex of an octagon. Each ant randomly picks a direction and starts to move along the edge of the octagon. a npe:iiwwwisareshers.com/2022/02Invdia-ase-design-inerviow-questions html s0n2915723, 3:55 PM ‘Nuala Asie Design Interview Questions | vsiteshers main() ( inti) Assume the following values for i & j print("%od al, i>j); ) Values: 68 2 41) First Output___ 2) Second Output__. a visi4freshers Hi 'm Designer of this blog. RELATED POSTS 0 comments: To leave a comment, click the button below to sign in with Blogger. Newer Post Home hitps sv. vsitrashers.com/2022/02/nvidia-asic-design-nterview-questions html Older Post nie915723, 3:55 PM ‘Nuala Asie Design Interview Questions | vsiteshers Copyright © 2023 visistreshers Published By visiafreshers Aa npe:iiwwwvisareshers.com/2022/02Invdia-ase-design-inerview-questions html rane