1)Convert the following number present in hexadecimal format to binary format:

(ECE.2021)16
A) 1110 1100 1110. 0010 0000 0010 0001
B) 1110 1100 1110. 10 0 10 1
C) 1110 1100 1110. 10 00 10 01
D) 1110 1100 1110. 010 000 010 001

2) A new Binary Coded Pentary (BCP) number system is proposed in which every digit of a
base-5 number is represented by its corresponding 3-bit binary code. For example, the base-5
number 24 will be represented by its BCP code 010100. In this numbering system, the BCP
code 100010011001 corresponds of the following number is base-5 system.
A)423
B)1324
C)2201
D)4231

3)A digital system is required to amplify a binary-encoded audio signal. The user should be
able to control the gain of the amplifier from minimum to a maximum in 100 increments. The
minimum number of bits required to encode, in straight binary, is
A)8
B)6
C)5
D)7

4)A signed integer has been stored in a byte using the 2’s complement format. We wish to
store the same integer in a 16 bit word. We should
A)Copy the original byte to the less significant byte of the word and fill the more significant
with zeros
B)Copy the original byte to the more significant byte of the word and fill the less significant
byte with zeros
C)Copy the original byte to the less significant byte of the word and make each fit of the
more significant byte equal to the most significant bit of the original byte
D)Copy the original byte to the less significant byte as well as the more significant byte of
the word

5)A Boolean function f of two variables x and y is defined as follows : ƒ(0,0) = ƒ(0,1) =
ƒ(1,1) = 1 ; ƒ(1,0) =0 ; Assuming complements of x and y are not available, a minimum cost
solution for realizing “ƒ” using only 2-input NOR gates and 2- input OR gates (each having
unit cost) would have a total cost of
A)1 unit
B) 4 units
C) 3 units
D) 2 units
6)If X = 1 in logic equation [𝑋 + 𝑍{𝑌' + (𝑍' + 𝑋𝑌')}]{𝑋' + 𝑋'(𝑋 + 𝑌)} = 1, then
A) Y=Z
B) Y=!Z
C) Z=1
D) Z=0
7)If 61 = 7 , the base if the number system is
A)7
B)8
C)9
D)6

8)The point P in the following figure is stuck at 1. The output f will be

A)𝐴𝐵𝐶'
B)𝐴'
C)𝐴𝐵'𝐶
D)A

9)The circuit shown in figure converts

A)BCD to binary code

B)Binary to excess-3 code
C)Excess-3 to gray code
D)Gray to binary code

10)Two products are sold from a vending machine, which has two push buttons P1 and P2.
When a buttons is pressed, the price of the corresponding product is displayed in a 7 -
segment display. If no buttons are pressed,'0’ is displayed signifying ‘Rs.0’. If only P1 is
pressed, ‘2’ is displayed, signifying ‘Rs.2’ If only P2 is pressed ‘5’ is displayed, signifying
‘Rs.5’ If both P1 and P2 are pressed, ‘E’ is displayed, signifying ‘Error’ The names of the
segments in the 7 - segment display, and the glow of the display for ‘0’, ‘2’, ‘5’ and ‘E’ are
shown below.

Consider (1)push buttons pressed/not pressed in equivalent to logic 1/0 respectively. (2) a
segment glowing/not glowing in the display is equivalent to logic 1/0 respectively What are
the minimum numbers of NOT gates and 2-input OR gates required to design the logic of the
driver for this 7 - Segment display
A)3 NOT and 4 OR
B)2 NOT and 4 OR
C)1 NOT and 3 OR
D)2 NOT and 3 OR

11)In the figure is A = 1 and B = 1, the input B is now replaced by a sequence 101010....., the
output x and y will be

A)Fixed at 0 and 1 respectively

B)x = 1010…………. and y = 0101…………..
C)x = 1010…………. and y = 1010………….
D)Fixed at 1 and 0 respectively

12)The figure is shows a mod-K counter, here K is equal to

A)1
B)2
C)3
D)4

13)In the figure, the J and K inputs of all the four Flip-Flips are made high. The frequency of
the signal at output Y is:

A)0.833 kHz
B)1 kHz
C)0.91 kHz
D)0.77 kHz

14)In the modulo-6 ripple counter shown in figure, the output of the 2- input gate is used to
clear the J-K flip-flop. The 2-input gate is

A)NAND gate
B)NOR gate
C)AND gate
D) OR gate

15)The given figure shows a ripple counter using positive edge triggered flip flops. If the
present state of the counter is Q2Q1Q0 = 001 then is next state Q2Q1Q0 will be
A)010
B)111
C)100
D)101

16)Two D - flip - flops, as shown below, are to be connected as a synchronous counter that
goes through the sequence 00-01-11-10- 00 – 01 -----. The inputs D0 and D1 respectively
should be connected as,

A) 𝑄1'𝑎𝑛𝑑𝑄0
B) 𝑄0'𝑎𝑛𝑑𝑄1
C) 𝑄1'𝑄0𝑎𝑛𝑑𝑄0𝑄1'
D) 𝑄1'𝑄0'𝑎𝑛𝑑𝑄0𝑄1

17)For the circuit shown in figures below, two 4 - bit parallel - in serial - out shift registers
loaded with the data shown are used to feed the data to a full adder. Initially, all the flip -
flops are in clear state. After applying two clock pulse, the output of the full-adder should be

A)S = 0 , C0 = 1
B)S = 1 , C0 = 1
C)S = 1 , C0 = 0
D)S = 0 , C0 = 0
18)In the following circuit, X is given by

A)𝑋 = 𝐴(𝐵𝐶)' + 𝐴'𝐵𝐶' + (𝐴𝐵)'𝐶 + 𝐴𝐵𝐶

B) 𝑋 = 𝐴'𝐵𝐶 + 𝐴𝐵'𝐶 + 𝐴𝐵𝐶' + (𝐴𝐵𝐶)'
C)𝑋 = 𝐵𝐶 + 𝐴𝐶 + 𝐴𝐵
D)𝑋 = (𝐵𝐶)' + (𝐴𝐶)' + (𝐴𝐵)'
19)The logic function implemented by the circuit below is (ground implies a logic “0”)

A)𝐹 = 𝑃𝑄
B)𝐹 = 𝑃 +𝑄
C)𝐹 = 𝑃' 𝑄 + 𝑃𝑄'
D)𝐹 = 𝑃|𝑄
20)For each of the positive edge-triggered J K - flip flop used in the following figure, the
propagation delay is Δt.

A)

B)

C)

D)