A PROGRAMMABLE PRE-CURSOR ISI EQUALIZATION CIRCUIT FOR HIGH-SPEED

SERIAL LINK OVER HIGHLY LOSSY BACKPLANE CHANNEL

Bo Wang1, Dianyong Chen1, Bangli Liang1, Jinguang Jiang2 and Tad Kwasniewski1
1
DOE, Carleton University, 1125 Colonel By Dr., Ottawa, ON, K1S 5B6, Canada
2
ISS, Wuhan University, Wuhan, Hubei, China 430079
ABSTRACT equalizers, etc. Among all the types of equalizers, DFE is
the most effective one and it is regarded as the sub-optimum
This paper presents a programmable pre-cursor ISI receiver without any decision delay [8]. Compared with the
equalization circuit for high-speed serial data transmission pre-emphasis in the transmitter, the DFE can be
over highly lossy electrical backplane channels. Although implemented with adaptation algorithms to compensate the
decision-feedback-equalizer (DFE) provides an effective time variation and piece-wise variation of the transmission
way to compensate various channel impairments, such as properties of the backplane channels without extra back-
frequency dependent loss, dispersion and reflections in the channel transmission as in adaptive pre-emphasis.
legacy backplane environment, for high-speed, highly lossy Although the adaptive DFE has advantages over other
band-limited channel, the pre-cursor inter-symbol equalization methods, it can not remove the pre-cursor ISI.
interference (ISI) is still a significant problem for channel The reason is that DFE is a strictly causal system or it
equalization. A programmable pre-cursor ISI equalizer removes ISI on the basis of decisions that have been made
combined with a 3-tap DFE is implemented to work at 10- (the past bits). Therefore, the DFE performance heavily
Gb/s and compensate the channel loss of -20 dB. The results depends on the joint channel pulse response. The joint
show it outperform a traditional 5-tap DFE. channel pulse response can be reshaped with linear
equalizers. Because the properties of a backplane channel
Index Terms—Backplane, ISI, equalization, decision- are time variant and piecewise variant, the linear equalizers
feedback equalizer (DFE), band-limited channel, serial link, used to reshape the joint channel pulse response should be
SerDes, wireline transceiver. programmable. This paper describes a programmable pre-
cursor ISI equalization method for 10-Gb/s transmission
1. INTRODUCTION over a backplane channel with –20 dB loss at Nyquist
frequency. This equalizer, combined with a 3-tap DFE, has
The continuous improvement on the performance of better performance than a 5-tap traditional DFE.
CMOS ICs made it possible to transmit signals at the data The next section discusses the general properties of the
rates above multi-Gb/s over cables or backplanes. Due to the backplane channels. A brief review of some widely used
price-competitiveness of the legacy backplane, it is still one equalization structures is also given. In Section 3, the
of the main transmission media for high-speed serial proposed pre-cursor ISI equalization circuit and DFE
communications. The backplane is a complex environment circuits are presented. Results on this equalizer are
consisting of at least 11 different components and presents a compared with the results on a 5-tap traditional DFE are
serious challenge to data rates above 5-Gb/s [2]. The multi- followed in Section 5. Conclusion is drawn in Section 5.
Gb/s data rates serial communications are running into the
bandwidth limitation of the backplanes. The bandwidth 2. BACKPLANE CHANNEL AND EQUALIZATION
limitation is mainly caused by dielectric loss, skin effect,
and impedance discontinuities of the media. At data rates 2.1 Backplane Channel Characteristics
above the bandwidth of the band-limited channels, the
received signals are severely distorted due to the inter- The magnitude and phase frequency response of a typical
symbol interference (ISI). backplane channel is shown in Fig. 1. The attenuation is
Equalization is one of the means to compensate the about -20 dB at the 5-GHz (Nyquist frequency for 10-Gb/s
distortion caused by the effects of the band-limited data rates). The 3-dB bandwidth of this backplane is 500-
transmission media. The equalizer can be implemented as MHz. The phase response is shown in wrapped mode to 5-
pre-emphasis (or de-emphasis) in the transmitter, or GHz frequency, the nearly linear phase response can be
decision-feedback equalizer (DFE) in the receiver. There are observed, and the delay at 5-GHz is 5.43-ns. Therefore, the
several categories of equalizers used extensively, linear or distortion of the received signals is mainly from the
non-linear equalizers, continuous-time or discrete-time frequency dependent loss of the channel. The notch around

978-1-4244-3508-1/09/$25.00 ©2009 IEEE 1221

4-GHz is caused by the impedance discontinuities and this
results in reflection that deteriorates ISI in the receiver. "B20 thru" channel − S21 (dB20) "B20 thru" channel − S22 (dB20)
0 0

"B20 thru" channel − S21 Magnitude (dB) −10

Magnitude (dB)

Magnitude (dB)
0 −20
−20
Magnitude (dB)

−20 Mag(dB)=−20
−30
−40
−40 −40

−60 −60 −50

0 5 10 15 0 5 10 15 0 5 10 15
Frequency (Hz) 9
x 10 Frequency (Hz) 9 Frequency (Hz) 9
x 10 x 10
"B20 thru" channel − S21 phase (deg) "B20 thru" channel − S23 (dB20) "B20 thru" channel − S24 (dB20)
400 −20 −10
Phase (deg)

Magnitude (dB)

Magnitude (dB)
−30 −20
200

−40 −30
0
0 1 2 3 4 5 −50 −40
Frequency (Hz) 9
x 10
Fig. 1. The magnitude and phase frequency response of a −60
0 5 10 15
−50
0 5 10 15
backplane channel (S21). Frequency (Hz) x 10
9 Frequency (Hz) x 10
9

Fig. 3. The S21, S22, S23, and S24 of the backplane channel.
The channel pulse response when a 1-V 100-ps
rectangular pulse is applied to the input is shown in Fig. 2. 2.2 Channel Equalization
The received pulse is attenuated in magnitude, extended in
time and delayed by ~5.45-ns. The pre-cursor ISI (83.33- The equalization is one of the effective means to
mV) is comparable to the second post-cursor ISI (92.06- compensate the impairments caused by the low-cost
mV). Therefore, for this channel, the DFE with as many taps backplane environment. It can be implemented with
as possible to completely remove post-cursor ISI can not different structures.
achieve the same performance of a 3-tap DFE when pre- Pre-emphasis (also called feed-forward equalizer) is
cursor ISI is not removed. For this channel with the pre- usually a multi-tap FIR filter implemented in the transmitter.
cursor ISI, the maximum received signal eye height that a Constrained by the peak transmitter power, it actually de-
conventional DFE can achieve is the distance from the main emphasizes the low frequency components to achieve a
tap to the pre-cursor tap (315.4mV – 83.33mV = ~232mV). response whose Discrete Fourier Transform is flat.
channel pulse response Therefore, the de-emphasis FIR reduces the ISI at the
0.4 expense of received signal swing, and the signal-to-noise
0.3 ratio (SNR) in the receiver is decreased. Another
Voltage (V)

0.2 disadvantage of the equalizer in the transmitter is the

0.1 difficulty to use adaptive algorithm without a back-channel.
0 For high-speed multi-Gb/s data transmission, it becomes
−0.1 more and more difficult to implement receiver equalizer in
4 4.5 5 5.5 6
Time (s)
6.5 7 7.5
−9
8
the format of FIR filter except for DFE, because it must
x 10
Input pulse − 1V 100−ps perform delaying, multiplying, and adding analog (or multi-
1
level) signals in only one bit period (the baud period).
0.8
Therefore, some continuous-time equalizer utilizes inductors
Voltage (V)

0.6
or/and capacitors to obtain zeros at high frequency to flatten
0.4
frequency response. It can be implemented with on-chip
0.2
inductors. Conventional design of this type of equalizer does
0
not provide any programmability to modify the inductance
0 0.5 1 1.5 2 2.5 3 3.5 4
Time (s) −9
x 10
or/and capacitance.
Fig. 2. The pulse response of the backplane channel. Although the feedback branch of DFE is also FIR filter,
its inputs are binary. This advantage greatly simplifies
The characteristics of a differential backplane channel circuit implementation at high data rates. In addition DFE
are usually represented by 4-port S parameters, as shown in theoretically does not enhance noise as linear equalizers do.
Fig. 3. S21 is the insertion loss, S22 is the return loss, S23 is The filter coefficients of the DFE can be adapted easily with
the far-end cross-talk (FEXT), and S24 is the near-end a sign-sign least-mean-square (SS-LMS) algorithm. The tap
cross-talk (NEXT). The maximum return loss of -10dB is coefficients are adapted with equation 1.
due to the impedance discontinuities of the backplane
environment. C ( n + 1) = C ( n) + 2 μ sgn [e( n)]sgn [d ( n) ] (1)

1222
 where, gm is the transconductance of NMOS MN1/MN2.
where, C(n+1) is new coefficient value, C(n) is present
coefficient value, μ is the convergence factor, e(n) is the VDD
error signal, d(n) is the received data signal and sgn[] is sign
LD LD
function. S1 S2

Despite the various advantages of DFE it does not

necessarily outperform other equalization methods for a
channel with strong pre-cursor ISI. To achieve the best RL RL

performance, a conventional equalizer is usually used as a

OUTN OUTP
feed-forward-equalizer (FFE) to reduce pre-cursor ISI, and
DFE is used to remove post-cursor ISI. Unfortunately, it has MN1 MN2
been reported the combination of transmitter FFE and DFE INP 2Rs INN
only damages the link performance for highly distorted
channels [3]. The combination of receiver FFE and DFE Cs/2

may help. However, if the FFE does not provide any

4-bit
programmability, it may reshape the channel response to VB
give more pre-cursor ISI when the channel properties vary. VB
MN3 MN4

VSS
3. PROPOSED PRE-CURSOR ISI EQUALIZATION
Fig. 4. The pre-cursor ISI linear equalization (prLE) circuit.
3.1 Equalization Architectures
The source degeneration capacitor CS is programmable
There are several high-speed equalization architectures with four control bits.
published recently. A parallel-path equalizing filter with
4
inductors and adaptive current source circuit is proposed for CS = ∑ bi CSi (3)
40-Gb/s copper cable with -10dB loss [4]. The equalizer is i =1
designed with 10 on-chip inductors. Another Rx equalizer is
a 4-stage equalizer for 6-Gb/s and each RxEQ unit in one The DC gain of the prLE is determined by the load
stage can compensate 5-dB at 3-GHz (Nyquist frequency) resistance RL and source degeneration resistance RS.
with 4-bit programmability [5]. These equalizers are merely
linear continuous-time equalization methods in the receiver RL
side. In paper [1], a 4-tap transmitter FFE and 5-tap receiver AV = (4)
DC
DFE are designed to work at 10-Gb/s. However, as RS
discussed in paper [3], transmitter FFE reduces SNR of the
received signals, and it interacts with DFE adaptation. This At frequency above the channel bandwidth, the two zeros
topology only deteriorates link performance. Therefore, this from the load inductors and source capacitor would enhance
paper locates the optimum sampling instants to reduce pre- the gain of the prLE. With gm*(Rs || /sCs) >> 1, the gain is
cursor ISI and use unrolling DFE to eliminate post-cursor
ISI.
AV (s ) =
(RL + sLD )(1 + sRS CS ) (5)
We proposed a continuous-time pre-cursor ISI linear RS
equalization (prLE) circuit for highly lossy backplane
channel in this paper. It is composed of 4-bit programmable
capacitive degeneration, and two optional on-chip spiral 3.2 Equalizer with prLE and 3-tap DFE
inductors. The circuit is shown in Fig. 4. The on-chip
inductors and capacitors generate two zeros above the It can be seen from Fig. 8 that the prLE not only reduces the
bandwidth of the channel to amplify the attenuated high pre-cursor ISI, but also makes the post-cursor ISI smaller.
frequency signals and boost the effective bandwidth. In this work, the equalization scheme combines in the
Therefore, the pre-cursor ISI can be reduced. The inductors receiver side a prLE for pre-cursor ISI reduction and a 3-tap
can be optionally bypassed for some type of channel with DFE for post-cursor ISI removal. There are trade-offs in the
low loss. design. The prLE is not used to compensate all the channel
loss in the whole pass-band, but to boost the channel
The voltage transfer function of the continuous-time bandwidth to reduce pre-cursor ISI. If the gain of the prLE
prLE is is too large, it will also amplify much of the noise and
crosstalk at frequencies where SNR is poor. The prLE can
be programmed to cope with time variant channel and piece-
VOUT gm
AV (s ) = (s ) = ⋅ (RL + sLD ) (2) wise variant channel.
VIN 1 + g m (RS || 1 / C S )

1223
 A sign-sign LMS adaptive DFE follows the prLE is used 20
"Channel S21, prLE and S21+prLE" Magnitude − dB

to remove post-cursor ISI. For the highly lossy backplane

channel without prLE, the height of the eye-opening can not 10
be improved even with 5 or more taps DFE. This is because
the pre-cursor ISI would be the dominant interference. With 0
prLE in the receiver to compensate the channel bandwidth,

Magnitude (dB)
both the pre-cursor ISI and post-cursor ISI can be reduced. −10
Therefore, the adaptive DFE can be implemented with 3-tap
in this architecture. The entire equalization circuit in the −20

receiver is shown in Fig. 5.

Channel
−30
prLE
Channel + prLE
−40 7 8 9 10
10 10 10 10
Frequency (Hz)

Fig. 7. The frequency response of the channel, prLE and

combination.

4. EXPERIMENT RESULTS

The equalizer with prLE and 3-tap DFE (EUQ2) is

compared with the equalizer with 5-tap DFE (EQU1).
Fig. 5. The equalization circuit in the receiver.
4.1 Impulse Response
The magnitude and phase frequency response of the prLE
is shown in Fig. 6. With the two zeros, the gain is boosted The 1-V 100-ps square impulse response of the EQU1 and
for 3-dB at 500-MHz for this high loss channel, and about EUQ2 is shown in Fig. 8. For the EQU1 (up) with 5-tap
14-dB at 5-GHz (the Nyquist frequency). From the phase DFE, the five post ISIs are cancelled at the sampling points
response, the two zeros also introduce phase distortion, but (the circles in the plot, and the pre-cursor one is not changed
it is neglectable in the systems. The decrease of the which is almost 1/3 of the main tap and close to the 2nd post
magnitude above is due to the CMOS technology. ISI in magnitude. However, the pre ISI of the EQU1 is 1/5
of the main tap, and the post 3 ISIs are cancelled with the 3-
"Pre−cursor ISI Equalization Circuit" Magnitude − dB tap DFE.
15
Magnitude (dB)

10 Receiver with 5−tap DFE

5
0.3
Voltage (V)

0
0.2
−5
7 8 9 10 11
0.1
10 10 10 10 10
Frequency (Hz) 0
"Pre−cursor ISI Equalization Circuit" Phase − degree
50 −0.1
6 6.5 7 7.5
Time (s) −9
x 10
Phase (deg)

0 Receiver with prLE and 3−tap DFE

1

−50
Voltage (V)

0.5

−100
7 8 9 10 11
10 10 10 10 10 0
Frequency (Hz)

Fig. 6. The frequency response of the pre-cursor ISI −0.5

equalizer. 6 6.5
Time (s)
7
−9
7.5
x 10

The frequency response of the channel, the prLE and the Fig. 8. The impulse response of equalized signals, prLE+3-
channel+prLE is shown in Fig. 7. The bandwidth of the tap DFE and 5-tap DFE.
channel is extended to around 2-GHz with the 4-bit
programmable prLE. The comparison of the impulse response between EQU1
and EQU2 is summarized in Table1. The main tap, 1st pre-
cursor ISI, and 5 post-cursor ISIs are compared. The main
tap of EQU2 (prLE+3-tap DFE) is almost 3 times larger
than the EQU1 (5-tap DFE), for the gain of the prLE at high

1224
frequency. The pre-cursor ISI is 26.4% of the main tap for 1
(a) received signal
0.6
(b) 5−tap DFE without prLE

EUQ1, and 15.4% for EUQ2. The 3rd post-cursor ISI is 0.8
lower than the first pre-cursor ISI; therefore, 3-tap DFE for

Amplitude (V)
Amplitude (v)
0.4
0.6
post-ISI cancellation is adequate. 0.4
0.2
0.2

Table 1: Comparison of impulse response with and 0

−0.5 0 0.5 1
0
−0.5 0 0.5 1
without pre-cursor ISI equalization (prLE) Time (s)
(c) signal after prLE
−10
x 10 Time (s)
(d) 3−tap DFE with prLE
−10
x 10

w/o prLE w/ prLE 1 1

Amplitude (V)

Amplitude (V)
Pre-cursor ISI 1 83.33mV 139.7mV 0.5 0.5

Main tap 315.4mV 906.6mV 0

Post-cursor ISI 1 215.5mV 169.3mV

0

−0.5 0 0.5 1 −0.5 0 0.5 1

Post-cursor ISI 2 92.06mV -196.3mV Time (s) −10
x 10 Time (s) −10
x 10

Post-cursor ISI 3 49.46mV -115.6mV Fig. 9. Comparison of eye diagrams. (a) received signals, (b)
Post-cursor ISI 4 32.92mV -23.07mV 5-tap DFE without prLE, (c) signals after prLE, and (d)
Post-cursor ISI 5 30.38mV 11.11mV equalizer with prLE and 3-tap DFE.

The vertical heights of the received signals at the data

4.2. Eye Diagram center sampling point (the dot line in Fig. 9) are compared,
as shown in Fig.10. From the plot, we can see the received
The proposed equalization system is designed for 10-Gb/s signals (a) are spread between 0-V and 1-V, and it is
data rate over the highly lossy backplane channel (-20dB difficult to detect the high or low logic levels from the
loss at 5-GHz). The eye diagram of 5-tap DFE and 3-tap distorted signals. From the histogram plot of 5-tap DFE in
DFE with prLE are compared and shown in Fig. 9. As Fig. 10(b), the center distributions of the low or high levels
shown in Fig 9, the received signal (a) is severely distorted are 0.1-V or 0.5-V, respectively. The magnitude and the eye
due to the frequency-dependent loss of the channel; (b) the opening of the received signals are improved with prLE and
equalized signal with only 5-tap DFE, the vertical height of 3-tap DFE equalization scheme, as shown in Fig. 10(b).
the eye is 165.8-mV. This is because the pre-cursor ISI is Now, the distribution centers of the low and high levels are
83.33-mV which is comparable with the 2nd post-cursor ISI. 0.1-V and 1.0-V, respectively.
The eye-opening can not be improved with even more taps
on the DFE; (c) the signal is equalized with prLE. The eye is 250
Received input data levels hist
300
Equalized data levels hist

opened, however the signal to noise ratio is not improved

200
too much; (d) the signal is compensated with prLE and 3-tap 200
DFE. The height of the eye is 558.6-mV which is enhanced 150

about three times than the 5-tap DFE equalization method. 100
100
The vertical height and horizontal jitter of the eye 50
diagram for the architecture with 5-tap DFE and with prLE 0 0
+ 3-tap DFE are compared and shown in Table 2. −0.5 0 0.5 1
Voltage levels at data center (V)
−0.2 0 0.2 0.4 0.6
Voltage levels at data center (V)
Received input data levels hist Equalized data levels hist
250 400
Table 2: Comparison of eye diagram of the two
architectures at 10-Gb/s. 200
300
150
200
Vertical Horizontal 100

height Jitter 50
100

DFE w/o prLE 165.83mV 29.65ps 0 0

−0.5 0 0.5 1 1.5 −0.5 0 0.5 1 1.5
DFE w/ prLE 558.60mV 27.60ps Voltage levels at data center (V) Voltage levels at data center (V)
Fig 10. Histogram of data center. (a) received signals, (b) 5-
tap DFE without prLE, (c) signals after prLE, and (d)
equalizer with prLE and 3-tap DFE.

The horizontal jitters of the received signals with the two

equalization architectures (5-tap DFE and prLE + 3-tap DFE)
are compared and shown in Fig. 11. There is a little
improvement on the jitter performance with the pre-cursor
ISI linear equalization (prLE) in the receiver.

1225
 CDR”, ISSCC Dig. Tech. Papers, pp. 100-101, Feb.
5−tap DFE: equalized data jitter 2008.
150 [5] H. Uchiki, Y. Ota, M. Tani, et al., “A 6Gb/s RX
equalizer adapted using direct measurement of he
100
equalizer output amplitude”, ISSCC Dig. Tech. Papers,
50 pp. 104-105, Feb. 2008.
Jitter =0.29651 UI
[6] Timothy O. Dickson, and Sorin P. Voinigescu, et al.,
0
0 0.2 0.4 0.6 0.8 1 “Low-power circuits for a 2.5V, 10.7-to-86-Gb/s serial
Time −10
x 10 transmitter in 130-nm SiGe BiCMOS”, IEEE J. Solid-
prLE + 3−tap DFE: equalized data jitter State Circuits, vol. 42, no. 10, pp. 2077-2085, Oct.
2007.
150
[7] Kannan Krishna, David A. Yokoyama-Martin, Aaron
100 Caffee, et al., “A multigigabit backplane transceiver
50
core in 0.13-um CMOS with a power-efficient
Jitter =0.27604 UI equalization architecture”, IEEE J. Solid-State Circuits,
0
0 0.2 0.4 0.6 0.8 1 vol. 40, no. 12, pp. 2658-2666, Dec. 2005.
Time −10
x 10 [8] Troy Beukema, Michael Sorna, Karl Selander, et al.,
Fig 11. Histogram of the horizontal jitters at zero crossing. “A 6.4-Gb/s CMOS SerDes core with feed-forward and
decision-feedback equalization”, IEEE J. Solid-State
5. CONCLUSION Circuits, vol. 42, no. 12, pp. 2633-2645, Dec. 2005.

The bandwidth of the transmission media and the data rates

of signals transmission conflict with each other. The inter-
symbol interference (ISI) is severe when the Nyquist
frequency of the transmitted signals is more above the
bandwidth of the channel. To transmit signals at high speed
and make the bandwidth used efficiently, the pre-coding (to
lower the signals bandwidth requirement) or equalization (to
compensate the channel bandwidth) is extensively utilized
in modern serial data communications. Decision-feedback
equalizer (DFE) is still the very effective equalization
method for cancelling the post-cursor ISI with adaptive
algorithms. In this paper, DFE combined with a
programmable pre-cursor ISI equalization (prLE) can
achieve larger eye-opening (higher SNR and lower BER)
with better trade-off on noise amplification and pre-cursor
ISI reduction.

6. REFERENCES

[1] John F. Bulzacchelli, Mounir Meghelli, Sergey V.

Rylov, et al., “A 10Gb/s 5-tap DFE/4-tap FFE
Transceiver in 90-nm CMOS technology”, IEEE J.
Solid-State Circuits, vol. 41, no. 12, pp. 2885-2900,
Dec. 2006.
[2] Jared L. Zerbe, Carl W. Werner, Vladimir Stojanovic,
et al., “Equalization and clock recovery for a 2.5-10-
Gb/s 2-PAM/4-PAM backplane transceiver cell”, IEEE
J. Solid-State Circuits, vol. 38, no. 12, pp. 2121-2130,
Dec. 2003.
[3] Jihong Ren, et al., “Precursor ISI reduction in high-
speed I/O”, IEEE Symposium on VLIS Circuits, pp.
134-135, 2007.
[4] Chih-Fan Liao and Shen-Iuan Liu, “A 40Gb/s CMOS
serial-link receiver with adaptive equalization and

1226