INTERNATIONAL UNIVERSITY

SCHOOL OF ELECTRICAL ENGINEERING

Digital Logic Design Laboratory

Lab 3

MSI Combinational Logic (II)

Full name: Đặng Huỳnh Minh Phúc

Student number: ITITIU22126
Class: ITIT22NE41
Date: 7/5/2024

Digital Logic Design Laboratory 1-13

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SCHOOL OF ELECTRICAL ENGINEERING

I. Objectives

In this laboratory, students will study:

- Understand the operation of combinational logic circuit.
- The operation of some combinational ICs such as: full adder, decoder, encoder.

II. Procedure

1. Design the adder with two one-bit binary.

a. Design the half adder two one-bit binary.
Two inputs are A, B. Two outputs are S and C.
Build the truth table and the expressions
A B C S
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
C= AB
S= A B+ A B
The simplified expressions:
C= AB
S= A ⨁ B
Implement the circuit via simulation software and paste the result in here

Make comment on the results

If both bits are 0, the sum is 0 and the carry is 0.
If one bit is 1 and the other bit is 0, the sum is 1 and the carry is 0.

Digital Logic Design Laboratory 2-13

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If both bits are 1, the sum is 0 and the carry is 1.

So, the half adder is quite efficient in performing binary addition, but it does not take
into account any carry that might be incoming from the previous bit addition.

b. Design the full adder two one-bit binary.

Three inputs are Cin, A, B. Two outputs are S and Cout.
Build the truth table and the expressions
A B Cin Cout S
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

Cout = A BC ¿ + A B C ¿ + AB C ¿ + ABC ¿
S = A BC ¿ + A B C ¿ + A B C ¿ + AB C¿
The simplified expressions:
S= A ⨁ B ⨁C
Implement the circuit via simulation software and paste the result in here

Digital Logic Design Laboratory 3-13

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Make comment on the results

If all three bits are 0, the sum is 0 and the carry is 0.
If only one bit is 1 (and the other two bits are 0), the sum is 1 and the carry is 0.
If two bits are 1 (and the other bit is 0), the sum is 0 and the carry is 1.
If all three bits are 1, the sum is 1 and the carry is 1.
So, the full adder is capable of handling the carry from the previous bit addition, which
makes it more versatile than a half adder for multi-bit addition operations.

2. 8-to-3 Priority Encoder (Interrupt sorter) – IC 74HC148

a. Investigate IC – 74HC148
Construct the circuit as below:

Figure 1 – Encoder 8-to-3 IC 74LS148

- The outputs are connected to LED displays to determine the logic levels.
- Choose the input data D0 - D7 by switches in the order from SW0 to SW7.
- Control EI by using switch.
- Observe the results and fulfill the truth table of 74HC148.

- What are the functions of GS and EO ?

Input Output
EI D0 D1 D2 D3 D4 D5 D6 D7 GS A2 A1 A0 E0
1 X X X X X X X X 1 1 1 1 1
0 1 1 1 1 1 1 1 1 1 1 1 1 0
0 X X X X X X X 0 0 0 0 0 1
0 X X X X X X 0 1 0 0 0 1 1
0 X X X X X 0 1 1 0 0 1 0 1
0 X X X X 0 1 1 1 0 0 1 1 1

Digital Logic Design Laboratory 4-13

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0 X X X 0 1 1 1 1 0 1 0 0 1
0 X X 0 1 1 1 1 1 0 1 0 1 1
0 X 0 1 1 1 1 1 1 0 1 1 0 1
0 0 1 1 1 1 1 1 1 0 1 1 1 1

GS
EO

Implement the circuit via simulation software and paste the result in here

b. Priority encoder
Let’s EI equal to 0, fill the outputs A2, A1, A0 in the following cases
A2 A1 A0
Case 1:
I3 = I2 = I1 = 0
1 0 0
I7 = I6 = I5 = I4 = I0 = 1.

Case 2:
I7 = I2 = 0.
0 0 0
I6 = I5 = I4 = I3 = I1= I0 =1

Case 3:
All 8 inputs are equal to 0. 0 0 0

Digital Logic Design Laboratory 5-13

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Case 1:
Implement the circuit via simulation software and paste the result in here

Make comment on results

The output Y2 Y1 Y0 is 001, which corresponds to input I1. This is because I1 is the
highest priority active (LOW) input.
GS' is 0 (LOW), indicating that at least one input is active (LOW).
EO' is 1 (HIGH), indicating that the Enable Input (EI) is inactive (HIGH). This is
because the IC 74HC148 is an active LOW device, and the Enable Output (EO’) is the
complement of the Enable Input (EI).

Case 2:
Implement the circuit via simulation software and paste the result in here

Digital Logic Design Laboratory 6-13

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Make comment on results

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Case 3:
Implement the circuit via simulation software and paste the result in here

Digital Logic Design Laboratory 7-13

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Make comment on results

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3. 2-to-4 Decoder - IC74HC139

Construct the circuit as below:

Figure 2 – Decoder 2-line-to-4-line IC 74HC139

- 4 outputs (Y0-Y3) are connected to LED display (Led 1-4).

- The data inputs (A, B) and control input (G) are connected to switches.
- Change the states of inputs to fulfill the truth table of IC 74HC139.

Inputs
Outputs
Control Data
G B A Y0 Y1 Y2 Y3
0 0 0 0 1 1 1
0 0 1 1 0 1 1
0 1 0 1 1 0 1
0 1 1 1 1 1 0
1 X X 1 1 1 1

Implement the circuit via simulation software and paste the result in here

Digital Logic Design Laboratory 8-13

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Briefly describe the operation of the IC

The decoders take as input a two-digit binary number (00, 01, 10, 11) and output by
selecting one of four lines.
The decoder can work either as a decoder or a demultiplexer. If the Enable pin (E’) is
connected to the ground, it works as a decoder. If the Enable pin is connected to the
VCC pin, it will work as a Demultiplexer.
The output pins for this decoder IC are active low, which means we will have an
inverted output.
When the enable input (nE) is HIGH, all outputs are forced HIGH. The enable input
can be used as the data input for a 1-to-4 demultiplexer application
4. 3-TO-8 Decoder– IC 74HC138
Construct the circuit as below:

Figure 3 – 3-to-8 Decoder/demultiplexer - IC 74HC138

- 8 outputs are connected by using LEDs.

- The inputs are controlled by switches.
- Observe the results and fulfill the truth table

Digital Logic Design Laboratory 9-13

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INPUT OUTPUT
E3 E2 E1 C B A Y0 Y1 Y2 Y 3 Y4 Y 5 Y 6 Y7
1 0 0 0 0 0 0 1 1 1 1 1 1 1
1 0 0 0 0 1 1 0 1 1 1 1 1 1
1 0 0 0 1 0 1 1 0 1 1 1 1 1
1 0 0 0 1 1 1 1 1 0 1 1 1 1
1 0 0 1 0 0 1 1 1 1 0 1 1 1
1 0 0 1 0 1 1 1 1 1 1 0 1 1
1 0 0 1 1 0 1 1 1 1 1 1 0 1
1 0 0 1 1 1 1 1 1 1 1 1 1 0
0 X X X X X 1 1 1 1 1 1 1 1
X 1 X X X X 1 1 1 1 1 1 1 1
X X 1 X X X 1 1 1 1 1 1 1 1

Implement the circuit via simulation software and paste the result in here

Briefly describe the operation of the IC

Inputs: The 74HC138 has three binary weighted address inputs (A0, A1, and A2),
which we can map to our inputs x, y, z.
Outputs: It decodes these inputs to eight mutually exclusive outputs (Y0 to Y7).
Enable Inputs: The device features three enable inputs (E1, E2, and E3). Every output
will be HIGH unless E1 and E2 are LOW and E3 is HIGH.

Digital Logic Design Laboratory 10-13

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Demultiplexing Capability: The 74HC138 can be used as an eight output

demultiplexer by using one of the active LOW enable inputs as the data input and the
remaining enable inputs as strobes.
Expansion: This multiple enable function allows easy parallel expansion of the
74HC138 to a 1-of-32 (5 lines to 32 lines) decoder with just four 74HC138 ICs and
one inverter.

5. Design combinational circuits using decoders and OR gate

- Implement Boolean expression using IC 74HC138 & OR gate.
- The data inputs A, B, C are connected to switches.
- The control inputs are in suitable levels.
- Implement the circuit and verify the truth table

a. f =x ' y z ' + xz
Establish the truth table
x y z f
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 0
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 1

Implement the circuit via simulation software and paste the result in here

Digital Logic Design Laboratory 11-13

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Verify the truth table and make comment on the results

The function is true for all cases where x is 1 and z is 1. This is because one of the
terms in the function is simply ‘xz’, so any time x and z are true, the function is true.
The function is also true when x is 0, y is 1, and z is 0 (x’yz’ term). This is the only
case where the function is true when x is 0.
The function is false for all other combinations of x, y, and z.

b. f =x ' yz + x + y ' z '

Establish the truth table
x y z f
0 0 0 1
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 1

Digital Logic Design Laboratory 12-13

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1 1 1 1

Implement the circuit via simulation software and paste the result in here

Verify the truth table and make comment on the results

The function is true for all cases where x is 1. This is because one of the terms in the
function is simply ‘x’, so any time x is true, the function is true.
The function is also true when x is 0, y is 1, and z is 1 (x’yz term) or when x is 0, y is
0, and z is 0 (y’z’ term). These are the only cases where the function is true when x is
0.
The function is false only when x is 0 and neither of the other two conditions (x’yz or
y’z’) are met.

Digital Logic Design Laboratory 13-13