Ina 199
Ina 199
1 Features 3 Description
• Wide Common-Mode Range: –0.3 V to 26 V The INA199 series of voltage-output, current-shunt
• Offset Voltage: ±150 μV (Maximum) monitors (also called current-sense amplifiers) are
(Enables Shunt Drops of 10-mV Full-Scale) commonly used for overcurrent protection, precision-
• Accuracy: current measurement for system optimization, or in
– Gain Error (Maximum Over Temperature): closed-loop feedback circuits. This series of devices
• ±1% (C Version) can sense drops across shunt resistors at common-
• ±1.5% (A and B Versions) mode voltages from –0.3 V to 26 V, independent of
– 0.5-μV/°C Offset Drift (Maximum) the supply voltage. Three fixed gains are available:
– 10-ppm/°C Gain Drift (Maximum) 50 V/V, 100 V/V, and 200 V/V. The low offset of the
• Choice of Gains: zero-drift architecture enables current sensing with
– INA199x1: 50 V/V maximum drops across the shunt as low as 10-mV
– INA199x2: 100 V/V full-scale.
– INA199x3: 200 V/V These devices operate from a single 2.7-V to 26-
• Quiescent Current: 100 μA (Maximum) V power supply, drawing a maximum of 100 µA
• Packages: 6-Pin SC70, 10-Pin UQFN of supply current. All versions are specified from –
40°C to 125°C, and offered in both SC70-6 and thin
2 Applications
UQFN-10 packages.
• Notebook Computers
• Cell Phones Device Information
• Qi-Compliant Wireless Charging Transmitters PART NUMBER PACKAGE(1) BODY SIZE (NOM)
• Telecom Equipment SC70 (6) 2.00 mm × 1.25 mm
INA199
• Power Management UQFN (10) 1.80 mm × 1.40 mm
• Battery Chargers
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
RSHUNT
Reference Supply Load
Voltage
GND R1 R3 IN-
2.7 V to 26 V IN+
V+
R2 R4
CBYPASS
0.01 mF
to
0.1 mF
Simplified Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
INA199
SBOS469H – APRIL 2009 – REVISED OCTOBER 2023 www.ti.com
Table of Contents
1 Features............................................................................1 8 Application and Implementation.................................. 18
2 Applications..................................................................... 1 8.1 Application Information............................................. 18
3 Description.......................................................................1 8.2 Typical Applications.................................................. 18
4 Device Comparison Table...............................................3 9 Power Supply Recommendations................................21
5 Pin Configuration and Functions...................................3 10 Layout...........................................................................21
6 Specifications.................................................................. 4 10.1 Layout Guidelines................................................... 21
6.1 Absolute Maximum Ratings........................................ 4 10.2 Layout Example...................................................... 21
6.2 ESD Ratings............................................................... 4 11 Device and Documentation Support..........................22
6.3 Recommended Operating Conditions.........................5 11.1 Documentation Support.......................................... 22
6.4 Thermal Information....................................................5 11.2 Receiving Notification of Documentation Updates.. 22
6.5 Electrical Characteristics.............................................6 11.3 Support Resources................................................. 22
6.6 Typical Characteristics................................................ 7 11.4 Trademarks............................................................. 22
7 Detailed Description...................................................... 11 11.5 Electrostatic Discharge Caution.............................. 22
7.1 Overview................................................................... 11 11.6 Glossary.................................................................. 22
7.2 Functional Block Diagram......................................... 11 12 Revision History.......................................................... 23
7.3 Feature Description...................................................12 13 Mechanical, Packaging, and Orderable
7.4 Device Functional Modes..........................................13 Information.................................................................... 24
V+ 3 4 IN+
GND 9 4 IN-
Figure 5-1. DCK Package 6-Pin SC70 Top View OUT 10 3 IN+
1 2
(1)
NC IN+
Figure 5-2. RSW Package 10-Pin UQFN Top View
A. NC(1) denotes no internal connection. These pins can be left floating or connected to any voltage between GND and V+.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Supply voltage 26 V
Differential (VIN+) – (VIN–) –26 26
Analog inputs, VIN+, VIN– (2) Common-mode(3), INA199Ax GND – 0.3 26 V
Common-mode(3), INA199Bx and INA199Cx GND – 0.1 26
REF input GND – 0.3 (V+) + 0.3 V
Output(3) GND – 0.3 (V+) + 0.3 V
Input current Into all pins(3) 5 mA
Operating temperature –40 125 °C
Junction temperature 150 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) VIN+ and VIN– are the voltages at the IN+ and IN– pins, respectively.
(3) Input voltage at any pin c an exceed the voltage shown if the current at that pin is limited to 5 mA.
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
20 1.0
15 0.8
0.6
10
Offset Voltage (mV)
0.4
CMRR (mV/V)
5 0.2
0 0
-5 -0.2
-0.4
-10
-0.6
-15
-0.8
-20 -1.0
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125
Temperature (°C) Temperature (°C)
Figure 6-1. Offset Voltage vs Temperature Figure 6-2. Common-Mode Rejection Ratio vs Temperature
70 160
60 140
G = 200
50 120
40 100
|PSR| (dB)
Gain (dB)
30 80
G = 50 G = 100
20 60
(V+) - 1.5
120
(V+) - 2.0 VS = 2.7V
(V+) - 2.5
|CMRR| (dB)
V+ 50
(V+) - 0.25
+25°C
(V+) - 0.50 40
-20°C
(V+) - 0.75 IB+, IB-, VREF = 0V
(V+) - 1.25 30
(V+) - 1.50
20
GND + 1.50 IB+, IB-, VREF = 2.5V
GND + 1.25 10
+85°C
GND + 1.00
+25°C
GND + 0.75
GND + 0.50 0
-20°C
GND + 0.25
GND -10
0 2 4 5 8 10 12 14 16 18 0 5 10 15 20 25 30
Output Current (mA) Common-Mode Voltage (V)
25
IB+, IB-, VREF = 0V 29
Input Bias Current (mA)
10
27
5
IB+, VREF = 2.5V 26
0
-5 25
0 5 10 15 20 25 30 -50 -25 0 25 50 75 100 125
Common-Mode Voltage (V) Temperature (°C)
Figure 6-9. Input Bias Current vs Common-Mode Voltage With Figure 6-10. Input Bias Current vs Temperature
Supply Voltage = 0 V (Shutdown)
70 100
Input-Referred Voltage Noise (nV/ÖHz)
G = 50
68
Quiescent Current (mA)
66 G = 100 G = 200
10
64
VS = ±2.5V
62
VREF = 0V
VIN-, VIN+ = 0V
60 1
-50 -25 0 25 50 75 100 125 10 100 1k 10k 100k
Temperature (°C) Frequency (Hz)
Figure 6-11. Quiescent Current vs Temperature Figure 6-12. Input-Referred Voltage Noise vs Frequency
Output Voltage
2VPP Output Signal
(0.5V/diV)
Voltage Noise (200nV/div)
Referred-to-Input
Input Voltage
VS = ±2.5V
(5mV/diV)
VCM = 0V
VDIF = 0V
VREF = 0V
Figure 6-13. 0.1-Hz to 10-Hz Voltage Noise (Referred-to-Input) Figure 6-14. Step Response (10-mVPP Input Step)
2V/div
0V
Output
Output Voltage
0V
0V
VS = 5V, VCM = 12V, VREF = 2.5V
1V/div
Output
Output Voltage
0V 0V
VS = 5V, VCM = 12V, VREF = 2.5V VS = 5V, 1kHz Step with VDIFF = 0V, VREF = 2.5V
Supply Voltage
1V/div
Output Voltage
7 Detailed Description
7.1 Overview
The INA199 is a 26-V common mode, zero-drift topology, current-sensing amplifier that can be used in both
low-side and high-side configurations. The device is a specially-designed, current-sensing amplifier that is able
to accurately measure voltages developed across a current-sensing resistor on common-mode voltages that far
exceed the supply voltage powering the device. Current can be measured on input voltage rails as high as 26 V
and the device can be powered from supply voltages as low as 2.7 V.
The zero-drift topology enables high-precision measurements with maximum input offset voltages as low as
150 µV with a maximum temperature contribution of 0.5 µV/°C over the full temperature range of –40°C to
+125°C.
7.2 Functional Block Diagram
V+
IN- -
OUT
IN+ +
REF
GND
5-V Supply
CBYPASS
0.1 µF
V+
IN-
-
OUT
ADC Microcontroller
+
IN+ REF
GND
Power-supply bypass capacitors are required for stability. Applications with noisy or high-impedance power
supplies may require additional decoupling capacitors to reject power-supply noise. Connect bypass capacitors
close to the device pins.
On the RSW package, two pins are provided for each input. These pins must be tied together (that is, tie IN+ to
IN+ and tie IN– to IN–).
7.3.2 Selecting RS
The zero-drift offset performance of the INA199 offers several benefits. Most often, the primary advantage of
the low offset characteristic enables lower full-scale drops across the shunt. For example, non-zero-drift current
shunt monitors typically require a full-scale range of 100 mV.
The INA199 series gives equivalent accuracy at a full-scale range on the order of 10 mV. This accuracy reduces
shunt dissipation by an order of magnitude with many additional benefits.
Alternatively, there are applications that must measure current over a wide dynamic range that can take
advantage of the low offset on the low end of the measurement. Most often, these applications can use the
lower gain of 50 or 100 to accommodate larger shunt drops on the upper end of the scale. For instance, an
INA199A1 operating on a 3.3-V supply can easily handle a full-scale shunt drop of 60 mV, with only 150 μV of
offset.
CBYPASS
V+
0.1µF
RINT
IN-
RS < 10 Ÿ
- OUT Output
CF Bias
RINT
+
IN+ REF
RS < 10 Ÿ
GND
The addition of external series resistance, however, creates an additional error in the measurement so the value
of these series resistors must be kept to 10 Ω (or less if possible) to reduce any affect to accuracy. The internal
bias network shown in Figure 7-2 present at the input pins creates a mismatch in input bias currents when a
differential voltage is applied between the input pins. If additional external series filter resistors are added to
the circuit, the mismatch in bias currents results in a mismatch of voltage drops across the filter resistors. This
mismatch creates a differential error voltage that subtracts from the voltage developed at the shunt resistor. This
error results in a voltage at the device input pins that is different than the voltage developed across the shunt
resistor. Without the additional series resistance, the mismatch in input bias currents has little effect on device
operation. The amount of error these external filter resistor add to the measurement can be calculated using
Equation 2 where the gain error factor is calculated using Equation 1.
The amount of variance in the differential voltage present at the device input relative to the voltage developed
at the shunt resistor is based both on the external series resistance value as well as the internal input resistors,
R3 and R4 (or RINT as shown in Figure 7-2). The reduction of the shunt voltage reaching the device input pins
appears as a gain error when comparing the output voltage relative to the voltage across the shunt resistor.
A factor can be calculated to determine the amount of gain error that is introduced by the addition of external
series resistance. The equation used to calculate the expected deviation from the shunt voltage to what is seen
at the device input pins is given in Equation 1:
(1250 ´ RINT)
Gain Error Factor =
(1250 ´ RS) + (1250 ´ RINT) + (RS ´ RINT) (1)
where:
• RINT is the internal input resistor (R3 and R4).
• RS is the external series resistance.
With the adjustment factor equation including the device internal input resistance, this factor varies with each
gain version, as listed in Table 7-1. Each individual device gain error factor is listed in Table 7-2.
Table 7-1. Input Resistance
PRODUCT GAIN RINT (kΩ)
INA199x1 50 20
INA199x2 100 10
INA199x3 200 5
10,000
INA199x2
(9 ´ RS) + 10,000
1000
INA199x3 RS + 1000
The gain error that can be expected from the addition of the external series resistors can then be calculated
based on Equation 2:
For example, using an INA199x2 and the corresponding gain error equation from Table 7-2, a series resistance
of 10-Ω results in a gain error factor of 0.991. The corresponding gain error is then calculated using Equation 2,
resulting in a gain error of approximately 0.89% solely because of the external 10-Ω series resistors. Using an
INA199x1 with the same 10-Ω series resistor results in a gain error factor of 0.991 and a gain error of 0.84%
again solely because of these external resistors.
7.4.2 Shutting Down the INA199 Series
Although the INA199 series does not have a shutdown pin, the low power consumption of the device allows the
output of a logic gate or transistor switch to power the INA199. This gate or switch turns on and turns off the
INA199 power-supply quiescent current.
However, in current shunt monitoring applications, there is also a concern for how much current is drained
from the shunt circuit in shutdown conditions. Evaluating this current drain involves considering the simplified
schematic of the INA199 in shutdown mode shown in Figure 7-3.
RSHUNT
Supply Load
Reference
Voltage
GND 1 MW R3 IN-
1-MΩ paths from shunt inputs to reference and the INA199 outputs.
Figure 7-3. Basic Circuit for Shutting Down the INA199 With a Grounded Reference
There is typically slightly more than 1-MΩ impedance (from the combination of 1-MΩ feedback and 5-kΩ input
resistors) from each input of the INA199 to the OUT pin and to the REF pin. The amount of current flowing
through these pins depends on the respective ultimate connection. For example, if the REF pin is grounded,
the calculation of the effect of the 1-MΩ impedance from the shunt to ground is straightforward. However, if the
reference or operational amplifier is powered when the INA199 is shut down, the calculation is direct; instead
of assuming 1-MΩ to ground, however, assume 1-MΩ to the reference voltage. If the reference or operational
amplifier is also shut down, some knowledge of the reference or operational amplifier output impedance under
shutdown conditions is required. For instance, if the reference source functions as an open circuit when not
powered, little or no current flows through the 1-MΩ path.
Regarding the 1-MΩ path to the output pin, the output stage of a disabled INA199 does constitute a good path to
ground. Consequently, this current is directly proportional to a shunt common-mode voltage impressed across a
1-MΩ resistor.
Note
When the device is powered up, there is an additional, nearly constant, and well-matched 25 μA that
flows in each of the inputs as long as the shunt common-mode voltage is 3 V or higher. Below 2-V
common-mode, the only current effects are the result of the 1-MΩ resistors.
ADC
REF OUT Output
GND R1 R3 IN-
2.7 V to 26 V IN+
V+
R2 R4
CBYPASS
0.01 mF
to
0.1 mF
Figure 7-4. Sensing the INA199 to Cancel Effects of Impedance on the REF Input
are satisfied with a 10-Ω resistor along with conventional Zener diodes of the lowest power rating that can be
found. This combination uses the least amount of board space. These diodes can be found in packages as
small as SOT-523 or SOD-523. See TIDA-00302 Transient Robustness for Current Shunt Monitor Design Guide,
TIDU473 for more information on transient robustness and current-shunt monitor input protection.
RSHUNT
Supply Load
RPROTECT RPROTECT
10 W 10 W
Reference
Voltage
Output
REF OUT
GND 1 MW R3 IN-
Shutdown V+ IN+
Control 1 MW R4
CBYPASS
In the event that low-power zeners do not have sufficient transient absorption capability and a higher power
transzorb must be used, the most package-efficient solution then involves using a single transzorb and back-to-
back diodes between the device inputs. The most space-efficient solutions are dual series-connected diodes in a
single SOT-523 or SOD-523 package. This method is shown in Figure 7-6. In either of these examples, the total
board area required by the INA199 with all protective components is less than that of an SO-8 package, and only
slightly greater than that of an MSOP-8 package.
RSHUNT
Supply Load
RPROTECT RPROTECT
10 W 10 W
Reference
Voltage
Output
REF OUT
GND 1 MW R3 IN-
Shutdown V+ IN+
Control 1 MW R4
CBYPASS
Figure 7-6. INA199 Transient Protection Using a Single Transzorb and Input Clamps
1 MW R3 IN-
GND
-
MMZ1608B601C
+
V+ IN+
2.7 V to 26 V
1 MW R4
0.01mF 0.01mF
to 0.1mF to 0.1mF
To minimize the cost of adding these external components to protect the device in applications where large
transient signals may be present, version B and C devices are now available with new ESD structures that
are not susceptible to this latching condition. Version B and C devices are incapable of sustaining these
damage-causing latched conditions so these devices do not have the same sensitivity to the transients that the
version A devices have, thus making the version B and C devices a better fit for these applications.
CBYPASS
V+
0.1 µF
IN-
-
OUT Output
IN+ REF
GND
input signal increases negatively, the output voltage moves downward from the saturated supply voltage. The
voltage applied to the REF pin must not exceed the device supply voltage.
8.2.1.3 Application Curve
An example output response of a unidirectional configuration is shown in Figure 8-2. With the REF pin
connected directly to ground, the output voltage is biased to this zero output level. The output rises above
the reference voltage for positive differential input signals but cannot fall below the reference voltage for negative
differential input signals because of the grounded reference voltage.
Output Voltage
(1 V/div)
0V
Output
VREF
Time (500 µs /div)
C001
CBYPASS
V+
0.1 µF
IN-
Reference
Voltage
-
OUT Output
IN+ REF
+
-
-
GND
state. The output then responds by increasing above VREF for positive differential signals (relative to the IN– pin)
and responds by decreasing below VREF for negative differential signals. This reference voltage applied to the
REF pin can be set anywhere between 0 V to V+. For bidirectional applications, VREF is typically set at mid-scale
for equal signal range in both current directions. In some cases, however, VREF is set at a voltage other than
mid-scale when the bidirectional current and corresponding output signal do not need to be symmetrical.
8.2.2.3 Application Curve
Output Voltage
(1 V/div)
VOUT
0V VREF
Time (500 µs/div)
C002
Output Signal
Trace
VIA to Power or
Ground Plane
IN+
OUT
GND
REF
V+
Supply
Voltage
Supply Bypass
Capacitor
11.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
12 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
• Added silicon version B data to Input, Common-Mode Input Range parameter of Electrical
Characteristics table........................................................................................................................................... 6
• Added QFN package information to Temperature Range section of Electrical Characteristics table.................6
• Updated Figure 6-3 ............................................................................................................................................7
• Updated Figure 6-9 ............................................................................................................................................7
• Updated Figure 6-12 ..........................................................................................................................................7
• Changed last paragraph of the Selecting RS section to cover both INA199Ax and INA199Bx versions..........12
• Changed Input Filtering section........................................................................................................................13
• Added Improving Transient Robustness section.............................................................................................. 17
www.ti.com 20-Aug-2024
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
INA199A1DCKR ACTIVE SC70 DCK 6 3000 RoHS & Green NIPDAU | SN Level-2-260C-1 YEAR -40 to 125 OBG Samples
INA199A1DCKT ACTIVE SC70 DCK 6 250 RoHS & Green NIPDAU | SN Level-2-260C-1 YEAR -40 to 125 OBG Samples
INA199A1RSWR ACTIVE UQFN RSW 10 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 NSJ Samples
INA199A1RSWT ACTIVE UQFN RSW 10 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 NSJ Samples
INA199A2DCKR ACTIVE SC70 DCK 6 3000 RoHS & Green NIPDAU | SN Level-2-260C-1 YEAR -40 to 125 OBH Samples
INA199A2DCKT ACTIVE SC70 DCK 6 250 RoHS & Green NIPDAU | SN Level-2-260C-1 YEAR -40 to 125 OBH Samples
INA199A2RSWR ACTIVE UQFN RSW 10 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 NTJ Samples
INA199A2RSWT OBSOLETE UQFN RSW 10 TBD Call TI Call TI -40 to 125 NTJ
INA199A3DCKR ACTIVE SC70 DCK 6 3000 RoHS & Green NIPDAU | SN Level-2-260C-1 YEAR -40 to 125 OBI Samples
INA199A3DCKT ACTIVE SC70 DCK 6 250 RoHS & Green NIPDAU | SN Level-2-260C-1 YEAR -40 to 125 OBI Samples
INA199A3RSWR ACTIVE UQFN RSW 10 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 NUJ Samples
INA199B1DCKR ACTIVE SC70 DCK 6 3000 RoHS & Green NIPDAU | SN Level-2-260C-1 YEAR -40 to 125 SEB Samples
INA199B1DCKT ACTIVE SC70 DCK 6 250 RoHS & Green NIPDAU | SN Level-2-260C-1 YEAR -40 to 125 SEB Samples
INA199B1RSWR ACTIVE UQFN RSW 10 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 SHV Samples
INA199B1RSWT OBSOLETE UQFN RSW 10 TBD Call TI Call TI -40 to 125 SHV
INA199B2DCKR ACTIVE SC70 DCK 6 3000 RoHS & Green NIPDAU | SN Level-2-260C-1 YEAR -40 to 125 SEG Samples
INA199B2DCKT ACTIVE SC70 DCK 6 250 RoHS & Green NIPDAU | SN Level-2-260C-1 YEAR -40 to 125 SEG Samples
INA199B2RSWR ACTIVE UQFN RSW 10 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 SHW Samples
INA199B3DCKR ACTIVE SC70 DCK 6 3000 RoHS & Green NIPDAU | SN Level-2-260C-1 YEAR -40 to 125 SHE Samples
INA199B3DCKT ACTIVE SC70 DCK 6 250 RoHS & Green NIPDAU | SN Level-2-260C-1 YEAR -40 to 125 SHE Samples
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 20-Aug-2024
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
INA199B3RSWR ACTIVE UQFN RSW 10 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 SHX Samples
INA199C1DCKR ACTIVE SC70 DCK 6 3000 RoHS & Green NIPDAU | SN Level-2-260C-1 YEAR -40 to 125 16L Samples
INA199C1DCKT OBSOLETE SC70 DCK 6 TBD Call TI Call TI -40 to 125 16L
INA199C1RSWR ACTIVE UQFN RSW 10 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 (160, 16O) Samples
INA199C1RSWT OBSOLETE UQFN RSW 10 TBD Call TI Call TI -40 to 125 (160, 16O)
INA199C2DCKR ACTIVE SC70 DCK 6 3000 RoHS & Green NIPDAU | SN Level-2-260C-1 YEAR -40 to 125 16M Samples
INA199C2DCKT OBSOLETE SC70 DCK 6 TBD Call TI Call TI -40 to 125 16M
INA199C2RSWR ACTIVE UQFN RSW 10 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 16P Samples
INA199C2RSWT OBSOLETE UQFN RSW 10 TBD Call TI Call TI -40 to 125 16P
INA199C3DCKR ACTIVE SC70 DCK 6 3000 RoHS & Green NIPDAU | SN Level-2-260C-1 YEAR -40 to 125 16N Samples
INA199C3DCKT ACTIVE SC70 DCK 6 250 RoHS & Green NIPDAU | SN Level-2-260C-1 YEAR -40 to 125 16N Samples
INA199C3RSWR ACTIVE UQFN RSW 10 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 16Q Samples
INA199C3RSWT OBSOLETE UQFN RSW 10 TBD Call TI Call TI -40 to 125 16Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com 20-Aug-2024
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
• Automotive : INA199-Q1
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com 25-Sep-2024
B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers
Sprocket Holes
Q1 Q2 Q1 Q2
Pocket Quadrants
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 25-Sep-2024
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 25-Sep-2024
Width (mm)
H
W
Pack Materials-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com 25-Sep-2024
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
INA199A3DCKT SC70 DCK 6 250 180.0 180.0 18.0
INA199A3DCKT SC70 DCK 6 250 190.0 190.0 30.0
INA199A3RSWR UQFN RSW 10 3000 210.0 185.0 35.0
INA199B1DCKR SC70 DCK 6 3000 190.0 190.0 30.0
INA199B1DCKT SC70 DCK 6 250 180.0 180.0 18.0
INA199B1DCKT SC70 DCK 6 250 190.0 190.0 30.0
INA199B1RSWR UQFN RSW 10 3000 200.0 183.0 25.0
INA199B2DCKR SC70 DCK 6 3000 180.0 180.0 18.0
INA199B2DCKR SC70 DCK 6 3000 190.0 190.0 30.0
INA199B2DCKT SC70 DCK 6 250 180.0 180.0 18.0
INA199B2DCKT SC70 DCK 6 250 190.0 190.0 30.0
INA199B2RSWR UQFN RSW 10 3000 210.0 185.0 35.0
INA199B3DCKR SC70 DCK 6 3000 180.0 180.0 18.0
INA199B3DCKR SC70 DCK 6 3000 190.0 190.0 30.0
INA199B3DCKT SC70 DCK 6 250 180.0 180.0 18.0
INA199B3DCKT SC70 DCK 6 250 190.0 190.0 30.0
INA199B3RSWR UQFN RSW 10 3000 200.0 183.0 25.0
INA199C1DCKR SC70 DCK 6 3000 340.0 340.0 38.0
INA199C1DCKR SC70 DCK 6 3000 190.0 190.0 30.0
INA199C1RSWR UQFN RSW 10 3000 210.0 185.0 35.0
INA199C2DCKR SC70 DCK 6 3000 180.0 180.0 18.0
INA199C2DCKR SC70 DCK 6 3000 190.0 190.0 30.0
INA199C2RSWR UQFN RSW 10 3000 210.0 185.0 35.0
INA199C3DCKR SC70 DCK 6 3000 190.0 190.0 30.0
INA199C3DCKR SC70 DCK 6 3000 180.0 180.0 18.0
INA199C3DCKT SC70 DCK 6 250 190.0 190.0 30.0
INA199C3DCKT SC70 DCK 6 250 180.0 180.0 18.0
Pack Materials-Page 4
PACKAGE OUTLINE
DCK0006A SCALE 5.600
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR
C
2.4
1.8 0.1 C
1.4
B
1.1 A 1.1
PIN 1 0.8
INDEX AREA
1
6
4X 0.65
2.15
1.3
2 1.85
0.30 3
6X
0.15
0.1 C A B 4X 0 -12 0.1
TYP
0.0
NOTE 5
4X 4 -14
0.15
0.22
GAGE PLANE TYP
0.08
8
TYP 0.46
0 TYP SEATING PLANE
0.26
4214835/C 08/2024
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.15 per side.
4. Falls within JEDEC MO-203 variation AB.
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EXAMPLE BOARD LAYOUT
DCK0006A SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR
PKG
6X (0.9)
1
6X (0.4) 6
SYMM
2
4X (0.65)
4
3
SOLDER MASK
SOLDER MASK METAL METAL UNDER OPENING
OPENING SOLDER MASK
4214835/C 08/2024
NOTES: (continued)
www.ti.com
EXAMPLE STENCIL DESIGN
DCK0006A SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR
PKG
6X (0.9)
1
6X (0.4) 6
SYMM
2
4X(0.65)
4
3
(R0.05) TYP
(2.2)
4214835/C 08/2024
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
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PACKAGE OUTLINE
RSW0010A SCALE 7.000
UQFN - 0.55 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
1.45
B A
1.35
1.85
1.75
0.55
0.45 C
NOTE 3
SEATING PLANE
0.05
0.00 0.05 C
2X 0.8
SYMM (0.13) TYP
3 5
0.45
9X
0.35
2
6
SYMM
6X 0.4
7
1
0.25
10X
0.15
0.07 C A B
10 8
0.05
0.55 PIN 1 ID
0.45
4224897/A 03/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This package complies to JEDEC MO-288 variation UDEE, except minimum package height.
www.ti.com
EXAMPLE BOARD LAYOUT
RSW0010A UQFN - 0.55 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
SYMM
10 8
SEE SOLDER MASK
DETAIL
10X (0.2)
1 (0.7)
7
SYMM
6X (0.4)
6 (1.6)
2
(R0.05) TYP
9X (0.6)
3 5
(1.2)
0.05 MIN
0.05 MAX ALL AROUND
ALL AROUND
METAL UNDER
METAL EDGE SOLDER MASK
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
RSW0010A UQFN - 0.55 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
SYMM
10 8
10X (0.2)
1 (0.7)
7
SYMM
6X (0.4)
6 (1.6)
2
(R0.05) TYP
9X (0.6)
3 5
(1.2)
4224897/A 03/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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