Linear Integrated Circuits

Unit 1
Differential Amplifier
Differential Amplifier
• The dc analysis begins with the assumption that Q1 and Q2 are ideally
matched.
• The mismatching effects will be considered later.
• Also, consider β >> 1, so that.

I E1 ≅ I C1 and I E 2 ≈ I C 2
VI 1 = VBE1 − VBE 2 + VI 2

=RE R=
E1 || RE 2 , since RE1 RE 2
R=
C1 R=
C2 RC
VCC = VEE
 VEE − VBE
IE =
2 RE

=
VC VCC − I C RC
VCE= VC − VE
=VCC − I C RC − VE
= VCC − I C RC + VBE ∴ VE =
−VBE
AC Analysis of Dual Input Balanced Output Configuration

Differential-mode gain (Adm)

 vS
I b ( RS + hie ) =
2
vS
Ib =
2 ( RS + hie )
vo = −h fe I b RC
vS
vo = −h fe RC
2 ( RS + hie )
−h fe RC
vS  vS 
vo
=
vid = −− = vS
vS 2 ( RS + hie ) 2  2 
vo vo −h fe RC
Adm= = =
vid vS 2 ( RS + hie )
Common-mode gain (Acm)

v1 + v2 vS + vS
vic = = vS
2 2

vo
Acm =
vs
 + 2 I b × + 2 ( I b + h fe I b ) RE
RS hie
vs = 2 I b ×
2 2
vs
Ib =
RS + hie + 2 (1 + h fe ) RE
vo = I L RC
= −h fe I b RC
 v0 −h fe RC
= =
Acm
vs RS + hie + 2 (1 + h fe ) RE

Common-Mode Rejection Ratio (CMRR)

Adm
CMRR = 20 log10 dB
Acm
RS + hie + 2 RE (1 + h fe )
CMRR = 20 log10 dB
RS + hie
RS + hie + 2 RE (1 + h fe )
CMRR = 20 log10 dB
2( RS + hie )
Current Source
I R = I C1 + I B1 + I B2
= I C1 + 2 I B1
2I C1
I= I C1 +
R
βF
IR
I= I=
1 + 2 / βF
C1 C2

VCC − VBE1 1
×
R1 1 + 2 / βF
Widlar Current Source
• The op-amps require very small input current.
• Therefore, the emitter-coupled pair of transistors at the input are
needed to be biased at very low current, with the collector
currents of the order of 5 μA.
• Realising such circuits using simple current sources are
difficult.
• Hence, a very large value of resistance must be connected with
the power supply VCC which will occupy a very large die area.
• The Widlar current source is designed for current values of very
low magnitude.
 Widlar Current Source (Cont.)
• This circuit employs moderate value of
resistors.
• The transistors Q1 and Q2 operate at
different values of VBE due to the presence
of resistor R2 in the emitter circuit of Q2.
• Due to the resistor R2, it can be observed
that,
VBE2 < VBE1 and hence, IC2 < IC1
• The reference current Iref is determined by
Q1, R1 and VCC.
• The resistance R2 and Iref decide the value of
IC2.
 VBE1 − VBE 2 − I C 2 R2 = 0
I C1 IC 2
VT ln − VT ln − I C 2 R2 =
0
I S1 IS 2
 I C1 
VT ln   = I C 2 R2
 IC 2 
VT  I C1 
R2 = ln  
IC 2  IC 2 
• For practical design purposes, the values of IC1
and IC2 are usually known, and the value of R2 is
calculated to achieve the desired value of IC2.
Multiple Current Sources

 1+ N 
I ref= I C +   IC
 β 
  1+ N  
=I ref I C 1 +  
  β 
β
I= I ref ×
C
β + N +1
Wilson Current Source
Since VBE1 = VBE2, IC1 = IC2 and IB1 = IB2 = IB.
Assuming that all base currents are equal to IB,
Iref = IC1 + IB
At node b,
IE3 = IC2 + 2IB
IE3 = IC3 + IB
We know that for the transistor pair Q1 and Q2
IC1 = IC2
IC3 = IE3 – IB = IC2 + 2IB – IB = IC2 + IB
IC3 = IC1 + IB
Iref = IC3
Hence, the effect of finite base currents stands
cancelled.
Q. Assuming identical transistors with VBE = 0.7 V,
determine the voltage Vo for the circuit shown
Q. Determine the output current I for the current source shown.
Assume hFE of the transistor is very high and VBE = 0.6 V.
Differential amplifiers with active loads

• Differential amplifiers are designed with active loads to increase the

differential mode voltage gain.
• The open circuit voltage gain of an op-amp is needed to be as large as
possible.
• This is achieved by cascading the gain stages which increases the phase
shift and the amplifier also becomes vulnerable to oscillations.
• The gain can be increased by using large values of collector resistance.
• For such a circuit, the voltage gain is given by

I C RC
Adm =
− g m RC =
−
VT
• To increase the gain
the ICRC product
must be made very
large.
• However, there are
limitations in IC
fabrication
I C=
4 I=
C3 I=
C1 ( g mVid ) / 2
I C 2 = − ( g mVid ) / 2
=
I L IC 2 − IC 4
− ( g mVid ) / 2 − ( g mVid ) / 2
IL =
I L = − g mVid
VO =− I L RL =− ( − g mVid ) RL
VO = g m RLVid
VO
=
AV = g m RL
Vid
Level Shifting Stage

VE= Vi − VBE

Vo =
(Vi − VBE ) R2
( R1 + R2 )
• The ac gain of the circuit starts reducing as R2 is decreased for improving the
net dc level shift.
• Moreover, its output impedance is also comparatively high.
• This limitation makes the level shift stage using diode an attractive alternative
circuit for shifting the dc level.
Level Shifting Stage (Cont.)

Vi − VO = VBE + VB

VO = Vi − (VBE + VB )
 Level Shifting Stage (Cont.)

 R2 + R1   R1 
=
VEF VBE  =  VBE 1 + 
 R2   R2 

Vi − (VBE + VEF )
Vo =
  R1  
Vo =
Vi − VBE + VBE 1 +  
  R2  
Q. Find the Q-point VC and IB for the differential amplifier shown. Assume β = 100.
Output Stage
• The output stage of an amplifier must satisfy a number of special
requirements.
• One of the most important requirements is to deliver a specified amount of
signal power to a load with acceptably low levels of signal distortion.
• Another common objective of output stage design is to minimize the
output impedance so that the voltage gain is relatively unaffected by the
value of load impedance.
• A well-designed output stage should achieve these performance
specifications while consuming low quiescent power
• And, in addition, should not be a major limitation on the frequency
response of the amplifier
The Emitter Follower as an Output Stage

=
Vi Vbe1 + Vo

kT  I C1 
Vbe1 = ln  
q  IS 

VO
I C=
1 IQ +
RL
 Vo 
 IQ + 
kT RL
Vi ln   + Vo
q  I S 
 
 
The Source Follower as an Output Stage
• The major disadvantage of Class A output stages is that large power
dissipation occurs even for no ac input.
• In many applications of power amplifiers, the circuit may spend
long periods of time in a standby condition with no input signal.
• Power dissipated by these stand by periods is wasted, which is
important for two reasons. First, in battery-operated equipment
supply power must be conserved to extend the battery life. Second,
any power wasted in the circuit is dissipated in the active devices,
increasing their operating temperatures and thus the chance of
failure.
• The power dissipated in the devices affects the physical size of
device required, and larger devices are more expensive in terms of
silicon area.
• A Class B output stage alleviates this problem by having
essentially zero power dissipation with zero input signal.

• Two active devices are used to deliver the power instead

of one, and each device conducts for alternate half cycles.
This behaviour is the origin of the name push-pull.

• Another advantage of Class B output stages is that the

efficiency is much higher than for a Class A output stage
(ideally 78.6 percent at full output power)
DC Characteristics of the Op-Amp
• An ideal operational amplifier draws no current from the signal source and
its response is independent of the temperature variations.
• However, a practical op-amp gets affected by the environmental and process
parameter variations.
• The current is indeed, taken from the source into the input of op-amp and the
two inputs respond differently to the input voltage and current. This happens
due to the inherent mismatch among the transistors.
• The non-ideal dc characteristics of the op-amp are
(i) Input bias current
(ii) Input offset current
(iii) Input offset voltage
(iv) Thermal drift
 (i) Input Bias Current
• The input bias current is the average of the currents that flow into the
inverting and non-inverting input terminals of an op-amp.
I B1 + I B 2
IB =
2
• where IB1 is the dc bias current entering the non-inverting input and IB2 is the
dc bias current entering the inverting input
VO = I B 2 R f
• This offset effect can be compensated by the use of a compensation resistor
Rcomp connected as shown

−Vcomp + 0 + V2 − VO =0

VO= V2 − Vcomp
Vcomp
I B1 =
Rcomp

Vcomp V2
I1 = , I2
R1 Rf
 Vcomp Vcomp
I B 2 = I 2 + I1 = +
Rf R1
 R1 + R f 
= Vcomp  
 RR
 1 f 
 R1 + R f  Vcomp
Vcomp   =
 RR  R
 1 f  comp

R1 R f
Rcomp = R1 ‖R f
R1 + R f
(ii) Input Offset Current
• The input transistors cannot be made identical, and there always
exists a small difference between the bias currents IB1 and IB2.
The difference in magnitude between IB1 and IB2 is called input
offset current IOS.

I=
OS I B1 − I B 2
• The manufacturers specify IOS for a circuit when the output Vo is
zero and temperature is 25oC.
• IOS is typically less than 25% of IB for the average input bias
current.
• It is approximately 200nA for BJT op-amp and 10pA for FET op-
amp.
• To find the effect of IOS on Vo, referring to Fig. below, and assuming Vi = 0, we
get
Vcomp∣
Vcomp =
I B1 × Rcomp , I1 =
R1

 Rcomp 
I 2 = I B 2 − I1 = I B 2 −  I B1 
 R1 
Vo = I 2 R f − Vcomp = I 2 R f − I B1 Rcomp

 Rcomp 
Vo =
 I B 2 − I B1  R f − I B1 Rcomp
 R1 
  Rcomp 
Vo =
 I B 2 − I B1  R f − I B1 Rcomp
 R1 

R1 R f
=
Rcomp = R1 ‖R f
R1 + R f

=Vo R f ( I B 2 − I B1 )
Vo = R f I OS
 (iii) Input Offset Voltage
• Input offset voltage VOS is the differential input voltage that exists
between the inverting and non-inverting input terminals of an op-amp.
• In other words, this can be defined as the voltage that is to be applied
between the two input terminals for making the output voltage zero.

 Rf 
VO= 1 +  VOS
 R1 
 Total Output Offset Voltage
• The total output offset voltage VOT can be due to either the input bias
current or the input offset voltage, and also, it can be either positive or
negative with respect to ground.
• Then, considering that both these output voltages are of same polarity, the
maximum output offset voltage will be
 Rf 
VOT =
1 +  VOS + R f I B
 R1 
• However, when Rcomp is connected in the circuit, then the total output offset
voltage will be
 Rf 
VOT =
1 +  VOS + R f I OS
 R1 
 Offset Voltage Compensation
• The two methods of achieving offset
voltage compensation are
• (i) op-amp with offset null terminals
and
• (ii) providing an externally connected
offset compensation network.
Nulling Procedure
(i) Connect the circuit by including the
compensating resistor Rcomp and the
voltage offset null circuit
(ii) Make all generator (source) signals
zero
(iii) Connect the load to the output and
turn the circuit ON
(iv) Connect a dc voltmeter or an
oscilloscope across the load to measure
Vo
(v) Vary the offset voltage adjustment
trimming potentiometer until Vo
becomes zero
  R4 
VOS = ±V  
 R4 + R3 
 (iv) Thermal Drift
• The parameters VOS, IB and IOS are assumed to be constant for a given op-
amp.
• However, in practice, the following operating conditions pose a great
challenge to these parameters:
• (i) Change in temperature ΔT (ii) Change in supply voltage and (iii) Change
in time
• The change in temperature causes the most serious variation in the values of
VOS, IB and IOS.
• The term thermal drift is used to identify such changes and it is defined as
the average rate of change of input offset voltage, input offset current and
input bias current per unit change in temperature.
∆VOS ∆I OS ∆I B
, ,
∆T ∆T ∆T