High Performance M1004204/M1008204/M1016204

Serial MRAM Memory M3004204/M3008204/M3016204

Description Features
Mxxxx204 is a magneto-resistive random-access memory  Interface
(MRAM). It is offered in density ranging from 4Mbit to 16Mbit. • Serial Peripheral Interface QSPI (4-4-4)
MRAM technology is analogous to Flash technology with SRAM
• Single Data Rate Mode: 108MHz
compatible read/write timings (Persistent SRAM, P-SRAM). Data is
always non-volatile. • Double Data Rate Mode: 54MHz
 Technology
MRAM is a true random-access memory; allowing both reads and • 40nm pMTJ STT-MRAM
writes to occur randomly in memory. MRAM is ideal for applications Virtually unlimited Endurance and Data Retention (see
that must store and retrieve data without incurring large latency Endurance and Data Retention specification in Table 31)
penalties. It offers low latency, low power, virtually infinite  Density
endurance and retention, and scalable non-volatile memory
• 4Mb, 8Mb, 16Mb
technology.
 Operating Voltage Range
• VCC: 1.71V – 2.00V
Mxxxx204 is available in small footprint 8-pad DFN (WSON) and 8-
pin SOIC packages. These packages are compatible with similar • VCC: 2.70V – 3.60V
low-power volatile and non-volatile products.  Operating Temperature Range
• Industrial: -40°C to 85°C
Mxxxx204 is offered with industrial (-40°C to 85°C) and industrial • Industrial Plus: -40°C to 105°C
plus (-40°C to 105°C) operating temperature ranges.  Packages
• 8-pad DFN (WSON) (5.0mm x 6.0mm)
• 8-pin SOIC (5.2mm x 5.2mm)
Typical Applications
 Data Protection
• Ideal for applications that must store and retrieve data • Hardware Based: Write Protect Pin (WP#)
without incurring large latency penalties.
Software Based: Address Range Selectable through
• Factory Automation Configuration bits (Top/Bottom, Block Protect[2:0])
• Multifunction Printers  Identification
• 64-bit Unique ID
• Industrial Control And Monitoring
• 64-bit User Programmable Serial Number
• Medical Diagnostics  Augmented Storage Array
• Data Switches And Routers • 256-byte User Programmable with Write Protection
 Supports JEDEC Reset
 RoHS & REACH Compliant
Block Diagram
CS# Address Register VCC

Serial Status Register

I/Os Column
Command Register Decoder
SO / IO[1] IO[3]
Row Decoder

MRAM
MRAM
MRAM
Array
WP# / IO[2] Command Array
Array CLK
&
Control
High Voltage
Generator
VSS SI / IO[0]
Regulator Data Buffer

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Contents
1. General Description ......................................................................................................................................................................................3
2. Ordering Options ..........................................................................................................................................................................................4
2.1 Valid Combinations — Standard .........................................................................................................................................................4
3. Signal Description and Assignment ..............................................................................................................................................................7
4. Package Options ..........................................................................................................................................................................................9
4.1 8-Pad DFN (WSON) (Top View)..........................................................................................................................................................9
4.2 8-Pin SOIC (Top View) ........................................................................................................................................................................9
5. Package Drawings......................................................................................................................................................................................10
5.1 8-Pad DFN (WSON) ..........................................................................................................................................................................10
5.2 8-Pin SOIC ........................................................................................................................................................................................11
6. Architecture ................................................................................................................................................................................................12
7. Device Initialization .....................................................................................................................................................................................14
8. Memory Map...............................................................................................................................................................................................16
9. Augmented Storage Array Map ..................................................................................................................................................................16
10. Register Addresses ....................................................................................................................................................................................16
11. Register Map ..............................................................................................................................................................................................17
11.1 Status Register / Device Protection Register (Read/Write) ...............................................................................................................17
11.2 Augmented Storage Array Protection Register (Read/Write) ............................................................................................................19
11.3 Device Identification Register (Read Only) ........................................................................................................................................19
11.4 Serial Number Register (Read/Write) ................................................................................................................................................20
11.5 Unique Identification Register (Read Only) .......................................................................................................................................20
11.6 Configuration Register 1 (Read/Write)...............................................................................................................................................21
11.7 Configuration Register 2 (Read/Write)...............................................................................................................................................22
11.8 Configuration Register 3 (Read/Write)...............................................................................................................................................24
11.9 Configuration Register 4 (Read/Write)...............................................................................................................................................24
12. Instruction Set.............................................................................................................................................................................................25
13. Instruction Description and Structures ........................................................................................................................................................28
14. Electrical Specifications ..............................................................................................................................................................................39
14.1 CS# Operation & Timing....................................................................................................................................................................43
14.2 Data Output Operation & Timing .......................................................................................................................................................45
14.3 WP# Operation & Timing ...................................................................................................................................................................46
Enter Deep Power Down Command (EDP – B9h) ............................................................................................................................47
Exit Deep Power Down Command (EXDPD - ABh) ..........................................................................................................................48
Enter Hibernate Command (EHBN – BAh) ........................................................................................................................................49
15. Thermal Resistance....................................................................................................................................................................................50
16. Revision History..........................................................................................................................................................................................51

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1. General Description
Mxxxx204 is a magneto-resistive random-access memory (MRAM). It is offered in density ranging from 4Mbit to 16Mbit.
MRAM technology is analogous to Flash technology with SRAM compatible read/write timings (Persistent SRAM, P-SRAM).
Data is always non-volatile.

Figure 1: Technology Comparison

SRAM Flash EEPROM MRAM
Non-Volatility − √ √ √
Write Performance √ − − √
Read Performance √ − − √
Endurance √ − − √
Power − − − √

MRAM is a true random-access memory; allowing both reads and writes to occur randomly in memory. MRAM is ideal for
applications that must store and retrieve data without incurring large latency penalties. It offers low latency, low power,
virtually infinite endurance and retention, and scalable non-volatile memory technology.

Mxxxx204 has a Serial Peripheral Interface (SPI). SPI is a synchronous interface which uses separate lines for data and
clock to help keep the host and slave in perfect synchronization. The clock tells the receiver exactly when to sample the bits
on the data line. This can be either the rising (low to high) or falling (high to low) or both edges of the clock signal; please
consult the instruction sequences in this datasheet for more details. When the receiver detects that correct edge, it can latch
in the data.

Mxxxx204 is available in small footprint 8-pad DFN (WSON) and 8-pin SOIC packages. These packages are compatible
with similar low-power volatile and non-volatile products.

Mxxxx204 is offered with industrial (-40°C to 85°C) and industrial plus (-40°C to 105°C) operating temperature ranges.

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2. Ordering Options
The ordering part numbers are formed by a valid combination of the following options:

M 1 004 2 04 0108 X 0I WA R

Packing Type
R: Tape & Reel
Y: Tray

Package Type
WA: 8-pad DFN (WSON)
SA: 8-pin SOIC

Temperature Range
0I: Industrial (-40°C to +85°C)
0P: Industrial Plus (-40°C to +105°C)

Reserved

Performance
0108: 108MHz
0054: 54MHz

Sub-Interface Type
04: x4

Interface Type
2: Serial Peripheral Interface (DDR)

Density
004: 4 Megabit
008: 8 Megabit
016: 16 Megabit

Operational Voltage
1: 1.8V (1.71V to 2.0V)
3: 3.0V (2.70V to 3.60V)

Brand – Product Family

M: Renesas - Persistant SRAM

2.1 Valid Combinations — Standard

Valid Combinations list includes device configurations currently available. Contact your local sales office to confirm
availability of specific valid combinations and to check on newly released combinations.

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Table 1: Valid Combinations List

Valid Combinations – 108MHz

Base Temperature Package Packing Part
Part Number Range Type Type Number
M10042040108X 0I, 0P WA, SA R, Y M10042040108X0IWAR
M10042040108X0IWAY
M10042040108X0ISAR
M10042040108X0ISAY
M10042040108X0PWAR
M10042040108X0PWAY
M10042040108X0PSAR
M10042040108X0PSAY
M30042040108X 0I, 0P WA, SA R, Y M30042040108X0IWAR
M30042040108X0IWAY
M30042040108X0ISAR
M30042040108X0ISAY
M30042040108X0PWAR
M30042040108X0PWAY
M30042040108X0PSAR
M30042040108X0PSAY
M10082040108X 0I, 0P WA, SA R, Y M10082040108X0IWAR
M10082040108X0IWAY
M10082040108X0ISAR
M10082040108X0ISAY
M10082040108X0PWAR
M10082040108X0PWAY
M10082040108X0PSAR
M10082040108X0PSAY
M30082040108X 0I, 0P WA, SA R, Y M30082040108X0IWAR
M30082040108X0IWAY
M30082040108X0ISAR
M30082040108X0ISAY
M30082040108X0PWAR
M30082040108X0PWAY
M30082040108X0PSAR
M30082040108X0PSAY
M10162040108X 0I, 0P WA, SA R, Y M10162040108X0IWAR
M10162040108X0IWAY
M10162040108X0ISAR
M10162040108X0ISAY
M10162040108X0PWAR
M10162040108X0PWAY
M10162040108X0PSAR
M10162040108X0PSAY
M30162040108X 0I, 0P WA, SA R, Y M30162040108X0IWAR
M30162040108X0IWAY
M30162040108X0ISAR
M30162040108X0ISAY
M30162040108X0PWAR
M30162040108X0PWAY
M30162040108X0PSAR
M30162040108X0PSAY

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Valid Combinations – 54MHz

Base Temperature Package Packing Part
Part Number Range Type Type Number
M10042040054X 0I, 0P WA, SA R, Y M10042040054X0IWAR
M10042040054X0IWAY
M10042040054X0ISAR
M10042040054X0ISAY
M10042040054X0PWAR
M10042040054X0PWAY
M10042040054X0PSAR
M10042040054X0PSAY
M30042040054X 0I, 0P WA, SA R, Y M30042040054X0IWAR
M30042040054X0IWAY
M30042040054X0ISAR
M30042040054X0ISAY
M30042040054X0PWAR
M30042040054X0PWAY
M30042040054X0PSAR
M30042040054X0PSAY
M10082040054X 0I, 0P WA, SA R, Y M10082040054X0IWAR
M10082040054X0IWAY
M10082040054X0ISAR
M10082040054X0ISAY
M10082040054X0PWAR
M10082040054X0PWAY
M10082040054X0PSAR
M10082040054X0PSAY
M30082040054X 0I, 0P WA, SA R, Y M30082040054X0IWAR
M30082040054X0IWAY
M30082040054X0ISAR
M30082040054X0ISAY
M30082040054X0PWAR
M30082040054X0PWAY
M30082040054X0PSAR
M30082040054X0PSAY
M10162040054X 0I, 0P WA, SA R, Y M10162040054X0IWAR
M10162040054X0IWAY
M10162040054X0ISAR
M10162040054X0ISAY
M10162040054X0PWAR
M10162040054X0PWAY
M10162040054X0PSAR
M10162040054X0PSAY
M30162040054X 0I, 0P WA, SA R, Y M30162040054X0IWAR
M30162040054X0IWAY
M30162040054X0ISAR
M30162040054X0ISAY
M30162040054X0PWAR
M30162040054X0PWAY
M30162040054X0PSAR
M30162040054X0PSAY

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3. Signal Description and Assignment

Figure 2: Device Pinout

CS#

WP# / IO[2]
4Mb – 16Mb
SI / IO[0] Quad SPI SO / IO[1]

CLK MRAM
IO[3]

Table 2: Signal Description

Signal Type Description
Chip Select: When CS# is driven High, the device will enter standby mode. All
other input pins are ignored and the output pin is tri-stated. Driving CS# Low
CS# Input
enables the device, placing it in the active mode. After power-up, a falling edge
on CS# is required prior to the start of any instructions.
Write Protect (SPI): Write protects the status register in conjunction with the
enable/disable bit of the status register. This is important since other write
protection features are controlled through the Status Register. When the
enable/disable bit of the status register is set to 1 and the WP# signal is driven
Input
Low, the status register becomes read-only and the WRITE STATUS
WP# / IO[2] /
REGISTER operation will not execute. This signal does not have internal pull-
Bidirectional
ups, it cannot be left floating and must be driven. WP# is valid only in Single SPI
mode. This pin can be tied to Vcc if not used.
Bidirectional Data 2 (DPI/QPI): The bidirectional I/O transfers data into and out
of the device in Dual and Quad SPI modes.
Clock: Provides the timing for the serial interface. Depending on the mode
selected, either single (rising or falling) edge or both edges of the clock are
utilized for information transfer.
In Single Data Rate mode (SDR) command, address and data inputs are
latched on the rising edge of the clock. Data is output on the falling edge of the
clock.
CLK Input
In Double Data Rate mode (DDR) command is latched on the rising edge of
the clock. Address and Data inputs are latched on both edges of the clock.
Similarly, Data is output on both edges of the clock.
The following two SPI clock modes are supported.
• SPI Mode 0 (CPOL = 0, CPHA = 0) – SDR and DDR
• SPI Mode 3 (CPOL = 1, CPHA = 1) – SDR only
Bidirectional Data 3 (DPI/QPI): The bidirectional I/O transfers data into and out
IO[3] Bidirectional of the device in Dual and Quad SPI modes. This pin can be tied to Vcc if not
used.
Serial Data Input (SPI): The unidirectional I/O transfers data into the device on
Input
the rising edge of the clock in Single SPI mode.
SI / IO[0] /
Bidirectional Data 0 (DPI/QPI): The bidirectional I/O transfers data into and out
Bidirectional
of the device in Dual and Quad SPI modes.

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Signal Type Description

Serial Data Output (SPI): The unidirectional I/O transfers data out of the device
Output
on the falling edge of the clock in Single SPI mode.
SO / IO[1] /
Bidirectional Data 1 (DPI/QPI): The bidirectional I/O that transfers data into
Bidirectional
and out of the device in Dual and Quad SPI modes.
VCC Supply VCC: Core and I/O power supply.
VSS Supply VSS: Core and I/O ground supply.

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4. Package Options

4.1 8-Pad DFN (WSON) (Top View)

Figure 3: 8-Pad DFN (WSON)

CS# 1 8 VCC

SO / IO[1] 2 7 IO[3]

WP# / IO[2] 3 6 CLK

VSS 4 5 SI / IO[0]

4.2 8-Pin SOIC (Top View)

Figure 4: 8-Pin SOIC

CS# 1 8 VCC

SO / IO[1] 2 7 IO[3]

WP# / IO[2] 3 6 CLK

VSS 4 5 SI / IO[0]

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5. Package Drawings

5.1 8-Pad DFN (WSON)

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5.2 8-Pin SOIC

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6. Architecture
Mxxxx204 is a high performance serial STT-MRAM device. It features a SPI-compatible bus interface running at 108MHz,
eXecute-In-Place (XIP) functionality, and hardware/software based data protection mechanisms.

When CS# is Low, the device is selected and in active power mode. When CS# is High, the device is deselected but can
remain in active power mode until ongoing internal operations are completed. Then the device goes into standby power
mode and device current consumption drops to ISB.

Mxxxx204 contains an 8-bit instruction register. All functionality is controlled through the values loaded into this instruction
register. In Single SPI mode, the device is accessed via the SI / IO[0] pin. In Dual and Quad SPI modes, IO[0:1] and IO[0:3]
are used to access the device respectively. Furthermore, Single Data Rate (SDR) and Double Data Rate (DDR) instructions
utilize CLK edges differently to transfer information; SDR uses a single CLK edge whereas DDR uses both edges of CLK.
Table 3 summarizes all the different interface modes supported and their respective I/O usage. Table 4 shows the clock
edge used for each instruction component.

Nomenclature adoption: A typical SPI instruction consists of command, address and data components. The bus width to
transmit these three components varies based on the SPI interface mode selected. To accurately represent the number of
I/Os used to transmit these three components, a nomenclature (command-address-data) is adopted and used throughout
this document. Integers placed in the (command-address-data) fields represent the number of I/Os used to transmit the
particular component. As an example, 1-1-1 means command, address and data are transmitted on a single I/O (SI / IO[0]
or SO / IO[1]). On the other hand, 1-4-4 represents command being sent on a single I/O (SI / IO[0]) and address/data being
sent on four I/Os (IO[3:0]).

Table 3: Interface Modes of Operations

Instruction Single Dual Dual DPI Quad Quad QPI
Component SPI Input I/O Input I/O
Output SPI Output SPI
SPI SPI
(1-1-1) (1-1-2) (1-2-2) (2-2-2) (1-1-4) (1-4-4) (4-4-4)
Command SI / IO[0] SI / IO[0] SI / IO[0] IO[1:0] SI / IO[0] SI / IO[0] IO[3:0]
Address SI / IO[0] SI / IO[0] IO[1:0] IO[1:0] SI / IO[0] IO[3:0] IO[3:0]
Data Input SI / IO[0] IO[1:0] IO[1:0] IO[1:0] IO[3:0] IO[3:0] IO[3:0]
Data Output SO / IO[1] IO[1:0] IO[1:0] IO[1:0] IO[3:0] IO[3:0] IO[3:0]

Table 4: Clock Edge Used for instructions in SDR and DDR modes
Instruction Type Command Address Data Input Data Output

(1-1-1) SDR F 1
R R R

(1-1-1) DDR F R 1
R R F R F

(1-1-2) SDR F 1
R R R

(1-2-2) SDR F 1
R R R

(2-2-2) SDR F 1
R R R

(2-2-2) DDR F R 1
R R F R F

(1-1-4) SDR F 1
R R R

(1-4-4) SDR F 1
R R R

(1-4-4) DDR F R 1
R R F R F

(4-4-4) SDR F 1
R R R

(4-4-4) DDR F R 1
R R F R F

Notes:
R: Rising Clock Edge
F: Falling Clock Edge
1: Data output from Mxxxx204 always begins on the falling edge of the clock – SDR & DDR

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Mxxxx204 supports eXecute-In-Place (XIP) which allows completing a series of read and write instructions without having
to individually load the read or write command for each instruction. Thus, XIP mode saves command overhead and reduces
random read & write access time. A special XIP byte must be entered after the address bits to enable/disable (Axh/Fxh)
XIP.

Mxxxx204 offers both hardware and software based data protection schemes. Hardware protection is through WP# pin.
Software protection is controlled by configuration bits in the Status register. Both schemes inhibit writing to the registers and
memory array.

Mxxxx204 has a 256-byte Augmented Storage Array which is independent from the main memory array. It is user
programmable and can be write protected against inadvertent writes.

Two lower power states are available in Mxxxx204, namely Deep Power Down and Hibernate. Data is not lost while the
device is in either of these two low power states. Moreover, the device maintains all its configurations.

Figure 5: Functional Block Diagram

CS# Address Register VCC

Serial Status Register

I/Os Column
Command Register Decoder
SO / IO[1] IO[3]
Row Decoder

MRAM
MRAM
MRAM
Array
WP# / IO[2] Command Array
Array CLK
&
Control
High Voltage
Generator
VSS SI / IO[0]
Regulator Data Buffer

Table 5: Modes of Operation

Mode Current CS# CLK SI / IO[3:0] SO / IO[3:0]
Standby ISB H Gated Gated / Hi-Z Hi-Z / Hi-Z
Active - Read IREAD L Toggle Command, Address Data Output
Active - Write IWRITE L Toggle Command, Address, Data Input Hi-Z
Deep Power Down IDPD H Gated Gated / Hi-Z Hi-Z / Hi-Z
Hibernate IHBN H Gated Gated / Hi-Z Hi-Z / Hi-Z
Notes:
H: High (Logic ‘1’)
L: Low (Logic ‘0’)
Hi-Z: High Impedance

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7. Device Initialization
When powering up, the following procedure is required to initialize the device correctly:
• Ramp up VCC (tRVR)
• CS# must follow VCC during power-up (a 10KΩ pull-up Resistor to VCC is recommended)
• It is recommended that no instructions are sent to the device when VCC is below VCC (minimum)
• During initial Power-up, recovering from power loss or brownout, a delay of tPU is required before normal operation
commences
• Upon Power-up, the device is in Standby mode

Figure 6: Power-Up Behavior

Device
Access
VCC Allowed
(Maximum)

VCC
(Minimum)

tPU

Time
0V

When powering down or in case of brown-out, the following procedure is required to turn off the device correctly:
• Ramp down VCC below VCC_RST level
• CS# must follow VCC during power-down (a 10KΩ pull-up Resistor to VCC is recommended)
• The device must not be selected and that no instructions are sent to the device when VCC is below VCC (minimum)
• The Power-up timing and device initialization needs to be observed after VCC ramps up above VCC (minimum)
• To stabilize the VCC level, suitable decoupling capacitors close to package VCC pin is recommended
• Chip functionality not guaranteed if VCC ramps down between VCC_CUTOFF and VCC_RST and then ramps up to VCC

Figure 7: Power-Down and Brown-out Behavior

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Table 6: Power Up/Down Timing – 3.0V

3.0V
Parameter Symbol Test Conditions
Minimum Typical Maximum Units
VCC Range VCC 2.7 - 3.6 V
VCC Ramp Up Time to VCC (min) tRVR 30 - 1500 µs
VCC Ramp Down Time to VCC_RST tRVF 20 - - µs
VCC Power Up to First Instruction tPU 250 - - µs
VCC Cutoff – Must Initialize Device VCC_CUTOFF 1.6 - - V
All operating
VCC Reset VCC_RST voltages and 0 - 0.3 V
VCC Power Down Low Time tPLOW temperatures 1000 - - µs
Time to Enter Deep Power Down tEDPD - - 3 µs
Time to Exit Deep Power Down tEXDPD - - 400 µs
Time to Enter Hibernate tENTHIB - - 3 µs
Time to Exit Hibernate tEXHIB - - 450 µs
CS# Pulse Width tCSDPD 50 - - ns

Table 7: Power Up/Down Timing – 1.8V

1.8V
Parameter Symbol Test Conditions
Minimum Typical Maximum Units
VCC Range VCC 1.71 - 2.0 V
VCC Ramp Up Time to VCC (min) tRVR 30 - 1000 µs
VCC Ramp Down Time to VCC_RST tRVF 20 - - µs
VCC Power Up to First Instruction tPU 250 - - µs
VCC Cutoff – Must Initialize Device VCC_CUTOFF 1.6 - - V
VCC Reset VCC_RST All operating 0 - 0.2 V
voltages and
VCC Power Down Low Time tPLOW temperatures 1000 - - µs
Time to Enter Deep Power Down tEDPD - - 3 µs
Time to Exit Deep Power Down tEXDPD - - 400 µs
Time to Enter Hibernate tENTHIB - - 3 µs
Time to Exit Hibernate tEXHIB - - 450 µs
CS# Pulse Width tCSDPD 50 - - ns

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8. Memory Map
Table 8: Memory Map
Density Address Range 24-bit Address [23:0]
4Mb 000000h – 07FFFFh [23:19] – Logic ‘0’ [18:0] - Addressable
8Mb 000000h – 0FFFFFh [23:20] – Logic ‘0’ [19:0] - Addressable
16Mb 000000h – 1FFFFFh [23:21] – Logic ‘0’ [20:0] - Addressable

9. Augmented Storage Array Map

Table 9: Augmented Storage Array Map
Density Address Range 24-bit Address [23:0]
4Mb 000000h – 0000FFh 1 [23:8] – Logic ‘0’ [7:0] - Addressable
8Mb 000000h – 0000FFh 1 [23:8] – Logic ‘0’ [7:0] - Addressable
16Mb 000000h – 0000FFh 1 [23:8] – Logic ‘0’ [7:0] - Addressable
Notes:
1: The 256-byte augmented storage array is divided into 8 individually readable and writeable sections (32 bytes per section). After an individual section is programmed,
it can be write protected to prevent further programming.

Table 10: Individual Section Address Range

Section Address Range 24-bit Address [23:0]
0 000000h – 00001Fh [23:8] – Logic ‘0’ [7:0] - Addressable
1 000020h – 00003Fh [23:8] – Logic ‘0’ [7:0] - Addressable
2 000040h – 00005Fh [23:8] – Logic ‘0’ [7:0] - Addressable
3 000060h – 00007Fh [23:8] – Logic ‘0’ [7:0] - Addressable
4 000080h – 00009Fh [23:8] – Logic ‘0’ [7:0] - Addressable
5 0000A0h – 0000BFh [23:8] – Logic ‘0’ [7:0] - Addressable
6 0000C0h – 0000DFh [23:8] – Logic ‘0’ [7:0] - Addressable
7 0000E0h – 0000FFh [23:8] – Logic ‘0’ [7:0] - Addressable

10. Register Addresses

Table 11: Register Addresses
Register Name Address
Status Register 0x000000h
Configuration Register 1 0x000002h
Configuration Register 2 0x000003h
Configuration Register 3 0x000004h
Configuration Register 4 0x000005h
Device Identification Register 0x000030h
Unique Identification Register 0x000040h
Note:
1: Register address space is different from the memory array and augmented storage array.

MRAM INITIALIZATION REQUIREMENT

After reflow temp cycle, MRAM Registers must be reconfigured to default settings. Please see the apps note; “Programming
Non-Volatile Registers to Factory Default State Post-Reflow Application Note” for details.

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11. Register Map

11.1 Status Register / Device Protection Register (Read/Write)

Status register is a legacy SPI register and contains options for enabling/disabling data protection.

Table 12: Status Register – Read and Write

Read / Default Selection
Bits Name Description
Write State Options
1: Protection Enabled – write protects
Hardware Based WP# when WP# is Low
SR[7] WP#EN R/W 0
Protection Enable/Disable 0: Protection Disabled – Doesn’t write
protect when WP# is Low
1: S/N Write protected - protection
Serial Number Protection
SR[6] SNPEN R/W 0 enabled
Enable/Disable
0: S/N Writable - protection disabled
1: Bottom Protection Enabled (Lower
Software Top/Bottom
Address Range)
SR[5] TBSEL Memory Array Protection R/W 0
0: Top Protection Enabled (Higher
Selection
Address Range)
SR[4] BPSEL[2] Block Protect Selection Bit 2 R/W 0
Block Protection Bits (Table 13, Table
SR[3] BPSEL[1] Block Protect Selection Bit 1 R/W 0
14)
SR[2] BPSEL[0] Block Protect Selection Bit 0 R/W 0
Write Operation Protection 1: Write Operation Protection Disabled
SR[1] WREN R 0
Enable/Disable 0: Write Operation Protection Enabled
SR[0] RSVD Reserved R 0 Reserved for future use

Table 13: Top Block Protection Address Range Selection (TBPSEL=0)

BPSEL BPSEL BPSEL Protected
4Mb 8Mb 16Mb
[2] [1] [0] Portion
0 0 0 None None None None
07E000h – 0FC000h – 1F8000h –
0 0 1 Upper 1/64 07FFFFh 0FFFFFh 1FFFFFh
07C000h – 0F8000h – 1F0000h –
0 1 0 Upper 1/32 07FFFFh 0FFFFFh 1FFFFFh
078000h – 0F0000h – 1E0000h –
0 1 1 Upper 1/16 07FFFFh 0FFFFFh 1FFFFFh
070000h – 0E0000h – 1C0000h –
1 0 0 Upper 1/8 07FFFFh 0FFFFFh 1FFFFFh
060000h – 0C0000h – 180000h –
1 0 1 Upper 1/4 07FFFFh 0FFFFFh 1FFFFFh
040000h – 080000h – 1F0000h –
1 1 0 Upper 1/2 07FFFFh 0FFFFFh 1FFFFFh
000000h – 000000h – 000000h –
1 1 1 All 07FFFFh 0FFFFFh 1FFFFFh

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Table 14: Bottom Block Protection Address Range Selection (TBPSEL=1)

BPSEL BPSEL BPSEL Protected
4Mb 8Mb 16Mb
[2] [1] [0] Portion
0 0 0 None None None None
000000h – 000000h – 000000h –
0 0 1 Lower 1/64 001FFFh 003FFFh 007FFFh
000000h – 000000h – 000000h –
0 1 0 Lower 1/32 003FFFh 007FFFh 00FFFFh
000000h – 000000h – 000000h –
0 1 1 Lower 1/16 007FFFh 00FFFFh 01FFFFh
000000h – 000000h – 000000h –
1 0 0 Lower 1/8 00FFFFh 01FFFFh 03FFFFh
000000h – 000000h – 000000h –
1 0 1 Lower 1/4 01FFFFh 03FFFFh 07FFFFh
000000h – 000000h – 000000h –
1 1 0 Lower 1/2 03FFFFh 07FFFFh 0FFFFFh
000000h – 000000h – 000000h –
1 1 1 All 07FFFFh 0FFFFFh 1FFFFFh

Table 15: Write Protection Modes

Status Memory1 Memory1
WREN WP#EN WP# & Array Array
(Status Register) (Status Register) (Pin) Configuration Protected Unprotected
Registers Area Area
0 X X Protected Protected Protected
1 0 X Unprotected Protected Unprotected
1 1 Low Protected Protected Unprotected
1 1 High Unprotected Protected Unprotected
Notes:
High: Logic ‘1’
Low: Logic ‘0’
X: Don’t Care – Can be Logic ‘0’ or ‘1’
Protected: Write protected
Unprotected: Writable
1: Memory address range protection based on Block Protection Bits

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11.2 Augmented Storage Array Protection Register (Read/Write)

Augmented Storage Array Protection register contains options for enabling/disabling data protection for eight 32-byte
sections.
Table 16: Augmented Storage Array Protection Register – Read and Write
Read
Default Selection
Bits Name Description /
State Options
Write
ASA Section 7 Write 1: Protection Enabled
ASP[7] ASPS[7] R/W 0 0: Protection Disabled
Protection Enable/Disable
ASA Section 6 Write 1: Protection Enabled
ASP[6] ASPS[6] R/W 0 0: Protection Disabled
Protection Enable/Disable
ASA Section 5 Write 1: Protection Enabled
ASP[5] ASPS[5] R/W 0 0: Protection Disabled
Protection Enable/Disable
ASA Section 4 Write 1: Protection Enabled
ASP[4] ASPS[4] R/W 0 0: Protection Disabled
Protection Enable/Disable
ASA Section 3 Write 1: Protection Enabled
ASP[3] ASPS[3] R/W 0 0: Protection Disabled
Protection Enable/Disable
ASA Section 2 Write 1: Protection Enabled
ASP[2] ASPS[2] R/W 0 0: Protection Disabled
Protection Enable/Disable
ASA Section 1 Write 1: Protection Enabled
ASP[1] ASPS[1] R/W 0 0: Protection Disabled
Protection Enable/Disable
ASA Section 0 Write 1: Protection Enabled
ASP[0] ASPS[0] R/W 0 0: Protection Disabled
Protection Enable/Disable

11.3 Device Identification Register (Read Only)

Device identification register contains Avalanche’s Manufacturing ID along with device configuration information.

Table 17: Device Identification Register – Read Only

Avalanche Device
Bits
Manufacturer's ID Configuration
Interface Voltage Temp Density Freq
ID[31:0] ID[31:24]
ID[23:20] ID[19:16] ID[15:12] ID[11:8] ID[7:0]

Manufacturer Interface Voltage Temperature Density Frequency

ID
31-24 23-20 19-16 15-12 11-8 7-0
1110 0110 0000-HP QSPI 0001 - 3V 0000 - -40⁰C- 85⁰C 0010 - 4Mb 00000001 - 108MHz
0010 - 1.8V 0001 - -40⁰C-105⁰C 0011 - 8Mb 00000010 – 54MHz
0100 - 16Mb 00000011 - Reserved
00000100 - Reserved
00000101 - Reserved

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11.4 Serial Number Register (Read/Write)

Serial Number register is user writable.

Table 18: Serial Number Register – Read and Write

Read
Selection
Bits Name Description / Default State 1
Options
Write
000000000000 Value stored is based on the customer
SN[63:0] SN Serial Number Value R/W
0000h
Notes:
1: The default value is how the device is shipped from the factory.

11.5 Unique Identification Register (Read Only)

Unique Identification register contains a number unique to every device.

Table 19: Unique ID Register – Read Only

Read / Selection
Bits Name Description
Write Options
Unique Identification Value stored is written in the factory and is
UID[63:0] UID R device specific
Number Value

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11.6 Configuration Register 1 (Read/Write)

Configuration Register 1 controls locking/unlocking data protection options set in the Status register. Once locked, the
protection options cannot be changed in the Status register.

Table 20: Configuration Register 1 – Read and Write

Read Selection
Default
Bits Name Description /
State Options
Write

CR1[7] RSVD Reserved R 0 Reserved for future use

CR1[6] RSVD Reserved R 0 Reserved for future use

CR1[5] RSVD Reserved R 0 Reserved for future use

CR1[4] RSVD Reserved R 0 Reserved for future use

CR1[3] RSVD Reserved R 0 Reserved for future use

Status Register Lock

1: Lock TBSEL and BPSEL[2:0]
CR1[2] MAPLK Enable/Disable R/W 0
0: Unlock TBSEL and BPSEL[2:0]
(TBSEL, BPSEL[2:0]

CR1[1] RSVD Reserved R 0 Reserved for future use

1: Write Protect Augmented

Augmented Storage Array Data
Storage Array
CR1[0] ASPLK Protection R/W 0
0: Not Write Protect Augmented
Storage Array

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11.7 Configuration Register 2 (Read/Write)

Configuration Register 2 controls the interface type along with memory array access latency.

Table 21: Configuration Register 2 – Read and Write

Read Selection
Default
Bits Name Description /
State Options
Write

CR2[7] RSVD Reserved R 0 Reserved for future use

Quad SPI (QPI 4-4-4) Interface 1: Quad SPI (QPI 4-4-4) Enabled
CR2[6] QPISL R2 0
Mode Enable/Disable 0: Single SPI (SPI 1-1-1) Enabled

CR2[5] RSVD Reserved R 0 Reserved for future use

Dual SPI (DPI 2-2-2) Interface 1: Dual SPI (DPI 2-2-2) Enabled
CR2[4] DPISL R2 0
Mode Enable/Disable 0: Single SPI (SPI 1-1-1) Enabled

0000: 0 Cycles - Default

CR2[3] MLATS[3] 0
0001: 1 Cycle

0010: 2 Cycles
CR2[2] MLATS[2] 0
0011: 3 Cycles

0100: 4 Cycles
CR2[1] MLATS[1] 0
0101: 5 Cycles

0110: 6 Cycles

Memory Array Read Latency 0111: 7 Cycles

R/W
Selection 1 1000: 8 Cycles

1001: 9 Cycle

1010: 10 Cycles
CR2[0] MLATS[0] 0
1011: 11 Cycles

1100: 12 Cycles

1101: 13 Cycles

1110: 14 Cycles

1111: 15 Cycles

Notes:
1: Latency is frequency dependent. Please consult Table 22 and Table 23.
2: These interface options can only be set through instructions.

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Table 22: Memory Array Read Latency Cycles vs. Maximum Clock Frequency (with XIP)
Max Frequency
Read Type Latency
Mxxxx2x108xx Mxxxx2x054xx
(1-1-1) SDR 108MHz 54MHz
(1-1-1) DDR 54MHz 27MHz
(1-1-2) SDR 108MHz 54MHz
(1-2-2) SDR 8-15 108MHz 54MHz
(2-2-2) SDR 108MHz 54MHz
(2-2-2) DDR 54MHz 27MHz
(1-1-4) SDR 108MHz 54MHz
(1-4-4) SDR 108MHz 54MHz
(1-4-4) DDR 12-15 54MHz 27MHz
108MHz
(4-4-4) SDR
54MHz
(4-4-4) DDR 54MHz 27MHz

Table 23: Memory Read Latency Cycles vs. Maximum Clock Frequency (without XIP)
Max Frequency
Read Type Latency
Mxxxx2x108xx Mxxxx2x054xx
(1-1-1) SDR 0 50MHz 40MHz

Table 24: Augmented Storage Array Read Latency Cycles vs. Maximum Clock Frequency
Max Frequency
Read Type Latency
Mxxxx2x108xx Mxxxx2x054xx
(1-1-1) SDR 8-15 50MHz 40MHz

Table 25: Read Any Register Command Latency Cycles vs. Maximum Clock Frequency

Read Type Max Frequency Latency Cycles

(1-1-1) SDR 108MHz 8

(2-2-2) SDR 108MHz 4
(4-4-4) SDR 108MHz 2

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11.8 Configuration Register 3 (Read/Write)

Configuration Register 3 controls the output driver strength along with read data wrap selection.
Table 26: Configuration Register 3 – Read and Write
Read Default Selection
Bits Name Description /
Options
Write 1.8V 3.0V
1.8V 3.0V
CR3[7] ODSEL[2] 0 0 000: 45Ω1 35Ω
001: 120Ω 75Ω
010: 90Ω 60Ω
CR3[6] ODSEL[1] Output Driver Strength Selector R/W 0 1 011: 70Ω 45Ω1
100: 45Ω 35Ω
101: 60Ω 40Ω
CR3[5] ODSEL[0] 0 1 110: 30Ω 20Ω
111: 20Ω 15Ω
Read WRAP Enable / Disable 1: Read Data Wrap Enabled
CR3[4] WRAPS R/W 0 0: Read Data Wrap Disabled
(16/32/64/128/256 Byte)
CR3[3] RSVD Reserved R 0 Reserved for future use
000: 16-byte Boundary
CR3[2] WRPLS[2] 0 001: 32-byte Boundary
010: 64-byte Boundary
011: 128-byte Boundary
CR3[1] WRPLS[1] Wrap Length Selector2 R/W 0 100: 256-byte Boundary
101: Reserved
110: Reserved
CR3[0] WRPLS[0] 0 111: Reserved
Notes:
1: Default Setting (VCC dependent).
2: If Wrap is enabled, the read data wraps within an aligned 16/32/64/128/256-byte boundary at any address. The starting address entered selects the
group of bytes and the first data returned is the addressed byte. Bytes are then read sequentially until the end of the group boundary is reached. If read
continues, the address wraps to the beginning of the group and continues to read sequentially.

11.9 Configuration Register 4 (Read/Write)

Configuration Register 4 controls Write Enable protection (WREN – Status Register) reset functionality during memory array
writing1. This functionality makes SPI MRAM compatible to other SPI devices.
Table 27: Configuration Register 4 – Read and Write
Read
Default Selection
Bits Name Description /
State Options
Write
CR4[7] RSVD Reserved 0 Reserved for future use
CR4[6] RSVD Reserved 0 Reserved for future use
CR4[5] RSVD Reserved 0 Reserved for future use
CR4[4] RSVD Reserved 0 Reserved for future use
CR4[3] RSVD Reserved 0 Reserved for future use
CR4[2] RSVD Reserved 1 Reserved2
WREN Reset R/W 00: Normal: WREN is prerequisite to all Memory Array
Write instruction. (WREN is reset after CS# goes High)
CR4[1] WRENS[1] Selector 0 01: SRAM: WREN is not a prerequisite to Memory Array
Write instruction (WREN is ignored)
(Memory & 10: Back-to-Back: WREN is prerequisite to only the first
Augmented Storage Memory Array Write instruction. WREN disable
CR4[0] WRENS[0] 1 instruction must be executed to reset WREN.
Array Write (WREN does not reset once CS# goes High)
Functionality) 11: Illegal - Reserved for future use
Notes:
1: Write Enable protection (WREN – Status Register) for Registers is maintained irrespective of the Configuration Register 4 settings. In other words, all
register write instructions require WREN to be set and WREN resets once CS# goes High for the write instruction.
2: Must be set to “1”. Writing a “0” to this bit may impact device functionality.

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12. Instruction Set

Table 28: Instruction Set

Max. Frequency
Latency Cycles

Prerequisite
Data Bytes
Command
(Opcode)

(1-0-1)

(1-1-2)

(2-0-0)

(2-0-2)

(2-2-2)

(1-1-4)

(4-0-0)

(4-4-4)
(1-0-0)

(1-1-1)

(1-2-2)

(1-4-4)

(4-0-4)

DDR
SDR
Instruction

XIP
#
Name

Control Instructions
NOOP 108
1 No Operation 00h • • • • MHz

WREN 108
2 Write Enable 06h • • • • MHz

WRDI 108
3 Write Disable 04h • • • • MHz

DPIE 108
4 Enable DPI 37h • • • MHz

QPIE 108
5 Enable QPI 38h • • • MHz

SPIE 108
6 Enable SPI FFh • • • MHz

DPDE 108
7 Enter Deep Power Down B9h • • • • MHz

HBNE 108
8 Enter Hibernate BAh • • • • MHz

SRTE 108
9 Software Reset Enable 66h • • • • MHz

SRST 108
10 Software Reset 99h • • • • MHz
SRTE

DPDX 108
11 Exit Deep Power Down ABh • • • • MHz

Read Register Instructions

RDSR 54
12 Read Status Register 05h • • • • 1
MHz

RDC1 54
13 Read Configuration Register 1 35h • • • • 1
MHz

RDC2 54
14 Read Configuration Register 2 3Fh • • • • 1
MHz

RDC3 54
15 Read Configuration Register 3 44h • • • • 1
MHz

RDC4 54
16 Read Configuration Register 4 45h • • • • 1
MHz

Read Configuration Register 1, RDCX 54

17
2, 3, 4 46h • • • • 4
MHz

RDID 54
18 Read Device ID 9Fh • • • • 4
MHz

RUID 54
19 Read Unique ID 4Ch • • • • 8
MHz

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Max. Frequency
Latency Cycles

Prerequisite
Data Bytes
Command
(Opcode)

(1-0-1)

(1-1-2)

(2-0-0)

(2-0-2)

(2-2-2)

(1-1-4)

(4-0-0)

(4-4-4)
(1-0-0)

(1-1-1)

(1-2-2)

(1-4-4)

(4-0-4)

DDR
SDR
Instruction

XIP
#
Name

RDSN 54
20 Read Serial Number Register C3h • • • • 8
MHz

Read Augmented Array RDAP 54

21
Protection Register 14h • • • • 1
MHz

Read Any Register - Address RDAR 108

22
Based 65h • • • • • 1 to 8
MHz

Write Register Instructions

WRSR 108
23 Write Status Register 01h • • • • 1
MHz
WREN

Write Configuration Registers WRCX 108

24
1, 2, 3, 4 87h • • • • 4
MHz
WREN

WRSN 108
25 Write Serial Number Register C2h • • • • 8
MHz
WREN

Write Augmented Array WRAP 108

26
Protection Register 1Ah • • • • 1
MHz
WREN

Write Any Register - Address WRAR 108

27
Based 71h • • • • 1 to 8
MHz
WREN

Read Memory Array Instructions

READ 1 to 50
28 Read Memory Array - SDR 03h • • ∞ MHz

RDFT 1 to 108
29 Fast Read Memory Array - SDR 0Bh • • • • • • ∞ MHz

DRFR 1 to 54
30 Fast Read Memory Array - DDR 0Dh • • • • • • ∞ MHz

Read Dual Output Memory RDDO 1 to 108

31
Array - SDR 3Bh • • • • ∞ MHz

Read Quad Output Memory RDQO 1 to 108

32
Array - SDR 6Bh • • • • ∞ MHz

Read Dual I/O Memory Read - RDDI 1 to 108

33
SDR BBh • • • • ∞ MHz

Read Dual I/O Memory Read - DRDI 1 to 54

34
DDR BDh • • • • ∞ MHz

Read Quad I/O Memory Read - RDQI 1 to 108

35
SDR EBh • • • • ∞ MHz

Read Quad I/O Memory Read - DRQI 1 to 54

36
DDR EDh • • • • ∞ MHz

Write Memory Array Instructions

WRTE 1 to 108
37 Write Memory Array - SDR 02h • • ∞ MHz
WREN

WRFT 1 to 108
38 Fast Write Memory Array - SDR DAh • • • • • ∞ MHz
WREN

Fast Write Memory Array - DRFW 1 to 54

39
DDR DEh • • • • • ∞ MHz
WREN

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 M1004204/M1008204/M1016204 M3004204/M3008204/M3016204

Max. Frequency
Latency Cycles

Prerequisite
Data Bytes
Command
(Opcode)

(1-0-1)

(1-1-2)

(2-0-0)

(2-0-2)

(2-2-2)

(1-1-4)

(4-0-0)

(4-4-4)
(1-0-0)

(1-1-1)

(1-2-2)

(1-4-4)

(4-0-4)

DDR
SDR
Instruction

XIP
#
Name

Write Dual Input Memory Array WDUI 1 to 108

40
- SDR A2h • • • ∞ MHz
WREN

Write Quad Input Memory WQDI 1 to 108

41
Array - SDR 32h • • • ∞ MHz
WREN

Write Quad Input Memory DWQI 1 to 54

42
Array - DDR 31h • • • ∞ MHz
WREN

Write Dual I/O Memory Array - WDIO 1 to 108

43
SDR A1h • • • ∞ MHz
WREN

Write Quad I/O Memory Array - WQIO 1 to 108

44
SDR D2h • • • ∞ MHz
WREN

Write Quad I/O Memory Array - DWQO 1 to 54

45
DDR D1h • • • ∞ MHz
WREN

Augmented Storage Array Instructions

Read Augmented Storage RDAS 1 to 50
46
Array - SDR 4Bh • • • 256 MHz

Write Augmented Storage WRAS 1 to 108

47
Array - SDR 42h • • ∞ MHz
WREN

Notes:
1: A typical SPI instruction consists of command, address and data components. The bus width to transmit these three components varies based on the
SPI interface mode selected. To accurately represent the number of I/Os used to transmit these three components, a nomenclature (command-address-
data) is adopted and used throughout this document. Integers placed in the (command-address-data) fields represent the number of I/Os used to transmit
the particular component. As an example, 1-1-1 means command, address and data are transmitted on a single I/O (SI / IO[0] or SO / IO[1]). On the other
hand, 1-4-4 represents command being sent on a single I/O (SI / IO[0]) and address/data being sent on four I/Os (IO[3:0]).
2: XIP allows completing a series of read and write instructions without having to individually load the read or write command for each instruction. A special
mode byte must be entered after the address bits to enable/disable XIP – Axh / Fxh.
3: Read instruction must include Latency cycles to meet higher frequency. They are configurable (Configuration Register 2 – CR2[3:0]) and frequency
dependent.
4: The augmented storage array is 256-Bytes in size. The address bits ADDR[23:8] must be Logic ‘0’ for this instruction.
5: Registers do not wrap data during reads. Reading beyond the specified number of bytes will yield indeterminate data.
6: WREN prerequisite for array writing is configurable (Configuration Register 4 – CR4[1:0]).
7: For the Exit Deep Power Down command, the maximum frequency is 108MHz for 1-1-1 operation and 36MHz for 2-2-2 and 4-4-4 operations.

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13. Instruction Description and Structures

All communication between a host and Mxxxx204 is in the form of instructions. Instructions define the operation that must
be executed. Instructions consist of a command followed by an optional address modifier and data transfer to or from
Mxxxx204. All command, address and data information is transferred sequentially. Instructions are structured as follows:

• Each instruction begins with CS# going Low (logic ‘0’) and ends with CS# returning High (Logic’1’).

• CLK marks the transfer of each bit.

• Each instructions starts out with an 8-bit command. The command selects the type of operation Mxxxx204 must
perform. The command is transferred on the rising edges of CLK.

• The command can be stand alone or followed by address to select a memory location or register. The address is
always 24-bits wide.

 SDR: The address is transferred on the rising edges of CLK.

 DDR: The address is transferred on both edges of the CLK in DDR.

• The address bits are followed by data bits. For Write instructions:

 SDR: Write data bits to Mxxxx204 are transferred on the rising edges of CLK.
 DDR: Write data bits to Mxxxx204 are transferred on both edges of CLK.

• In normal operational mode, Write instructions must be preceded by the WREN instruction. WREN instruction sets
the WREN bit in the Status register. WREN bit is reset at the end of every Write instruction. WREN bit can also be
reset by executing the WRDI instruction. Mxxxx204 offers two other modes, namely SRAM and Back-to-Back Write
where WREN does not get reset after a write instruction to the memory array or the augmented storage array.
These modes are set in Configuration Register 4.

• Similar to write instructions, the address bits are followed by data bits for read instructions:

 SDR: Read data bits from Mxxxx204 are transferred on the falling edges of CLK.
 DDR: Read data bits from Mxxxx204 are transferred on both edges of CLK. The start of read data transfer is
always on the falling edge of the CLK.

• Mxxxx204 is a high performance serial memory and at higher frequencies, read instructions require latency cycles
to compensate for the memory array access time. The number of latency cycles required depends on the
operational frequency and is configurable – Configuration Register 2. The latency cycles are inserted after the
address bits before the data comes out of Mxxxx204.

• For Read and Write instructions, Mxxxx204 offers XIP mode. XIP allows similar instructions to be executed
sequentially without incurring the command cycles overhead. XIP is enabled by entering byte Axh and disabled by
entering byte Fxh. These respective bytes must be entered following the address bits.

• For Read instructions, Mxxxx204 offers wrap mode. Wrap bursts are confined to address aligned 16/32/64/128/256
byte boundary. The read address can start anywhere within the wrap boundary. 16/32/64/128/256 wrap
configuration is set in Configuration Register 3.

• The entire memory array can be read from or written to using a single read or write instruction. After the staring
address is entered, subsequent address are internally incremented as long as CS# is Low and CLK continues to
cycle.

• All commands, address and data are shifted with the most significant bit first.

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Figure 8 to Figure 24 show the description of SDR instruction types supported.

Figure 8: Description of (1-0-0) Instruction Type

1
Byte
CS#
3
CLK
0
Command
SI / IO[0] 7 6 5 4 3 2 1 0

Figure 9: Description of (1-0-1) Instruction Type

1 1 to 8 Bytes
Byte
CS#
3
CLK
0
Command Input Data

SI / IO[0] 7 6 5 4 3 2 1 0 7 6 5 4 2 1 0

Output Data Read/Write

SO / IO[1] 7 6 5 4 2 1 0

Figure 10: Description of (1-1-1) Instruction Type (Without XIP)

1 3 1 to ∞
Byte Bytes Bytes
CS#
3
CLK
0
Command Address Input Data

SI / IO[0] 7 6 5 4 3 2 1 0 7 6 5 4 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 2 1 0

Output Data Read/Write

SO / IO[1] 7 6 5 4 2 1 0 7 6 5 4 2 1 0

Figure 11: Description of (1-1-1) Augmented Storage Instruction Type

8-15
1 3
Latency
Byte Bytes
Cycles
CS#
3
CLK
0
Command Address Input Data

SI / IO[0] 7 6 5 4 3 2 1 0 7 6 5 4 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 2 1 0

Output Data Read/Write

SO / IO[1] 7 6 5 4 2 1 0

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Figure 12: Description of (1-1-1) Instruction Type (With XIP)

XIP 8 to 15
1 3 1 to ∞
(Axh, Fxh) Latency
Byte Bytes Bytes
(Enable, Disable) Cycles
CS#
3
CLK
0
Command Address XIP Input Data

SI / IO[0] 7 6 5 4 3 2 1 0 7 6 5 4 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 2 1 0 7 6 5 4 2 1 0

Output Data Read/Write

SO / IO[1] 7 6 5 4 2 1 0

Figure 13: Description of (1-1-2) Instruction Type (With XIP)

1 3
XIP 8 to 15 1 to ∞
(Axh, Fxh) Latency Bytes
Byte Bytes
(Enable, Disable) Cycles (Read)
CS#
3
CLK
0
Command Address XIP Output Data

IO[0] 7 6 5 4 3 2 1 0 7 6 5 4 2 1 0 7 6 5 4 3 2 1 0 6 4 0 6 4 0

Read
IO[1] 7 5 1 7 5 1

1 to ∞
Bytes
(Write)

6 4 0 6 4 0 6 4 0 6 4 0

Input Data Input Data Write

7 5 1 7 5 1 7 5 1 7 5 1

Figure 14: Description of (1-2-2) Instruction Type (With XIP)

1 3
8 to 15 1 to ∞
XIP Latency Bytes
Byte Bytes (A xh, Fxh)
(E nabl e, Disable) Cycles (Read)
CS#
3
CLK
0
Command Address XIP

IO[0] 7 6 5 4 3 2 1 0 6 4 0 4 2 0 6 4 2 0 6 4 0 6 4 0

Output Data Read

IO[1] 7 5 1 5 3 1 7 5 3 1 7 5 1 7 5 1

1 to ∞
Bytes
(Write)

6 4 0 6 4 0 6 4 0 6 4 0

Write
7 5 1 7 5 1 7 5 1 7 5 1

Feb.21.23 Page 30
 M1004204/M1008204/M1016204 M3004204/M3008204/M3016204

Figure 15: Description of (2-0-0) Instruction Type

B yt e

CS#
3
CLK
0
Comm and

IO[0] 6 4 2 0

IO[1] 7 5 3 1

Figure 16: Description of (2-0-2) Instruction Type

1 to 8
Bytes
B yt e (Read)
CS#
3
CLK
0
Comm and

IO[0] 6 4 2 0 6 4 0 6 4 2 0

Output Data Read

IO[1] 7 5 3 1 7 5 1 7 5 3 1

Figure 17: Description of (2-2-2) Any Register Instruction Type

3 4
Latency
B yt e
Bytes Cycles
CS#
3
CLK
0
Comm and Address

IO[0] 6 4 2 0 6 4 0 4 2 0 6 4 0 6 4 0 6 4 0

Output Data Read

IO[1] 7 5 3 1 7 5 1 5 3 1 7 5 1 7 5 1 7 5 1

1 to 8
Bytes
(Write)

6 4 0 6 4 0 6 4 0 6 4 0

Write
7 5 1 7 5 1 7 5 1 7 5 1

Feb.21.23 Page 31
 M1004204/M1008204/M1016204 M3004204/M3008204/M3016204

Figure 18: Description of (2-2-2) Instruction Type (With XIP)

3
8 to 15 1 to ∞
XIP Latency Bytes
Bytes (A xh, Fx h)
B yt e
(E nabl e, Dis able) Cycles (Read)
CS#
3
CLK
0
Comm and Address XIP

IO[0] 6 4 2 0 6 4 0 4 2 0 6 4 2 0 6 4 0 6 4 0

Output Data Read

IO[1] 7 5 3 1 7 5 1 5 3 1 7 5 3 1 7 5 1 7 5 1

1 to ∞
Bytes
(Write)

6 4 0 6 4 0 6 4 0 6 4 0

Write
7 5 1 7 5 1 7 5 1 7 5 1

Figure 19: Description of (1-1-4) Instruction Type (With XIP)

1 3
XIP 8 to 15 1 to ∞
(Axh, Fxh) Latency Bytes
Byte Bytes
(Enable, Disable) Cycles (Read)
CS#
3
CLK
0
Command Address XIP Output Data

IO[0] 7 6 5 4 3 2 1 0 7 6 5 4 2 1 0 7 6 5 4 3 2 1 0 4 0 4 0 4 0

IO[1] 5 1 5 1 5 1

Read
IO[2] 6 2 6 2 6 2

IO[3] 7 3 7 3 7 3

1 to ∞
Bytes
(Write)

4 0 4 0 4 0 4 0 4 0 4 0

Input Data Input Data

5 1 5 1 5 1 5 1 5 1 5 1

Write
6 2 6 2 6 2 6 2 6 2 6 2

7 3 7 3 7 3 7 3 7 3 7 3

Feb.21.23 Page 32
 M1004204/M1008204/M1016204 M3004204/M3008204/M3016204

Figure 20: Description of (1-4-4) Instruction Type (With XIP)

XIP
(Axh, Fxh)

1 3
(Enable, Disable) 8 to 15 1 to ∞
Latency Bytes
Byte Bytes
Cycles (Read)
CS#
3
CLK
0
Command Address XI P Output Dat a

IO[0] 7 6 5 4 3 2 1 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0

IO[1] 5 1 5 1 5 1 5 1 5 1 5 1 5 1

Read
IO[2] 6 3 6 2 6 2 6 2 6 2 6 2 6 2

IO[3] 7 3 7 3 7 3 7 3 7 3 7 3 7 3

1 to ∞
Bytes
(Wr ite)

4 0 4 0 4 0 4 0 4 0 4 0

Input Data Input Data

5 1 5 1 5 1 5 1 5 1 5 1

Write
6 2 6 2 6 2 6 2 6 2 6 2

7 3 7 3 7 3 7 3 7 3 7 3

Figure 21: Description of (4-0-0) Instruction Type

1
Byte

CS#
3
CLK
0
Command

IO[0] 4 0

IO[1] 5 1

IO[2] 6 2

IO[3] 7 3

Feb.21.23 Page 33
 M1004204/M1008204/M1016204 M3004204/M3008204/M3016204

Figure 22: Description of (4-0-4) Instruction Type

1
Byte 1 to 8
Bytes
(Read)
CS#
3
CLK
0
Command
Output Data

IO[0] 4 0 4 0 4 0 4 0

IO[1] 5 1 5 1 5 1 5 1

Read
IO[2] 6 2 6 2 6 2 6 2

IO[3] 7 3 7 3 7 3 7 3

Figure 23: Description of (4-4-4) Any Register Instruction Type (Without XIP)

2
1 Latency
Byte 3 Cycles
Bytes
CS#
3
CLK 0 Comman
d
Address Output Data

IO[0] 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0

IO[1] 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1

Read
IO[2] 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2

IO[3] 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3

1 to 8
Bytes
(Write)
4 0 4 0 4 0 4 0 4 0 4 0

Input Data Input Data

5 1 5 1 5 1 5 1 5 1 5 1

Write
6 2 6 2 6 2 6 2 6 2 6 2

7 3 7 3 7 3 7 3 7 3 7 3

Feb.21.23 Page 34
 M1004204/M1008204/M1016204 M3004204/M3008204/M3016204

Figure 24: Description of (4-4-4) Instruction Type (With XIP)

XIP
1 (Axh, Fxh)
Byte 3
(Enable, Disable) 8 to 15 1 to ∞
Latency Bytes
Bytes
Cycles (Read)
CS#
3
CLK
0
Command
Address XIP Output Data

IO[0] 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0

IO[1] 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1

Read
IO[2] 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2

IO[3] 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3

1 to ∞
Bytes
(Write)

4 0 4 0 4 0 4 0 4 0 4 0

Input Data Input Data

5 1 5 1 5 1 5 1 5 1 5 1

Write
6 2 6 2 6 2 6 2 6 2 6 2

7 3 7 3 7 3 7 3 7 3 7 3

Feb.21.23 Page 35
 M1004204/M1008204/M1016204 M3004204/M3008204/M3016204

Figure 25 to Figure 29 show the description of DDR instruction types supported.

Figure 25: Description of (1-1-1) DDR Instruction Type (With XIP)

XIP 8 to 15
1 3 1 to ∞
(Axh, Fxh) Latency
Byte Bytes Bytes
(Enable, Disable) Cycles
CS#

CLK
0
Command Address XI P Input Data

SI / IO[0] 7 6 5 4 3 2 1 0 7 6 5 4 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 2 1 0

Output Dat a Read/Write

SO / IO[1] 7 6 5 4 2 1 0

Figure 26: Description of (2-2-2) DDR Instruction Type (With XIP)

1 3
8 to 15 1 to ∞
XIP Latency Bytes
Byte Bytes (A xh, Fx h)
(E nabl e, Dis able) Cycles (Read)
CS#

CLK

Comm and Address XIP

IO[0] 6 4 2 0 6 4 1 6 4 0 6 4 2 0 6 4 0 6 4 2 0

Output Data Read

IO[1] 7 5 3 1 7 5 0 7 5 1 7 5 3 1 7 5 1 7 5 3 1

1 to ∞
Bytes
(Write)

6 4 0 6 4 2 0 6 4 0 6 4 2 0

Write
7 5 1 7 5 3 1 7 5 1 7 5 3 1

Feb.21.23 Page 36
 M1004204/M1008204/M1016204 M3004204/M3008204/M3016204

Figure 27: Description of (4-4-4) DDR Instruction Type (With XIP)

XIP
(Axh, Fxh)

3
(Enable, Disable) 8 to 15 1 to ∞
Latency Bytes
Bytes
Cycles (Read)
CS#

CLK
Command
Address XIP Output Data

IO[0] 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0

IO[1] 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1

Read
IO[2] 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2

IO[3] 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3

1 to ∞
Bytes
(Write)

4 0 4 0 4 0 4 0 4 0 4 0

Input Data Input Data

5 1 5 1 5 1 5 1 5 1 5 1

Write
6 2 6 2 6 2 6 2 6 2 6 2

7 3 7 3 7 3 7 3 7 3 7 3

Figure 28: Description of (1-2-2) DDR Instruction Type (With XIP)

3
8 to 15 1 to ∞
XIP Latency Bytes
Bytes (A xh, Fx h)
(E nabl e, Dis able) Cycles (Read)
CS#

CLK

Command Address XIP

IO[0] 7 6 5 4 3 2 1 0 6 4 2 0 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0

Output Data Read

IO[1] 7 5 3 1 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1

1 to ∞
Bytes
(Write)

6 4 0 6 4 2 0 6 4 2 0 6 4 2 0

Write
7 5 1 7 5 3 1 7 5 3 1 7 5 3 1

Feb.21.23 Page 37
 M1004204/M1008204/M1016204 M3004204/M3008204/M3016204

Figure 29: Description of (1-4-4) DDR Instruction Type (With XIP)

XIP
(Axh, Fxh)

3
(Enable, Disable) 8 to 15 1 to ∞
Latency Bytes
Bytes
Cycles (Read)
CS#

CLK

Command Address XIP Output Data

IO[0] 7 6 5 4 3 2 1 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0

IO[1] 5 1 5 1 5 1 5 1 5 1 5 1 5 1

Read
IO[2] 6 2 6 2 6 2 6 2 6 2 6 2 6 2

IO[3] 7 3 7 3 7 3 7 3 7 3 7 3 7 3

1 to ∞
Bytes
(Write)

4 0 4 0 4 0 4 0 4 0 4 0

Input Data Input Data

5 1 5 1 5 1 5 1 5 1 5 1

Write
6 2 6 2 6 2 6 2 6 2 6 2

7 3 7 3 7 3 7 3 7 3 7 3

Feb.21.23 Page 38
 M1004204/M1008204/M1016204 M3004204/M3008204/M3016204

14. Electrical Specifications

Table 29: Recommended Operating Conditions

Parameter / Condition Minimum Typical Maximum Units
Industrial -40.0 - 85.0 °C
Operating Temperature
Industrial Plus -40.0 - 105.0 °C
VCC Supply Voltage (3.0V) 3.0V 2.7 3.0 3.6 V
VCC Supply Voltage (1.8V) 1.8V 1.71 1.8 2.0 V
VSS Supply Voltage 0.0 0.0 0.0 V

Table 30: Pin Capacitance

Parameter Test Conditions Symbol Maximum Units
Input Pin Capacitance TEMP = 25°C; f = 1 MHz; VIN = 3.0V CIN 5.0 pF
Output Pin Capacitance TEMP = 25°C; f = 1 MHz; VIN = 3.0V CINOUT 6.0 pF

Table 31: Endurance & Retention

Parameter Symbol Test Conditions Minimum Units
Write Endurance END - 1014 cycles
105°C 10
85°C 1,000
Data Retention RET years
75°C 10,000
65°C 1,000,000

Feb.21.23 Page 39
 M1004204/M1008204/M1016204 M3004204/M3008204/M3016204

Table 32: 3.0V DC Characteristics

3.0V Device (2.7V-3.6V)
Parameter Symbol Test Conditions
Minimum Typical Maximum Units

Read Current (1-1-1) SDR IREAD1 - 8 9 mA

VCC = 3.6V, IOUT=0mA,
Read Current (2-2-2) SDR IREAD2 CLK=54MHz (VIL / VIH), - 9 10 mA
CS#= VIL, SI= VIL or VIH
Read Current (4-4-4) SDR IREAD3 - 10 12 mA
Read Current (1-1-1) SDR IREAD4 - 13 15 mA
VCC = 3.6V, IOUT=0mA,
Read Current (2-2-2) SDR IREAD5 CLK=108MHz (VIL / VIH), - 15 17 mA
CS#= VIL, SI= VIL or VIH
Read Current (4-4-4) SDR IREAD6 - 19 21 mA
Read Current (1-1-1) DDR IREAD7 - 13 18 mA
VCC = 3.6V, IOUT=0mA,
Read Current (2-2-2) DDR IREAD8 CLK=54MHz (VIL / VIH), - 20 24 mA
CS#= VIL, SI= VIL or VIH
Read Current (4-4-4) DDR IREAD9 - 23 28 mA
Write Current (1-1-1) SDR IWRITE1 - 14 16 mA
VCC = 3.6V, IOUT=0mA,
Write Current (2-2-2) SDR IWRITE2 CLK=54MHz (VIL / VIH), - 17 20 mA
CS#= VIL, SI= VIL or VIH
Write Current (4-4-4) SDR IWRITE3 - 22 25 mA
Write Current (1-1-1) SDR IWRITE4 - 22 28 mA
VCC = 3.6V, IOUT=0mA,
Write Current (2-2-2) SDR IWRITE5 CLK=108MHz (VIL / VIH), - 25 32 mA
CS#= VIL, SI= VIL or VIH
Write Current (4-4-4) SDR IWRITE6 - 38 45 mA
Write Current (1-1-1) DDR IWRITE7 - 15 25 mA
VCC = 3.6V, IOUT=0mA,
Write Current (2-2-2) DDR IWRITE8 CLK=54MHz (VIL / VIH), - 20 30 mA
CS#= VIL, SI= VIL or VIH
Write Current (4-4-4) DDR IWRITE9 - 30 45 mA
Ta = 25⁰C - 160 - µA
VCC = 3.6V, CLK=VCC,
Standby Current ISB Ta = 85⁰C - - 400 µA
CS#=VCC, SI=VCC
Ta =105⁰C - - 600 µA
Deep Power Down Current IDPD VCC = 3.6V, CLK=VCC, CS#=VCC, SI=VCC - 5 25 µA
Hibernate Current IHBN VCC = 3.6V, CLK=VCC, CS#=VCC, SI=VCC - 0.1 - µA
Input Leakage Current ILI VIN=0 to VCC (max) - - ±1.0 µA
Output Leakage Current ILO VOUT=0 to VCC (max) - - ±1.0 µA
Input High Voltage VIH 0.7xVCC - VCC+0.3 V
Input Low Voltage VIL -0.3 - 0.3xVCC V
IOH = -100µA VCC-0.2 - - V
Output High Voltage Level VOH
IOH = -1mA 2.4 - - V
IOL = 150µA - - 0.2 V
Output Low Voltage Level VOL
IOL = 2mA - - 0.4 V

Feb.21.23 Page 40
 M1004204/M1008204/M1016204 M3004204/M3008204/M3016204

Table 33: 1.8V DC Characteristics

1.8V Device (1.71V-2.0V)
Parameter Symbol Test Conditions
Minimum Typical Maximum Units

Read Current (1-1-1) SDR IREAD1 - 5 8 mA

VCC = 2.0V, IOUT=0mA,
Read Current (2-2-2) SDR IREAD2 CLK=54MHz (VIL / VIH), - 6 9 mA
CS#= VIL, SI= VIL or VIH
Read Current (4-4-4) SDR IREAD3 - 7 11 mA
Read Current (1-1-1) SDR IREAD4 - 8 12 mA
VCC = 2.0V, IOUT=0mA,
Read Current (2-2-2) SDR IREAD5 CLK=108MHz (VIL / VIH), - 9 13 mA
CS#= VIL, SI= VIL or VIH
Read Current (4-4-4) SDR IREAD6 - 12 17 mA
Read Current (1-1-1) DDR IREAD7 - 11 14 mA
VCC = 2.0V, IOUT=0mA,
Read Current (2-2-2) DDR IREAD8 CLK=54MHz (VIL / VIH), - 17 20 mA
CS#= VIL, SI= VIL or VIH
Read Current (4-4-4) DDR IREAD9 - 21 25 mA
Write Current (1-1-1) SDR IWRITE1 - 13 15 mA
VCC = 2.0V, IOUT=0mA,
Write Current (2-2-2) SDR IWRITE2 CLK=54MHz (VIL / VIH), - 16 19 mA
CS#= VIL, SI= VIL or VIH
Write Current (4-4-4) SDR IWRITE3 - 20 23 mA
Write Current (1-1-1) SDR IWRITE4 - 20 26 mA
VCC = 2.0V, IOUT=0mA,
Write Current (2-2-2) SDR IWRITE5 CLK=108MHz (VIL / VIH), - 23 30 mA
CS#= VIL, SI= VIL or VIH
Write Current (4-4-4) SDR IWRITE6 - 36 43 mA
Write Current (1-1-1) DDR IWRITE7 - 13 23 mA
VCC = 2.0V, IOUT=0mA,
Write Current (2-2-2) DDR IWRITE8 CLK=54MHz (VIL / VIH), - 19 28 mA
CS#= VIL, SI= VIL or VIH
Write Current (4-4-4) DDR IWRITE9 - 28 43 mA

Ta = 25⁰C - 140 - µA
VCC = 2.0V, CLK=VCC,
Standby Current ISB Ta = 85⁰C - - 350 µA
CS#=VCC, SI=VCC
Ta=105⁰C - - 500 µA
Deep Power Down Current IDPD VCC = 2.0V, CLK=VCC, CS#=VCC, SI=VCC - 4 20 µA
Hibernate Current IHBN VCC = 2.0V, CLK=VCC, CS#=VCC, SI=VCC - 0.1 - µA
Input Leakage Current ILI VIN=0 to VCC (max) - - ±1.0 µA
WP# Leakage Current IWP#LI VIN=0 to VCC (max) -100.0 - +1.0 µA
Output Leakage Current ILO VOUT=0 to VCC (max) - - ±1.0 µA
Input High Voltage VIH 0.7xVCC - VCC+0.3 V
Input Low Voltage VIL -0.3 - 0.3xVCC V
IOH = -100µA VCC-0.2 - - V
Output High Voltage Level VOH
IOH = -1mA 1.5 - - V
IOL = 150µA - - 0.2 V
Output Low Voltage Level VOL
IOL = 2mA - - 0.4 V

Feb.21.23 Page 41
 M1004204/M1008204/M1016204 M3004204/M3008204/M3016204

Absolute Maximum Ratings

Stresses greater that those listed may cause permanent damage to the device. This is a stress rating only. Exposure to
maximum rating for extended periods may adversely affect reliability.

Table 34:Absolute Maximum Ratings

Parameter Minimum Maximum Units

Magnetic Field During Write --- 24000 A/m

Magnetic Field During Read --- 24000 A/m

Junction Temperature --- 125 °C

Storage Temperature -55 to 150 °C

Supply Voltage Vcc relative to Vss -0.5 4.0 V

Voltage on any pin -0.5 Vcc + 0.4 V

DC output current Iout ± 20 mA

ESD HBM (Human Body Model)

≥ |2000 V| V
ANSI/ESDA/JEDEC JS-001-2017

ESD CDM (Charged Device Model)

≥ |500 V| V
ANSI/ESDA/JEDEC JS-002-2018

Latch-Up (I-test)
≥ |100 mA| mA
JESD78

Latch-Up (Vsupply over-voltage test)

Passed ---
JESD78

Table 35: AC Test Conditions

Parameter Value
Input pulse levels 0.0V to VCC
Input rise and fall times 3.0ns
Input and output measurement timing levels VCC/2
Output Load CL = 30.0pF

Feb.21.23 Page 42
 M1004204/M1008204/M1016204 M3004204/M3008204/M3016204

14.1 CS# Operation & Timing

Figure 30: CS# Operation & Timing

CS#
tCS
tCSS
tCSH

CLK

tCSS

Table 36: CS# Operation

Parameter Symbol Minimum Maximum Units
Clock Frequency fCLK 1 108 (SDR) MHz
Clock Low Time tCL 0.45 * 1/ fCLK - ns
Clock High Time tCH 0.45 * 1/ fCLK - ns
Chip Deselect Time after Read Cycle tCS1 20 - ns
Chip Deselect Time after Register Write Cycle1 tCS2 5 - µs
Chip Deselect Time after Write Cycle (SPI) tCS3 280 - ns
Chip Deselect Time after Write Cycle (DPI) tCS4 350 - ns
Chip Deselect Time after Write Cycle (QPI) tCS5 490² - ns
CS# Setup Time (w.r.t CLK) tCSS 5 - ns
CS# Hold Time (w.r.t CLK) tCSH 4 - ns
Notes:
Power supplies must be stable
1:SDR operation only
2:For single byte operations, tCS5 is 280ns

Feb.21.23 Page 43
 M1004204/M1008204/M1016204 M3004204/M3008204/M3016204

Command, Address, XIP and Data Input Operation & Timing

Figure 31: SDR Command, Address and Data Input Operation & Timing

CS#

tCSS

CLK

tSU tHD

SI New Data

Don’t
Care

Table 37: SDR Command, Address, XIP, and Data Input Operation & Timing
Parameter Symbol Minimum Maximum Units
Data Setup Time (w.r.t CLK) tSU 2.0 - ns
Data Hold Time (w.r.t CLK) tHD 3.0 - ns
Notes:
Power supplies must be stable

Figure 32: DDR Command, Address and Data Input Operation & Timing

CS#

tCSS

CLK

tSU tHD tSU tHD

SI New Data 1 New Data 2

Don’t
Care

Table 38: DDR Command, Address, XIP, and Data Input Operation & Timing
Parameter Symbol Minimum Maximum Units
Data Setup Time (w.r.t CLK) tSU 4.0 - ns
Data Hold Time (w.r.t CLK) tHD 4.0 - ns
Notes:
Power supplies must be stable

Feb.21.23 Page 44
 M1004204/M1008204/M1016204 M3004204/M3008204/M3016204

14.2 Data Output Operation & Timing

Figure 33: SDR Data Output Operation & Timing

CS#

tCSS tCSH

CLK

tOH tHZCS
tCO

High-Z
SO New Data x
tCLZ
Don’t
Care

Table 39: SDR Data Output Operation & Timing

Parameter Symbol Minimum Maximum Units
CLK Low to Output Low Z (Active) tCLZ 0 - ns
Output Valid (w.r.t CLK) tCO - 7.0 ns
Output Hold Time (w.r.t CLK) tOH 1.0 - ns
Output Disable Time (w.r.t CS#) tHZCS - 7.0 ns
Notes:
Power supplies must be stable

Figure 34: DDR Data Output Operation & Timing

CS#

tCSS

CLK

tOH tOH tHZCS

tCO

High-Z
SO New Data 1 New Data 2 X

tCLZ
Don’t
Care

Table 40: DDR Data Output Operation & Timing

Parameter Symbol Minimum Maximum Units
CLK Low to Output Low Z (Active) tCLZ 0 - ns
Output Valid (w.r.t CLK) tCO - 7.0 ns
Output Hold Time (w.r.t CLK) tOH 1.0 - ns
Output Disable Time (w.r.t CS#) tHZCS - 6.0 ns
Notes:
Power supplies must be stable

Feb.21.23 Page 45
 M1004204/M1008204/M1016204 M3004204/M3008204/M3016204

14.3 WP# Operation & Timing

Figure 35: WP# Operation & Timing

CS#

WP#
tWPSU tWPHD

Table 41: WP# Operation & Timing

Parameter Symbol Minimum Maximum Units
WP# Setup Time (w.r.t CS#) tWPSU 20 - ns
WP# Hold Time (w.r.t CS#) tWPHD 20 - ns
Notes:
Power supplies must be stable

JEDEC Reset Operation & Timing

Figure 36: JEDEC Reset Operation & Timing

Device Fully
Operational

1 2 3 4
CS#

tCSL tCSH

CLK

SI

Device
Reset

Table 42: JEDEC Reset Operation & Timing

Parameter Symbol Minimum Maximum Units
CS# Low Time tCL 1.0 - µs
CS# High Time tCH 1.0 - µs
SI Setup Time (w.r.t CS#) tSU 5.0 - ns
SI Hold Time (w.r.t CS#) tHD 5.0 - ns
JEDEC Hardware Reset tRESET - 450.0 µs
Software Reset1 tSRST - 50.0 µs
Notes:
Power supplies must be stable
1: Software Reset timing is for Instruction based Reset (SRST)

Feb.21.23 Page 46
 M1004204/M1008204/M1016204 M3004204/M3008204/M3016204

Enter Deep Power Down Command (EDP – B9h)

The command sequences are shown below. Executing the Enter Deep Power down (EDP) command is the only way to put the
device in the deep power down mode. The device consumption drops to IDP.

The deep power down mode subsequently reduces the standby current from ISB to IDP. No other command must be issued while
the device is in deep power down mode.

To enter the deep power down mode, CS# is driven low, following the enter deep power down (EDPD) command, CS# must be
driven high after the eighth bit of the command code has been latched in or the EDP command will not be executed. After CS# is
driven high, it requires a delay of tEDPD (Table 6 and 7) before the supply current is reduced to IDP and the Deep Power Down mode
is entered. The command can be issued in SPI, DPI or QPI modes.

CS#
tEDPD
0 1 2 3 4 5 6 7

CLK

Command (ABh)

SI(I/O0) X 1 0 1 0 1 0 1 1 X

MSB LSB Deep Power Down Standby

High Z
SO(I/O1)

Figure 37: Enter Deep Power Down in SPI Command Sequence

CS#
tEDPD
0 1 2 3

CLK

Command (B9h)

High Z High Z
SI(I/O0) 0 1 0 1

LSB Standby Mode Deep Power Down Mode

High Z High Z
SO(I/O1) 1 1 1 0

MSB

Figure 38: Enter Deep Power Down in DPI Command Sequence

CS#
tEDPD
0 1

CLK

Command
(B9h)
High Z High Z
SI(I/O0) 1 1

LSB

High Z High Z
SO(I/O1) 1 0

High Z High Z
WP#(I/O2) 0 0

Standby Deep Power Down

High Z High Z
I/O3 1 1

MSB

Figure 39: Enter Deep Power Down in QPI Command Sequence

Feb.21.23 Page 47
 M1004204/M1008204/M1016204 M3004204/M3008204/M3016204

Exit Deep Power Down Command (EXDPD - ABh)

The command sequences are shown below. There are two ways to exit deep power down mode:
1. Toggling CS# with a CS# pulse width of tCSDPD while CLK and I/Os are Don’t Care. During waking up from deep power
down, I/Os remain to be in high Z.

2. Driving CS# low follows with the Exit Deep Power Down (EXDPD) command. CS# must be driven high after the eight bit
of the command code has been latched in or the EXDPD command will not executed.

tEXDPD

tCSDPD
CS# Standby
Deep Power Down

CLK

High Z
I/Os X

Figure 41: Exit Deep Power Down by Toggling CS#

CS#
tEXDPD
0 1 2 3 4 5 6 7

CLK

Command (B9h)

SI(I/O0) X 1 0 1 1 1 0 0 1 X

MSB LSB Standby Deep Power Down

High Z
SO(I/O1)

Figure 40: Exit Deep Power Down in SPI Command Sequence

It requires a delay of tEXDPD (Table 6 and 7) before the device can fully exit the deep power down mode and enter standby mode.
The command can be issued in SPI, DPI, and QPI mode. Status of all non-volatile bits in registers remains unchanged when the
SPnvSRAM enters or exits the deep power down mode.

CS#
CS#
tEXDPD
tEXDPD 0 1
4 5 6 7 CLK
CLK
Command
(ABh)
High Z High Z
Command (ABh) SI(I/O0) 0 1

High Z High Z LSB

SI(I/O0) 0 0 0 1
High Z High Z
SO(I/O1) 1 1
LSB Deep Power Down Standby

High Z High Z WP#(I/O2) High Z High Z

SO(I/O1) 0 1 1 1 0 0

MSB Deep Power Down Standby

High Z High Z
I/O3 1 1

MSB

Figure 42: Exit Deep Power Down in DPI

Command Sequence Figure 43: Exit Deep Power Down in QPI
Command Sequence

Feb.21.23 Page 48
 M1004204/M1008204/M1016204 M3004204/M3008204/M3016204

Enter Hibernate Command (EHBN – BAh)

The command sequences are shown below. Executing the Enter Hibernate command is the only way to put the device in the
hibernate mode. The device drops down to the lowest power consumption mode: IHBN. When in hibernate mode, the CLK and SI
pins are ignored and SO will be high-Z.

To enter the hibernate mode, CS# is driven low, following the Enter Hibernate (EHBN) command. After CS# is driven high, it
requires a delay of tENTHIB time (Table 6 and 7) before the supply current is reduced to IHBN and the hibernate mode is entered.

Toggling CS# (low to high) will return the SPnvSRAM to standby mode. The command can be issued in SPI, DPI, and QPI modes.

CS#
tENTHIB
0 1 2 3 4 5 6 7 0 1 2

CLK

Command (BAh) tEXHIB

SI(I/O0) X 1 0 1 1 1 0 1 0
Enter Hibernate Mode
MSB LSB Exit Hibernate
Hibernate

SO(I/O1) High Z

Figure 44: Enter Hibernate in SPI Command Sequence

CS#
tENTHIB
0 1 2 3

CLK

Command (BAh)

High Z High Z
SI(I/O0) 0 1 0 0

LSB Standby Mode Hibernate Mode

High Z High Z
SO(I/O1) 1 1 1 1

MSB

Figure 45: Enter Hibernate in DPI Command Sequence

CS#
tENTHIB
0 1

CLK

Command
(BAh)
High Z High Z
SI(I/O0) 1 0

LSB

High Z High Z
SO(I/O1) 1 1

High Z High Z
WP#(I/O2) 0 0

Standby Hibernate

High Z High Z
I/O3 1 1

MSB

Figure 46: Enter Hibernate in QPI Command Sequence

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 M1004204/M1008204/M1016204 M3004204/M3008204/M3016204

15. Thermal Resistance

Table 43: Thermal Resistance

Parameter Description Test Conditions 8-pad DFN 8-pin SOIC Unit
(WSON)
θJA Thermal resistance Test conditions follow 43.67 53.59 oC/W

(junction to ambient) standard test methods and

θJC Thermal resistance procedures for measuring 18.54 4.29
(junction to case) thermal impedance, per
EIA/JESD51
Notes:
1: These parameters are guaranteed by characterization; not tested in production.

Feb.21.23 Page 50
 M1004204/M1008204/M1016204 M3004204/M3008204/M3016204

16. Revision History

Revision Date Description of Change
Apr.16.20 Initial release.
Feb.25.21 Update to the Endurance and Electrical parameters. Thermal Resistance table added to the
datasheet. Revise various tables including Tables 22, 31, 32, 33, 34, 36 and 43.
Mar.18.22 Added REACH compliant to features and updated Absolute Maximum Ratings table.
Feb.21.23 Removed Performance table
Updated Signal Description table
Updated Power-Up Behavior diagram
Updated Power-Down/Power-Up description
Updated Power-Down and Brown-out Behavior diagram
Added VCC Ramp Up Time (max)
Added VCC-RST parameters
Updated SDR and DDR Data Output Operation & Timing diagrams

Feb.21.23 Page 51
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