Embedded Systems Design I

Unit 1: AVR Architecture

GIDEON, K. (2023) EMBEDDED SYSTEMS DESIGN I 1

 Microcontroller Basics
• Microcontroller
o A small computer on a single chip
o Has limited amounts of data and program memory
o Contains program in non-volatile memory e.g. ROM, or flash memory
o Designed to begin operating as soon as it is powered.
o Examples
• PIC series,
• Atmel AVR series, etc.
• Our focus:
o Atmel AVR Atmega32, an 8 bit microcontroller.

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 Microcontroller Architectures

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 AVR ATmega32 Architecture
Three Memories:
• Program memory = 32K Flash
o For code or constant data
o Addressed with 15 bits
o (PC is 16 bit wide)
• Data memory:(volatile variables)
o 32 General purpose registers
o 64 IO register
o 2K SRAM
• EEPROM
o 1K constant non-volatile data
o Accessed through I/O space
o Requires 10 bit address width

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 AVR MEMORY

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 AVR Program Memory
• 32 Kilobytes On-chip In-
System Re-programmable
Flash memory
• 16 bit word size
• Organized as 16k x 16
• Non-volatile
• Stores the executable
program opcodes and static
data tables.
• Can be reprogrammed by
user at least 10,000 times

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 AVR Data Memory
• Data Address space includes:
o 32 x 8 General purpose registers
o Six can be used as 16 bit pointers
• X = R26:R27,
• Y = R28:29,
• Z = R30:R31)
o 64 x 8 I/O registers
• Mapped to IO devices (i.e.,
PORTS)
o 2K x 8 of SRAM (2048)
• Actual usable SRAM starting at
006016
o Byte addressable
• Total data address space =
0x0000 – 0x085F
• Volatile

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 AVR EEPROM & Fuse Bits
• EEPROM
o non-volatile data storage
o Not directly mapped in either the program or data space
o Accessed indirectly as a peripheral, using I/O regisers
o Can be reliably re-written a maximum of 100,000 times
o AVRs ship from the factory with the EEPROM erased, i.e. the value in
each byte of EEPROM is FF16
• FUSE bits
o A Fuse is an EEPROM bit that controls low level features, pin
assignments, CPU clock frequency etc.
o Only modifiable by a programmer (e.g. AVRASP) not through code
• e.g. AVRDUDE

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 ATmega32 Main Features
• 32x8 fast access general purpose working registers
o All 32 registers are directly connected to the ALU
• RISC based (Reduced Instruction Set Computer) as opposed to CISC.
• 32K bytes of In-System Programmable Flash Program memory
• 1024 bytes EEPROM
• 2K byte data SRAM
• 32 general purpose I/O lines
• Two 8-bit Timer/Counters and One 16-bit Timer/Counter
• Internal and External Interrupts
• 8-channel, 10-bit ADC
• Communication: Serial programmable USART, Master/slave SPI interface, I2C interface.
• Six software selectable power saving modes
• Programmable Watchdog Timer with Internal Oscillator
• On-chip Boot program used to download application flash memory.
• 4.5 – 5.5 V for Atmega32 and 2.7 – 5.5 V for Atmega32L and Atmega32A

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 ATmega32 Block Diagram

Pin Configuration

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 ATmega32
• AVR CPU
o AVR uses Harvard architecture
o with separate memories and buses for program and data.
o CPU employs single level pipelining
• Main function is to ensure proper code execution:
o Fetches instructions from program memory and data from data
memory.
o Decodes program instructions
o Executes program instructions i.e. calculations, peripheral control, and
interrupts handling.
• Program Memory (In-System programmable Flash memory)
o Stores program instructions
o Non-volatile flash memory

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 Status Register (SREG)
• 8 bits contains information about the result of the most recently
executed arithmetic and logic instruction
• Updated after every ALU operation.
• NOT automatically stored when entering an interrupt routine or
restored when returning from an interrupt.

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 Status Register (SREG)

• Bit 7 – I: Global Interrupt Enable

o Set to enable all interrupts; cleared to disable all interrupts.
o Cleared by hardware after interrupt has occurred.
o Set by RETI instruction to enable subsequent instructions.
o Can also be set using SEI and cleared using CLI instructions
• Bit 6 – T: Bit Copy Storage
o Used by the bit copy instructions as source and destination for the
operated bit
o Bit copy instructions are: BLD (Bit Load – copies register bit to T) and
BST (Bit Store - stores T bit in register)
• Bit 5 – H: Half Carry Flag
o indicates that a a carry from lower nibble occurred. Useful information
for some arithmetic operations (e.g. BCD)
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 Status Register (SREG)

• Bit 4 – S: Sign Bit, S = N⊕V

o This is an XOR result between the Negative Flag N and the Two’s
Complement Overflow Flag V
• Bit 3 – V: Two’s Complement Overflow Flag
o Provides supports for two’s complement arithmetics.
• Bit 2 – N: Negative Flag
o Indicates a negative result in an arithmetic or logic operation
• Bit 1 – Z: Zero Flag
o Indicates a zero result in an arithmetic or logic operation
• Bit 0 – C: Carry Flag
o Indicates a carry in an arithmetic or logic operation
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 General Purpose Registers File
• 32 x 8 fast-access general
purpose registers
• Most general purpose
instructions have direct access
• Most instructions are single
cycle instructions
• Each register is also assigned a
data memory address

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 General Purpose Registers File
• Registers
o X (R26, R27), Y (R28, R 29), and Z(R30, R 31)
• Used as 16 bit address pointers for indirect access of data
space.

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 Stack Pointer
• A stack is a LIFO memory (also called a PUSH-DOWN stack)
• 16 bit long implemented using two 8-bit registers
• Used for storing temporary data, local variables and return
addresses after interrupts and subroutine calls.
• Points to the data SRAM Stack area where the subroutine and
interrupt stacks are located.
• Always points to the top of the Stack.
• Decremented by one when data is pushed onto the Stack with the
PUSH instruction; incremented by one when data is popped
• Decremented by two when the return address is pushed onto the
stack with subroutine call or interrupt;
• Incremented by two when address is popped from the Stack with
return from subroutine RET or return from interrupt RETI

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 I/O Ports
• DDRx (where x = A,B,C or D) • PINx (where x = A,B,C or D)
o Used to set terminal as either an o Data put on the corresponding
input or output terminal from the outside world
o A “1” in a specific bit sets the appear in this register if DDRx is
corresponding physical terminal as set as input)
an output. • The terminals can be in other
o A “0” in a specific bit sets the state e.g. Tri-state (Hi-Z etc)
corresponding physical terminal as using the SFIOR in conjunction
an input.
with DDRxn and PORTxn as
• PORTx (where x = A,B,C or D) below.
o Data put in this register by the
MCU will appear on the terminal if
DDRx is set as output)

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