Calibre® 3DSTACK Quick Reference

Software Version 2020.2

2020

Command Line Invocation 4. Set up the Internal Schematic Viewer to display source and
layout netlists as follows:
calibre -3dstack { [-help] [-turbo [number_of_processors] ] o Choose Setup > Options and click Schematic Viewer.
[-system {GDS | OASIS}] [{-create_assembly assembly_name} o Enable Show netlist schematics when highlighting
| {-use_assembly assembly_path} | -cs ] rule_file_name connectivity objects.
[-run_dir directory] [-compile_only]
o Enable Schematic, Hierarchy and Text and click Apply.
Calibre Interactive 3DSTACK 5. Choose View > Schematics > All.
Launch Calibre Interactive 3DSTACK, use this command:
calibre -gui -3dstack [-runset runset_file] Cross-Reference Database Results in Calibre RVE
Launch Calibre Interactive 3DSTACK from Calibre DESIGNrev:
Verification > Run 3DSTACK
Calibre 3DSTACK Output Files
The following output files are created in your working directory:
3dstack_assembly.gds.gz — assembled view of the chip stack.
3dstack_assembly.gds.gz.layerprops — layer properties file.
3dstack_assembly.gds.gz.layermap — SVRF layer definitions
generated from the assembly process.
3dstack_cross_section.gds.gz — x, y, and z view of your stack.
3dstack_cross_section.gds.gz.layerprops— layer properties file
3dstack_overlay_generator.tcl — a Tcl script used to generate
the chip stack layout view from the individual layouts. Click on the layout net and source
3dstack.rdb — RDB file containing analysis results. RDB files are net icons to highlight them in the
also created for each layout file in the chip stack. Internal Schematic Viewer. The
layout net is also highlighted in the
3dstack.dfmdb (directory) — DFMDB analysis results. layout viewer.
<3dstack+_rules>.3dstack — compiled 3DSTACK+ rule file.
3dstack.log — transcript of the complete run.
3dstack.warnings — collection of all warnings issued by the run.
readerprefs — saved exception settings.
Browse 3DSTACK Results in Calibre RVE
Calibre RVE highlights Calibre 3DSTACK results to the associated
geometry in the layout viewer.
Enter the following command to open the results in Calibre RVE:
calibre -rve 3dstack.rdb
Database Results Browsing with Calibre RVE
The highlight button ( ) in the highlight toolbar browses directly
to the result in the layout viewer.
Click Schematic Nets to Highlight the Layout Geometry

3DSTACK+ Command Reference

Opening a 3DSTACK DFMDB in Calibre RVE The 3DSTACK+ command file defines the physical assembly of a
Cross-referencing between source and layout is supported in 3D or 2.5D IC. It follows these formatting and syntax rules:
Calibre RVE if a source netlist is specified at runtime. • The file must consist only of Calibre 3DSTACK commands and
1. Open 3dstack_assembly.gds.gz in a supported layout editor. standard Tcl constructs.
2. Start Calibre RVE from the layout editor’s interface: • The file must begin with the following two statements:
o Calibre DESIGNrev — Verification > Start RVE. #!3dstack+
o Other supported layout viewers — Calibre > Start RVE. set_version -version 1.0
3. In the Calibre RVE dialog box, select DFM database and enter • The assembly commands are die, config, and stack.
the path to your 3dstack.dfmdb database. • All distances are specified in microns.

Unpublished work. © Siemens 2020

 config and process Commands Rule Check Commands
Specifies system configuration and control options for the run. The extended Calibre 3DSTACK syntax supports the standard set
config [-layout_primary name] [-layer_props_file props_file] of verification commands with additional layer options.
[-netlist ‘{’-file file_name -format {SPICE | VERILOG version | CSV The following options apply to geometrical rule check commands:
| MGC} [-case {YES | NO}] [-hier [-wrap name]] ‘}’] [-order {list}] [-comment “comment”] [rve_option …]
[-subckt_pins {type}] [-apply_bboxing cell_list]
centers -check_name check_name
[-report ‘{’-file report_path [-max_results value]
-placement1 placed_layer1 [-placement2 placed_layer2]
[-child_rdbs {NO | YES }] -report_ignored_pins {NO | YES} ‘}’]
-constraint “constraint_value” [-overlapping]
[-ignore_trailing_chars char_list] [-layout_case {no | yes}]
[-alignment {octagonal_only | orthogonal_only }] [-square]
[-export_connectivity ‘{’-file output_file [-format {VERILOG | AIF
| MGC | SPICE | XSI }] … connected -check_name check_name {{-layer_type1 layertype
[-pin_map -pins pins -to name] [-import_pin_map -file file] [-layer_type2 layertype]} | {-die1 die {[-standalone] | [-die2 die}}
[-net_map -nets nets -to name] [-import_net_map -file file] [-black_box | -white_box] [-net_mismatch {ALL | MULTI_NAME |
[-svrf_spec svrf_file] [-set_rve_cto_file cto_file] MISMATCH | MISSING_NAME}] [-no_dangling_ports]
[-set_auto_rve_show_layers {NO | YES}] [-units [-distance {um [-no_extra_ports] [-no_missing_ports] [-isolate_path]
| mm | nm}] [-power {W | mW | uW}] [-time {s | hr | min | ms | us}]] [-pin_list pins_to_report]
process process_layer_information copy -check_name check_name -layer_type placed_layertype
die Command custom_check -check_name check_name
[-stack stack_list ] [-direction {up | down | both}]
Specifies information about a single die in the assembly.
die -die_name die_name -layer_type1 ‘{’ placed_layer_type1… [-merge] ‘}’
{-layout ‘{’ -path layout_path [-type {gdsii | oasis}] [-layer_type2 ‘{’ placed_layer_type2 … [-merge] ‘}’ ]
[-primary primary_name] [-depth {all | top-only}] -tvf ‘{’ tvf_body ‘}’
[-precision value]‘}’
| {-lefdef ‘{’ -lef tech_lef [lef_file …] -def def_file ‘}’ } { dangling_ports | extra_ports | missing_ports }
-check_name check_name -layer_types layer_types_list
[-thickness die_thickness]
-process name | {-layer_info ‘{’ -type type -name name density -check_name check_name
{-layer ‘{’ layer_numbers [-depth {all | top-only}] ‘}’ -layer_types {placed_layertype …}
[-expression “density_expression”] -constraint “expression”
| -svrf ‘{’ layer_derivation ‘}’ [-show]
[-window {wxy | wx wy} [-step {sxy | sx sy}] ]
[-text ‘{’ layer_numbers [-depth {number ...}] [-no_update]
[-window_type {truncate | backup | ignore | wrap}]
| [-net_text layers] | [-trace_text] ‘}’ [-pex_map layer_name]
[-ext_connect die_name ...] [-icrx -file file | -mipt -file file] [-inside { extent | placed_layer }] [-centers value]
[-rc_model] [-top | -bottom] [-virtual] [-via] } … enclosure -check_name check_name -placement1 placement1
‘}’ } … [-placement2 placement2] -constraint “constraint_value”
[-anchor ‘{’-name anchor_name {-placement x_offset y_offset external -check_name check_name {-layer_type1
| -layer number -text label}‘}’] … placed_layertype [-layer_type2 placed_layertype]} -constraint
[-interposer | -package | -laminate | -substrate] “constraint_value”
[-import_text_labels file {xsi_args}] [-rename_text “expression ...”] floating_pads -check_name name -layer_type layer_type
[-wb_connect layer1 layer2 [BY layer3] [-use_in_svrf]] { floating_texts | multi_texts | no_texts }
component Command -check_name check_name -layer_types layer_types_list
Allows you to define objects in your assembly that are not dies. The syntax is the { floating_trace | multi_trace | no_trace }
same as die with one additional option (-swappable). -check_name check_name -layer_types layer_types_list
component -component_name name internal -check_name check_name
{ die_command_options … [-swappable pin_list] } {-layer_type1 placed_layertype [-layer_type2 placed_layertype]}
-constraint “constraint_value”
stack Command
locations -check_name check_name
Defines the locations of dies and stacks of dies in an assembly. {-layer_type1 placed_layertype [-layer_type2 placed_layertype]}
stack -stack_name name {die_stack | tier_spec | stack_ref }… [-constraint “constraint_value” ] [-text_only | -overlap_only]
die_stack Usage [-direction {both | up | down} | {both | direct | reverse}]]
stack -stack_name stack_name offgrid_centers -check_name check_name
-layer_type placed_layertype -resolution {resolution_value |
{die_stack | tier_spec | stack_ref }…
x_resolution_value y_resolution_value } [-hint]
-die | -component | -package | -laminate | -substrate
overlap -check_name check_name -placement1 placed_layer1
‘{’ -name die_name
{ -layer_type placed_layertype [placed_layertype] } -constraint
[-anchor die_anchor_name from_anchor_name to_anchor_name “constraint_expression” [by_area] [-intersection]
| -placement location] [-mag factor] [-rotate angle] [-flip {x | y}] [-invert] [-
select_checks { -check_names ‘{’chk_pattern [chk_pattern…]‘}’
rename_text “expression” …]
| -placements ‘{’place_pattern [place_pattern …] ‘}’ }
[-ignore_pin “expression” …] [-source source_name]
[-check_types ‘{’check_type …‘}’]
‘}’ [-z_origin vertical_height]
unselect_checks { -check_names ‘{’chk_name [chk_name …]‘}’
tier_spec Usage | -placements ‘{’placement_pattern [placement_pattern …] ‘}’ }
stack -tier ‘{’ {die_stack | stack_ref }…‘}’ [-check_types ‘{’check_type …‘}’]
stack_ref Usage 3dstack_block ‘{’ body ‘}’
stack -stack stack_name ‘{’ 3dstack_cmds ‘}’— Block of standard syntax commands
Unpublished work. © Siemens 2020. This document contains information that is confidential and proprietary to Mentor Graphics Corporation, Siemens
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