ISSCC 2024

Forum 6
Toward Next Generation of Highly Integrated
Electrical and Optical Transceivers
 Forum 6

Toward Next Generation of Highly

Integrated Electrical and Optical
Transceivers

International Solid State Circuit Conference

February 22nd, 2024

Presentations will start at 8:15am

ISSCC 2024 1 of 5
© 2024 IEEE
International Solid-State Circuits Conference
 Organizing Committee
❑ Hosted by the Wireline and TD Subcommittees

❑ Organizers: Mozhgan Mansuri, Intel, Hillsboro, OR

Jay Im, AMD, San Jose, CA

❑ Co-Organizers: Didem Turker Melek, Cadence Design Systems, San Jose, CA

Masum Hossain, Carleton University, Ottawa, Canada
Peter Ossieur, Imec, University of Ghent, Ghent, Belgium
Sudip Shekhar, University of British Columbia, Vancouver, Canada
Tamer Ali, Mediatek, Irvine, CA

❑ Champions: Bill Redman-White, HiLight Semiconductor, Southampton, United Kingdom

Yohan Frans, AMD, San Jose, CA
ISSCC 2024 - Forum 6: Toward Next Generation of Highly Integrated Electrical 2 of 5
© 2024 IEEE and Optical Transceivers
International Solid-State Circuits Conference
 Forum Abstract
 The next generation of highly integrated transceivers for high
throughput applications poses significant design challenges in terms of power
efficiency, signal integrity, ISI and noise cancellation. This forum discusses
the key issues for deploying 100G+ SERDES and design approaches for
200G+, including noise mitigation, power efficient analog/digital equalization
schemes (CTLE, analog FFE, DSP FFE/DFE/MLSD), modulation, and system
integration (packaging, connectors, etc).

 Optical transceivers also play a crucial role in extending the reach of

electrical interconnects as data rates continue to increase. Various aspects of
optical transceivers based on silicon photonics are discussed, such as foundry
perspectives, directly modulated vs coherent optical links, packaging
techniques and fiber termination challenges. In addition, the forum covers
emerging technologies including co-packaged optics and heterogenous
integration of both photonic and electronic chiplets, promising denser
integration while introducing new challenges.
ISSCC 2024 - Forum 6: Toward Next Generation of Highly Integrated Electrical 3 of 5
© 2024 IEEE and Optical Transceivers
International Solid-State Circuits Conference
 Forum Agenda
Start Title Speaker Affiliation
8:15 Introduction Mozhgan Mansuri Intel
8:25 Highlights and Challenges in Deploying 100G+ SERDES Francis Lin Mediatek
Alphawave Semi and
9:15 The Impact of Industry Trends on 200+Gbps Wireline R&D Tony Carusone
University of Toronto
10:05 Break
Beyond 200Gbps Electrical Transceivers – Circuit Architecture, Design Implementation and Silicon-
10:20 Ariel Cohen Intel
Based Results
11:10 Modulation Schemes for Ultra-High-Speed Transceivers Naim Ben-Hamida Ciena
12:00 Lunch
13:20 Silicon Photonics Based High Throughput Optical Transceivers Mayank Raj AMD
14:10 Micro-Transfer Printing for Heterogeneous Electronic-Photonic Integrated Circuits Gunther Roelkens Ghent University - imec
15:00 Break
15:15 Silicon Photonics and Foundry Requirements for AI Datacenters Tom Gray NVIDIA
16:05 Electronic-Photonic Systems-on-Chip for Compute, Communications and Sensing Vladimir Stojanovic UC Berkeley
16:55 Closing remarks Jay Im AMD

ISSCC 2024 - Forum 6: Toward Next Generation of Highly Integrated Electrical 4 of 5

© 2024 IEEE and Optical Transceivers
International Solid-State Circuits Conference
 General Information
 8 presentations

 2 coffee breaks and one lunch break

 40 minutes presentation followed by 10 minutes Q&A

 Digital copy of all slides will be provided for the forum

 Please switch your mobile device to silent mode

 Please state your name and affiliation during Q&A

 Please remember to complete speaker evaluations

ISSCC 2024 - Forum 6: Toward Next Generation of Highly Integrated Electrical 5 of 5

© 2024 IEEE and Optical Transceivers
International Solid-State Circuits Conference
 Highlights and Challenges
in deploying 100G+ SERDES

Francis Lin
MediaTek Inc.

ISSCC 2024 - Forum 6.1: Highlights and 1 of 37

© 2024 IEEE Challenges in deploying 100G+ SERDES
International Solid-State Circuits Conference
 Outline
 Motivation

 System and Performance Target Implications

 Big Chip Problems

 SIPI Challenges and Mitigations

 Thermal

 Serdes Requirement

ISSCC 2024 - Forum 6.1: Highlights and 2 of 37

© 2024 IEEE Challenges in deploying 100G+ SERDES
International Solid-State Circuits Conference
 Motivation
 On top of designing a 100+Gbps Serdes, deploying the Serdes
has been trickier than ever as fNyq is increasing at an
unprecedented rate

 Early adopters also face the lack of guidance from developing

standards

 This study is intended to provide an overview on the challenges

outside the die, regarding deploying state of the art high speed
Serdes in hope to help expedite industry wide adoption

ISSCC 2024 - Forum 6.1: Highlights and 3 of 37

© 2024 IEEE Challenges in deploying 100G+ SERDES
International Solid-State Circuits Conference
 Increasing Challenge
 On top of designing a 100+Gbps Serdes, deploying the Serdes
has been trickier than ever as fNyq is increasing at an
unprecedented rate

[1][2]

ISSCC 2024 - Forum 6.1: Highlights and 4 of 37

© 2024 IEEE Challenges in deploying 100G+ SERDES
International Solid-State Circuits Conference
 Standard Timeline
 Early adopters also face the lack of guidance from developing
standards
802.3dj Timeline

D1.0: Comment Resolution 30~40% TBD Technical Completeness (no TBDs)

Oopsie what if I need to deploy at this point

[3]

ISSCC 2024 - Forum 6.1: Highlights and 5 of 37

© 2024 IEEE Challenges in deploying 100G+ SERDES
International Solid-State Circuits Conference
 Agenda
 Motivation

 System and Performance Target Implications

 Big Chip Problems

 SIPI Challenges and Mitigations

 Thermal

 Serdes Requirement

ISSCC 2024 - Forum 6.1: Highlights and 6 of 37

© 2024 IEEE Challenges in deploying 100G+ SERDES
International Solid-State Circuits Conference
 System Portraits
 Spec from system application scenario

Serdes Lane Count 256+ 16~64 16~64 8~16 8~16

PKG size(mm) 82 55~80 55~80 11 -
PCB layers 42 24 24 10 -
max PKG trace length (mm) 70 34 35 5 5
max PCB trace length (inches) 13~20 5 30 0.5 -
Via depth (mil) 160 120 120 6 1
Likely scenario Hi Radix switch C2M Server Board C2M Line Card C2C Transceiver Module Direct Drive Optics

[4] [5]

ISSCC 2024 - Forum 6.1: Highlights and 7 of 37

© 2024 IEEE Challenges in deploying 100G+ SERDES
International Solid-State Circuits Conference
 Channel Reach and BER performance
 112G Serdes provides robust support for High loss passive Cu links
 Will it still work in legacy system architecture?
pre FEC BER v/s/ Channel IL
150+ 224G channels investigated 1.0E-05
System A112
3.3m AWG27
1.0E-06

1.0E-07
224G C2C

BER
1.0E-08
224G CR 1mDAC
1.0E-09 224G C2M config1
System A224
224G C2M config2 Same dimension
1.0E-10 System A112 state of the art material.
1m AWG28 112G CR/KR IL(53G) -> 55.68dB
IL(26G 37dB)
1.0E-11
30 35 40 45 50 55 60
IL(dB)

ISSCC 2024 - Forum 6.1: Highlights and 8 of 37

© 2024 IEEE Challenges in deploying 100G+ SERDES
International Solid-State Circuits Conference
 Agenda
 Motivation

 System and Performance Target Implications

 Big Chip Problems

 SIPI Challenges and Mitigations

 Thermal

 Serdes Requirement

ISSCC 2024 - Forum 6.1: Highlights and 9 of 37

© 2024 IEEE Challenges in deploying 100G+ SERDES
International Solid-State Circuits Conference
 Big chip problems
 Feature and BW driven package dimension increase
◼ 1Logic + 2HBM -> exceeds 1 reticle with 400mm2 logic die
◼ Signal Fanout – pin larger package
◼ Power density – layers for power distribution
◼ Die partition / HBM – Heterogeneous integration

 Assemble reliability challenges with larger pkg

◼ Warpage, COP/Coplanarity, Si crack, UF crack

 PDN competition from adjacent high-density logics

 Thermal preheat

ISSCC 2024 - Forum 6.1: Highlights and 10 of 37

© 2024 IEEE Challenges in deploying 100G+ SERDES
International Solid-State Circuits Conference
 Mechanical Considerations
 Control Warpage, COP, UF and Si crack risk
 Low CTE(thermal expansion) thick core
 Interposer bonding Structure
Organic Substrate
CTE
12~15
 Cu density control Silicon
Organic RDL
3
4
◼ Overall density distribution
◼ C4 and non-C4 area
◼ Vertical asymmetry control
 BGA ball size & Pitch to avoid solder joint & breakage
 Via density constraint Stiffener FP

 Antipad design rule constraints

 Stiffener Ring
◼ high Young’s modulus and low CTE to avoid localized stress Si INT

◼ Adequate ring width to avoid die/interposer crack from overstress

ISSCC 2024 - Forum 6.1: Highlights and 11 of 37

© 2024 IEEE Challenges in deploying 100G+ SERDES
International Solid-State Circuits Conference
 Factors of BW preservation challenge
 Higher than desired dimensions
◼ TSV&C4 junction
◼ PKG # of layers
◼ PKG # of stacking vias
◼ PKG core thickness
◼ PKG trace length
◼ PTH via depth
◼ Via drill size, stub length
◼ BGA pitch
◼ Ball size
 Lower than desired
◼ Cu density
◼ Cu distribution flexibility
ISSCC 2024 - Forum 6.1: Highlights and 12 of 37
© 2024 IEEE Challenges in deploying 100G+ SERDES
International Solid-State Circuits Conference
 Agenda
 Motivation

 System and Performance Target Implications

 Big Chip Problems

 SIPI Challenges and Mitigations

 Thermal

 Serdes Requirement

ISSCC 2024 - Forum 6.1: Highlights and 13 of 37

© 2024 IEEE Challenges in deploying 100G+ SERDES
International Solid-State Circuits Conference
 SIPI Challenges and Mitigations
 Overall IL Improvement

 BW preservation

 Skew tunning

 Crosstalk mitigation

 Reflection mitigation

ISSCC 2024 - Forum 6.1: Highlights and 14 of 37

© 2024 IEEE Challenges in deploying 100G+ SERDES
International Solid-State Circuits Conference
 Pkg IL improvement
 PKG unit IL grows 3x or more even with updated material technology
 Thicker ABF – up to 20% improvement, impacts stiffness
 Skip Layer – cut IL below half, subject to CTE and Cu ratio constraint

ISSCC 2024 - Forum 6.1: Highlights and 15 of 37

© 2024 IEEE Challenges in deploying 100G+ SERDES
International Solid-State Circuits Conference
 BGA pitch & ball size issues
 Ground cavity resonance inside fnyq Square Hex
 Increased ball size further drops BW
 Must push the envelope!
f1 = 51GHz

Pitch & ball dia vs pkg size in mm

Pkg size BGA pitch Ball size f1 = 49GHz
55-65 0.8 0.5~0.55
65-75 0.8~1 0.6
>75 1 0.6

ISSCC 2024 - Forum 6.1: Highlights and 16 of 37

© 2024 IEEE Challenges in deploying 100G+ SERDES
International Solid-State Circuits Conference
 Breakout Style Impact
 For 112Gbps, both breakout style works at 28G
 For 224Gbps, Tx3 excites additional mode causing dips at 53GHz

D0TX3(L3) D0TX4(L3)

ISSCC 2024 - Forum 6.1: Highlights and 17 of 37

© 2024 IEEE Challenges in deploying 100G+ SERDES
International Solid-State Circuits Conference
 BGA pattern and break out style improve
 Hex pattern for cavity size shrink
 Ground fence for reduced aperture coupling

ISSCC 2024 - Forum 6.1: Highlights and 18 of 37

© 2024 IEEE Challenges in deploying 100G+ SERDES
International Solid-State Circuits Conference
 Ball pitch Ball Size Impact Mitigation
 Push resonance beyond Nyquist
◼ Via Junction Optimization
◼ low Dk Material
◼ Via pattern with shrunk cavity
◼ Break out pattern avoid stimulating mode

 Junction effect maybe improved

◼ Impedance matching
◼ Attenuation

ISSCC 2024 - Forum 6.1: Highlights and 19 of 37

© 2024 IEEE Challenges in deploying 100G+ SERDES
International Solid-State Circuits Conference
 Skew tuning
 UI time: 8.89~9.41pS, 0.3-0.4UI tolerance allocated for
◼ On-Die
1 3
◼ PKG/PCB
2 4
◼ Connector
◼ DAC/flyover/overpass cables 1.5-3ps [6]
◼ Bend/twist/temperature/humidity etc

 Skew involves
◼ PN length difference K1=S31-S42

◼ PN trace Asymmetry K2=S41-S32

 Overall Electrical Length Difference S C 2 D1 =

1
(S31 − S 42 + S 41 − S32 )
2

ISSCC 2024 - Forum 6.1: Highlights and 20 of 37

© 2024 IEEE Challenges in deploying 100G+ SERDES
International Solid-State Circuits Conference
 Skew Impact on Link Budget
 Skew impact in the form of IL and Common mode Noise
 Substantial impact above 3pS, or roughly 0.3UI

SDD21
SDC21

ISSCC 2024 - Forum 6.1: Highlights and 21 of 37

© 2024 IEEE Challenges in deploying 100G+ SERDES
International Solid-State Circuits Conference
 Skew Tolerance / tuning target
 TxVaccmrms sensitivity

 Modified SCMR for skew index

 Target mSCMR > 15dB

(𝑆𝐷𝐷21 𝑆𝐵𝑅 𝑝𝑒𝑎𝑘)2

𝑚𝑆𝐶𝑀𝑅 = 10𝑙𝑜𝑔10
𝑆𝐷𝐶21 𝑝𝑜𝑤𝑒𝑟
𝑚𝑆𝐶𝑀𝑅 (𝑑𝐵)

ISSCC 2024 - Forum 6.1: Highlights and 22 of 37

© 2024 IEEE Challenges in deploying 100G+ SERDES
International Solid-State Circuits Conference
 Skew tuning technique
 Serpentine parameters tuned per
stackup and design rule for S sensitivity
minimized Physical and Electrical T
Length Difference S

 Impedance control for tuning pattern

T sensitivity
EM diff vs T

T
160

140

S
120

100

80
60 80 100 120 140

ISSCC 2024 - Forum 6.1: Highlights and 23 of 37

© 2024 IEEE Challenges in deploying 100G+ SERDES
International Solid-State Circuits Conference
 Skew Tuning Summary
 Skew tuning with correct S/T dimensions to avoid short cut impact

 Skew tuning location choice for better common mode cancellation

 For PKG/PCB 100-150fS tuning target can be achieved

ISSCC 2024 - Forum 6.1: Highlights and 24 of 37

© 2024 IEEE Challenges in deploying 100G+ SERDES
International Solid-State Circuits Conference
 Crosstalk Considerations
 Example : Deriving crosstalk specs for the package
 System configuration
 TSV adds more challenge
 Retimed/long loss combination
 Off-board or on die chip to chip connection
 Inter Lane isolation:
 T2R, T2T, R2R
 Break-out region : T2R <-65dB, T2T <=-35dB, R2R < -35 dB
 Ball + PCB via : suggest T2R <-60dB, T2T < -35dB, R2R <-35dB
 Inter Serdes isolation:
 Extra R2R isolation needed for Retimed/long loss port combination
 R2R < (-65dB + min trace loss from SOC bump to retimed source)

ISSCC 2024 - Forum 6.1: Highlights and 25 of 37

© 2024 IEEE Challenges in deploying 100G+ SERDES
International Solid-State Circuits Conference
 CR channel cross talk major contributor
 Cable Assembly (Path1) Dominates FEXT
TX PKG PCB + Cable + RX PKG
PCB

Path1

Path2

Path3

ISSCC 2024 - Forum 6.1: Highlights and 26 of 37

© 2024 IEEE Challenges in deploying 100G+ SERDES
International Solid-State Circuits Conference
 Dealing with inevitable reflections
 SBR w/ideal termination for junction distribution visualization
◼ TSV, C4junction, skip layer breakout, PTH, BGA, PCB via, connector
 Low loss is not always better
6

5.5

4.5
COM(dB)

3.5

2.5

2
10 15 20 25 30 35 40
bump to tump IL(dB)

ISSCC 2024 - Forum 6.1: Highlights and 27 of 37

© 2024 IEEE Challenges in deploying 100G+ SERDES
International Solid-State Circuits Conference
 Dealing with inevitable reflections
 F domain observation : ILD increases with more junctions included

ISSCC 2024 - Forum 6.1: Highlights and 28 of 37

© 2024 IEEE Challenges in deploying 100G+ SERDES
International Solid-State Circuits Conference
 Reflection Mitigation
 Front end design shall not enhance HF component, but it only do so much
◼ Energy distribution can be different between channel design
◼ Majority of energy is in-band, regardless channel scenario
 Time domain mitigation required
 Junction Improvement is crucial

Red: SBRint ch1

Yellow: SBRint ch2

ISSCC 2024 - Forum 6.1: Highlights and 29 of 37

© 2024 IEEE Challenges in deploying 100G+ SERDES
International Solid-State Circuits Conference
 Time Domain Reflection cancelling
 Compare 2 channels with similar junction compositions but
different geometry
◼ One distributed along a longer trace with higher overall IL
◼ The other distributed in a tighter region with shorter overall IL
 Lower loss channel turns out to be more challenging
 Junction optimization remains a key
 Design goal
◼ Balancing channel flexibility and reflection canceling cost

ISSCC 2024 - Forum 6.1: Highlights and 30 of 37

© 2024 IEEE Challenges in deploying 100G+ SERDES
International Solid-State Circuits Conference
 Agenda
 Motivation

 System and Performance Target Implications

 Big Chip Problems

 SIPI Challenges and Mitigations

 Thermal

 Serdes Requirement

ISSCC 2024 - Forum 6.1: Highlights and 31 of 37

© 2024 IEEE Challenges in deploying 100G+ SERDES
International Solid-State Circuits Conference
 Thermal
 Serdes can be hot with advanced nodes
 But not the hottest - typical Power density assumption
◼ Serdes 0.5-3W/mm2
◼ High density logic 3-6W/mm2 [7]

 Ta could increase from preheat of other subsys

 Tj threshold often dictated by memory
 Low lane count scenario
◼ Lid/hat type pkg for ganged HS
◼ Exposed die in transceiver modules
 Large pkg high lane count scenario
◼ Ring type pkg, exposed die
ISSCC 2024 - Forum 6.1: Highlights and 32 of 37
© 2024 IEEE Challenges in deploying 100G+ SERDES
International Solid-State Circuits Conference
 Agenda
 Motivation

 System and Performance Target Implications

 Big Chip Problems

 SIPI Challenges and Mitigations

 Thermal

 Serdes Requirement

ISSCC 2024 - Forum 6.1: Highlights and 33 of 37

© 2024 IEEE Challenges in deploying 100G+ SERDES
International Solid-State Circuits Conference
 Serdes Considerations
 Process node, Monolithic or Chiplet integration
 Intra die / Floorplan considerations
◼ Power Ground placement for crosstalk consideration
◼ Power density
◼ Skew tunning and breakout consideration
◼ Structures need to be wavelength aware
 Low jitter timing path
 Low common mode noise
 Adequate frontend response
 Robust thermal performance
 Flexible termination
 Reflection cancelling within reasonable power budget
 Datapath width and rate for reducing latency

ISSCC 2024 - Forum 6.1: Highlights and 34 of 37

© 2024 IEEE Challenges in deploying 100G+ SERDES
International Solid-State Circuits Conference
 Combined System Goal
 Reasonably behaved channel consider manufacturing variations
 Serdes design fulfilling channel, power, floorplan requirements
 BER provide enough guard band for post FEC performance
IL(dB)
15 20 25 30 35 40 45
1.0E-05

1.0E-06

C2C
BER

CR 1m bump to bump
1.0E-07 C2M config1
C2M config2

1.0E-08

ISSCC 2024 - Forum 6.1: Highlights and 35 of 37

© 2024 IEEE Challenges in deploying 100G+ SERDES
International Solid-State Circuits Conference
 Summary
 On Circuit design the inevitable migration to advanced process
node and packaging technology has imposed more rules and
constraints on the design
 On the system side it has become far more difficult for the
industry to keep up with the unprecedented trend of Nyquist
rate increasing
 Low Dk material, thicker ABF, increased stack via, new design
technique in junction optimization, substrate launch
twinax/coaxial provide trajectory for more efficient HN CAB-B
designs, or to enable phyless HH CAB-C designs
 The rapid advance in materials, components and SIPI
techniques has granted the path for volume deployment in
2025.

ISSCC 2024 - Forum 6.1: Highlights and 36 of 37

© 2024 IEEE Challenges in deploying 100G+ SERDES
International Solid-State Circuits Conference
 Reference
[1] Understanding the high speed SerDes solution space 10G-112G Ronen Laviv
https://www.linkedin.com/pulse/understanding-high-speed-serdes-solution-space-10g-
112g-ronen-laviv
[2] Survey of 2+ published demoes
[3] IEEE802 - dambrosia_3dj_01b_2311.pdf (11-28-2023)
[4] A summary of High Speed Ethernet ASICs, Justin Pietsch 2016
https://elegantnetwork.github.io/posts/A-Summary-of-Network-ASICs/
[5] HC34 https://www.servethehome.com/wp-content/uploads/2022/08/HC34-Juniper-
Express-5-Scale-up-Modular-Chassis-scaled.jpg
[6]Twinax Intra Pair Skew Comparison Report Samtec
https://suddendocs.samtec.com/notesandwhitepapers/samtec-twinax-skew-study-vs-
competitors-comparison-report.pdf
[7] The breakdown of Dennard scaling - Vertical Stacked LEGO-PoL CPU Voltage Regulator
Jaeil Baek, Youssef Elasser, Kaladhar Radhakrishnan, Minjie Chen, Dec 2021

ISSCC 2024 - Forum 6.1: Highlights and 37 of 37

© 2024 IEEE Challenges in deploying 100G+ SERDES
International Solid-State Circuits Conference
 Please Scan to Rate
This Paper

ISSCC 2024 - Forum 6.1: Highlights and 38 of 37

© 2024 IEEE Challenges in deploying 100G+ SERDES
International Solid-State Circuits Conference
 The Impact of Industry Trends on
200+Gbps Wireline R&D

Tony Chan Carusone

Alphawave Semi
University of Toronto

Tony Chan Carusone ISSCC 2024 - Forum 6.2: The Impact of Industry Trends on 200+Gbps Wireline R&D 1 of 86
© 2024 IEEE International Solid-State Circuits Conference
 Outline
 Overview of Connectivity Trends
◼ Megatrends
◼ Wireline Transceiver & Application Trends
 New Technologies and Considerations for 200G Links
◼ Within Transceivers
◼ 200G Optics
◼ Optical/Electrical Co-Design
 Beyond 200Gb/s

Tony Chan Carusone ISSCC 2024 - Forum 6.2: The Impact of Industry Trends on 200+Gbps Wireline R&D 2 of 86
© 2024 IEEE International Solid-State Circuits Conference
 Relentless Growth in Data Consumption
AI INFLECTION POINT EXPONENTIAL RISE IN DATA
2010-2025

Number of synapses in Next Gen.

the human brain 100+ Trillion
parameters*
Text + Images
ChatGPT4.0
175 Billion
parameters
45TB data
(one million feet
ChatGPT2.0 of bookshelf
1.5 Billion space)
parameters
40GB data
* Z. Ma et al, “BaGuaLu: targeting brain scale pretrained models
with over 37 million cores,” ACM SIGPLAN Symposium on
PPoPP, New York, https://doi.org/10.1145/3503221.3508417 (1. The Data Center Journey, From Central Utility To Center Of The Universe (semiengineering.com).
Source Statista https://semiengineering.com/thedatacenter-journey-from-central-utility-to-center-of-the-universe/.)

Tony Chan Carusone ISSCC 2024 - Forum 6.2: The Impact of Industry Trends on 200+Gbps Wireline R&D 3 of 86
© 2024 IEEE International Solid-State Circuits Conference
 AI Connectivity
DGX H100 256 GPU SuperPOD
Networking
Revenue Share %*
Server Market

AI ASICs Switch Switch Switch Switch

General
Purpose
xPU

By 2027, approximately:
• 50% of market revenue will be AI-accelerated servers
• 20% of Ethernet Data Center Switch Ports connected to AI xPU’s consuming more bandwidth
servers
• 50% of data center switch ports driven by 400Gbps or higher 10+Tb/s: Bandwidth for xPU to xPU

800 Gbps is expected to eclipse 400 Gbps by 2025 Growing AI clusters:

30% of time in AI/ML spent in networking (Meta at OCP 2022) 100’s – 10,000’s xPUs per cluster
• Moving data between GPUs * Souce: Dell’Oro Group Data Center IT Capex Forecast, Jan 2023

Tony Chan Carusone ISSCC 2024 - Forum 6.2: The Impact of Industry Trends on 200+Gbps Wireline R&D 4 of 86
© 2024 IEEE International Solid-State Circuits Conference
 AI Driving Connectivity

Server Shipments Source: 650 Group, July 2023

Source: 650 Group, July 2023

Tony Chan Carusone ISSCC 2024 - Forum 6.2: The Impact of Industry Trends on 200+Gbps Wireline R&D 5 of 86
© 2024 IEEE International Solid-State Circuits Conference
 Connectivity Trends in Modern Compute Infrastructure

Data Rates Double every 2-3 Years

• AI/ML technologies require huge
2017 2020 2022 2025
amounts of data
x2 x2 x2 • Data bandwidth and latency for
5Tbps 12.8Tbps 25.6Tbp
s
51.2Tbps connections within the datacenter
Switch Data Rates x2 x2 x2
become critical metrics
200Gbps 400Gbps 800Gbps
100Gbps
Transceiver Data Rates 4x25Gbps
4x50Gbps
4PAM
4x100Gbps
4PAM /
4x200Gbps
8x100Gbps ➢ The industry is making the necessary
investments so as not to limit the
400G 4PAM /
Coherent 800G
Coherent
potential of AI

AI will be the most

• Typical data center bandwidth grows 30-40% annually significant growth driver
• Bandwidth for AI workloads will grow over 100% per year for connectivity in for the
Source: “Silicon Photonics Market and Technology Report 2020”, April 2020
Silicon Photonics Market & Technology 2020 - Yole Développement (i-micronews.com) next decade

Tony Chan Carusone ISSCC 2024 - Forum 6.2: The Impact of Industry Trends on 200+Gbps Wireline R&D 6 of 86
© 2024 IEEE International Solid-State Circuits Conference
 Connectivity Demands for AI

Higher per-lane data rates

Scale out to larger clusters

Flatter network topologies with higher radix switches

to reduce latency

Proliferation of optical connectivity within the rack

Tony Chan Carusone ISSCC 2024 - Forum 6.2: The Impact of Industry Trends on 200+Gbps Wireline R&D 7 of 86
© 2024 IEEE International Solid-State Circuits Conference
 Example of xPU Cluster Network Topology
Front-End Datacenter Network [Norm Jouppi, … David A Patterson,
“TPU v4: An Optically Reconfigurable
• Connects traditional compute servers Supercomputer for Machine Learning
• Carries relatively short-lived streams of data with Hardware Support for
➢ Flexible architecture preferred Embedding,” ISCA, June 21, 2023]

➢ Multiple layers of hierarchy

➢ Redundancy is incorporated

Back-End ML Network
• xPU AI accelerator
interconnections
• Large training workloads
create sustained high-
bandwidth traffic with
regular patterns
• Low latency
➢ Flat hierarchy
➢ Non-blocking
Tony Chan Carusone ISSCC 2024 - Forum 6.2: The Impact of Industry Trends on 200+Gbps Wireline R&D 8 of 86
© 2024 IEEE International Solid-State Circuits Conference
 Google TPU v4: 4096-Chip AI Supercomputer

Optical Connectivity

TPUs1

Electrical interconnect
Norm Jouppi, … David A Patterson, “TPU v4: An Optically
within a rack Reconfigurable Supercomputer for Machine Learning with
Hardware Support for Embedding,” ISCA, June 21, 2023

1 Tensor Processing Unit – is a purpose-built processing IC for neuronal networks

Tony Chan Carusone ISSCC 2024 - Forum 6.2: The Impact of Industry Trends on 200+Gbps Wireline R&D 9 of 86
© 2024 IEEE International Solid-State Circuits Conference
 Disaggregated Storage
• Concentration of Optical Interconnect
storage in shared pools
improves efficiency CPU CPU
GPU GPU

• Larger shared pools

GPU GPU
CPU CPU

allows for better Memory

efficiency Storage
Memory
Memor

• Relies on low-latency y

interconnect ➢ Scale-out beyond the rack

will require optics
• PCIe ⇒ CXL

Tony Chan Carusone ISSCC 2024 - Forum 6.2: The Impact of Industry Trends on 200+Gbps Wireline R&D 10 of 86
© 2024 IEEE International Solid-State Circuits Conference
 WIRELINE TRENDS

© 2024 IEEE International Solid-State Circuits Conference

 Published Wireline Transceivers 2010-2023

Data rate trend:

2× every 5 years

Tony Chan Carusone ISSCC 2024 - Forum 6.2: The Impact of Industry Trends on 200+Gbps Wireline R&D 12 of 86
© 2024 IEEE International Solid-State Circuits Conference
 Published Wireline Transceivers 2010-2023

224
112

Data Rate [Gbps]

64
32
16
8
Data rate trend: 4
2× every 2 technology nodes
2

Process Node [nm]

Tony Chan Carusone ISSCC 2024 - Forum 6.2: The Impact of Industry Trends on 200+Gbps Wireline R&D 13 of 86
© 2024 IEEE International Solid-State Circuits Conference
 Published Wireline Links 2010 – 2023 with Loss > 20dB

Transition to DSP 31.6

equalization

Energy/Bit [pJ/bit]
20.0

10.0

5.0

3.2

Tony Chan Carusone ISSCC 2024 - Forum 6.2: The Impact of Industry Trends on 200+Gbps Wireline R&D 14 of 86
© 2024 IEEE International Solid-State Circuits Conference
 Anatomy of the DSP Transceiver
• Combination of ISI and 4-PAM
necessitates extensive DSP for
Ref.
– encoding/decoding – equalization Clk ∫ 𝐾𝐼
– modulation/demodulation – timing recovery
∫ 𝐾𝑃
• As data rates increase:
– Equalization and FEC complexity increases
𝜙 FFE-t MM-PD
➢Challenging to keep power and latency low

FEC FEC
FIR AFE FFE
Enc. Dec.

DFE

Tony Chan Carusone ISSCC 2024 - Forum 6.2: The Impact of Industry Trends on 200+Gbps Wireline R&D 15 of 86
© 2024 IEEE International Solid-State Circuits Conference
 Evolution of Datacentre Rates

2017 2020 2022 2025 2027

x2 x2 x2 x2

5Tbps 12.8Tbps 25.6Tbps 51.2Tbps 102.4Tbps

Switch Data Rates
x2 x2 x2 x2

200Gbps 400Gbps 800Gbps 1.6Tbps

100Gbps
Transceiver Data Rates 4x50Gbps 4x100Gbps 4x200Gbps 8x200Gbps
4x25Gbps
4PAM 4PAM 8x100Gbps Coherent
400G Coherent 4PAM
800G Coherent

Tony Chan Carusone ISSCC 2024 - Forum 6.2: The Impact of Industry Trends on 200+Gbps Wireline R&D 16 of 86
© 2024 IEEE International Solid-State Circuits Conference
 Benefits of 200G Links
32 Modules • A 51.2T 1RU switch requires 32 x 1.6T
modules
• 16x100G optical links generally
requires twice the number of lasers as
1 RU Switch Faceplate
8x200G links
➢200G links halve the laser power and
Optical Transceiver cost
➢Realization of these benefits requires
robust 200G SerDes within available
power and cost envelopes

Tony Chan Carusone ISSCC 2024 - Forum 6.2: The Impact of Industry Trends on 200+Gbps Wireline R&D 17 of 86
© 2024 IEEE International Solid-State Circuits Conference
 Benefits of 200G Links
32 Modules

1 RU Switch Faceplate

• 102.4T switch would require 2x100x100G differential pair connections

challenging:
• SerDes area and power density on the switch
• Crosstalk through dense bumps, package routing, PCB / flyover cables, and module
connectors
➢200G links likely to be preferred
Tony Chan Carusone ISSCC 2024 - Forum 6.2: The Impact of Industry Trends on 200+Gbps Wireline R&D 18 of 86
© 2024 IEEE International Solid-State Circuits Conference
 APPLICATIONS

© 2024 IEEE International Solid-State Circuits Conference

 Direct-Attach Cabling

 Signal integrity is
challenging
 High-power transceivers
in the ASIC

☺ Low cost
☺ Low power

Tony Chan Carusone ISSCC 2024 - Forum 6.2: The Impact of Industry Trends on 200+Gbps Wireline R&D 20 of 86
© 2024 IEEE International Solid-State Circuits Conference
 200G Passive Cable Channel Responses
• Blue: 13” cable has higher loss – 37dB
• Red: 8” cable has worse distant post-cursor reflections
Reflections

Tony Chan Carusone ISSCC 2024 - Forum 6.2: The Impact of Industry Trends on 200+Gbps Wireline R&D 21 of 86
© 2024 IEEE International Solid-State Circuits Conference
 Chip-to-Module Links
• Difficult routing for some
channels Switch
• Significant additional loss PCB
introduced by large
packages
➢ Total chip-to-module
channel loss may exceed
ASIC 9”
35dB at 200G
• Potential measures: 3”
▪ Extensive equalization
▪ Repeaters
Modules
▪ Flyover cables

Tony Chan Carusone ISSCC 2024 - Forum 6.2: The Impact of Industry Trends on 200+Gbps Wireline R&D 22 of 86
© 2024 IEEE International Solid-State Circuits Conference
 Repeaters or Active Cables

 Signal integrity is relaxed

 Higher system cost and
power
Added
repeaters
☺ Simpler (lower-power)
transceivers in the ASIC

Tony Chan Carusone ISSCC 2024 - Forum 6.2: The Impact of Industry Trends on 200+Gbps Wireline R&D 23 of 86
© 2024 IEEE International Solid-State Circuits Conference
 Flyover Cables
 Signal integrity is relaxed
 Higher system cost and
power

☺ Simpler (lower-power)
transceivers in the ASIC

Tony Chan Carusone ISSCC 2024 - Forum 6.2: The Impact of Industry Trends on 200+Gbps Wireline R&D 24 of 86
© 2024 IEEE International Solid-State Circuits Conference
 200G Flyover Cable vs. PCB Responses

• Blue channel: 13” PCB trace 32dB loss

• Red channel: short PCB trace + 10” flyover cable

Tony Chan Carusone ISSCC 2024 - Forum 6.2: The Impact of Industry Trends on 200+Gbps Wireline R&D 25 of 86
© 2024 IEEE International Solid-State Circuits Conference
 Massive Scale-Out

• Driven by increasingly large

parallel compute and
disaggregation
• Necessitates links with
longer reach

 Signal integrity is
challenging
 Power consumption is high

Tony Chan Carusone ISSCC 2024 - Forum 6.2: The Impact of Industry Trends on 200+Gbps Wireline R&D 26 of 86
© 2024 IEEE International Solid-State Circuits Conference
 Optical Interconnect

 Signal integrity over the

long links is simplified
 High system cost and power

 Relatively simple (lower-

power) transceivers in the
ASIC
☺ Reach is extended

Tony Chan Carusone ISSCC 2024 - Forum 6.2: The Impact of Industry Trends on 200+Gbps Wireline R&D 27 of 86
© 2024 IEEE International Solid-State Circuits Conference
 OPTICAL MODULES

© 2024 IEEE International Solid-State Circuits Conference

 Optical Modules in The Datacentre
Core Switch

Spine Switch

Leaf Switch

TOR Switch

Pluggable
Modules or Switch System (box) in all levels Switch
(Core, spine, leaf, TOR) ASIC
Transceivers

Tony Chan Carusone ISSCC 2024 - Forum 6.2: The Impact of Industry Trends on 200+Gbps Wireline R&D 29 of 86
© 2024 IEEE International Solid-State Circuits Conference
 Optical Module Anatomy
Host Interface

• DSP = Digital Signal Processing

for both line and host interfaces
• TIAs and Drivers are linear amplifiers with a broad
bandwidth
• Detectors and Lasers in III-V or similar technologies Line Interface
Tony Chan Carusone ISSCC 2024 - Forum 6.2: The Impact of Industry Trends on 200+Gbps Wireline R&D 30 of 86
© 2024 IEEE International Solid-State Circuits Conference
 Optical Module Anatomy
Host Interface
[Liu et al, ACM SIGCOMM’23]

• DSP with integrated drivers

reduces the component count

Line Interface
Tony Chan Carusone ISSCC 2024 - Forum 6.2: The Impact of Industry Trends on 200+Gbps Wireline R&D 31 of 86
© 2024 IEEE International Solid-State Circuits Conference
 Optical Module Anatomy
Host Interface • Silicon photonics allows for integration of
several optoelectronic components into a
single silicon die
• Laser count may be reduced

Line Interface
Tony Chan Carusone ISSCC 2024 - Forum 6.2: The Impact of Industry Trends on 200+Gbps Wireline R&D 32 of 86
© 2024 IEEE International Solid-State Circuits Conference
 Linear Pluggable Optical (LPO) Module Anatomy
Host Interface • Alternative architecture to eliminate the DSP
• No receive and retransmit function between
the host and line interfaces to reset noise and
timing jitter
⇒ “Linear Pluggable Optics”

• Note: with no DSP in the module, host

and line interface baud rate,
modulation, coding must be identical
Line Interface
Tony Chan Carusone ISSCC 2024 - Forum 6.2: The Impact of Industry Trends on 200+Gbps Wireline R&D 33 of 86
© 2024 IEEE International Solid-State Circuits Conference
 Traditional DSP vs. Linear Pluggable Optics
• Traditional DSP optical modules are a
workhorse of optical connectivity
• Robust and reliable
• Backward & forward compatible
• Robust ecosystem
• Flexible deployment
Traditional • Linear pluggable modules create an end-
DSP
to-end link where every intervening
connection and component is
interdependent
Linear
• Transceivers must compensate for the
aggregated loss on two series-concatenated
chip-to-module links plus the optoelectronics
• Analog equalization in the LPO module
can help
• Potential for power and latency savings
Tony Chan Carusone ISSCC 2024 - Forum 6.2: The Impact of Industry Trends on 200+Gbps Wireline R&D 34 of 86
© 2024 IEEE International Solid-State Circuits Conference
 Linear Pluggable Optics Usage Scenario

Example:

Switch System
Traditional
DSP

Linear
Traditional Linear Traditional
DSP DSP

Tony Chan Carusone ISSCC 2024 - Forum 6.2: The Impact of Industry Trends on 200+Gbps Wireline R&D 35 of 86
© 2024 IEEE International Solid-State Circuits Conference
 Parallel optical fiber

Miniature
optical engines

CO-PACKAGED OPTICS

© 2024 IEEE International Solid-State Circuits Conference

 Transition to Co-Packaged Optics
Gen I: Pluggable Optics Chip-to-Module Links

Chip-to-Chip Links
Gen II – OBO/NPO

Gen III – 2.5D CPO

OR
Laser Laser

Tony Chan Carusone ISSCC 2024 - Forum 6.2: The Impact of Industry Trends on 200+Gbps Wireline R&D 37 of 86
© 2024 IEEE International Solid-State Circuits Conference
 Electronic / Photonic Integration
ASIC Many permutations possible:
Laser a) RF circuits + DSP integrated onto ASIC
• Heavy burden on the nano-CMOS ASIC

b) DSP on ASIC, RF circuits on chiplets: “Direct Drive”

ASIC • Allows dedicated process (e.g. SiGe) for the RF
Laser
circuits
• The same ASIC can directly drive electrical links

c) RF + DSP on chiplet: “Digital Drive”

ASIC
• Die-to-die interface between the ASIC and chiplet
Laser
• Occupies lowest area and lowest power on the ASIC
• Flexible interface options with different chiplets

ASIC d) RF, DSP and optical control spread across chiplet + PIC
Laser • Requires silicon photonics technology with CMOS
integration

Tony Chan Carusone ISSCC 2024 - Forum 6.2: The Impact of Industry Trends on 200+Gbps Wireline R&D 38 of 86
© 2024 IEEE International Solid-State Circuits Conference
 Opportunities and Challenges for CPO
Pros Cons
• May eliminate retimers • Concentrates power/heat
➢ Lower system power within the ASIC package
➢ Low latency
➢ Potential to lower cost
• Switch assembly more
complex
• Potential to improve
• Field service more difficult
aggregate I/O bandwidth
• Alleviates faceplate density issues • Reduced ecosystem for
innovation

vs.

Tony Chan Carusone ISSCC 2024 - Forum 6.2: The Impact of Industry Trends on 200+Gbps Wireline R&D 39 of 86
© 2024 IEEE International Solid-State Circuits Conference
 NEW TECHNOLOGIES FOR 200G

© 2024 IEEE International Solid-State Circuits Conference

 DSP Directly Mitigating Analog Limitations
Impact of FFE tap count on CTLE requirements for
Chip to Module Channel

Tony Chan Carusone ISSCC 2024 - Forum 6.2: The Impact of Industry Trends on 200+Gbps Wireline R&D 41 of 86
© 2024 IEEE International Solid-State Circuits Conference
 System Impairment Sensitivity
➢ At 200G, links can be extremely sensitive to termination and package
discontinuities unless highly capable equalizers are provided

9-Tap Post-Cursor Sensitivity

Post
Cursor CTLE TX TX Die Term PKG
TX TX Dual Bump PKG
Taps BW RLM Cap Inductor Ball Imped.
Swing SNR RJ Dirac Cap Trace
Cap
Jitter
Noise
Tony Chan Carusone ISSCC 2024 - Forum 6.2: The Impact of Industry Trends on 200+Gbps Wireline R&D 42 of 86
© 2024 IEEE International Solid-State Circuits Conference
 Channel Loss @
Number 53.125GHz

200G Bandwidth Requirements 1

2
-7.4 dB
-12 dB
3 -18 dB
• With extensive DSP (35 Tap FFE + 1 Tap DFE), target BER can be met
4 -28.1 dB
by scaling bandwidth only 1.6x compared to a 100G transceiver
➢ Even in Channels 5 & 6 having > 30dB loss 5 -33.4 dB
6 -38.6 dB

Channel: 1 2 3 4 5 6 Channel: 1 2 3 4 5 6
Tony Chan Carusone ISSCC 2024 - Forum 6.2: The Impact of Industry Trends on 200+Gbps Wireline R&D 43 of 86
© 2024 IEEE International Solid-State Circuits Conference
 • Short channels present
Roving-Tap FIR Equalizer additional challenge due to
reflections
• Roving equalization taps can
help address this concern

Short Cable channel

Long channel
(vertically normalized)

0 20 40 60 80 100
UI
Tony Chan Carusone ISSCC 2024 - Forum 6.2: The Impact of Industry Trends on 200+Gbps Wireline R&D 44 of 86
© 2024 IEEE International Solid-State Circuits Conference
 Segmented FEC Encoder
C1
Decoder
C1
Encoder
C2

• Higher data rates require more

powerful FEC
• More complex decoding
• More power consumption
• More latency
• Segmented FEC protects each
portion of the end-to-end link
with its own FEC
• Allows for each link segment to
have its own optimized FEC
• Requires decoders in the optical
module: extra power & latency
• Used, for example, in 80+km
Decoder Encoder Decoder
optical links
C3 C3 C2

Tony Chan Carusone ISSCC 2024 - Forum 6.2: The Impact of Industry Trends on 200+Gbps Wireline R&D 45 of 86
© 2024 IEEE International Solid-State Circuits Conference
 200G Concatenated FEC Encoder Decoder Encoder
C1 C1 C2

• Concatenating codes provides

double-protection to the optical
link
• Allows for relatively simple
constituent codes
• Lower power in the module
• Lower latency
• In general, may require higher
overhead for the same coding
gain than a single optimized FEC
Decoder Encoder Decoder
C1 C3 C2

Tony Chan Carusone ISSCC 2024 - Forum 6.2: The Impact of Industry Trends on 200+Gbps Wireline R&D 46 of 86
© 2024 IEEE International Solid-State Circuits Conference
 Interleaving Concatenated Codes
• Inner code will
fail with Encoder Encoder
significant Interleaver
C1 C2
probability
➢ Burst-error
correction “Outer” code “Inner” code
performance
e.g. RS(544,514) e.g. Hamming
is a key
(128,120)
consideration
⇒ aided by an
interleaver
• Further source (Soft)
Decoder
of latency Deinterleaver Decoder
C1
C2

Tony Chan Carusone ISSCC 2024 - Forum 6.2: The Impact of Industry Trends on 200+Gbps Wireline R&D 47 of 86
© 2024 IEEE International Solid-State Circuits Conference
 Ensuring Satisfactory Post-FEC BER
• Large DFE tap weights
can introduce error
propagation that is
more likely to cause
post-FEC errors
• Difficult to model since
it is dependent on
interleaving details

Tony Chan Carusone ISSCC 2024 - Forum 6.2: The Impact of Industry Trends on 200+Gbps Wireline R&D 48 of 86
© 2024 IEEE International Solid-State Circuits Conference
 Differing Optima for Pre-FEC and Post-FEC BER

Pre-FEC BER Post-FEC BER

[Yang, Shahramian, Wong, Krotnev,

Chan Carusone, ISCAS’21]
Tony Chan Carusone ISSCC 2024 - Forum 6.2: The Impact of Industry Trends on 200+Gbps Wireline R&D 49 of 86
© 2024 IEEE International Solid-State Circuits Conference
 Architectural Impact of Soft FEC
• Strong potential for 1, -1, -1 Hard
AFE FEC
soft decision FEC Dec.
technology to be Analog SERDES ⇒ Hard decisions made along with analog sampling
used at 200G
➢ Effectively precludes DSP Eq. 1, -1, -1
Hard
AFE w/ Hard FEC
analog SERDES Decisions Dec.
architectures
ADC Based DSP SERDES ⇒ Hard decisions made in the DSP
➢ Require
substantially tighter DSP Eq. 0.2, -1, -0.2
Soft
AFE w/ Soft FEC
integration between Decisions Dec.
the FEC and AFE
ADC Based DSP SERDES ⇒ Digitized decision made in the FEC
Tony Chan Carusone ISSCC 2024 - Forum 6.2: The Impact of Industry Trends on 200+Gbps Wireline R&D 50 of 86
© 2024 IEEE International Solid-State Circuits Conference
 200G OPTICS

© 2024 IEEE International Solid-State Circuits Conference

 Optical Modulation Technologies
Overview
Voltage
Technology BW Size/Cost Maturity
Swing Req’t
InP EAM (EML)  ☺ ☺ ☺
InP MZM ☺ ☺  ☺
SiP MZM   ☺ ☺
SiP MRM   ☺ 
TFLN MZM ☺ ☺  
BTO MZM ☺  ☺ 

Tony Chan Carusone ISSCC 2024 - Forum 6.2: The Impact of Industry Trends on 200+Gbps Wireline R&D 52 of 86
© 2024 IEEE International Solid-State Circuits Conference
 200G EMLs
• CW DFB laser monolithically integrated with
Interconnect Model
an electro-absorption modulator (EAM)
• P-contact for DFB and EAM are separated by EAM-
~10s kW
• N-contact is usually shared between EAM and Termination
DFB Resistance
• DFB is forward biased in gain region and EAM 𝑅𝑡
is reverse biased in absorption CMN
• Challenges
• Simultaneous optimization of ER and Chirp especially EAM Diode Model
at longer reaches
DFB+ EAM-
• Crosstalk between EMLs in an array
• Modest swing requirement (challenging for CMOS) p-type InP
• Differential variants under research and 𝑅𝑡
development Light
• e.g. [K. Adachi et al., "53-Gbaud PAM4 Differential Drive of a
Conventional EA/DFB Toward Driver-Amplifier-Less Optical n-type InP
Transceivers," OFC’19]
CMN
Tony Chan Carusone ISSCC 2024 - Forum 6.2: The Impact of Industry Trends on 200+Gbps Wireline R&D 53 of 86
© 2024 IEEE International Solid-State Circuits Conference
 200G EMLs
• CW DFB laser monolithically integrated with
an electro-absorption modulator (EAM) [K. Nishimura et al., "225-Gb/s PAM4
Operation Using Lumped-Electrode-Type
• P-contact for DFB and EAM are separated by EA-DFB Laser for 5- and 10-km
~10s kW Transmission with Low TDECQ," OFC 2023.]
• N-contact is usually shared between EAM and
DFB
• DFB is forward biased in gain region and EAM
is reverse biased in absorption
• Challenges
• Simultaneous optimization of ER and Chirp especially
at longer reaches
• Crosstalk between EMLs in an array
• Modest swing requirement (challenging for CMOS)
• Differential variants under research and
development
• e.g. [K. Adachi et al., "53-Gbaud PAM4 Differential Drive of a
Conventional EA/DFB Toward Driver-Amplifier-Less Optical
Transceivers," OFC’19]

Tony Chan Carusone ISSCC 2024 - Forum 6.2: The Impact of Industry Trends on 200+Gbps Wireline R&D 54 of 86
© 2024 IEEE International Solid-State Circuits Conference
 Chirp at 200G vs 100G
• EML chirp is the variation in its
output wavelength with output
level
➢A significant potential challenge
at 200G when combined with
chromatic dispersion
• Results on the right assume
bandwidth is scaled to maintain
similar TDECQ (~2dB) and ER
(~5dB) at zero dispersion for
both 100G and 200G links
• c.f Worst-case dispersion in
CWDM applications is
approximately -6/+3.5 ps/nm⋅km
Tony Chan Carusone ISSCC 2024 - Forum 6.2: The Impact of Industry Trends on 200+Gbps Wireline R&D 55 of 86
© 2024 IEEE International Solid-State Circuits Conference
 200G Optics: Silicon Photonic MZMs
• SiP is attractive due to its low cost, 𝑳
integration, reliability, potential for differential 𝒁𝟎
drive
G S G S G
• SiP MZMs demonstrated for 100G 4-PAM Oxide
• Typical 1.5 – 2 V⋅cm phase efficiency
• 𝑉𝜋 = 6-7V and BW=30-35GHz ⇒ ≈2Vppd swing Doping Si Substrate
• 1 laser shared for multiple lanes
• Challenges of achieving 200G/lambda: Design Tx Swing BW Area Optical
• Required 𝑉𝜋 , bandwidth, and loss are difficult Parameter Req’t Loss
to achieve simultaneously
• Marginal improvements are expected by
further optimization of doping, length, or
𝐿 ↑
☺   
bias voltage
• Advanced packaging solutions:
Junction
doping ↑ ☺  – 
• Remove termination with tight integration
of the driver
Characteristic
Impedance,
 ☺ – –
• Segmented MZM with multiple NRZ
𝑍0 ↓
drivers ⇒ requires more Tx drivers

Tony Chan Carusone ISSCC 2024 - Forum 6.2: The Impact of Industry Trends on 200+Gbps Wireline R&D 56 of 86
© 2024 IEEE International Solid-State Circuits Conference
 200G Optics: EML vs. Silicon Photonics MZM
• Symbol rate = 106.25GB/s SiP MZM EML

• Tx driver: 55GHz bandwidth and OMA [dBm] 3.5 4.1

3Vppd swing ER [dB] 3.2 4.9
• Interconnect loss = 2dB TDECQ [dB] 2.5 1.9
• SER target = 4.8e-4
• 13-tap TX-FIR optimized for
Eye Diagram
TDECQ
after TDECQ
• 11-tap FIR in reference receiver
• 53.125GHz BT4 filter in reference
receiver • BW = 46GHz • BW = 70GHz
• Vp = 6V • 5dB ER @ 1Vpp
• ZT,diff = 80W • ZT,SE = 50W
Parameters • 18dBm Laser Pwr
• PIC loss (exc.
Modulation loss)
= 10dB
Tony Chan Carusone ISSCC 2024 - Forum 6.2: The Impact of Industry Trends on 200+Gbps Wireline R&D 57 of 86
© 2024 IEEE International Solid-State Circuits Conference
 200G DMZ = DFB + InP MZM
• InP MZMs are proven technology for long-reach DFB
due to small 𝑉𝜋 , large bandwidth, controlled chirp, Laser
and bandwidth exceeding 80GHz
Transition
• e.g. [J. Ozaki et al., "Over-85-GHz-Bandwidth InP-Based
Coherent Driver Modulator Capable of 1-Tb/s/λ-Class
Operation," JLT 2023]
• Integrated laser + MZM on an InP platform
• e.g. [S. Lange et al., "100 GBd Intensity
Modulation and Direct Detection With an InP-Based
Monolithic DFB Laser Mach–Zehnder Modulator,"
JLT 2018] MZM
• Compatible with differential drive
• Challenges
• MZM integration with DFB lasers presents technical
challenges
• Expect cost to be higher than EMLs Light
Tony Chan Carusone ISSCC 2024 - Forum 6.2: The Impact of Industry Trends on 200+Gbps Wireline R&D 58 of 86
© 2024 IEEE International Solid-State Circuits Conference
 200G Optics: Silicon Photonic MRMs
• Offer the potential for compact
modulation suitable for WDM
applications
• Different optimal tuning
required depending on the
criteria: ER, optical loss,
linearity
• Particularly challenging for
4-PAM where linearity is more
critical

After Tuning

Tony Chan Carusone ISSCC 2024 - Forum 6.2: The Impact of Industry Trends on 200+Gbps Wireline R&D 59 of 86
© 2024 IEEE International Solid-State Circuits Conference
 200G Optics: TFLN
• Low loss and high bandwidth TFLN
achievable • High-speed modulators
• Longer modulators can achieve
low 𝑉𝜋
• Two approaches
1.LNOI offering higher performance
2.Hybrid LN over SiN waveguides to leverage
from existing SiP platforms Silicon Photonic Platform
• Challenges • Photodetection
• Technology maturity • Splitters
• Generally large sized & high cost • Couplers
• Differential drive being researched • etc.

Tony Chan Carusone ISSCC 2024 - Forum 6.2: The Impact of Industry Trends on 200+Gbps Wireline R&D 60 of 86
© 2024 IEEE International Solid-State Circuits Conference
 OPTICAL/ELECTRICAL CO-DESIGN

© 2024 IEEE International Solid-State Circuits Conference

 Optical Engine Co-Design
• Packaging interconnect
has a strong impact on
broadband optical front-
end frequency response
at both the Rx and Tx
• Optimal “matching” is not
obvious considering:
• Equalization capabilities of
the Rx and Tx
• Impact on voltage swings

Tony Chan Carusone ISSCC 2024 - Forum 6.2: The Impact of Industry Trends on 200+Gbps Wireline R&D 62 of 86
© 2024 IEEE International Solid-State Circuits Conference
 Receiver Interconnect Optimization Passive Modelling

Optical input RX CMOS IC

100 fF k = 0.5
60 fF
PD
Bump Bump Tcoil in i TIA
Pad input
L, Z0
W
iPD 60 pH
CESD
50 pH

Interconnect with optimized Rin Cin

80 fF
Z0 for a given length (L) 100 fF
26 Ω
Package Substrate
TIA input impedance model
Bump
model 20 pH Lbump+Lvia

10 fF Cbump+Cvia

Tony Chan Carusone ISSCC 2024 - Forum 6.2: The Impact of Industry Trends on 200+Gbps Wireline R&D 63 of 86
© 2024 IEEE International Solid-State Circuits Conference
 On-Die T-Coil Incorporated into Co-Optimization

2x BW
w/ T-coil
Bump
model 20 pH Lbump+Lvia

10 fF Cbump+Cvia

Tony Chan Carusone ISSCC 2024 - Forum 6.2: The Impact of Industry Trends on 200+Gbps Wireline R&D 64 of 86
© 2024 IEEE International Solid-State Circuits Conference
 Optical Receiver Front-End + DSP Co-Design
[Radi et al, “Optimal Optical Receivers in
Nanoscale CMOS: A Tutorial,” TCAS-II, 2022] Rx bump
model TIA

Pkg.
Trace
Tcoil
Photodiode model Tx bump

FFE

DFE

Tony Chan Carusone ISSCC 2024 - Forum 6.2: The Impact of Industry Trends on 200+Gbps Wireline R&D 65 of 86
© 2024 IEEE International Solid-State Circuits Conference
 PD to RX Interconnect Optimization Simulations
60 GHz 60 GHz
• Click to edit Master text styles
• Second level
• Third level
• Fourth level
• Fifth level

For L = 250 µm, Z0 = 80 Ω* is selected For L = 500 µm, Z0 = 50 Ω is selected

*Due to manufacturing limitations,
Z0 = 75 Ω was fabricated.

Tony Chan Carusone ISSCC 2024 - Forum 6.2: The Impact of Industry Trends on 200+Gbps Wireline R&D 66 of 86
© 2024 IEEE International Solid-State Circuits Conference
 Complete Optical Receiver Co-Design
• Dozens of design
parameters
• Co-optimization
can minimize
output noise

[Radi, Li, Patel, Chan Carusone, "Optimizing the Photodetector/Analog

Front-End Interface in Optical Communication Receivers," IEEE Trans.
Signal and Power Integrity, 2023]

Tony Chan Carusone ISSCC 2024 - Forum 6.2: The Impact of Industry Trends on 200+Gbps Wireline R&D 67 of 86
© 2024 IEEE International Solid-State Circuits Conference
 T-Coil Optimization Flow Chart

Z. Li, A. Chan Carusone, “Design and Optimization of T-Coil-Enhanced ESD

Circuits with Upsampling Convolutional Neural Network,” IMS, June 2022.
Tony Chan Carusone ISSCC 2024 - Forum 6.2: The Impact of Industry Trends on 200+Gbps Wireline R&D 68 of 86
© 2024 IEEE International Solid-State Circuits Conference
 Optimization Flow
[B. Radi, Z. Li, D. Patel and A. Chan Carusone, "Optimizing the
Photodetector/Analog Front-End Interface in Optical Communication
Receivers," in IEEE Transactions on Signal and Power Integrity, Aug. 2023]

• Different optima depending on the DSP

• No DSP equalization requires low
reflections:

Tony Chan Carusone ISSCC 2024 - Forum 6.2: The Impact of Industry Trends on 200+Gbps Wireline R&D 69 of 86
© 2024 IEEE International Solid-State Circuits Conference
 Optimization Flow
[B. Radi, Z. Li, D. Patel and A. Chan Carusone, "Optimizing the
Photodetector/Analog Front-End Interface in Optical Communication
Receivers," in IEEE Transactions on Signal and Power Integrity, Aug. 2023]

• Different optima depending on the DSP

• With DSP equalization, better to leave
some reflections:

Tony Chan Carusone ISSCC 2024 - Forum 6.2: The Impact of Industry Trends on 200+Gbps Wireline R&D 70 of 86
© 2024 IEEE International Solid-State Circuits Conference
 Proposed TIA overview

Tony Chan Carusone ISSCC 2024 - Forum 6.2: The Impact of Industry Trends on 200+Gbps Wireline R&D 71 of 86
© 2024 IEEE International Solid-State Circuits Conference
 16nm FinFET Prototype TIAs
RX1

RX2 OUT OUTB

200 µm
RX4 RX3

Digital Control
3

# Block
L W iPD
(µm) (µm) 2
1 3-Satge TIA 150 70
600 µm
2 DCOC Loop 80 75
CML Output
3 80 110
Buffers
Tony Chan Carusone ISSCC 2024 - Forum 6.2: The Impact of Industry Trends on 200+Gbps Wireline R&D 72 of 86
© 2024 IEEE International Solid-State Circuits Conference
 Co-Packaged Photodiodes + TIA Prototypes: Diagram

RX1 RX2 RX3 RX4

RX1 RX2 RX3
PD label PD-A PD-B PD-C RX4
Elec.
PD label PD-A PD-B PD-C Elec.
PD responsivity (A/W) 0.6 0.6 0.7 N/A
PD responsivity (A/W) 0.6 0.6 0.7 N/A
PDPDcapacitance
capacitance (fF)(fF) 60
60 6060 7070 N/A
N/A
PDPDO-E BW (GHz)
O-E BW (GHz) 40
40 4040 3535 N/A
N/A
PD-to-RX
PD-to-RX trace(µm) 250
trace length 500 250 250
250 500 250 250
length (µm)
PD-to-RX trace Z0 (Ω) 75 50 75 75
PD-to-RX trace Z0 (Ω) 75 50 75 75

Tony Chan Carusone ISSCC 2024 - Forum 6.2: The Impact of Industry Trends on 200+Gbps Wireline R&D 73 of 86
© 2024 IEEE International Solid-State Circuits Conference
 Experimental results
• Performance
improvement
validated
using higher
Z0 over
shorter
package
traces
[Radi, Li, Patel, Chan
Carusone, "Optimizing the
Photodetector/Analog Front-
End Interface in Optical
Communication Receivers," in
IEEE Trans. Signal and Power
Integrity, 2023.]

Tony Chan Carusone ISSCC 2024 - Forum 6.2: The Impact of Industry Trends on 200+Gbps Wireline R&D 74 of 86
© 2024 IEEE International Solid-State Circuits Conference
 BEYOND 200GB/S

© 2024 IEEE International Solid-State Circuits Conference

 Parallelism: WDM and/or PSM
DWDM: Δ𝜆 = 0.8 nm
Enabling research: Optical Spectrum Δ𝜆 CWDM: Δ𝜆 = 20 nm
• Compact modulation (e.g. MRMs
with associated thermal tuning,
microLEDs, …)
• Low-cost, low-loss and compact
wavelength
mux/demux 100G
𝜆
100G
E→O,  O→E, 1
• Multi- laser
1
Tx Rx

source with 100G 100G

Wavelength

Wavelength
E→O,  O→E, 2

Demux
2
Tx Rx
sufficient

Mux
100G 100G
accuracy/ Tx
E→O,  3 O→E, 3
Rx
tunability 100G 100G
E→O, 4 O→E, 4
Tx Rx

Tony Chan Carusone ISSCC 2024 - Forum 6.2: The Impact of Industry Trends on 200+Gbps Wireline R&D 76 of 86
© 2024 IEEE International Solid-State Circuits Conference
 Signaling Beyond 200Gb/s
• 4-PAM with increased baud rate
➢Combination of increased analog and
optical bandwidth, enhanced DSP and
coding
• Early technology demonstrations for
6-PAM and 8-PAM optics
• Right: [K. Naoe, "Ultrahigh Speed EA-DFB Lasers beyond 200 Gbps
per Lane," 2023 OFC 2023.]

• Potential for using dual-polarization

and/or coherent modulation formats
➢All require significant R&D on the
associated analog, DSP, and coding

Tony Chan Carusone ISSCC 2024 - Forum 6.2: The Impact of Industry Trends on 200+Gbps Wireline R&D 77 of 86
© 2024 IEEE International Solid-State Circuits Conference
 Evolution of Coherent Transmission
 Coherent optical communication is a proven technology that allows for 4x data rate at the
same baud rate compared with IMDD
 Trend towards
the use of
3200G coherent
transmission
MODULE SPEED

over shorter
1600G distances
 Power and cost
100+ GBaud is reduced at
800G each step
50 GBaud
➢ Coherent
transmission
400G pushing
towards use
2-5m 0.1km 0.5km 2km 10km 40km 120km inside the
REACH datacenter

Tony Chan Carusone ISSCC 2024 - Forum 6.2: The Impact of Industry Trends on 200+Gbps Wireline R&D 78 of 86
© 2024 IEEE International Solid-State Circuits Conference
 Coherent-Lite Solutions for less than 10km Reach
Transmitter:
• Avenues for research: Receiver:
• Reductions in laser cost
• Reductions in DSP power consumption
• Recent adoption of O-Band for
100+Gbaud (800Gbps DP-16QAM)
coherent links below 10km in length
• O-Band allows for lower power DSP
implementation
• Higher fiber loss in X Tx, X Rx Y Tx, X Rx X Tx, Y Rx Y Tx, Y Rx
O-Band (compared
with traditional
C-Band) is acceptable
for short distances
(< 10km)
Example at 56GBaud [Maharry et al, UCSB, OFC 2023]
Tony Chan Carusone ISSCC 2024 - Forum 6.2: The Impact of Industry Trends on 200+Gbps Wireline R&D 79 of 86
© 2024 IEEE International Solid-State Circuits Conference
 Coherent-Lite Solutions for less than 10km Reach
• 64 Gbaud
DP-16QAM carries
400+Gb/s over a QPSK @ 64Gbd
EVM < 10%
single wavelength
➢Potential path
towards
3.2Gbps/fiber and beyond
using multiple wavelengths
QAM-16 @ 64Gbd
EVM < 9%
Right: [Intel, OFC’23]

Tony Chan Carusone ISSCC 2024 - Forum 6.2: The Impact of Industry Trends on 200+Gbps Wireline R&D 80 of 86
© 2024 IEEE International Solid-State Circuits Conference
 Short-Reach Coherent DSP Alternatives
Analog / Oversampled Baud-Rate
Mixed-Signal Digital Digital
1. C-Band Coherent DSP
• Modest oversampling, M/N
• FFT based CD filter
• Rate conversion after the CD
filter

2. O-Band Coherent DSP

• Greatly reduced CD filter
• Reduced DSP latency using
time domain EQ

3. O-Band Coherent Synchronous

Baud-Rate-Sampling DSP
• Significant further power
savings
• Further reduction in DSP
latency
Tony Chan Carusone ISSCC 2024 - Forum 6.2: The Impact of Industry Trends on 200+Gbps Wireline R&D 81 of 86
© 2024 IEEE International Solid-State Circuits Conference
 Simulation to Illustrate Re-sampler Aliasing
M/N = 1.5
Linear interp.
High sampling rate Baud-Rate
M/N rate Phase-locked downsampling
sampling
↓ Digital MMSE
↓
Analog signal generation LPF FFE M/N = 1.2

Ideal Tx filter Rx filter

0.67 ⋅ 𝑓𝑏𝑎𝑢𝑑 0.47 ⋅ 𝑓𝑏𝑎𝑢𝑑
PAM4
8th-order 3rd-order Re-sampler aliasing is the
Signaling Butterworth Butterworth only artifact in this simulation

Assumptions:
MMSE
• No noise FFE
• Ideal samplers (no quantization) Synchronous
Baud-Rate Sampling
• Unlimited tap count
Tony Chan Carusone ISSCC 2024 - Forum 6.2: The Impact of Industry Trends on 200+Gbps Wireline R&D 82 of 86
© 2024 IEEE International Solid-State Circuits Conference
 Aliasing Penalty of Low Over-Sampling Rate DSP
➢ Non-negligible penalty due
to aliasing of the signal for
oversampling ratios up to
M/N = 1.2
➢ No penalty for
synchronous baud-rate
sampling
➢ Performance improvement
noticeable over short
Penalty due to reaches
re-sampler ➢ Performance improvement
aliasing is increased with higher Tx
BW

Tony Chan Carusone ISSCC 2024 - Forum 6.2: The Impact of Industry Trends on 200+Gbps Wireline R&D 83 of 86
© 2024 IEEE International Solid-State Circuits Conference
 Experimental Demonstration of Low-BER Floor
• Low-BER floor
demonstration using an
FPGA baud rate
architecture
➢ Potential for lower
power and lower latency
coherent optical
communication over
short-reach applications

Tony Chan Carusone ISSCC 2024 - Forum 6.2: The Impact of Industry Trends on 200+Gbps Wireline R&D 84 of 86
© 2024 IEEE International Solid-State Circuits Conference
 Summary
DSP
• Megatrends driving connectivity:
• Massive scale-out of compute for AI
Analog
• AI workloads demanding low latency, Devices
Design
low power, high throughput
• Disaggregated storage is another
driver R&D
• Proliferation of new connectivity Collab.
technologies
• Electrical links with 40+dB loss
• Optical connectivity over shorter FEC
Optics
reaches Coding
• Linear optics, co-packaged optics, new
Compute
optical modulation technologies, …
• Coherent optical links over shorter
and
reaches Network
Arch.
Tony Chan Carusone ISSCC 2024 - Forum 6.2: The Impact of Industry Trends on 200+Gbps Wireline R&D 85 of 86
© 2024 IEEE International Solid-State Circuits Conference
 Acknowledgements
• Behzad Dehlaghi, Shayan Shahramian, Ming Yang,
Or Vidal, Alik Gorshtein, Nir Sheffi
• Dhruv Patel, Chris Li, Bahaa Radi

Tony Chan Carusone ISSCC 2024 - Forum 6.2: The Impact of Industry Trends on 200+Gbps Wireline R&D 86 of 86
© 2024 IEEE International Solid-State Circuits Conference
 Please Scan to Rate
This Paper

Tony Chan Carusone ISSCC 2024 - Forum 6.2: The Impact of Industry Trends on 200+Gbps Wireline R&D 87 of 86
© 2024 IEEE International Solid-State Circuits Conference
 Beyond 200Gbps Electrical
transceivers – Circuit Architecture,
Design Implementation and
Silicon Results

Ariel Cohen
Intel Corporation

ISSCC Forum 2024

Ariel Cohen Beyond 200Gbps Electrical transceivers – Circuit

© 2024 IEEE International Solid-State Circuits Conference Architecture, Design Implementation and Silicon Results 1
 Outline
 Background and key challenges

 224Gb/s transceiver architecture

 Key circuits implementation

 Receiver
 Transmitter

 Package design

 Measurement results in 5nm and 3mn processes

 Potential applications and looking forward for higher rate

 Summary
Ariel Cohen Beyond 200Gbps Electrical transceivers – Circuit
© 2024 IEEE International Solid-State Circuits Conference Architecture, Design Implementation and Silicon Results 2
 Ethernet Port Speed Evolution
15 years ago

Now/Future(?)

Ariel Cohen Beyond 200Gbps Electrical transceivers – Circuit

© 2024 IEEE International Solid-State Circuits Conference Architecture, Design Implementation and Silicon Results 3
 Ethernet Port Speed Evolution
15 years ago

Now/Future(?)

Ariel Cohen Beyond 200Gbps Electrical transceivers – Circuit

© 2024 IEEE International Solid-State Circuits Conference Architecture, Design Implementation and Silicon Results 4
 Ethernet Port Speed Evolution
15 years ago
Source:https://eth
ernetalliance.or
g/wp-
content/uploads
/2023/03/Ether
netRoadmap-
2023-Website-
REV-March-
17.pdf

Now/Future(?)

Ariel Cohen Beyond 200Gbps Electrical transceivers – Circuit

© 2024 IEEE International Solid-State Circuits Conference Architecture, Design Implementation and Silicon Results 5
 Ethernet Port Speed Evolution
15 years ago
Source:https://eth
ernetalliance.or
g/wp-
content/uploads
/2023/03/Ether
netRoadmap-
2023-Website-
REV-March-
17.pdf

Now/Future(?)

Trending 1.6Tb
in 2025!!
• Ethernet single lane speed is increased at 20x/15yr
Ariel Cohen Beyond 200Gbps Electrical transceivers – Circuit
© 2024 IEEE International Solid-State Circuits Conference Architecture, Design Implementation and Silicon Results 6
 CMOS Electrical Links in the Past 21 Years
 Both speed and efficiency have scaled by >21x in the past 21 years!

From ISSCC/VLSI (2002-2022) [1-40]

Ariel Cohen Beyond 200Gbps Electrical transceivers – Circuit
© 2024 IEEE International Solid-State Circuits Conference Architecture, Design Implementation and Silicon Results 7
 100+Gb/s SerDes PHY Examples
FPGAs, NW-SW SOCs, ASICs, IPs, …

▪ 28.8 Tb/s SW 800GbE ▪ 25.6 Tb/s SW

▪ 288x112G SerDes in 7nm ▪ 128x100G SerDes

▪ AlaskaTM ▪ EPHYTM
▪ Dual 400GbE w/ ▪ 112G LR SerDes in
▪ TomahawkTM 5 100G PAM4 SerDes 7nm
▪ Agilex-ITM FPGA ▪ 51.2 Tb/s in 5nm
▪ 116Gb/s PAM-4 LR ▪ 64x800GbE
▪ 4.2 Tb/s Max BW ▪ 8x106Gb/s PAM4 LR
112G-ELR PAM4
▪ AlphaCORETM SerDes PHY in 5nm
▪ 112G LR SerDes IP

Ariel Cohen Beyond 200Gbps Electrical transceivers – Circuit

© 2024 IEEE International Solid-State Circuits Conference Architecture, Design Implementation and Silicon Results 8
 224Gb/s SerDes Considerations: Modulation
 Modulation → PAM-4
◼ Best SNR SNR and power performing at tested channel
◼ Backward compatibility
◼ Electrical to optical compatibility
◼ Testing methodology and equipment maturity/availability

Source: “PAMn vs Channel and FEC investigation for 224 Gb/s”, IEEE P802.3df Ethernet Task Force

Ariel Cohen Beyond 200Gbps Electrical transceivers – Circuit

© 2024 IEEE International Solid-State Circuits Conference Architecture, Design Implementation and Silicon Results 9
 Key PAM4 224Gb/s Serdes Challenges
• Ultra high circuit BW > 56Ghz 224Gb/s PAM-4
• UI=8.9ps -> extra-low random jitter
< 100fs

8.9ps

J. Kim et al., ISSCC 2021

Ariel Cohen Beyond 200Gbps Electrical transceivers – Circuit

© 2024 IEEE International Solid-State Circuits Conference Architecture, Design Implementation and Silicon Results 10
 Key PAM4 224Gb/s Serdes Challenges
• Ultra high circuit BW > 56Ghz 224Gb/s PAM-4
• UI=8.9ps -> extra-low random jitter
< 100fs
• Developing Analog to Digital converter
sampling in 112GS/s (like high end scope)
8.9ps

J. Kim et al., ISSCC 2021

Ariel Cohen Beyond 200Gbps Electrical transceivers – Circuit

© 2024 IEEE International Solid-State Circuits Conference Architecture, Design Implementation and Silicon Results 11
 Key PAM4 224Gb/s Serdes Challenges
• Ultra high circuit BW > 56Ghz 224Gb/s PAM-4
• UI=8.9ps -> extra-low random jitter
< 100fs
• Developing Analog to Digital converter
sampling in 112GS/s (like high end scope)
8.9ps
• Developing Digital to Analog Converter
working in 112GS/s with low noise (like J. Kim et al., ISSCC 2021
high end signal generator)

Ariel Cohen Beyond 200Gbps Electrical transceivers – Circuit

© 2024 IEEE International Solid-State Circuits Conference Architecture, Design Implementation and Silicon Results 12
 Key PAM4 224Gb/s Serdes Challenges
• Ultra high circuit BW > 56Ghz 224Gb/s PAM-4
• UI=8.9ps -> extra-low random jitter
< 100fs
• Developing Analog to Digital converter
sampling in 112GS/s (like high end scope)
8.9ps
• Developing Digital to Analog Converter
working in 112GS/s with low noise (like J. Kim et al., ISSCC 2021
high end signal generator)
• Package, channels IL and reflections
Ariel Cohen Beyond 200Gbps Electrical transceivers – Circuit
© 2024 IEEE International Solid-State Circuits Conference Architecture, Design Implementation and Silicon Results 13
 Nano Scaled Si Technology and its Befits
Fin FET Stacked nanosheet FET Stacked CFET with 3 Nano Wires

IEEE Spectrum, July 2019 (link)

√ Transistor’s But …
Bandwidth X Not friendly for
√ Low Power analog design
√ Dimensions X Heat aware design Radosavljević et. el, IEDM,2023 (Intel)
√ Low patristics X Reliability
Ariel Cohen Beyond 200Gbps Electrical transceivers – Circuit
© 2024 IEEE International Solid-State Circuits Conference Architecture, Design Implementation and Silicon Results 14
 Outline
 Background and key challenges

 224Gb/s transceiver architecture

 Key circuits implementation

 Receiver
 Transmitter

 Package design

 Measurement results in 5nm and 3mn processes

 Potential applications and looking forward for higher rate

 Summary
Ariel Cohen Beyond 200Gbps Electrical transceivers – Circuit
© 2024 IEEE International Solid-State Circuits Conference Architecture, Design Implementation and Silicon Results 15
 Why DAC-ADC Transceiver for 224Gb/s
At 224Gb/s data-rate, we need to deal with
 Tough channels with higher 56GHz Nyquist
◼ Higher insertion loss (package, board, connector, etc.)
◼ Critical reflections at many UIs later than the cursor (large package and short UI)
◼ Sharp roll-offs or some notches
◼ Non-ideal smoothness (ripples in insertion loss)
 Implementation
◼ Analog DFE loop timing in RX can not be done with a UI=8.9ps

Need more powerful and flexible channel equalization for good BER
→ Need many-tap TX/RX FFE, continuous time EQ, DFE, sometimes advanced
equalization (sliding-block DFE, MLSD, etc)

Ariel Cohen Beyond 200Gbps Electrical transceivers – Circuit

© 2024 IEEE International Solid-State Circuits Conference Architecture, Design Implementation and Silicon Results 16
 112/224 Gb/s Serdes Top-Level Block-Diagram

Data in Data DAC Driver Analog

FFE
Enc output

TX

Ariel Cohen Beyond 200Gbps Electrical transceivers – Circuit

© 2024 IEEE International Solid-State Circuits Conference Architecture, Design Implementation and Silicon Results 17
 112/224 Gb/s Serdes Top-Level Block-Diagram

Data in Data DAC Driver Analog

FFE
Enc output

TX

uP + DSP

Controls Coefficients

Slicers Data Out

Analog CTLE
ADC SIPO FFE DFE + Data
input VGA
Dec

CDR

RX Analog domain Digital parallel data path

Ariel Cohen Beyond 200Gbps Electrical transceivers – Circuit
© 2024 IEEE International Solid-State Circuits Conference Architecture, Design Implementation and Silicon Results 18
 Outline
 Background and key challenges

 224Gb/s transceiver architecture

 Key circuits implementation

 Receiver
 Transmitter

 Package design

 Measurement results in 5nm and 3mn processes

 Potential applications and looking forward for higher rate

 Summary
Ariel Cohen Beyond 200Gbps Electrical transceivers – Circuit
© 2024 IEEE International Solid-State Circuits Conference Architecture, Design Implementation and Silicon Results 19
 RX Architecture Philosophy
DSP
In
Analog Front End 6-bit 16X4 Digital out
with powerful interleaved Equalizer
Equalizer ADC

Low noise
clock
clock & data
phases recovery

● ISI is minimized in the ADC input by powerful Analog equalizer

● Using 6-bit ADC enables a low-power solution

Ariel Cohen Beyond 200Gbps Electrical transceivers – Circuit

© 2024 IEEE International Solid-State Circuits Conference Architecture, Design Implementation and Silicon Results 20
 RX Architecture Philosophy
DSP
In
Analog Front End 6-bit 16X4 Digital out
with powerful interleaved Equalizer
Equalizer ADC

Low noise
clock
clock & data
phases recovery

● ISI is minimized in the ADC input by powerful Analog equalizer

● Using 6-bit ADC enables a low-power solution
● Fine equalization done in the digital domain
● Low-jitter clocks are essential
Ariel Cohen Beyond 200Gbps Electrical transceivers – Circuit
© 2024 IEEE International Solid-State Circuits Conference Architecture, Design Implementation and Silicon Results 21
RX Architecture and Design Considerations

Analog Front End ADC-FE SAR Array 6-bit ADC DSP

Pre- Post-
buffer TH1 Amp TH2
x4
x4
Φ1,0 Φ2,x

16x6b
+-

i clgc

x4
x4
Φ1,1 Φ2,x

16x6b

DGlobal Align
+-

clgc
In Matching Digital out

64x6b
Network in x4
+ESD Φ1,2 Φ2,x
x4 Equalizer

16x6b
+
-
EQ CTLE
+2 STG clgc

VGA x4
x4
Φ1,3 Φ2,x

16x6b
+
-

clgc

4 phase clock & data

÷ 2,4,8
16 PI s and non-overlap logic
7GHz
14GHz DCO recovery

Ariel Cohen Beyond 200Gbps Electrical transceivers – Circuit

© 2024 IEEE International Solid-State Circuits Conference Architecture, Design Implementation and Silicon Results 22
RX Architecture and Design Considerations

Analog Front End ADC-FE SAR Array 6-bit ADC DSP

Pre- Post-
buffer TH1 Amp TH2
x4
x4
Φ1,0 Φ2,x

16x6b
+-

i clgc

x4
x4
Φ1,1 Φ2,x

16x6b

DGlobal Align
+-

clgc
In Matching Digital out

64x6b
Network in x4
+ESD Φ1,2 Φ2,x
x4 Equalizer

16x6b
+
-
EQ CTLE
+2 STG clgc

VGA x4
x4
Φ1,3 Φ2,x

16x6b
+
-

clgc

4 phase clock & data

÷ 2,4,8
16 PI s and non-overlap logic
7GHz
14GHz DCO recovery
AFE with hybrid CTLE
controlling both peaking
and
Ariel transfer function slope
Cohen Beyond 200Gbps Electrical transceivers – Circuit
© 2024 IEEE International Solid-State Circuits Conference Architecture, Design Implementation and Silicon Results 23
RX Architecture and Design Considerations

Analog Front End ADC-FE SAR Array 6-bit ADC DSP

Pre- Post-
buffer TH1 Amp TH2
x4
x4
Φ1,0 Φ2,x

16x6b
+-

i clgc

x4
x4
Φ Φ2,x

16x6b

DGlobal Align
1,1
+-

clgc
In Matching Digital out

64x6b
Network in x4
+ESD Φ1,2 Φ2,x
x4 Equalizer

16x6b
+
-
EQ CTLE
+2 STG clgc

VGA x4
x4
Φ1,3 Φ2,x

16x6b
+
-

clgc

4 phase clock & data

÷ 2,4,8
16 PI s and non-overlap logic
7GHz
14GHz DCO recovery
High BW 4 parallel buffers
preventing cross-talk
between T&Hs
Ariel Cohen Beyond 200Gbps Electrical transceivers – Circuit
© 2024 IEEE International Solid-State Circuits Conference Architecture, Design Implementation and Silicon Results 24
RX Architecture and Design Considerations

Analog Front End ADC-FE SAR Array 6-bit ADC DSP

Pre- Post-
buffer TH1 Amp TH2
x4
x4
Φ1,0 Φ2,x

16x6b
+-

i clgc

x4
x4
Φ1,1 Φ2,x

16x6b

DGlobal Align
+-

clgc
In Matching Digital out

64x6b
Network in x4
+ESD Φ1,2 Φ2,x
x4 Equalizer

16x6b
+
-
EQ CTLE
+2 STG clgc

VGA x4
x4
Φ1,3 Φ2,x

16x6b
+
-

clgc

4 phase clock & data

÷ 2,4,8
16 PI s and non-overlap logic
7GHz
14GHz DCO recovery

16 parallel wide BW T&Hs sampling

with equally spaced 7 GHz clocks
Ariel Cohen Beyond 200Gbps Electrical transceivers – Circuit
© 2024 IEEE International Solid-State Circuits Conference Architecture, Design Implementation and Silicon Results 25
RX Architecture and Design Considerations
Analog Front End ADC-FE SAR Array 6-bit ADC DSP
Pre- Post-
buffer TH1 Amp TH2
x4
x4
Φ1,0 Φ2,x

16x6b
+-

i clgc

x4
x4
Φ1,1 Φ2,x

16x6b

DGlobal Align
+-

clgc
In Matching Digital out

64x6b
Network in x4
+ESD Φ1,2 Φ2,x
x4 Equalizer

16x6b
+
-
EQ CTLE
+2 STG clgc

VGA x4
x4
Φ1,3 Φ2,x

16x6b
+
-

clgc

4 phase clock & data

÷ 2,4,8
16 PI s and non-overlap logic
7GHz
14GHz DCO recovery

Clocks are filtered by shunt-series peaked clock

Ariel Cohen buffers
Beyond 200Gbps Electrical for low-jitter
transceivers – Circuitand low-power solution
© 2024 IEEE International Solid-State Circuits Conference Architecture, Design Implementation and Silicon Results 26
RX Architecture and Design Considerations
Analog Front End ADC-FE SAR Array 6-bit ADC DSP
Pre- Post-
buffer TH1 Amp TH2
x4
x4
Φ1,0 Φ2,x

16x6b
+-

i clgc

x4
x4
Φ1,1 Φ2,x

16x6b

DGlobal Align
+-

clgc
In Matching Digital out

64x6b
Network in x4
+ESD Φ1,2 Φ2,x
x4 Equalizer

16x6b
+
-
EQ CTLE
+2 STG clgc

VGA x4
x4
Φ1,3 Φ2,x

16x6b
+
-

clgc

4 phase clock & data

÷ 2,4,8
16 PI s and non-overlap logic
7GHz
14GHz DCO recovery

16 low-jitter programmable 7Ghz phases

Ariel Cohen generated by 16 CMOS phase interpolators
Beyond 200Gbps Electrical transceivers – Circuit
© 2024 IEEE International Solid-State Circuits Conference Architecture, Design Implementation and Silicon Results 27
RX Architecture and Design Considerations
16 low-power post-T&Hs amplifiers
with programmable gain
Analog Front End ADC-FE SAR Array 6-bit ADC DSP
Pre- Post-
buffer TH1 Amp TH2
x4
x4
Φ1,0 Φ2,x

16x6b
+-

i clgc

x4
x4
Φ1,1 Φ2,x

16x6b

DGlobal Align
+-

clgc
In Matching Digital out

64x6b
Network in x4
+ESD Φ1,2 Φ2,x
x4 Equalizer

16x6b
+
-
EQ CTLE
+2 STG clgc

VGA x4
x4
Φ Φ2,x

16x6b
1,3
+
-

clgc

4 phase clock & data

÷ 2,4,8
16 PI s and non-overlap logic
7GHz
14GHz DCO recovery

Ariel Cohen Beyond 200Gbps Electrical transceivers – Circuit

© 2024 IEEE International Solid-State Circuits Conference Architecture, Design Implementation and Silicon Results 28
RX Architecture and Design Considerations
64(16*4) 6-bit low-power loop-unrolled
SAR ADC sampling at 1.75GS/s

Analog Front End ADC-FE SAR Array 6-bit ADC DSP

Pre- Post-
buffer TH1 Amp TH2
x4
x4
Φ1,0 Φ2,x

16x6b
+-

i clgc

x4
x4
Φ Φ2,x

16x6b

DGlobal Align
1,1
+-

clgc
In Matching Digital out

64x6b
Network in x4
+ESD Φ1,2 Φ2,x
x4 Equalizer

16x6b
+
-
EQ CTLE
+2 STG clgc

VGA x4
x4
Φ1,3 Φ2,x

16x6b
+
-

clgc

4 phase clock & data

÷ 2,4,8
16 PI s and non-overlap logic
7GHz
14GHz DCO recovery
Ariel Cohen Beyond 200Gbps Electrical transceivers – Circuit
© 2024 IEEE International Solid-State Circuits Conference Architecture, Design Implementation and Silicon Results 29
RX Architecture and Design Considerations
Digital equalizer includes 16 FFE taps. The
digital CDR loop is based on Mueller-Muller
baud-rate phase detectors

Analog Front End ADC-FE SAR Array 6-bit ADC DSP

Pre- Post-
buffer TH1 Amp TH2
x4
x4
Φ1,0 Φ2,x

16x6b
+-

i clgc

x4
x4
Φ Φ2,x

16x6b

DGlobal Align
1,1
+-

clgc
In Matching Digital out

64x6b
Network in x4
+ESD Φ1,2 Φ2,x
x4 Equalizer

16x6b
+
-
EQ CTLE
+2 STG clgc

VGA x4
x4
Φ1,3 Φ2,x

16x6b
+
-

clgc

4 phase clock & data

÷ 2,4,8
16 PI s and non-overlap logic
7GHz
14GHz DCO recovery
Ariel Cohen Beyond 200Gbps Electrical transceivers – Circuit
© 2024 IEEE International Solid-State Circuits Conference Architecture, Design Implementation and Silicon Results 30
 RX Analog Front-End
Analog Front End ADC-FE SAR Array 6-bit ADC DSP
Pre- Post-
buffer TH1 Amp TH2
x4
x4
Φ1,0 Φ2,x

16x6b
+-

i clgc

x4
x4
Φ1,1 Φ2,x

16x6b

DGlobal Align
+-

clgc
In Matching Digital out

64x6b
Network in x4
+ESD Φ1,2 Φ2,x
x4 Equalizer

16x6b
+
-
EQ CTLE
+2 STG clgc

VGA x4
x4
Φ1,3 Φ2,x

16x6b
+
-

clgc

4 phase clock & data

÷ 2,4,8
16 PI s and non-overlap logic
7GHz
14GHz DCO recovery
AFE with hybrid CTLE
controlling both peaking
and
Ariel transfer function slope
Cohen Beyond 200Gbps Electrical transceivers – Circuit
© 2024 IEEE International Solid-State Circuits Conference Architecture, Design Implementation and Silicon Results 31
 RX Analog Front-End [41]
Input Pad Matching Network

 9-th order LC filter

 1-dB BW of 56GHz
 <2ps group-delay variation
 AC coupling cap
◼ Independent CM for TX and RX
◼ <0.5dB broad-band insertion loss
 Meeting RL spec with CDM-125V ESD

Ariel Cohen Beyond 200Gbps Electrical transceivers – Circuit

© 2024 IEEE International Solid-State Circuits Conference Architecture, Design Implementation and Silicon Results 32
 RX Analog Front-End [41]
Stage-1 Hybrid CTLE

 Hybrid CTLE
◼ Shunt peaking (Q-shaping) & RC source
degeneration → Better channel matching
 CMOS gm
◼ 2x gm at the same bias current
 20dB boost & 7dB peak gain @ 53GHz
 Noise optimized sizing
 1.2-1.5V supply to ensure linearity
 Low impedance Vcm for low CM gain
Ariel Cohen Beyond 200Gbps Electrical transceivers – Circuit
© 2024 IEEE International Solid-State Circuits Conference Architecture, Design Implementation and Silicon Results 33
 Q-Shaping (LC-tuned Amplifier)

L 𝜔𝐿 2
CL 𝑄𝑖𝑛𝑑 = 𝑅𝑝 = 𝑄𝑖𝑛𝑑 𝑅𝐿 = 𝑄𝑖𝑛𝑑 𝜔𝐿
gm 𝑅𝐿
RL
RD CD 𝑔𝑚 1
𝐴𝑣 = 𝑔
𝑚 𝐷 𝑅 𝑄𝑖𝑛𝑑 𝜔𝐿 , 𝜔 =
1+ 1+𝑗𝜔𝑅 2𝜋 𝐿𝐶𝐿
𝐷 𝐶𝐷

Ignored output poles (actually faster roll-off due to inductor)

Decrease RL Decrease RD Increase CD

gm
RP L CL
RD CD

Ariel Cohen Beyond 200Gbps Electrical transceivers – Circuit

© 2024 IEEE International Solid-State Circuits Conference Architecture, Design Implementation and Silicon Results 34
 RX Analog Front-End [41]
Stage-2 & 3 VGA ST2 ST3
9dB
4dB

70GHz 70GHz

 Switchable CMOS gm for gain control

 70GHz bandwidth
 Up to 4dB/9dB gain for stage-2/3
 Series-shunt peaking at load
◼ BWER ~2.56
◼ Minimum pass-band ripple
 Linearity is important

Ariel Cohen Beyond 200Gbps Electrical transceivers – Circuit

© 2024 IEEE International Solid-State Circuits Conference Architecture, Design Implementation and Silicon Results 35
 Other Bandwidth Extended Amplifiers
 Cherry-Hooper topology has been widely used to extend amplifier bandwidth
for 112-116Gb/s receivers
 It can be used for 200+Gb/s RX-AFE

LaCroix, ISSCC 2021 [42] Xu, ISSCC 2021 [43] Guo, ISSCC 2022 [36]
116Gb/s 112Gb/s 112.5Gb/s
Ariel Cohen Beyond 200Gbps Electrical transceivers – Circuit
© 2024 IEEE International Solid-State Circuits Conference Architecture, Design Implementation and Silicon Results 36
 Interleaved ADC Front-End

Analog Front End ADC-FE SAR Array 6-bit ADC DSP

Pre- Post-
buffer TH1 Amp TH2
x4
x4
Φ1,0 Φ2,x

16x6b
+-

i clgc

x4
x4
Φ1,1 Φ2,x

16x6b

DGlobal Align
+-

clgc
In Matching Digital out

64x6b
Network in x4
+ESD Φ1,2 Φ2,x
x4 Equalizer

16x6b
+
-
EQ CTLE
+2 STG clgc

VGA x4
x4
Φ Φ2,x

16x6b
1,3
+
-

clgc

4 phase clock & data

÷ 2,4,8
16 PI s and non-overlap logic
7GHz
14GHz DCO recovery

Ariel Cohen Beyond 200Gbps Electrical transceivers – Circuit

© 2024 IEEE International Solid-State Circuits Conference Architecture, Design Implementation and Silicon Results 37
 Interleaved ADC Front-End [41,44]
From To SAR array
TH1 Post-amplifier Buffer
pre-buffer Drives 4 SAR sub-ADCs

VBP VBP
clk clk
VCMFB

inp outp outn ODAC outp inn

inp
VBCAS outp outn
inp inn
inn outn
TH1 Clock
feedthrough VCMFB
cancellation VBN VBN
VCM-REF

Ariel Cohen Beyond 200Gbps Electrical transceivers – Circuit

© 2024 IEEE International Solid-State Circuits Conference Architecture, Design Implementation and Silicon Results 38
 Interleaved ADC Front-End [41,44]
From To SAR array
TH1 Post-amplifier Buffer
pre-buffer Drives 4 SAR sub-ADCs

VBP VBP
clk clk
VCMFB

inp outp outn ODAC outp inn

inp
VBCAS outp outn
inp inn
inn outn
TH1 Clock
feedthrough VCMFB
cancellation VBN VBN
VCM-REF

Ariel Cohen Beyond 200Gbps Electrical transceivers – Circuit

© 2024 IEEE International Solid-State Circuits Conference Architecture, Design Implementation and Silicon Results 39
 Interleaved ADC Front-End [41,44]
From To SAR array
TH1 Post-amplifier Buffer
pre-buffer Drives 4 SAR sub-ADCs

VBP VBP
clk clk
VCMFB

inp outp outn ODAC outp inn

inp
VBCAS outp outn
inp inn
inn outn
TH1 Clock
feedthrough VCMFB
cancellation VBN VBN
VCM-REF

Ariel Cohen Beyond 200Gbps Electrical transceivers – Circuit

© 2024 IEEE International Solid-State Circuits Conference Architecture, Design Implementation and Silicon Results 40
 Interleaved ADC Front-End [41,44]
From To SAR array
TH1 Post-amplifier Buffer
pre-buffer Drives 4 SAR sub-ADCs

VBP VBP
clk clk
VCMFB

inp outp outn ODAC outp inn

inp
VBCAS outp outn
inp inn
inn outn
TH1 Clock
feedthrough VCMFB
cancellation VBN VBN
VCM-REF

Ariel Cohen Beyond 200Gbps Electrical transceivers – Circuit

© 2024 IEEE International Solid-State Circuits Conference Architecture, Design Implementation and Silicon Results 41
 Low-jitter and Low-Power Clocking
Analog Front End ADC-FE SAR Array 6-bit ADC DSP
Pre- Post-
buffer TH1 Amp TH2
x4
x4
Φ1,0 Φ2,x

16x6b
+-

i clgc

x4
x4
Φ1,1 Φ2,x

16x6b

DGlobal Align
+-

clgc
In Matching Digital out

64x6b
Network in x4
+ESD Φ1,2 Φ2,x
x4 Equalizer

16x6b
+
-
EQ CTLE
+2 STG clgc

VGA x4
x4
Φ1,3 Φ2,x

16x6b
+
-

clgc

4 phase clock & data

÷ 2,4,8
16 PI s and non-overlap logic
7GHz
14GHz DCO recovery

Ariel Cohen Beyond 200Gbps Electrical transceivers – Circuit

© 2024 IEEE International Solid-State Circuits Conference Architecture, Design Implementation and Silicon Results 42
 Low-jitter and Low-Power Clocking
4 phase
÷ 2,4,8 Control from
7GHz clock & data
16 PI s and non-overlap logic 14GHz DCO
recovery
en
LDO LDO LDO
(0.7, 0.8 and 0.9 V) (0.7 V) (0.8 V)
Clkgen
For low random jitter
(Rj), a LC based Digitally
controlled Oscillator
(DCO) is used and
controlled by the CDR
loop

Ariel Cohen Beyond 200Gbps Electrical transceivers – Circuit

© 2024 IEEE International Solid-State Circuits Conference Architecture, Design Implementation and Silicon Results 43
 Low-jitter and Low-Power Clocking
4 phase
÷ 2,4,8 Control from
7GHz clock & data
16 PI s and non-overlap logic 14GHz DCO
recovery
en
LDO LDO LDO
(0.7, 0.8 and 0.9 V) (0.7 V) (0.8 V)
Clkgen

4 7GHz phases are filtered

by shunt-series peaked
clock buffer to meet low-
jitter requirement

Ariel Cohen Beyond 200Gbps Electrical transceivers – Circuit

© 2024 IEEE International Solid-State Circuits Conference Architecture, Design Implementation and Silicon Results 44
 Frequency Response of LC Loaded Amps
 Shunt L provides bandpass response → jitter filtering
 Series L provides (Q dependent) amplitude peaking
 Combination of shunt-series provides benefit of both
Vo Vo Vo

Vs Vs Vs

Swing increase Swing increase

Jitter filtering Q Jitter

|Vo/Vs|
|Vo/Vs|
|Vo/Vs|

filtering

Frequency Frequency Frequency

Ariel Cohen Beyond 200Gbps Electrical transceivers – Circuit

© 2024 IEEE International Solid-State Circuits Conference Architecture, Design Implementation and Silicon Results 45
 Low-jitter and Low-Power Clocking
4 phase
÷ 2,4,8 Control from
7GHz clock & data
16 PI s and non-overlap logic 14GHz DCO
recovery
en
LDO LDO LDO
(0.7, 0.8 and 0.9 V) (0.7 V) (0.8 V)
Clkgen
X16 Non-overlap logic
CMOS PI and duty-cycle control
16 CMOS based
phase interpolators
(PIs) generate
programmable high- TH1
Φ1 Φ2
resolution, low-
jitter phases of TH2
7GHz Prev-PI Duty-cycle correction

Ariel Cohen Beyond 200Gbps Electrical transceivers – Circuit

© 2024 IEEE International Solid-State Circuits Conference Architecture, Design Implementation and Silicon Results 46
 Low-jitter and Low-Power Clocking
4 phase
÷ 2,4,8 Control from
7GHz clock & data
16 PI s and non-overlap logic 14GHz DCO
recovery
en
LDO LDO LDO
(0.7, 0.8 and 0.9 V) (0.7 V) (0.8 V)
Clkgen
X16 Non-overlap logic
CMOS PI and duty-cycle control
The combinational
logic used to create
25% duty-cycle for
TH1 clock and the
Φ1 Φ2 TH1 50% duty-cycle TH2
clock
TH2
Prev-PI Duty-cycle correction

Ariel Cohen Beyond 200Gbps Electrical transceivers – Circuit

© 2024 IEEE International Solid-State Circuits Conference Architecture, Design Implementation and Silicon Results 47
 Low-jitter and Low-Power Clocking
4 phase
÷ 2,4,8 Control from
7GHz clock & data
16 PI s and non-overlap logic 14GHz DCO
recovery
en
LDO LDO LDO
(0.7, 0.8 and 0.9 V) (0.7 V) (0.8 V)
Clkgen

Low-dropout regulators
(LDO) regulate the supply
noise and and ensure low
deterministic jitter (Dj)

Ariel Cohen Beyond 200Gbps Electrical transceivers – Circuit

© 2024 IEEE International Solid-State Circuits Conference Architecture, Design Implementation and Silicon Results 48
 Loop-unrolled SAR ADC
64(16*4) 6-bit low-power loop-unrolled
SAR ADC sampling at 1.75GS/s

Analog Front End ADC-FE SAR Array 6-bit ADC DSP

Pre- Post-
buffer TH1 Amp TH2
x4
x4
Φ1,0 Φ2,x

16x6b
+-

i clgc

x4
x4
Φ Φ2,x

16x6b

DGlobal Align
1,1
+-

clgc
In Matching Digital out

64x6b
Network in x4
+ESD Φ1,2 Φ2,x
x4 Equalizer

16x6b
+
-
EQ CTLE
+2 STG clgc

VGA x4
x4
Φ1,3 Φ2,x

16x6b
+
-

clgc

4 phase clock & data

÷ 2,4,8
16 PI s and non-overlap logic
7GHz
14GHz DCO recovery
Ariel Cohen Beyond 200Gbps Electrical transceivers – Circuit
© 2024 IEEE International Solid-State Circuits Conference Architecture, Design Implementation and Silicon Results 49
 Loop-unrolled SAR ADC
Comparators
RST
clk TH2 DAC P
inp UP5
(c)
DAC N SLCn-1 en
inn DN 5
clk
16C 2C C 16C 2C C

UP5 UP2UP1DN 5DN 2DN 1

DAC
▪ Each comparator holds its decision instead of having a memory unit, like a
latch, between comparator and CDAC and therefore reduces power
Ariel Cohen Beyond 200Gbps Electrical transceivers – Circuit
© 2024 IEEE International Solid-State Circuits Conference Architecture, Design Implementation and Silicon Results 50
 Outline
 Background and key challenges

 224Gb/s transceiver architecture

 Key circuits implementation

 Receiver
 Transmitter

 Package design

 Measurement results in 5nm and 3mn processes

 Potential applications and looking forward for higher rate

 Summary
Ariel Cohen Beyond 200Gbps Electrical transceivers – Circuit
© 2024 IEEE International Solid-State Circuits Conference Architecture, Design Implementation and Silicon Results 51
 224Gb/s TX – Clocking & Serialization
 Final data serialization comes with clocking architecture (# of phases)
 Should be planned together and co-optimized given technology’s capability

Deven D0 D0
D1
Dodd 2:1 D2 4:1 8:1
D3
D7
2 4 8

56GHz 28GHz 14GHz

▪ Expensive clocking ▪ Good balance of MUX ▪ MUX output BW limit

output BW and ▪ Large systematic clock
jitter/power of clock spacing error
distribution

Ariel Cohen Beyond 200Gbps Electrical transceivers – Circuit

© 2024 IEEE International Solid-State Circuits Conference Architecture, Design Implementation and Silicon Results 52
 N3 224Gb/s TX Design [45] - Architecture
9-Tap
FFE
NRZ
PAM-4
PAM-6

Timing

Jitter BW
Ariel Cohen Beyond 200Gbps Electrical transceivers – Circuit
© 2024 IEEE International Solid-State Circuits Conference Architecture, Design Implementation and Silicon Results 53
 N3 224Gb/s TX Design [45] - Architecture
7b-
9-Tap segmented
FFE DAC
NRZ
PAM-4
PAM-6
4:1 serializer
directly at the
output
>36dB SNDR
>0.97 RLM
>1Vpp swing

Timing

Jitter BW
Ariel Cohen Beyond 200Gbps Electrical transceivers – Circuit
© 2024 IEEE International Solid-State Circuits Conference Architecture, Design Implementation and Silicon Results 54
 N3 224Gb/s TX Design [45] - Architecture

LC D-PLL
<-99dBc/Hz
@1MHz

Timing
CMOS
w/without
inductors
<RJ 62fs
<DJ 110fs Jitter BW
Ariel Cohen Beyond 200Gbps Electrical transceivers – Circuit
© 2024 IEEE International Solid-State Circuits Conference Architecture, Design Implementation and Silicon Results 55
 N3 224Gb/s TX Design [45] - Architecture

Timing

Replica based
Jitter BW
DRV with phase
detector for
Ariel Cohen phase calibration
Beyond 200Gbps Electrical transceivers – Circuit
© 2024 IEEE International Solid-State Circuits Conference Architecture, Design Implementation and Silicon Results 56
 N3 224Gb/s TX Design [45] - Architecture
7b-
9-Tap segmented
FFE DAC
NRZ
PAM-4
PAM-6
4:1 serializer
directly at the
output
LC D-PLL
>36dB SNDR
<-99dBc/Hz
>0.97 RLM
@1MHz
>1Vpp swing

Timing
CMOS
w/without
inductors Replica based DRV
<RJ 62fs with phase
Jitter detector for phase
<DJ 110fs BW calibration
Ariel Cohen Beyond 200Gbps Electrical transceivers – Circuit
© 2024 IEEE International Solid-State Circuits Conference Architecture, Design Implementation and Silicon Results 57
 Low-power 224Gb/s TX [45] - Driver
4:1 Serializer and output driver 4UI clock dist. and output network floorplan

TX power - 0.92pJ/b TSMC 3nm

Ariel Cohen Beyond 200Gbps Electrical transceivers – Circuit
© 2024 IEEE International Solid-State Circuits Conference Architecture, Design Implementation and Silicon Results 58
 Low-power 224Gb/s TX [45]-clocks, replica and sensors

Clocks Replica and Sensor (on the right)

TX power - 0.92pJ/b TSMC 3nm

Ariel Cohen Beyond 200Gbps Electrical transceivers – Circuit
© 2024 IEEE International Solid-State Circuits Conference Architecture, Design Implementation and Silicon Results 59
 224Gb/s TX- 4:1 MUX followed by pre-Driver [46]
 CML 4:1 MUX output bandwidth is extended by active peaking (M3-M4)
 Common-mode at node-Y can be controlled by DC biasing of M3-M4
 Pulse generator VSS is elevated for swing improvement
DRVP DRVN
Node X
1.2
1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2
VCC

Voltage (V)
Q4 0.25V 0.8
Q3
0.6
Q2
M3 1 1 0 1 0 0 1 0 1 1
1V M4
Q1 0.4
8:4 MUX Retimer Pulse Gen
0.2
VCC
M5 0
Y 1.05E-09 1.07E-09 1.09E-09 1.11E-09 1.13E-09 1.15E-09
Time (s)
8:4 D M6
L X M2 Node Y
1.2
M7
1
M1

Voltage (V)
0.8
0.6 0 0 1 0 1 1 0 1 0 0
4:1 MUX Driver
VSSHI 0.4
0.2

CK8 CK4_0 CK4_90 Kim, ISSCC 22 [42] 0

1.05E-09 1.07E-09 1.09E-09 1.11E-09 1.13E-09 1.15E-09

Intel 10nm Time (S)

Ariel Cohen Beyond 200Gbps Electrical transceivers – Circuit

© 2024 IEEE International Solid-State Circuits Conference Architecture, Design Implementation and Silicon Results 60
 200Gb/s Analog FFE TX [33]
 Segmented FFE → Coarse FFE & Fine FFE by analog bias control → minimize
self loading & maximizes BW
 Merged 4:1 MUX and output driver (tailess CML)

Choi, ISSCC 21 [33]

TSMC 28nm
Ariel Cohen Beyond 200Gbps Electrical transceivers – Circuit
© 2024 IEEE International Solid-State Circuits Conference Architecture, Design Implementation and Silicon Results 61
 200Gb/s Analog FFE TX - Output Stage [33]
 Tailess CML driver → requires smaller input swing & no parasitic cap associated
with current source → overall BW improvement
 Cascode device regulates swing and increases output impedance

To lower CDRV → Width & Vov → Rout → RLM & SNDR

→ Elevate output CM level → Rout & linearity

28nm CMOS

Ariel Cohen Beyond 200Gbps Electrical transceivers – Circuit

© 2024 IEEE International Solid-State Circuits Conference Architecture, Design Implementation and Silicon Results 62
 Outline
 Background and key challenges

 224Gb/s transceiver architecture

 Key circuits implementation

 Receiver
 Transmitter

 Package design

 Measurement results in 5nm and 3mn processes

 Potential applications and looking forward for higher rate

 Summary
Ariel Cohen Beyond 200Gbps Electrical transceivers – Circuit
© 2024 IEEE International Solid-State Circuits Conference Architecture, Design Implementation and Silicon Results 63
 Package Design – On Package Connector
Top-side
Die
Key aspects:
Connector 1
1

 Two different chip routing

BGA
2
Package

 C4 – BGA connectivity
 C4 –on package connector
Board
2

 Custom pitch
 Custom ball size
 Optimizing high speed
Bump

plated-through holes (PTH)

TX1 RX3
design
RX0 TX2
Connector  Best available materials
 Best available technology
Ariel Cohen Beyond 200Gbps Electrical transceivers – Circuit
© 2024 IEEE International Solid-State Circuits Conference Architecture, Design Implementation and Silicon Results 64
 Package Ball Pitch Design [47]

𝐷 N P Cut-off frequency of vertical transition

𝑑 F in GHz
G
2
2 D,d in inches Small pitch/small ball and via diameter →
higher f_cutoff
Lower Dk → higher f_cutoff

Ariel Cohen Beyond 200Gbps Electrical transceivers – Circuit

© 2024 IEEE International Solid-State Circuits Conference Architecture, Design Implementation and Silicon Results 65
 Package Localized Skip Layer Trace [47]

Ariel Cohen Beyond 200Gbps Electrical transceivers – Circuit

© 2024 IEEE International Solid-State Circuits Conference Architecture, Design Implementation and Silicon Results 66
 Package Simulation Results (TX Path)

0.8mm ball pitch - ease of implementation with minimal performance degradation

Ariel Cohen Beyond 200Gbps Electrical transceivers – Circuit
© 2024 IEEE International Solid-State Circuits Conference Architecture, Design Implementation and Silicon Results 67
 Co-Design of Package and Die

 Minimizing reflections by targeting to 85-90 Ohm traces impedance

 Using time-domain reflectometer (TDR) analysis for impedance matching optimization
Ariel Cohen Beyond 200Gbps Electrical transceivers – Circuit
© 2024 IEEE International Solid-State Circuits Conference Architecture, Design Implementation and Silicon Results 68
 Outline
 Background and key challenges

 224Gb/s transceiver architecture

 Key circuits implementation

 Receiver
 Transmitter

 Package design

 Measurement results in 5nm and 3mn processes

 Potential applications and looking forward for higher rate

 Summary
Ariel Cohen Beyond 200Gbps Electrical transceivers – Circuit
© 2024 IEEE International Solid-State Circuits Conference Architecture, Design Implementation and Silicon Results 69
 Die images

N5 receiver [41] N3 TX [45]

Ariel Cohen Beyond 200Gbps Electrical transceivers – Circuit

© 2024 IEEE International Solid-State Circuits Conference Architecture, Design Implementation and Silicon Results 70
 N3 TX + PLL measurements [45]

Ariel Cohen Beyond 200Gbps Electrical transceivers – Circuit

© 2024 IEEE International Solid-State Circuits Conference Architecture, Design Implementation and Silicon Results 71
 N3 TX + PLL measurements [45]
Technology 3nm
Data rate [Gb/s] 224 224 112
FFE taps 9
Modulation PAM-4 PAM-6 PAM-4
Analog Power [pJ/bit] 0.92 0.61 1.13
Digital Power [pJ/bit] 0.12 0.14 0.12
Swing [Vpkpk] 1.0 1.0 1.0
RJ [fsrms] 62 @56GHz 66 @44.8GHz 104 @28GHz

SNDR [dB] 36.0 - 42.6

RLM 0.97 - 0.97
J3u03 [mUI] 55 - 33
Jrms [mUI] 16 - 9
EOJ [mUI] 16 - 9
Power supplies [V] 0.75/0.9/1.2
Area [mm2] 0.15 (w/ LDOs), 0.10 (w/o LDOs)
Ariel Cohen Beyond 200Gbps Electrical transceivers – Circuit
© 2024 IEEE International Solid-State Circuits Conference Architecture, Design Implementation and Silicon Results 72
 N5 RX Measurement Setup [41]
QPRBS13/ AWG ISI Channel RX
Sine wave
>31 dB Insertion Loss @ Tested
224G-PAM4 (56 GHz Nyquist) receiver

Ariel Cohen Beyond 200Gbps Electrical transceivers – Circuit

© 2024 IEEE International Solid-State Circuits Conference Architecture, Design Implementation and Silicon Results 73
 N5 RX Measurement Setup [41]
QPRBS13/ AWG ISI Channel RX
Sine wave
>31 dB Insertion Loss @ Tested
224G-PAM4 (56 GHz Nyquist) receiver

Channel insertion loss

Ariel Cohen Beyond 200Gbps Electrical transceivers – Circuit

© 2024 IEEE International Solid-State Circuits Conference Architecture, Design Implementation and Silicon Results 74
 Measurement Setup [41]
QPRBS13/ AWG ISI Channel RX
Sine wave
>31 dB Insertion Loss @ Tested Keysight
224G-PAM4 (56 GHz Nyquist) receiver reference clock

Channel insertion loss Keysight

1m cable and ISI coupon M8199A AWG
for channel loss of
31.6dB (including PCB
connectors and package)

High-density Packaged &

V-connector on PCB Socketed Die

Ariel Cohen Beyond 200Gbps Electrical transceivers – Circuit

© 2024 IEEE International Solid-State Circuits Conference Architecture, Design Implementation and Silicon Results 75
 N5 RX Measurement Setup [41]
QPRBS13/ AWG ISI Channel RX
Sine wave
>31 dB Insertion Loss @ Tested Keysight
224G-PAM4 (56 GHz Nyquist) receiver reference clock

Keysight
1m cable and ISI coupon M8199A AWG
for channel loss of
31.6dB (including PCB
connectors and package)
Die

Package High-density
Connector

Board
High-density Packaged &
connector on PCB Socketed Die

Ariel Cohen Beyond 200Gbps Electrical transceivers – Circuit

© 2024 IEEE International Solid-State Circuits Conference Architecture, Design Implementation and Silicon Results 76
 N5 RX Measurements Results(41)
AFE+ADC frequency response with different CTLE configurations

Increasing Cd

▪ A peak gain of 18dB at a

frequency of 53GHz
▪ Mid-band slope control
through a degeneration
capacitance (Cd)
Max Q-shaping

Ariel Cohen Beyond 200Gbps Electrical transceivers – Circuit

© 2024 IEEE International Solid-State Circuits Conference Architecture, Design Implementation and Silicon Results 77
 N5 RX Measurement Results[41]
Received QPRBS-13 histogram

▪ Healthy histogram measured at the receiver output with BER of 1e-6

for long channel (AWG imitates the TX with 1V swing and 4 FFE taps)
Ariel Cohen Beyond 200Gbps Electrical transceivers – Circuit
© 2024 IEEE International Solid-State Circuits Conference Architecture, Design Implementation and Silicon Results 78
 N5 Transceiver PAM4 224 Gb/s Measurement Setup

QPRBS31
QPRBS31 TX ISI Channel RX Checker

All-Digital 31 dB Insertion Loss @ 224G-PAM4 Nyquist 56 GHz* All-Digital

DAC-based TX ADC-based RX

Ariel Cohen Beyond 200Gbps Electrical transceivers – Circuit

* Measured bump to bump Architecture, Design Implementation and Silicon Results 79
© 2024 IEEE International Solid-State Circuits Conference
 N5 Transceiver PAM4 224 Gb/s Measurement Result
Received QPRBS-31 histogram @31 dB loss TX Eye Diagram

Meeting 224Gbps data rate

RX Voltage Histogram / ”open eye”, BER < 3e-8 with healthy “open eye”
Ariel Cohen Beyond 200Gbps Electrical transceivers – Circuit
© 2024 IEEE International Solid-State Circuits Conference Architecture, Design Implementation and Silicon Results 80
 N5 224Gb/s Measurement Results [41]
RX JTOL
QPRBS13/ BERT ISI Channel
Sine wave
38 dB Insertion Loss @ Tested
224G-PAM4 (56 GHz Nyquist) receiver

PreFEC BER vs IL

RX analog power: 1.41pJ/b

Ariel Cohen Beyond 200Gbps Electrical transceivers – Circuit

© 2024 IEEE International Solid-State Circuits Conference Architecture, Design Implementation and Silicon Results 81
 N3 224Gb/s Measurement Results
RX JTOL
QPRBS13/ BERT ISI Channel
Sine wave
40dB Insertion Loss @ Tested
224G-PAM4 (56 GHz Nyquist) receiver

PAM-4 Histogram
X 1e6

BER of 2.5e-8 with 40dB Channel

Ariel Cohen Beyond 200Gbps Electrical transceivers – Circuit
© 2024 IEEE International Solid-State Circuits Conference Architecture, Design Implementation and Silicon Results 82
 Key PAM4 224Gb/s Serdes challenges
✓ Ultra high circuit BW > 56Ghz 224Gb/s PAM-4

✓ UI=8.9ps -> extra-low random jitter <

100fs
✓ Developing Analog to Digital converter
sampling in 112GS/s (like high end 8.9ps
scope)
✓ Developing DAC working in 112GS/s with J. Kim et al., ISSCC 2021

SNDR > 33dB

✓ Package, channels IL and reflections
Ariel Cohen Beyond 200Gbps Electrical transceivers – Circuit
© 2024 IEEE International Solid-State Circuits Conference Architecture, Design Implementation and Silicon Results 83
 Outline
 Background and key challenges

 224Gb/s transceiver architecture

 Key circuits implementation

 Receiver
 Transmitter

 Package design

 Measurement results in 5nm and 3mn processes

 Potential applications and looking forward for higher rate

 Summary
Ariel Cohen Beyond 200Gbps Electrical transceivers – Circuit
© 2024 IEEE International Solid-State Circuits Conference Architecture, Design Implementation and Silicon Results 84
 Passive Cable: 1-meter with 2 OSFP connectors
Collaborative demo with
Amphenol @ ECOC23

Ariel Cohen Beyond 200Gbps Electrical transceivers – Circuit

© 2024 IEEE International Solid-State Circuits Conference Architecture, Design Implementation and Silicon Results 85
 Passive Cable: 1-meter with 2 OSFP connectors

X 1e6

BER < 1e-5 with a very reflective channel

Ariel Cohen Beyond 200Gbps Electrical transceivers – Circuit
© 2024 IEEE International Solid-State Circuits Conference Architecture, Design Implementation and Silicon Results 86
 224Gb/s PAM4 Direct Drive Optics
 No retimer -> power and latency advantages
 Breaking the physical reach limitation from meter to km
◼ Compute and memory scalability for AI hardware
 Can be implemented as Co-Package Optics (CPO) or Near-End Optics

Laser
RIN noise Fiber

Modulator
TIA RX
TX Drv TP2 TP3
Photo diode

SOC EIC(Electrical IC) PIC(Photonic IC) PIC(Photonic IC) EIC(Electrical IC) SOC

Ariel Cohen Beyond 200Gbps Electrical transceivers – Circuit

© 2024 IEEE International Solid-State Circuits Conference Architecture, Design Implementation and Silicon Results 87
 224Gb/s PAM4 Direct Drive Optics - results
Laser
RIN noise Fiber

r
Modulato
Drv TIA RX
TX TP2 TP3
Photo diode

SOC EIC(Electrical IC) PIC(Photonic IC) PIC(Photonic IC) EIC(Electrical IC) SOC
End-to-end data transmission in 224Gb/s through >10 km fiber optic cable! With 1e-4 BER
First seen in the industry

Collaborative demo
with NewPhotonics
LTD @ ECOC2023

Ariel Cohen Beyond 200Gbps Electrical transceivers – Circuit

© 2024 IEEE International Solid-State Circuits Conference Architecture, Design Implementation and Silicon Results 88
 What’s next? 448Gb/s? Electro-Optics?
 Electro optics transceivers with “Electric Brain”:
◼ Based on powerful DSP and power efficient presented Serdes
◼ Breaking the physical reach limitation from meter to km
◼ Move some equalization and distortion treatment to the optic part
◼ Near-End Optics is a promising direction

 Higher rate electrical interfaces (400Gbs/s):

◼ DAC-ADC + massive DSP combination can still be promising option
◼ Modulation scheme → PAM4/6/8… or multi-tone modulation [48]?
◼ Power efficient implementation techniques for advanced equalization in DSP:
FFE, speculative DFE, slicing-DFE, MLSE, combination of these…
◼ But.. seems like signal integrity performance, reach and cost is a “wall” limit

Ariel Cohen Beyond 200Gbps Electrical transceivers – Circuit

© 2024 IEEE International Solid-State Circuits Conference Architecture, Design Implementation and Silicon Results 89
 What’s next? 448Gb/s? Electro-Optics?
 Area to investigate:
◼ Circuit architecture: low noise AFE and LNA, power efficient ADC
and DAC, low-noise clocks, extra high BW circuits …
◼ Modulation scheme → PAM4/6/8… or multi-tone modulation [49] ?
◼ Advanced DEQ in DSP: FFE, speculative DFE, sliding-DFE, MLSE, …
◼ Process technology evolution: low-noise, better gm/c, gm/I, EM, …
◼ Signal Integrity: package, connector, cable, co-optic package,
cooling …
◼ Compatibility: multi-protocol support, optical interface, …

Ariel Cohen Beyond 200Gbps Electrical transceivers – Circuit

© 2024 IEEE International Solid-State Circuits Conference Architecture, Design Implementation and Silicon Results 90
 Outline
 Background and key challenges

 224Gb/s transceiver architecture

 Key circuits implementation

 Receiver
 Transmitter

 Package design

 Measurement results in 5nm and 3mn processes

 Potential applications and looking forward for higher rate

 Summary
Ariel Cohen Beyond 200Gbps Electrical transceivers – Circuit
© 2024 IEEE International Solid-State Circuits Conference Architecture, Design Implementation and Silicon Results 91
 Summary
 We presented the details of state-of-the-art 224Gb/s TX and RX focusing on
design techniques for core circuit blocks

 Recent publications and demonstrations proved the feasibility of PAM-4 at

224Gb/s up to 40dB channel loss (bump-to-bump)

 >30% power reduction versus 100G transceivers with a comparable die size:
◼ RX - 1.41pJ/b achieved by the combination of hybrid CTLE, inductive peaking clocks
and 6-bit memory-less ADC
◼ TX - 0.92pJ/b achieved by the combination 1UI pulse generation drives 1:4 mux
driver, inductive peaking clocks and circuit adaptation based on replica

 Breakthrough in Signal Integrity and co-design with Serdes is essential for the
deployment of 200G technology

 Critical applications of direct optics and OSF cables are demonstrated to be

feasible in 200G rate
Ariel Cohen Beyond 200Gbps Electrical transceivers – Circuit
© 2024 IEEE International Solid-State Circuits Conference Architecture, Design Implementation and Silicon Results 92
 References
 [1] M. M. Green et al., “OC-192 Transmitter in Standard 0.18um CMOS”, ISSCC 2002.
 [2] J. Cao et al., “OC-192 receiver in Standard 0.18um CMOS”, ISSCC 2002.
 [3] C. Menolfi et al., “A 25Gb/s PAM4 Transmitter in 90nm CMOS SOI,” ISSCC 2005.
 [4] J. Kim et al., “Circuit Techniques for a 40Gb/s Transmitter in 0.13um CMOS,” ISSCC 2005.
 [5] P. Landman et al., “A Transmit Architecture with 4-Tap Feedforward Equalization for 6.25/12.5Gb/s Serial Backplane Communications,”
ISSCC 2005
 [6] M. Harwood et al., “A 12.5Gb/s SerDes in 65nm CMOS Using a Baud-Rate ADC with Digital Receiver Equalization and Clock Recovery,”
ISSCC 2007
 [7] C. Menolfi et al., “A 16Gb/s Source-Series Terminated Transmitter in 65nm CMOS SOI,” ISSCC 2007.
 [8] F. Spagna et al., “A 78mW 11.8Gb/s Serial Link Transceiver with Adaptive RX Equalization and Baud-Rate CDR in 32nm CMOS,” ISSCC 2010
 [9] T. Toifl et al., “A 3.1mW/Gbps 30Gbps Quarter-Rate Triple-Speculation 15-tap SC-DFE RX Data Path in 32nm CMOS,” VLSI 2011
 [10] A. A. Hafez et al., “A 32-to-48Gb/s Serializing Transmitter Using Multiphase Sampling in 65nm CMOS,” ISSCC 2012
 [11] P. -C. Chiang et al., “60Gb/s NRZ and PAM4 Transmitter for 400GbE in 65nm CMOS,” ISSCC 2014.
 [12] E. -Hung Chen et al., “A 40-Gb/s Serial Link Transceiver in 28-nm CMOS Technology,” VLSI 2014.
 [13] B. Zhang et al., “A 28Gb/s Multi-Standard Serial-Link Transceiver for Backplane Applications in 28nm CMOS,” ISSCC 2015
 [14] A. Nazemi et al., “A 36Gb/s PAM4 Transmitter Using an 8b 18GS/s DAC in 28nm CMOS,” ISSCC 2015.
 [15] J. Kim et al., “A 16-to-40Gb/s Quarter-Rate NRZ/PAM4 Dual-Mode Transmitter in 14nm CMOS,” ISSCC 2015
 [16] J. Han et al., “A 60Gb/s 173mW Receiver Frontend in 65nm CMOS Technology,” VLSI 2015
 [17] S. Rylov et al., “A 25Gb/s ADC-Based Serial Line Receiver in 32nm CMOS SOI,” ISSCC 2015
 [18] M. Bassi et al., “A 45 Gb/s PAM-4 Transmitter Delivering 1.3Vppd Output Swing with 1V supply in 28nm CMOS FDSOI,” ISSCC 2016
 [19] Y. Frans et al., “A 40-to-64Gb/s NRZ Transmitter with Supply-Regulated Front-End in 16nm FinFET,” ISSCC 2016
 [20] J. Im et al., “A 40-to-56Gb/s PAM-4 Receiver with 10-Tap Direct Decision-Feedback Equalization in 16nm FinFET,” ISSCC 2017

Ariel Cohen Beyond 200Gbps Electrical transceivers – Circuit

© 2024 IEEE International Solid-State Circuits Conference Architecture, Design Implementation and Silicon Results 93
 References
 [21] G. Steffan et al., “A 64Gb/s PAM-4 Transmitter with 4-Tap FFE and 2.26pJ/b Energy Efficiency in 28nm CMOS FDSOI,” ISSCC 2017
 [22] T. O. Dickson et al., “A 1.8pJ/b 56Gb/s PAM-4 Transmitter with Fractionally Spaced FFE in 14nm CMOS,” ISSCC 2017
 [23] J. Kim et al., “A 112Gb/s PAM-4 Transmitter with 3-Tap FFE in 10nm CMOS,” ISSCC 2018
 [24] C. Menolfi et al., “A 112Gb/s 2.6pJ/b 8-Tap FFE PAM-4 SST TX in 14nm CMOS,” ISSCC 2018
 [25] P. Upadhyaya et al., “A Fully Adaptive 19-to-56Gb/s PAM4 Wireline Transceiver with Configurable ADC in 16nm FinFET,” ISSCC 2018
 [26] J Hudner et al., “A 112Gb/s PAM4 Wireline Receiver using a 64-way Time-Interleaved SAR ADC in 16nm FinFET,” VLSI 2018
 [27] A. Cevrero et al., “A 100 Gb/s 1.1 pJ/b PAM-4 RX with Dual-Mode 1-tap PAM4 / 3-tap NRZ Speculative DFE in 14nm CMOS FinFET,” ISSCC
2019
 [28] Z. Toprak-Deniz et al., “A 128Gb/s 1.3pJ/b PAM-4 Transmitter with Reconfigurable 3-Tap FFE in 14nm CMOS,” ISSCC 2019
 [29] Y. Krupnik et al., “112Gb/s PAM4 ADC Based SERDES Receiver for Long-Reach Channels in 10nm Process,” VLSI 2019
 [30] T. Ali et al., “A 460mW 112Gbps DSP-Based Transceiver with 38dB Loss Compensation for Next Generation Data Centers in 7nm FinFET
technology,” ISSCC 2020
 [31] J. Im et al., “A 112Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR-ADC and Inverter-Based RX Analog
Front-End in 7nm FinFET,” ISSCC 2020
 [32] J. Kim et al., “A 224Gb/s DAC-Based PAM-4 Transmitter with 8-Tap FFE in 10nm CMOS,” ISSCC 2021
 [33] M. Choi et al., “An Output Bandwidth Optimized 200Gb/s PAM-4 100Gb/s NRZ Transmitter with 5-Tap FFE in 28nm CMOS,” ISSCC 2021
 [34] S. Kiran et al., “A 56GHz Receiver Analog Front End for 224Gb/s PAM-4 SerDes in 10nm CMOS,” VLSI 2021
 [35] Y. Segal et al., “A 1.41pJ/b 224Gb/s PAM-4 SerDes Receiver with 31dB Loss Compensation,” ISSCC 2022
 [36] Z. Guo et al., “A 112.5Gb/s ADC-DSP-Based PAM-4 Long-Reach Transceiver with >50dB Channel Loss in 5nm,” ISSCC 2022
 [37] H. Pary et al., “A 4.63pJ/b 112Gb/s DSP-Based PAM-4 Transceiver for a Large-Scale Switch in 5nm FinFET,” ISSCC 2023
 [38] B. Zhang et al., “A 112Gb/s Serial Link Transceiver With 3-tap FFE and 18-tap DFE Receiver for up to 43dB Insertion Loss Channel in 7nm
FinFET Technology,” ISSCC 2023
 [39] K. Sheng et al., “A 128Gb/s PAM-4 Transmitter with Programmable-Width Pulse Generator and Pattern-Dependent Pre-Emphasis in 28nm
CMOS,” ISSCC 2023
Ariel Cohen Beyond 200Gbps Electrical transceivers – Circuit
© 2024 IEEE International Solid-State Circuits Conference Architecture, Design Implementation and Silicon Results 94
 References
 [40] J. Yang et al., “A 100Gb/s 1.6Vppd PAM-8 Transmitter with High-Swing 3+1 Hybrid FFE Taps in 40nm
,” JSSC 2023
 [41] A. Khairi et al., “A 1.41-pJ/b 224-Gb/s PAM4 6-bit ADC-Based SerDes Receiver With Hybrid AFE Capable of Supporting Long Reach Channels
,” JSSC 2023
 [42] M. –A. LaCroix et al., “A 116Gb/s DSP based Wireline Transceiver in 7nm CMOS achieving 6pJ/bit at 45dB Loss in PAM-4/Duo-PAM-4 and
52dB in PAM-2,” ISSCC 2021
 [43] D. Xu et al., “A Scalable Adaptive ADC/DSP-Based 1.25-to-56Gbps/112Gbps High-Speed Transceiver Architecture Using Decision-Directed
MMSE CDR in 16nm and 7nm,” ISSCC 2021.
 [44] Y. Shifman et al., “A 1.64mW Differential Super Source-Follower Buffer with 9.7GHz BW and 43dB PSRR for Time Interleaved ADC Application
in 10nm,” A-SSCC 2019.
 [45] M. Cusmai et al., “A 224Gb/s sub pJ/b PAM-4 and PAM-6 DAC-Based Transmitter in 3nm FinFET,” JSSC 2024.
 [46] J. Kim et al., “A 224-Gbs DAC-Based PAM-4 Quarter-Rate Transmitter With 8-Tap FFE in 10-nm FinFET,” JSSC 2022.
 [47] M. Li et al., “224G Package and PCB Investigations and COM Reference Model,” available online: https://www.ieee802.org, 2023.
 [48] B. Vatankhahghadim, et al., “A study of discrete multitone modulation for wireline links beyond 100Gb/s,” IEEE Open J. Circuits Syst. 2021

Ariel Cohen Beyond 200Gbps Electrical transceivers – Circuit

© 2024 IEEE International Solid-State Circuits Conference Architecture, Design Implementation and Silicon Results 95
 Thank You

Ariel Cohen Beyond 200Gbps Electrical transceivers – Circuit

© 2024 IEEE International Solid-State Circuits Conference Architecture, Design Implementation and Silicon Results 96
 Please Scan to Rate
This Paper

Ariel Cohen Beyond 200Gbps Electrical transceivers – Circuit

© 2024 IEEE International Solid-State Circuits Conference Architecture, Design Implementation and Silicon Results 97
 Modulation schemes for ultra-high-speed
transceivers

Naim Ben-Hamida

Senior Director
Ciena Corporation

ISSCC 2024 - Forum 6.4: Modulation schemes 1

© 2024 IEEE for ultra-high-speed transceivers
International Solid-State Circuits Conference
 Outline
 Introduction
 High Speed Data Converters
◼ Clocking
◼ ADCs
◼ DACs
 Coherent 1.6Tb/s Optical Transceiver
◼ Requirements
◼ Performance
 Rich modulation formats for 400G Transceiver
◼ PAM4, PAM6, PAM8
◼ DMT potential and challenges
 Architecture
 Performance
 Conclusions

ISSCC 2024 - Forum 6.4: Modulation schemes 2

© 2024 IEEE for ultra-high-speed transceivers
International Solid-State Circuits Conference
 Data Center: Clos architecture

J. Wei et al, “Experimental demonstration of advanced modulation formats for data center networks on 200 Gb/s lane rate IMDD links”,Vol. 28 No. 23 / 9
November 2020 / Optics Express

ISSCC 2024 - Forum 6.4: Modulation schemes 3

© 2024 IEEE for ultra-high-speed transceivers
International Solid-State Circuits Conference
 Network Walls
Fabric bandwidth for next generation AI cluster expected to exceed 1 Exabit/sec
•1 Million 800G optics module per cluster
•Dominant failure mode is laser (90%): @ 200 FIT => one optics will fail every 5 hours

Cost of Optics
•IMDD module: 0.5$/Gbps (400$ for 800G)
•Copper cables: 0.05$/Gbps (80$ per cable)

Power of Optics
•IMDD: 16pJ/bit
•LPO: 5-8pJ/bit
•Half retime: 8-12pJ/bit

Chip walls
•Power wall per chip at 1kW
•Cost wall
•Reticle size (26 mm by 33 mm or 858 mm²)
•Time to market and accelerated demand
•Yield issues

ISSCC 2024 - Forum 6.4: Modulation schemes 4

© 2024 IEEE for ultra-high-speed transceivers
International Solid-State Circuits Conference
 Optics for AI Cluster
 Urgency to reduce the power consumption of optical connectivity in AI
Clusters.
 AI clusters need 32x increase in network connectivity bandwidth. It would
double the cost of the whole system and add another 20-25% to the power
consumption.

Data center power 800MW-1000MW

• Network power: 200MW-250MW
• Network capacity: 1 Exabyte/s

ISSCC 2024 - Forum 6.4: Modulation schemes 5

© 2024 IEEE for ultra-high-speed transceivers
International Solid-State Circuits Conference
 Circuits For High-Speed Transceivers

ADC/DAC Based Transceivers:

Convergence Between Optical and Serdes Circuits
Requirements

ISSCC 2024 - Forum 6.4: Modulation schemes 6

© 2024 IEEE for ultra-high-speed transceivers
International Solid-State Circuits Conference
 Ciena ASIC's enabling exponential traffic growth
Wavelogic 6p
Wavelogic 5n 3nm CMOS
7nm CMOS >120Gs/s DAC/ADC
80Gs/s DAC/ADC
1000.00 Wavelogic Ai 400G
28nm FD-SOI CMOS
68 Gs/s 8 bit DAC
and ADC
HunQ 32nm
CMOS
40 Gs/s 6 bit ADC
SQZR 65nm CMOS
28Gs/s 4x6 bit ADC
Transmission Rate (Gbit/s)

Wavelogic 6e
3nm CMOS
>200 Gs/s DAC/ADC
100.00 Wavelogic 5e
QREW 90nm CMOS 7nm CMOS
4x22Gs/s 6 bit ADC 120 Gs/s DAC/ADC

OC-768 Wavelogic 3 nano

GaAs HBT HunT 28nm FD-SOI
20 Gb/s Dual 2:1 65nm CMOS CMOS
Mux TWZR 130nm 4x56 Gs/s 6 bit DAC 40 Gs/s 6 bit DAC
BiCMOS and ADC
OC-192 GaAs HBT TREW 130nm 56 Gb/s QPSK
10 Gb/s MUX BiCMOS Quad Transmitter
10.00 40 Gb/s QPSK
Quad Transmitter
OC-48 GaAs Super
WARP
Decoder DeMUX
130nm BiCMOS
Two 22 Gs/s 6 bit DAC

OC-192 GaAs HBT

10 Gb/s DeMUX

1.00
© 2024 IEEE 1990 1995 2000 2005 2010 2015 2020 2025
International Solid-State Circuits Conference Year
 Common IP for Flexible Reach

Power/Performance Optimization through:

o Variable Vdd IP Library
o Variable bit-resolution
o Interleave ratio
o CMOS or BiCMOS VGA/EQ/CTLE

Long reach
Medium reach
Short reach

ISSCC 2024 - Forum 6.4: Modulation schemes 8

© 2024 IEEE for ultra-high-speed transceivers
International Solid-State Circuits Conference
 Coherent optical transceiver block diagram

ISSCC 2024 - Forum 6.4: Modulation schemes 9

© 2024 IEEE for ultra-high-speed transceivers
International Solid-State Circuits Conference
 Trends in PLLs

© 2024 IEEE
International Solid-State Circuits Conference
 Digital Fractional PLLs
Bang-Bang PLLs with Quantization Noise Cancellation
 76.7fs-Integrated-Jitter and -71.9dBc In-Band Fractional-  A 66fsrms Jitter 12.8-to-15.2GHz Fractional-N Bang-Bang
Spur Bang-Bang Digital PLL Based on an Inverse- PLL with Digital Frequency-Error Recovery for Fast
Constant-Slope DTC and FCW Subtractive Dithering Locking (Santiccioli, ISSCC 2020)

S. M. Dartizio et al., "4.3 A 76.7fs-lntegrated-Jitter and −71.9dBc In-Band A. Santiccioli et al., "17.2 A 66fsrmsJitter 12.8-to-15.2GHz Fractional-
Fractional-Spur Bang-Bang Digital PLL Based on an Inverse-Constant-Slope N Bang-Bang PLL with Digital Frequency-Error Recovery for Fast
DTC and FCW Subtractive Dithering," 2023 IEEE International Solid-State Locking," 2020 IEEE International Solid-State Circuits Conference -
Circuits Conference (ISSCC), San Francisco, CA, USA, 2023, pp. 3-5 (ISSCC), San Francisco, CA, USA, 2020, pp. 268-270

ISSCC 2024 - Forum 6.4: Modulation schemes 11

© 2024 IEEE for ultra-high-speed transceivers
International Solid-State Circuits Conference
 Trends in Analog PLLs:
 Sub-Sampling:  Time-Amplification:
14 GHz Integer-N Sub-Sampling PLL A 25.8GHz Integer-N PLL with Time-
With RMS-Jitter of 85.4 fs Occupying an Amplifying PFD achieving 60fsrms Jitter, -
Ultra Low Area of 0.0918mm 252.8dB FoMJ, and Robust Lock Acquisition
Performance

D. Kar, S. Mohapatra, M. A. Hoque and D. Heo, "A 14 GHz Integer-N X. Geng, Y. Tian, Y. Xiao, Z. Ye, Q. Xie and Z. Wang, "A 25.8GHz Integer-N PLL With
Sub-Sampling PLL With RMS-Jitter of 85.4 fs Occupying an Ultra Low Time-Amplifying Phase-Frequency Detector Achieving 60fsrms Jitter, -252.8dB FoMJ,
Area of 0.0918 mm 2," in IEEE Transactions on Circuits and Systems I and Robust Lock Acquisition Performance," 2022 IEEE International Solid-State
Circuits Conference (ISSCC), San Francisco, CA, USA, 2022, pp. 388-390

ISSCC 2024 - Forum 6.4: Modulation schemes 12

© 2024 IEEE for ultra-high-speed transceivers
International Solid-State Circuits Conference
 High Frequency Synthesis >100GHz
 A 264-to-287GHz, −2.5dBm Output Power,  A 47fsrms-Jitter and 26.6mW 103.5GHz PLL
and −92dBc/Hz 1MHz-Phase-Noise CMOS with Power-Gating Injection-Locked
Signal Source Adopting a 75fsrms Jitter D- Frequency-Multiplier-Based Phase Detector
Band Cascaded Sub-Sampling PLL and Extended Loop Bandwidth

B. -T. Moon, S. -G. Lee and J. Choi, "24.2 A 264-to-287GHz, −2.5dBm Output J. Bang, J. Kim, S. Jung, S. Park and J. Choi, "4.6 A 47fsrms-Jitter and 26.6mW
Power, and −92dBc/Hz 1MHz-Phase-Noise CMOS Signal Source Adopting a 75fsrms 103.5GHz PLL with Power-Gating Injection-Locked Frequency-Multiplier-Based
Jitter D-Band Cascaded Sub-Sampling PLL," 2023 IEEE International Solid-State Phase Detector and Extended Loop Bandwidth," 2023 IEEE International Solid-
Circuits Conference (ISSCC), San Francisco, CA, USA, 2023, pp. 364-36 State Circuits Conference (ISSCC), San Francisco, CA, USA, 2023, pp. 84-86

ISSCC 2024 - Forum 6.4: Modulation schemes 13

© 2024 IEEE for ultra-high-speed transceivers
International Solid-State Circuits Conference
 Trends in high-speed ADCs

© 2024 IEEE
International Solid-State Circuits Conference
 High Speed ADC

Since our original publication at ISSCC

2008, the architecture of high-speed
ADCs for wireline transceivers did not
change much:
• Time interleaved
• SAR-Based ADC
The main challenges are:
• AFE Bandwidth
• Multi-phase generation
• Timing mismatch
• Clock Jitter
• Power consumption
• Size
P. Schvan et al., "A 24GS/s 6b ADC in 90nm CMOS," 2008 IEEE
International Solid-State Circuits Conference - Digest of Technical Papers,
San Francisco, CA, USA, 2008, pp. 544-63

ISSCC 2024 - Forum 6.4: Modulation schemes 15

© 2024 IEEE for ultra-high-speed transceivers
International Solid-State Circuits Conference
 Time Interleaved ADC

Performance curve showing both SNDR and ENOB as a function of the output frequency of an 8-bit
time-interleaved ADC operating at a sampling rate of 68GS/s and fabricated in 28nm CMOS SOI.
Y. Greshishchev et al “A 60 GS/s 8-b DAC with > 29.5dB SINAD up to Nyquist frequency in 7nm FinFET CMOS” 2019 IEEE BiCMOS and Compound Semiconductor
Integrated Circuits and Technology Conference

ISSCC 2024 - Forum 6.4: Modulation schemes 16

© 2024 IEEE for ultra-high-speed transceivers
International Solid-State Circuits Conference
 224G PAM-4 Receiver Block Diagram

Y. Segal et al., “A 1.41pJ/b 224Gb/s PAM-4 SerDes Receiver with 31dB Loss Compensation,” in Proc. IEEE Int. Solid-State Circuits Conf. (ISSCC),
2022, pp. 114-115.

ISSCC 2024 - Forum 6.4: Modulation schemes 17

© 2024 IEEE for ultra-high-speed transceivers
International Solid-State Circuits Conference
 Resonant AFE

Silicon performance:
✓ The AFE and ADC supports
up to 25-dB boost and 18-dB
gain at a peak frequency of 53
GHz.
✓ Power consumption is 49mW.
✓ CMOS5nm

 Linear equalization using a passive RLC resonant technique

 The degeneration capacitance Cd controls the mid-band boost. A. Khairi et al., "A 1.41-pJ/b 224-Gb/s PAM4 6-bit ADC-Based SerDes Receiver With Hybrid
 Complementary gm to maximize the transconductance AFE Capable of Supporting Long Reach Channels," in IEEE Journal of Solid-State Circuits,
vol. 58, no. 1, pp. 8-18, Jan. 2023, doi: 10.1109/JSSC.2022.3211475.
 The differential offset is continuously compensated by a
differential current source.
 Ringing can be corrected by reducing the Q of CTLE

ISSCC 2024 - Forum 6.4: Modulation schemes 18

© 2024 IEEE for ultra-high-speed transceivers
International Solid-State Circuits Conference
 Clock and Data Recovery For Serdes

Generic ADC-based RX. Dashed lines

represent the jitter critical clocking path.

CML Based Phase Rotator

I. Ozkaya et al., “A 60-Gb/s 1.9-pJ/bit NRZ Optical Receiver CMOS Based Diamond Phase Rotator
With Low Latency Digital CDR in 14-nm CMOS FinFET,” IEEE J.
Solid-State Circuits, vol. 53, no. 4, pp. 1227-1237, Feb. 2018 J Pike et al, “Phase Rotator Topologies for Wireline Transceivers” Submitted to
JSSC

ISSCC 2024 - Forum 6.4: Modulation schemes 19

© 2024 IEEE for ultra-high-speed transceivers
International Solid-State Circuits Conference
 Trends in high-speed DACs

© 2024 IEEE
International Solid-State Circuits Conference
 High Speed DAC

Y. Greshishchev et al., "A 60 GS/s 8-b DAC with > 29.5dB SINAD up to Nyquist frequency
in 7nm FinFET CMOS," 2019 IEEE BiCMOS and Compound semiconductor Integrated
Circuits and Technology Symposium (BCICTS), Nashville, TN, USA, 2019, pp. 1-4

ISSCC 2024 - Forum 6.4: Modulation schemes 21

© 2024 IEEE for ultra-high-speed transceivers
International Solid-State Circuits Conference
 SERDES Tx: 2-bit DAC + FIR

J. Im et al., "A 112-Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way M. -A. LaCroix et al., "8.4 A 116Gb/s DSP-Based Wireline Transceiver in 7nm CMOS
Time-Interleaved SAR ADC and Inverter-Based RX Analog Front-End in 7-nm Achieving 6pJ/b at 45dB Loss in PAM-4/Duo-PAM-4 and 52dB in PAM-2," 2021 IEEE
FinFET," in IEEE Journal of Solid-State Circuits, vol. 56, no. 1, pp. 7-18, Jan. 2021 International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA,
2021, pp. 132-134

ISSCC 2024 - Forum 6.4: Modulation schemes 22

© 2024 IEEE for ultra-high-speed transceivers
International Solid-State Circuits Conference
 SERDES DAC

J. Kim et al., "A 224-Gb/s DAC-Based PAM-4 Quarter-Rate Transmitter With 8-Tap FFE in 10-nm FinFET," in IEEE Journal of Solid-State Circuits, vol. 57, no. 1, pp. 6-20, Jan. 2022

ISSCC 2024 - Forum 6.4: Modulation schemes 23

© 2024 IEEE for ultra-high-speed transceivers
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 High Speed DAC and Time Domain Muxing

D. Widmann et al, “A Time-Interleaved Digital-to-Analog Converter up to 118 GS/s With Integrated Analog Multiplexer in 28-nm FD-SOI CMOS Technology”
IEEE Journal of Solid-State Circuits, pp. 1--15, 2023

ISSCC 2024 - Forum 6.4: Modulation schemes 24

© 2024 IEEE for ultra-high-speed transceivers
International Solid-State Circuits Conference
 High Speed DAC and Frequency Interleaving

Conceptual block diagram of the

frequency-interleaved DAC (FI-DAC)
and the FI-ADC, each based on an
analog processing system consisting
of mixers and filters

ISSCC 2024 - Forum 6.4: Modulation schemes 25

© 2024 IEEE for ultra-high-speed transceivers
International Solid-State Circuits Conference
 Optical Frequency Interleaving

C. Schmidt et al., "Data Converter Interleaving: Current Trends and Future Perspectives," in IEEE Communications Magazine, vol. 58, no. 5, pp. 19-25, May 2020

ISSCC 2024 - Forum 6.4: Modulation schemes 26

© 2024 IEEE for ultra-high-speed transceivers
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 Comparison of interleaving concepts

Electrical interleaving will be pursued in the next couple of years enabling broad-bandwidth
single-wavelength transceivers. Later, optical interleaving will complement the electrical approach
allowing waveforms spanning multiple Terahertz of bandwidth, which would enable truly flexible
optical networks.
C. Schmidt et al., "Data Converter Interleaving: Current Trends and Future Perspectives," in IEEE Communications Magazine, vol. 58, no. 5, pp. 19-25, May 2020

ISSCC 2024 - Forum 6.4: Modulation schemes 27

© 2024 IEEE for ultra-high-speed transceivers
International Solid-State Circuits Conference
 Coherent 1.6Tb/s Optical Transceiver

400Gb/s per dimension

© 2024 IEEE
International Solid-State Circuits Conference
 Baud rates for different line rates and modulation formats assuming 28% FEC overhead and Dual Polarization

Higher order modulation provides higher spectral

efficiency but is more susceptible to noise.
Bandwidth increase is more efficient in increasing
capacity than snr improvement

𝐶 = 𝐵𝑊 ∗ 𝑙𝑜𝑔2 (𝑠𝑛𝑟 + 1)
(a) Without constellation shaping and (b)
with shaping [Roberts, 2016]
ISSCC 2024 - Forum 6.4: Modulation schemes 29
© 2024 IEEE for ultra-high-speed transceivers
International Solid-State Circuits Conference
 High Speed Optical Transceiver Requirements
Ciena’s WL6 @1600Gb/s

Net rate vs. symbol rate for high thruput applications

C. Schmidt et al., "Data Converter Interleaving: Current Trends and Future Perspectives," in IEEE Communications Magazine, vol. 58, no. 5, pp. 19-25, May 2020

ISSCC 2024 - Forum 6.4: Modulation schemes 30

© 2024 IEEE for ultra-high-speed transceivers
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 Coherent Innovation Economic value
Capacity, Cost, Power, Environment
160x Throughput Improvement – 1600G in 2024
1600 >90% reduction in
Watts/Gbps

800

400
200
100
10 40
Equivalent capacity per technology generation
2005 2008 2009 2012 2017 2020 2024
WL WL2 WL2 WL3 WLAI WL5E WL6

20 Years of Leading Innovation – E/O & DSP

130nm 90nm CMOS 32nm CMOS 28nm 7nm 3nm

BiCMOS FD SOI FinFET FinFET
2005 2008 2012 2017 2020 In development
10GBd 14Gbd 35GBd 56GBd 95GBd WL3 – 100G WLAi – 400G WL5 – 800G WL6 – 1600G
100 - 200GBd

ISSCC 2024 - Forum 6.4: Modulation schemes 31

© 2024 IEEE for ultra-high-speed transceivers
International Solid-State Circuits Conference
 Coherent transceiver block diagram

ISSCC 2024 - Forum 6.4: Modulation schemes 32

© 2024 IEEE for ultra-high-speed transceivers
International Solid-State Circuits Conference
 Digital Signal Processing: Coherent receiver
Dispersion Polarization Carrier
Comp. Comp. Recovery

A/D FIR FI
xpol A/D R xpol (equalized)
FI
R exp(-
FI j*φ(t))
R
FI
ypol A/D
A/D FIR ypol (equalized)
R

• Filtering coefficients are adapted to

minimize SNR at the decision device
ISSCC 2024 - Forum 6.4: Modulation schemes 33
© 2024 IEEE for ultra-high-speed transceivers
International Solid-State Circuits Conference
 Digital Signal Processing: Coherent receiver
~ ~ ~
| Rx + A |2 =| Rx |2 + A2 + 2 Re[ ARx ]
  Rx = R1 + j  R2
coherent signal
~ PIN Rx SoC
Input Signal Rx
R1
DP-QPSK PBS 90-deg LPF
R2
A/D
~ Hybrid LPF A/D Digital
Ry Signal
LPF
R3
90-deg A/D Processing
R4
Hybrid LPF A/D

R y = R3 + j  R4
Rx Laser A
‘LO’
 Rx  hxx hyx   E x 
Channel  R  = h    , E x & E y are transmitted
Model:  y   xy hyy   E y 
 Eˆ x  c xx c yx   Rx 
Function of ˆ =  R 
coherent Rx:  y   xy
E c c yy   y 

to minimize mean square error = | E x -Eˆ x |2 + | E y -Eˆ y |2

ISSCC 2024 - Forum 6.4: Modulation schemes 34
© 2024 IEEE for ultra-high-speed transceivers
International Solid-State Circuits Conference
 Optical Impairments by Type
“DSP Loops”
DSP filtering
Effects of Chromatic Dispersion
Dispersion Phase noise
100 km of fiber

1 3
0 0
0
p
s
Effects of Polarization Mode Dispersion
0
p
s

DSP tracking
Amplitude
Polarization
noise

X-pol PDL Y-pol

Strong FEC

ISSCC 2024 - Forum 6.4: Modulation schemes 35

© 2024 IEEE for ultra-high-speed transceivers
International Solid-State Circuits Conference
 Pulse Shaping
Time Domain Frequency Domain
High tolerance to jitter – higher bandwidth

Standard

a = 1.0

SNR as a function of pulse

shaping and untracked jitter.
a = 0.5

C. Laperle, N. Ben-Hamida and M. O'Sullivan,

"Advances in High-Speed DACs, ADCs, and DSP
for Software Defined Optical Modems," 2013
a = 0.14 IEEE Compound Semiconductor Integrated
Circuit Symposium (CSICS), Monterey, CA, USA,
2013, pp. 1-4

Smaller bandwidth – less tolerance to jitter

ISSCC 2024 - Forum 6.4: Modulation schemes 36
© 2024 IEEE for ultra-high-speed transceivers
International Solid-State Circuits Conference
 Time-Domain and Frequency-Domain Equalization
Time-domain
In t-N/2 t-N/2+1 t0 tN/2-1 tN/2

h-N/2 h-N/2+1 h0 hN/2-1 hN/2

Adaptive
[h] Algorithm

Out
Adaptive
Algorithm

Frequency-domain HN-1

tN-1 t’N-1
HN-2 Given a filter length of N taps operating on N samples
tN-2 t’N-2 ◼ Time domain complexity O(N2)
HN/2
◼ Frequency domain complexity O(N x log2(N)) ;
tN/2 t’N/2 N~radix2
HN/2-1
CFFT ICFFT
◼ Power dissipation at a given process node ~
tN/2-1 t’N/2-1
complexity
H1
For 115 Gb/s DP-QPSK and 1500 km of G.652 fiber,
t1
H0
t’1
dispersion spreads across ~160 T/2 samples
See, for example, R. Kudo et al., JLT, v.27 No.16 pp. 3721-3728 (2009).
t0 t’0

ISSCC 2024 - Forum 6.4: Modulation schemes 37

© 2024 IEEE for ultra-high-speed transceivers
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 Coherent Optical DSP Chip
Overview
Technology 28nm FD-SOI
DAC Die Size 18.4 x 18.4 mm2
Gate Count 484 Mgates
100 Mbit SRAM
Package 1661 FC-BGA

ARM Tx Filter Key Analog Macros

ADC 80 GS/s, 35 GHz BW, 8b
DAC 80 GS/s, 35 GHz BW, 8b
PLL 40 GHz
SerDes 16 x 28 Gb/s

SerDes
Encryption
ADC Client Interfaces & IP
Rx Filter
Client n x 100GE over CAUI
1 x 400GE over CDAUI
n x OTU-4 over OTL4.4
1 x OTUC4 over 4 x OTL4.4
Encryption 256-AES per ODUFlex, ODU4
25G Flex Rate Granularity

BDA FEC

ISSCC 2024 - Forum 6.4: Modulation schemes 38

© 2024 IEEE for ultra-high-speed transceivers
International Solid-State Circuits Conference
 Coherent 1.6Tb/s Optical Transceiver
 Requirements

ISSCC 2024 - Forum 6.4: Modulation schemes 39

© 2024 IEEE for ultra-high-speed transceivers
International Solid-State Circuits Conference
 Industry’s first 200GBaud Modem in 3nm
OE S21 RF Response EO S21 RF Response

100GHz 100GHz
ICR CDM

200GBaud, 1.6Tb/s

N3E ADC bandwidth testing results

© 2024 IEEE
International Solid-State Circuits Conference
 400ZR Coherent Pluggable

Best in class performance and minimum

power consumption
Performance margin across adjustable
optical output power range

ISSCC 2024 - Forum 6.4: Modulation schemes 41

© 2024 IEEE for ultra-high-speed transceivers
International Solid-State Circuits Conference
 Rich Modulation Formats for 400Gb/s

Pulsed Amplitude Modulation (PAM) and Discrete

Muti-Tone (DMT)

© 2024 IEEE
International Solid-State Circuits Conference
 BER vs SNDR for PAM2-4-6-8-12-16

1e-2

1e-4

6dB 1e-6

ISSCC 2024 - Forum 6.4: Modulation schemes 43

© 2024 IEEE for ultra-high-speed transceivers
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 Electrical Testbed

• Calculate LMS estimate of channel impulse response

• Inverse impulse response estimate is used for FIR equalization.
• Select LMS estimate to maximize post-equalization SNR.

ISSCC 2024 - Forum 6.4: Modulation schemes 44

© 2024 IEEE for ultra-high-speed transceivers
International Solid-State Circuits Conference
 Electrical Testbed Results

7nm measurement results: SNR and BER results for different residual channel loss

ISSCC 2024 - Forum 6.4: Modulation schemes 45

© 2024 IEEE for ultra-high-speed transceivers
International Solid-State Circuits Conference
 3nm 224G Measurement Results

112Gb/s PAM-4 224Gb/s PAM-4

ISSCC 2024 - Forum 6.4: Modulation schemes 46

© 2024 IEEE for ultra-high-speed transceivers
International Solid-State Circuits Conference
 High voltage driver: Potential designs

H. Li et al., "A 3-D-Integrated Silicon Photonic Microring-Based 112-Gb/s PAM-4 J. Rafique, T. Nguyen and S. P. Voinigescu, "A 4.6V, 6-bit, 64GS/s Transmitter in
Transmitter With Nonlinear Equalization and Thermal Control," in IEEE Journal of 22nm FDSOI CMOS," 2019 IEEE BiCMOS and Compound semiconductor Integrated
Solid-State Circuits, vol. 56, no. 1, pp. 19-29, Jan. 2021 Circuits and Technology Symposium (BCICTS), Nashville, TN, USA, 2019, pp. 1-4

ISSCC 2024 - Forum 6.4: Modulation schemes 47

© 2024 IEEE for ultra-high-speed transceivers
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 3.5V Driver in 3nm

NRZ 112Gb/s

PAM-4 112Gb/s
ISSCC 2024 - Forum 6.4: Modulation schemes 48
© 2024 IEEE for ultra-high-speed transceivers
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 224GS/s System for 400Gb/s

Measurement: 3nm 1.6T chip used in PAM 4

application
ISSCC 2024 - Forum 6.4: Modulation schemes 49
© 2024 IEEE for ultra-high-speed transceivers
International Solid-State Circuits Conference
 224G SerDes Applications

ISSCC 2024 - Forum 6.4: Modulation schemes 50

© 2024 IEEE for ultra-high-speed transceivers
International Solid-State Circuits Conference
 Channel Loss by FEC/MLSD Options
MLSD Options
Low High
No
Power Power
Terminated
77 88 99
FEC Custom FEC
Options
Terminated
44 55 66
KP4 FEC

Unterminated 1 2 3

3.5dB SNR margin: Inner soft-decoding

Latency: 5-8ns on top of KP4 latency

ISSCC 2024 - Forum 6.4: Modulation schemes 51

© 2024 IEEE for ultra-high-speed transceivers
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 Discrete Multi-Tone Quick Overview
 DMT uses a series of uniformly separated subcarriers to transmit
data, where each subcarrier uses QAM-n modulation
 The richness of modulation is adjusted based on the available
SNR within each subcarrier to maximize the number of bits per
symbol within that subcarrier
 Flexible modulation on each of the subcarriers allows DMT to
compensate for link impairments and allow the best use of the
available channel bandwidth and signal SNR
 Frequency domain calculations with efficient IFFT & FFT
implementations
 Transmit data is assembled in the frequency domain before
passing through an IFFT and high-speed DAC
 Receive DMT data is digitized using a high-speed ADC, converted
back into the frequency domain via FFT where subcarrier
amplitude and phase are mapped into received data

ISSCC 2024 - Forum 6.4: Modulation schemes 52

© 2024 IEEE for ultra-high-speed transceivers
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 DMT:BER vs SNDR for QAM-4-256

SNR 1e-2

1e-4
Low SNR High SNR
1e-6

ISSCC 2024 - Forum 6.4: Modulation schemes 53

© 2024 IEEE for ultra-high-speed transceivers
International Solid-State Circuits Conference
 Block diagram of a DMT transceiver

Z. Jiang, H. Beshara, J. Lam, N. Ben-Hamida and C. Plett, "High Speed DMT for 224 Gb/s and Faster Wireline Transmission," in IEEE Transactions on Circuits and
Systems I: Regular Papers, vol. 70, no. 4, pp. 1758-1771, April 2023,

ISSCC 2024 - Forum 6.4: Modulation schemes 54

© 2024 IEEE for ultra-high-speed transceivers
International Solid-State Circuits Conference
 Channel Model

• Measured characteristics of a 14” PCB line used for board transmission

characterization showing worsening frequency response and group delay over
14 GHz
• Conventional NRZ/PAM-4 dependent on high frequency characteristics- high
group delay and worsening magnitude response degrades received signal eye
and introduces inter-symbol interference (ISI)

ISSCC 2024 - Forum 6.4: Modulation schemes 55

© 2024 IEEE for ultra-high-speed transceivers
International Solid-State Circuits Conference
 BER vs sub-channel and bit loading

ISSCC 2024 - Forum 6.4: Modulation schemes 56

© 2024 IEEE for ultra-high-speed transceivers
International Solid-State Circuits Conference
 Pre and post compensation

BER for the DMT system at different data rates with both transmit pre-compensation and
receive-side post compensation applied and with only receive-side post-compensation
ISSCC 2024 - Forum 6.4: Modulation schemes 57
© 2024 IEEE for ultra-high-speed transceivers
International Solid-State Circuits Conference
 Test bed setup

ISSCC 2024 - Forum 6.4: Modulation schemes 58

© 2024 IEEE for ultra-high-speed transceivers
International Solid-State Circuits Conference
 DMT test result: 400Gb/s, 112GS/s

Plot of the frequency plan for the 252 to 400 Plot of the measured BER vs sub-channel
Gb/s measurement run showing constellation frequency for the 252 to 400 Gb/s DMT runs
size vs sub-channel frequency

ISSCC 2024 - Forum 6.4: Modulation schemes 59

© 2024 IEEE for ultra-high-speed transceivers
International Solid-State Circuits Conference
 DMT test result

Plot of DMT simulated and measured BER vs data

Measurement of the received constellation for rate for different transmission rates, both with and
different bit loading without transmit pre-compensation in comparison to
measured PAM BER results

ISSCC 2024 - Forum 6.4: Modulation schemes 60

© 2024 IEEE for ultra-high-speed transceivers
International Solid-State Circuits Conference
 448Gb/s: DMT vs PAM

FEC PAM-4 PAM-6 PAM-8 DMT

1e-2 Baud rate 240G 185G 160G 135G
SNR [dB] 14.9 18.7 21.2 7.3-27.5
Latency KP4+10% KP4+10% KP4+10% KP4+20%
1e-6 Baud rate 224G 173G 150G 125G-135G
SNR [dB] 20.7 24.4 27 13.5-33
Latency KP4+10% KP4+10% KP4+10% KP4+20%

 Power: For long reach Serdes requiring a larger number of taps, frequency
domain correction is advantageous over time domain.
 Latency: Both advanced FEC and DMT add to the latency, but it can be
minimized.

ISSCC 2024 - Forum 6.4: Modulation schemes 61

© 2024 IEEE for ultra-high-speed transceivers
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 Conclusions
 We have a transceiver with a 100GHz bandwidth sampling at 224GS/s in 3nm
Silicon
 We see a path for 400Gb/s using rich modulation format PAM4-6-8 or DMT
◼ Dependent on power/area/latency tradeoff
 DAC Monolithic CMOS implementation is the preferred solution for
◼ DAC Analog Muxing
◼ High Voltage Driver
 ADC can benefit from Analog Demuxing as well
 Better DSP needed for:
◼ Channel Compensation
◼ Higher coding gain FEC implementation
◼ Analog impairment correction

ISSCC 2024 - Forum 6.4: Modulation schemes 62

© 2024 IEEE for ultra-high-speed transceivers
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 Please Scan to Rate
This Paper

ISSCC 2024 - Forum 6.4: Modulation schemes 63

© 2024 IEEE for ultra-high-speed transceivers
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 Backup

ISSCC 2024 - Forum 6.4: Modulation schemes 64

© 2024 IEEE for ultra-high-speed transceivers
International Solid-State Circuits Conference
 DMT System Model Using Matlab

Data Rec
Source
IFFT DAC ADC FFT
Data
Sample&Hold

Channel Model

Matlab

Channel Channel
Compensation Compensation
• Base DMT system- relies on multiple independent channels
• Less susceptible to ISI, varying frequency response
ISSCC 2024 - Forum 6.4: Modulation schemes 65
© 2024 IEEE for ultra-high-speed transceivers
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 Crest factor vs SNR

Overall SNR vs Crest Factor for Different Quantization Bits

ISSCC 2024 - Forum 6.4: Modulation schemes 66

© 2024 IEEE for ultra-high-speed transceivers
International Solid-State Circuits Conference
 Cyclic Prefix

BER and data rate with varied CP length in a 280Gb/s DMT simulation

ISSCC 2024 - Forum 6.4: Modulation schemes 67

© 2024 IEEE for ultra-high-speed transceivers
International Solid-State Circuits Conference
 PAM vs DMT

DMT test setup

PAM test setup

ISSCC 2024 - Forum 6.4: Modulation schemes 68

© 2024 IEEE for ultra-high-speed transceivers
International Solid-State Circuits Conference
 PAM vs DMT: Simulation results

Comparison of simulated BER vs. data rate of Comparison of simulated BER vs. data rate of
conventional SERDES systems (varied from NRZ to conventional SERDES systems and DMT with and
PAM-16 with no DFE and a 50-tap ideal DFE) without the described pre-correction algorithm

ISSCC 2024 - Forum 6.4: Modulation schemes 69

© 2024 IEEE for ultra-high-speed transceivers
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 ISSCC 2024 Forums

Silicon Photonics-Based High-Throughput

Optical Transceivers

Mayank Raj

ISSCC 2024 - Forum 6.5: Silicon Photonics- 1 of 50

© 2024 IEEE Based High-Throughput Optical Transceivers
International Solid-State Circuits Conference
 Outline
 Why Si-Pho?
 PIC Design
◼ TX Architecture
◼ MRM
◼ RX Architecture
◼ CRR
 EIC Design
◼ EIC Architecture
◼ TIA
◼ Driver
◼ Common CDR
 WDM Optical Link Measurement Results
 Summary

ISSCC 2024 - Forum 6.5: Silicon photonics 2 of 50

© 2024 IEEE based high throughput optical transceivers
International Solid-State Circuits Conference
 Computing Trend: Distributed/Disaggregated
1e15

1e14
Model Size: ~2x/4months
Model Parameters

1e13

GPT4
1e12
Megtron-Turing NLG PaLM
Gopher PaLM2
GPT3
1e11 LLaMA2

Turing-NLG
1e10 T5
Megtron-LM

1e9 GPT2
BERT Large
ELMo
1e8
2017 2018 2019 2020 2021 2022 2023 2024 2025 2026
Year
Source: Meta, Optica Photonic-Enabled Cloud Computing, 2023

 AI model size scaling dramatically!

 Trend: parallelism, distributed/disaggregated compute nodes
 Need: high BW, low-power, low-latency, and long-reach link

ISSCC 2024 - Forum 6.5: Silicon photonics 3 of 50

© 2024 IEEE based high throughput optical transceivers
International Solid-State Circuits Conference
 Electrical Link Will Have Reach Issue
Source : ISSCC 2022 Wireline Trend 30 dB chip-to-chip loss budget

11” PCB reach

(2 dB/inch @28 GHz)

5” PCB reach
(3 dB/inch @56 GHz)

112Gbps 224Gbps

PKG BGA breakout Budget for PCB

Source: OIF/IEEE conferences

 Data rate is growing ~2x every 3-4 years

 Running into reach/distance issue at +100 Gbps, higher cost
 In-package Si-Photonics transceiver is a potential solution

ISSCC 2024 - Forum 6.5: Silicon photonics 4 of 50

© 2024 IEEE based high throughput optical transceivers
International Solid-State Circuits Conference
 Optical Link Application
Our Focus

ASIC
Substrate
ASIC
System Board

Top View Side View

 Optical error free w/o FEC – important for compute applications

 External laser to alleviate heating issues
 Single mode – (10m-2km)
 Energy efficient
ISSCC 2024 - Forum 6.5: Silicon photonics 5 of 50
© 2024 IEEE based high throughput optical transceivers
International Solid-State Circuits Conference
 Metrics for Optical Link

Metric Spec
Aggregate Bandwidth +10 Tbps
Energy per bit 2.5 pJ/bit
Edge Bandwidth 1 Tbps/mm
Link latency 200 ns + TOF
Link reach 100m+
BER 1e-12

ISSCC 2024 - Forum 6.5: Silicon photonics 6 of 50

© 2024 IEEE based high throughput optical transceivers
International Solid-State Circuits Conference
 MCM Prototype
Proxy Core IC EIC 50Gb/s x7
Pat. RXSerDes
Serdes V-groove (250µm
(not used)
&TIA
Checker Driver & TIA pitch) fiber attach

Organic Interposer CRRs, PDs (PIC)

BGA

 Electrical IC (EIC) RX input directly on top of the Photonic IC (PIC) using Cu-
pillar bumps
 15-fiber array with a 250 μm pitch via V-grooves
ISSCC 2024 - Forum 6.5: Silicon photonics AMD generated image for illustrative 7 of 50
© 2024 IEEE based high throughput optical transceivers purposes only
International Solid-State Circuits Conference
 PIC

ISSCC 2024 - Forum 6.5: Silicon photonics 8 of 50

© 2024 IEEE based high throughput optical transceivers
International Solid-State Circuits Conference
 PIC Architecture: TX
Channel Spacing = Channel Spacing =
1.5nm 1.5nm
1 15 1 15

Channel Spacing = Channel Spacing =

0.75nm 8 MRMs 0.75nm
1 2 15 16 1 2 15 16

Channel Spacing = Channel Spacing =

1.5nm 1.5nm
2 16 2 16

8 MRMs
 16x WDM 1.5 nm channel spacing, large enough to avoid inter-modulation
 Cartoon shows one bank. There are six banks per PIC
ISSCC 2024 - Forum 6.5: Silicon photonics 9 of 50
© 2024 IEEE based high throughput optical transceivers
International Solid-State Circuits Conference
 What is a Micro Ring Modulator (MRM)?
Input κt Output

 Resonant-based modulator

 Phase shift using depletion mode p n

 Junction design controls Modulation

Efficiency κd
Drop
1

 Q controls optical BW designed by Kt 0.8 1

(transmission coupling coefficient)

Transmission
Vnp =0V
0.6
Vnp =1.8V

0.4
 Kd (drop coupling coefficient) + insertion 0

loss in ring to Kt for critical coupling 0.2

0
1308 1309 1310 1311 1312
Wavelength(nm)

ISSCC 2024 - Forum 6.5: Silicon photonics 10 of 50

© 2024 IEEE based high throughput optical transceivers
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 Why MRM?
EAM* MRM** MZM***
Temperature Sensitivity Medium High Low
Size ~10 µm x 50 µm ~10 µm x 10 µm 0.5 mm-5 mm
Electro-Optical Bandwidth High Medium-High Medium-High
Capacitive load Low Low High
Optical Bandwidth Medium Medium High
Modulation Efficiency Medium High-Medium High-Medium
Wavelength 1550 nm 1310 nm/1550 nm 1310 nm/1550 nm

*Electro Absorption Modulator **Micro Ring Modulator *** Mach Zehnder Modulator

 Wavelength selective unlike EAM (naturally suited for WDM)

 Smaller than an MZM

ISSCC 2024 - Forum 6.5: Silicon photonics 11 of 50

© 2024 IEEE based high throughput optical transceivers
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 MRM Junction Design
 Lateral Junction Lateral Junction
0.5
◼ Conventional design
◼ Less sensitive to doping conditions

Z (µm)
n++ p++
0
◼ Less efficient overlap with mode
◼ “Wasted” junction capacitance (Cj) -0.5
-1 0 1
X (µm)

 Vertical Junction Vertical Junction

0.5
◼ Slightly higher Cj

Z (µm)
◼ More sensitive to doping condition 0
◼ Better junction overlap with the light
◼ More sensitive to doping condition -0.5
-1 0 1
◼ ~1.5x better modulation efficiency (ME) X (µm)

ISSCC 2024 - Forum 6.5: Silicon photonics 12 of 50

© 2024 IEEE based high throughput optical transceivers
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 MRM Transfer Function and OMA
1
 Design for critical coupling 𝑇 𝑓 =
𝑓𝑜2
1+ 2 2
4𝑄 𝑓 − 𝑓𝑜
 Slope of T(f) is maximized 1 5
when T(f) = 0.25 (for any 4
Q) 3
0.75
2

Transmission

Slope (/nm)
1
1
 𝑓max _𝑠𝑙𝑜𝑝𝑒 = 𝑓𝑜 1 − 0.5 0
2 3𝑄
-1
-2
 Choose laser λ for max 0.25
-3
optical modulation -4
amplitude(OMA) 0 -5
1309 1309.5 1310 1310.5 1311
Wavelength (nm)

ISSCC 2024 - Forum 6.5: Silicon photonics 13 of 50

© 2024 IEEE based high throughput optical transceivers
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 TX Heater Loop
 Stabilization across process variation & temperature
1

change 0.8 Input Output

Transmission
DSP 0.6
PIC
Low-speed
1. DC loop sets the IDAC code 0.4
PD 0.25
2. Sweep the thermal DAC code 0.2
to find the maximum IDAC value
Tx RM TIA Slicer
CapFF 0
3. Initialize the thermal DAC to 1308 1309 1310 1311 1312
Vcm_set value that gives max OMA based Wavelength(nm)
Heater
on the known shape of the ring 100
Uncorrelated
UnCorrr. modulator drop port output. Input
Clk.
Clk 80 75%
4. Freeze the DC loop. Monitor
IDAC

Drop (%)
the avg. power by looking no of 60
1s and 0s.
40 Drop
5. Keep the avg power fixed by
changing DAC code to maintain 20
50%1s and 50% 0s.
DAC 0
1308 1309 1310 1311 1312
Thermal Wavelength(nm)

ISSCC 2024 - Forum 6.5: Silicon photonics

based high throughput optical transceivers 14 of 50
© 2024 IEEE
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 WDM: Channel Spacing vs. Crosstalk
1 -5

0.8 -10
Transmission

Crosstalk (dB)
0.6 -15

0.4 -20

0.2 -25
Left Right
Adjacent Channel Adjacent
0 -30
-2 -1 0 1 2 0.6 0.8 1 1.2 1.4 1.6 1.8 2
Wavelength – Resonant Wavelength (nm) Channel Spacing (nm)

 > 20 dB isolation for channel spacing > 1.2 nm at 50 Gb/s per channel

ISSCC 2024 - Forum 6.5: Silicon photonics 15 of 50

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 PIC Architecture: RX
Channel Spacing = Channel Spacing =
1.5nm 1.5nm
1 15 1 15

PD
Channel Spacing =
0.75nm

1 2 15 16

PD

PD
RX1 RX15

Channel Spacing = Channel Spacing =

1.5nm 1.5nm

PD
2 16 2 16

 16x WDM 1.5 nm channel

spacing
 Six banks/PIC

PD
PD

RX2 RX16

ISSCC 2024 - Forum 6.5: Silicon photonics 16 of 50

© 2024 IEEE based high throughput optical transceivers
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 Cascaded Ring Resonator (CRR) WDM Filter

IL 0dB
Through

Drop (dB)
-15dB
Drop

RX PD
λ
1.5nm
 <1.5 dB insertion loss (IL)
 Crosstalk of <15 dB
 1.5 nm channel separation M. Raj et al., ISSCC 2023
ISSCC 2024 - Forum 6.5: Silicon photonics 17 of 50
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 WDM Filter – Advantages of CRR Over RR

Through 0dB 0dB

Through

Drop (dB)

Drop (dB)
-15dB -15dB Drop
Drop

PD
RX
PD

RX
1.5nm λ 1.5nm λ
CRR RR
 40 dB/dec roll off → better channel isolation
 Flat top → better bandwidth
 Flat top → kinder to channel misalignment

ISSCC 2024 - Forum 6.5: Silicon photonics 18 of 50

© 2024 IEEE based high throughput optical transceivers
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 RX Heater Loop: Individual Tuning
To RX
datapath DSP
PIC
1. DC loop sets the IDAC code.
PD 2. Sweep the thermal DAC code A
CRM

to categorize filter to the correct

TIA shape and initialize DAC to the
Slicer correct location.
Heater Vcm_set
3. In tracking mode for shape A
UnCorrr. do a dither based max locking.
Clk
4. For shape B do a dither
IDAC

based min locking.

5. For shape C do dither based

B
max search then reset to the
mid point of the filter.
DAC

Thermal C
 Stabilization across process variation & temperature change
ISSCC 2024 - Forum 6.5: Silicon photonics 19 of 50
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 CRR Design: Improving Process Variation
 Racetrack design → longer coupling section
coupling Through
gaps

 Coupling gap can be wider

Drop

PD
RX
 Channel spacing implemented by vertical
spacers

 Same coupler design used in all eight filters

channel
spacers
RX1

PD

PD
RX7
ISSCC 2024 - Forum 6.5: Silicon photonics 20 of 50
© 2024 IEEE based high throughput optical transceivers
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 EIC

ISSCC 2024 - Forum 6.5: Silicon photonics 21 of 50

© 2024 IEEE based high throughput optical transceivers
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 EIC System Architecture
 One EIC die features 3 x 16 =
48 TX/RX lanes to achieve
2.544 Tb/s throughput

 One LCPLL per 16 TX & RX bank proxy IC

(i.e., per fiber)

 TX/RX/drop/heater bump
pitched matched to PIC (55 µm)
proxy IC
and supply bumps for EIC only
uses 36 µm pitch micro-bumps
for InFO

ISSCC 2024 - Forum 6.5: Silicon photonics

based high throughput optical transceivers 22 of 50
© 2024 IEEE
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 EIC TX

ISSCC 2024 - Forum 6.5: Silicon photonics 23 of 50

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 TX Output Driver
2Vdd - 1.8v
 T-Coil between the drains of the cascode
‘1’ eq.
devices ctrl
 Provides high frequency boost and helps in Din
“hiding” self-loading 0.9-1.8V

 Data rise and fall times are independently Doutb

controlled 0-1.8V
Vdd Tx
0.9v Bump
2.4 2.4
2.1 TX w/o T-coil 2.1 TX w T-coil
1.8 1.8
1.5 1.5
1.2 1.2
V (V)

V (V)

0.9 1.3V 0.9

2.9ps 1.6V 1.7ps Din
0.6 0.6
0.3 0.3 0-0.9V
‘0’ eq.
0.0 0.0
-0.3 -0.3 ctrl
-0.6 -0.6
0 4 8 12 16 20 24 28 32 36 40 0 4 8 12 16 20 24 28 32 36 40 0v
Time (ps) Time (ps) M. Raj et al., JSSC 2020
ISSCC 2024 - Forum 6.5: Silicon photonics
based high throughput optical transceivers 24 of 50
© 2024 IEEE
International Solid-State Circuits Conference
 T-Coil Structure
Out (m10)
600 30 µm
L1 (bottom) L2 (top)
550
L (pH)

500

20 µm
450

400
0 10 20 30 40 50 60
Frequency (GHz)

Top two metal layers stacked

k of ~0.7, SRF of ~90 GHz and
Q>5 at Nyquist
(m12) P N (m11)
ISSCC 2024 - Forum 6.5: Silicon photonics
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© 2024 IEEE
International Solid-State Circuits Conference
 Data Level Shifter
1.8v 1.8v
 Static biased cascode stage ‘1’ eq.
requires an upshifted logic ctrl
voltage (0.9V-1.8V)

PRBS Generators 20µmx30µm

 AC coupled latch is used to
128:1 Serializer

T-coil
achieve this. AC cap 200fF. 0.9v Tx
0-0.9v 0.9v
Bump
 Unlike passive AC coupling, 0.9v
the latch-based solution is
insensitive to CIDs as it has

EAM
memory
‘0’ eq.
ctrl
Programmable Sub-UI Laser
Pre Equalization 0v
ISSCC 2024 - Forum 6.5: Silicon photonics
based high throughput optical transceivers 26 of 50
© 2024 IEEE
International Solid-State Circuits Conference
 TX Architecture
1.8v 1.8v
‘1’ eq.
ctrl

On-chip sub-UI
20µmx30µm
eq. allows for PRBS Generators

128:1 Serializer

T-coil
larger fanout of
0.9v
the predriver 0.9v
Tx
Bump
stages without 0.9v
significantly
increasing ISI

EAM
induced jitter

‘0’ eq.
ctrl
Programmable Sub-UI Laser
Pre Equalization 0v
ISSCC 2024 - Forum 6.5: Silicon photonics 27 of 50
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 EIC RX

ISSCC 2024 - Forum 6.5: Silicon photonics 28 of 50

© 2024 IEEE based high throughput optical transceivers
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 TIA Architecture

8X <4> <4> 4X
4X <3> <3> 2X 80
70
2X <2> <2> 1X 60
1X <1> <1> 1X 50
5b

Zt (dB
5b
<0> <0> 1X 40 Zt 4k-6K
30
R3 R1 Photo 0.9A/W
20
BW > 35 GHz
0.12-1k 0.2-1.5k
Diode 10 Integ. Noise <3 µA
Voutb Rx µ
PD
Bump
InFo 0 105 106 107 108 109 1010 1011
Parasitic
gm3 gm2 gm1 E
S 25fF Parasitic 10fF Frequency (Hz)
D 25fF

 Single ended inverter-based TIA to utilize gm/C scaling

 T-coil peaking to reduce number of stages and save power
 Programmable NMOS-based resistor to control gain/BW

ISSCC 2024 - Forum 6.5: Silicon photonics 29 of 50

© 2024 IEEE based high throughput optical transceivers
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 TIA: Low Noise Design
𝟐 1.2V
𝟐 𝟏 𝑪𝒊𝒏 𝝎
𝒊𝟐𝒏 𝒊𝒏 ≈ 𝒊𝟐𝒏 𝒈𝒎 × 𝒁𝒕_𝒔𝒄𝒂𝒍𝒆𝒅 (𝝎) × × Regulator
(𝒈𝒎 𝑹𝒇 )𝟐 𝒈𝒎
0.9V M. Raj et al., JSSC 2020

Vout
Rx
Bump

Cin

 First invertor is the main noise source due to peaking from Cin
 Reduce Cin as much as possible—waveguide-based PD, no Power Grid (PG)
under bump
 Increase gm until it does not increase Cin
 Reduce parasitic and gate resistance in the Ipd path – use low fin mos
ISSCC 2024 - Forum 6.5: Silicon photonics 30 of 50
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 TIA DC Loop and PSRR
5b 5b

R3 R1 Photo 0.9A/W
0.12-1k 0.2-1.5k
Diode
To Slicers

Voutb Rx µ
PD
Bump
InFo Parasitic
Vcm2 gm3 gm2 gm1 E
S 25fF Parasitic 10fF
2b res 21k Cancel
D 25fF
w/o RC filter on

Diff. Output PSRR (dB)

- Low Pass
Average
- 3b 0
21k
+ 0-1.3mA Vcm
4b p
OTA PD Current -20
1.2V
w RC filter on
Vcm Improves -40 Vcm
Reg
4b n differential 𝑽𝒐𝒖𝒕𝒃 − 𝑽𝒄𝒎𝟐
PSRR 0.88V -60 𝟐𝟎𝒍𝒐𝒈𝟏𝟎
TIA 𝑺𝒖𝒑𝒑𝒍𝒚
Common Mode Gen. -80 5
10 106 107 108 109 1010 1011
Frequency (Hz)
 Regulated supply with DC loop and common mode gen

ISSCC 2024 - Forum 6.5: Silicon photonics 31 of 50

© 2024 IEEE based high throughput optical transceivers
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 Overall RX Architecture
5b 5b

R3 R1 Photo 0.9A/W
0.12-1k 0.2-1.5k
Deser. 4 +1 Diode
Voutb Rx µ
PD
Bump
InFo Parasitic
gm3 gm2 gm1 E
S 25fF Parasitic 10fF
PRBS Checker

12.5GHz 2b res 21k Cancel

D 25fF
4 -
Clk Low Pass - Average 3b 1.2V
64 +16

21k 0-1.3mA
+
4b p Reg
OTA PD Current range
0.88V
Vcm Improves
To TIA
differential
CDR 4b n
PSRR

Common Mode Gen.

 Voutb is directly fed to the four data and one error slicers
 Kickback matched on the Vcm and Voutb node
ISSCC 2024 - Forum 6.5: Silicon photonics 32 of 50
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 EIC CDR

ISSCC 2024 - Forum 6.5: Silicon photonics 33 of 50

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 Common CDR
select
RX µ- RX16
bump
16x
RX2
RX1

Common LC PLL
Regulator
RX µ- Error Time
bump 16x5 64x16x5 64x5
Single ended 8:64 16:1 MUX Interleaved
4 CDR
TIA Data
Data
Data
Data
Common
Mode Gen.

4 7b
16x7 PI Codes for 16 Channels 12.5GHz
ILO1 PI ILO2
Common 8 Common
PI ILO
12.5GHz ppm tracked

 Reference channel for ppm tracking globally

 Time-interleaved CDR updates local skew “slowly”
 Save power and area
ISSCC 2024 - Forum 6.5: Silicon photonics 34 of 50
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 Clock Generation for CDR
To Slicers
8

Common LC
ILO2 ILO1
Baud-rate CDR

12.5GHz 4 2 8 2 12.5GHz

PLL
S/D PI S/D

4 QED VtoI
Quadrature
Error Detector
Voltage to C1
Current

Proposed QLL
Proposed Quadrature Locked Loop (QLL)
 Baud-rate CDR with ILO-PI-ILO architecture
 QLL corrects I/Q mismatches and generates supply voltage
 Reference 12.5 GHz is generated by a common LC PLL
ISSCC 2024 - Forum 6.5: Silicon photonics 35 of 50
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 MEASUREMENTS

ISSCC 2024 - Forum 6.5: Silicon photonics 36 of 50

© 2024 IEEE based high throughput optical transceivers
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 Chip Micrographs

PIC
PRBS RX fiber
Blocked out Checker input
RX

Parallel interface (not used) Optical

Transceiver
Blocked out MRM CRR array
array

EIC: 7 nm FinFET PIC: 45 nm SOI

ISSCC 2024 - Forum 6.5: Silicon photonics AMD generated image for illustrative 37 of 50
© 2024 IEEE based high throughput optical transceivers purposes only
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 Measurement Setup
 Tunable laser source for 3.7dB ER 0dBm avg. power

wavelength sweep

 Reference modulator to
Tunable Laser Reference Variable Optical
generate optical data input Source Modulator Attenuator
PIC (DUT)

 Variable optical attenuator

for sensitivity
measurements

ISSCC 2024 - Forum 6.5: Silicon photonics AMD generated image for illustrative 38 of 50
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 RX OMA Sensitivity (BER 1e-12)
OMA Sensitivity for RX1 - RX7
OMA Sensitivity for RX1 - RX7
1E-02
1E-02
1E-03
1E-03
1E-04
1E-04 0.61
1E-05 0.61
1E-05 0.59
1E-06 0.59

TIA Output (V)

1E-06 0.57

TIA Output (V)

1E-07 0.57
BER
0.55
1E-07
BER

1E-08 0.550.53
1E-08
1E-09 0.530.51
1E-09 0.51
1E-10 0.49
0.49 -0.75
1E-10
1E-11 -1
-0.75
-0.5-0.25 00.250.250.50.750.751
-0.25
Delta
-1 Delta wavelength
0 from
-0.5wavelength 0.5 grid (nm)
1
1E-11
1E-12 Delta wavelength from
from grid (nm)grid
1E-12 Deltarx1+1.5dBm
wavelength from rx7 grid rx1
1E-13 rx1+1.5dBm rx7 rx1
1E-13 -17 -16 -15 -14 -13 -12 -11 -10
-17 -16 -15 -14 OMA (dBm)
-13 -12 -11 -10
OMA (dBm)
RX1 RX2 RX3 RX4 RX5 RX6 RX7
RX1 RX2 RX3 RX4 RX5 RX6 RX7

 RX1-RX7 show median sensitivity of -11.1 dBm OMA

 Sensitivity reduction in RX4 and RX1 → CRR insertion loss

ISSCC 2024 - Forum 6.5: Silicon photonics 39 of 50

© 2024 IEEE based high throughput optical transceivers
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 RX BER Bathtub Measurements
BERwith
BER with 1dB
1dB link
link margin
margin
1e-2
1E-02

1e-3
1E-03
1e-4
1E-04
1e-5
1E-05
RX1
RX1
1e-6
1E-06
RX2
RX2
BER
BER

1e-7
1E-07 RX3
RX3
1e-8
1E-08 RX4
RX4

1e-9
1E-09
RX5
RX5
RX6
RX6
1e-10
1E-10 RX7
RX7
1e-11
1E-11 14% over all RXs
1e-12
1E-12
20
20 30
30 40
40 50
50 60
60 70
70 80
80
%UI
%UI

 RX1-RX7 1e-12 error-free without FEC

◼ Despite RX5’s laser wavelength being off from the filter center by 200pm (due to
process variation)

ISSCC 2024 - Forum 6.5: Silicon photonics 40 of 50

© 2024 IEEE based high throughput optical transceivers
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 RX Internal 2D Eye Scans
1313nm
1313nm
RX1 1307nm
1307nm
RX5

211mV
1311.5nm RX2 1305.5nm RX6
1311.5nm 1305.5nm

211mV
1310nm
1310nm RX3 1304nm
1304nm
RX7

211mV
1308.5nm RX4
1308.5nm 1UI

0.5 1e-5 <1e-10

1UI
 RX1-RX7 show healthy vertical and horizontal eye openings
ISSCC 2024 - Forum 6.5: Silicon photonics 41 of 50
© 2024 IEEE based high throughput optical transceivers
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 RX2–RX3 Crosstalk

211mV
1e-4
1E-04 RX2 with
RX2with crosstalk
crostalk
fromRX3
from RX3
1e-6
1E-06 RX2nono
RX2 crosstalk w. crosstalk
crosstalk
BER
BER

211mV
1e-8
1E-08

1e-10
1E-10
no crosstalk
1e-12
1E-12 1UI
20
20 40
40 60
60 80
80
%UI
% UI
0.5 1e-5 <1e-10
 RX2-RX3 enabled at the same time using a 2-λ laser source
 Minimal crosstalk impact on vertical and horizontal eye margins

ISSCC 2024 - Forum 6.5: Silicon photonics 42 of 50

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 TX Optical Eye 50 Gb/s

λ=1308.04 nm ER: 3 dB

ISSCC 2024 - Forum 6.5: Silicon photonics AMD generated image for illustrative 43 of 50
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 424Gbps in a single fiber (8x53Gbps)

ISSCC 2024 - Forum 6.5: Silicon photonics 44 of 50

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 Full Link 2x WDM Demo

ISSCC 2024 - Forum 6.5: Silicon photonics AMD generated image for illustrative 45 of 50
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 Conclusions
 45 Gb/s/λ WDM Link

 424Gbps in a single fiber

 Error-free (BER<1e-12) performance w/o FEC

 Hybrid integration with EIC in 7 nm and PIC in 45 nm SOI process to get best
of both worlds

 EIC consumes < 1.6 pJ/bit. Each RX and TX channel only occupies 0.031mm2

 Median sensitivity of -11.1 dBm (OMA) across seven RX channels

ISSCC 2024 - Forum 6.5: Silicon photonics 46 of 50

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 Challenges
 Multi-lambda O-band laser development

 Manufacturing process improvements

ISSCC 2024 - Forum 6.5: Silicon photonics 47 of 50

© 2024 IEEE based high throughput optical transceivers
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 Acknowledgements
 The work is funded by DARPA PIPES contract HR0011-19-3-0004. The views,
opinions, and/or findings expressed are those of the authors and should not
be interpreted as representing the official views or policies of the Department
of Defense or the U.S. Government.

 The authors thank the AMD design, layout, and verification teams.

ISSCC 2024 - Forum 6.5: Silicon photonics 48 of 50

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 References
 M. Raj et al., "A O.96pJ/b 7 × 50Gb/s-per-Fiber WDM Receiver with Stacked 7nm CMOS and
45nm Silicon Photonic Dies," 2023 IEEE International Solid-State Circuits Conference (ISSCC),
San Francisco, CA, USA, 2023, pp. 11-13.
 M. Rakowski et al., "A 4×20Gb/s WDM ring-based hybrid CMOS silicon photonics
transceiver,"IEEE ISSCC Dig. Tech. Papers, Feb. 2015, pp. 1-3.
 M. Raj et al., “Design of a 50-Gb/s Hybrid Integrated Si-Photonic Optical Link in 16-nm FinFET,”
IEEE JSSC, pp. 1086-1095, Apr. 2020.
 C. F. Poon et al., "A 1.24-pJ/b 112-Gb/s (870 Gb/s/Mm) Transceiver for In-Package Links in 7-
nm FinFET," IEEE JSSC, vol. 57, pp. 1199-1210, Apr. 2022.
 H. Li et al., “11.6 A 100Gb/s-8.3dBm-Sensitivity PAM-4 Optical Receiver with Integrated TIA,FFE
and Direct-Feedback DFE in 28nm CMOS,” in 2021 IEEE ISSCC, vol. 64, 2021, pp. 190–192.
 I. Ozkaya et al., “A 64Gb/s 1.4-pJ/b NRZ Optical Receiver Data Path in 14nm CMOS FinFET,”IEEE
JSSC, pp. 3458-3473, Dec. 2017.
 C. Xie et al.,”High Speed 64 Gb/s NRZ Ring Modulator with 3.2 THz Wide FSR for DWDM
Applications,” OFC , 2024.

ISSCC 2024 - Forum 6.5: Silicon photonics 49 of 50

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 COPYRIGHT AND DISCLAIMER
© 2024 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD Arrow logo, and combinations thereof are
trademarks of Advanced Micro Devices, Inc. Other product names used in this publication are for identification purposes
only and may be trademarks of their respective companies.

The information presented in this document is for informational purposes only and may contain technical inaccuracies,
omissions, and typographical errors. The information contained herein is subject to change and may be rendered
inaccurate for many reasons, including but not limited to product and roadmap changes, component and motherboard
version changes, new model and/or product releases, product differences between differing manufacturers, software
changes, BIOS flashes, firmware upgrades, or the like. Any computer system has risks of security vulnerabilities that
cannot be completely prevented or mitigated. AMD assumes no obligation to update or otherwise correct or revise this
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ISSCC 2024 - Forum 6.5: Silicon photonics 50 of 50

© 2024 IEEE based high throughput optical transceivers
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 Please Scan to Rate
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ISSCC 2024 - Forum 6.5: Silicon photonics 51 of 45

© 2024 IEEE based high throughput optical transceivers
International Solid-State Circuits Conference
 ISSCC 2024 Forums

Micro-transfer printing for heterogeneous

electronic-photonic integrated circuits

Gunther Roelkens

Ghent University - imec

ISSCC 2024 - Forum 6.6: Micro-transfer printing for 1 of 39

© 2024 IEEE heterogeneous electronic-photonic integrated circuits
International Solid-State Circuits Conference
 Outline
 Electronic-photonic integrated circuits
◼ SiPho integration platforms
◼ Applications

 Heterogeneous integration technologies

◼ Flip-chip
◼ Wafer-bonding and wafer-reconstitution
◼ Hetero-epitaxial growth

 Micro-transfer printing
◼ Technology deep-dive
◼ Demonstrations
◼ Outlook

 Conclusions
ISSCC 2024 - Forum 6.6: Micro-transfer printing for 2 of 39
© 2024 IEEE heterogeneous electronic-photonic integrated circuits
International Solid-State Circuits Conference
 SiPho integration platforms
 Several foundries have a silicon photonics offering
 Most focus on a pure silicon photonics offering, not including monolithically
integrated electronics / lasers
 Example:

ISSCC 2024 - Forum 6.6: Micro-transfer printing for 3 of 39

© 2024 IEEE heterogeneous electronic-photonic integrated circuits
International Solid-State Circuits Conference
 SiPho integration platforms
 Typical cross-section

ISSCC 2024 - Forum 6.6: Micro-transfer printing for 4 of 39

© 2024 IEEE heterogeneous electronic-photonic integrated circuits
International Solid-State Circuits Conference
 Applications
 Platforms are originally developed for optical transceiver products
◼ 1.3-1.55um wavelength
◼ High-speed: 50-100GBaud
◼ Next-gen products will have to reach higher baudrates, not obtainable with SiPho
◼ Next-gen products will require lasers with better performance, obtainable with SiPho
 Other applications are emerging
◼ not necessarily at 1.3-1.55um: platforms support 0.5-2.5um wavelength range
◼ Not necessarily leveraging the high-speed capabilities of the platform
◼ Examples:
 Sensing (LiDAR, laser doppler vibrometry, …)
 Health (optical coherence tomography, photo-acoustic imaging, neural probes,…)
 AR/VR light engines
 Photonic interposers for artificial intelligence chips: optical I/O (1.3um, 1.06um, 0.85um)
 Photonic quantum computing
 …
ISSCC 2024 - Forum 6.6: Micro-transfer printing for 5 of 39
© 2024 IEEE heterogeneous electronic-photonic integrated circuits
International Solid-State Circuits Conference
 Outline
 Electronic-photonic integrated circuits
◼ SiPho integration platforms
◼ Applications

 Heterogeneous integration technologies

◼ Flip-chip
◼ Wafer-bonding
◼ Hetero-epitaxial growth

 Micro-transfer printing
◼ Technology deep-dive
◼ Demonstrations
◼ Outlook

 Conclusions
ISSCC 2024 - Forum 6.6: Micro-transfer printing for 6 of 39
© 2024 IEEE heterogeneous electronic-photonic integrated circuits
International Solid-State Circuits Conference
 Customer’s pain
 Missing building blocks for fully integrated photonic systems-on-chip
Function Material systems Application domains
Gain,lasers (VIS-SWIR) GaN, GaAs, InP, GaSb All
Electro-optic modulators LiNbO3, BaTiO3, … Transceivers, Optical I/O, Quantum
1.3um electro-absorption mods InP, 2D materials Transceivers, Optical I/O
Optical isolators and circulators Ce:YIG, BIG All
Single photon sources/detectors InAs/GaAs QDs, NbTiN Quantum, Sensing
Electronics Si, SOI, III-V All
Detection beyon 1600nm InP, GaSb Sensing, Health

 III-V semiconductors and thin-film materials (X-on-insulator, X-on-silicon)

 Devices based on these materials typically comprise non-CMOS compatible
elements (Au, Li, …)
ISSCC 2024 - Forum 6.6: Micro-transfer printing for 7 of 39
© 2024 IEEE heterogeneous electronic-photonic integrated circuits
International Solid-State Circuits Conference
 How to co-integrate non-native devices
 Integration approaches: from hybrid to monolithic
◼ Micro-optic bench approach
◼ Flip-chip integration
◼ Wafer bonding
◼ Micro-transfer printing
◼ Hetero-epitaxial growth

ISSCC 2024 - Forum 6.6: Micro-transfer printing for 8 of 39

© 2024 IEEE heterogeneous electronic-photonic integrated circuits
International Solid-State Circuits Conference
 Micro-optic bench
 Grating coupler interface
 Back-end integration
 Known good die
 Hermetic sealing
 Active alignment
 Sequential integration
 Unit + assembly cost high

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© 2024 IEEE heterogeneous electronic-photonic integrated circuits
International Solid-State Circuits Conference
 Flip-chip
 Edge coupler interface
 Back-end integration
 Known good die
 Passive alignment
◼ X-Y: +/- 0.5um 3sigma
◼ Z: mechanical stops
 Sequential integration -> cost high
 No native hermetic sealing

ISSCC 2024 - Forum 6.6: Micro-transfer printing for 10 of 39

© 2024 IEEE heterogeneous electronic-photonic integrated circuits
International Solid-State Circuits Conference
 Wafer bonding
 Middle of line integration
 Lithographic alignment
 Modification of back-end-of-line
 Minimum die size: limits density
 Very critical surface preparation
 No known good die

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© 2024 IEEE heterogeneous electronic-photonic integrated circuits
International Solid-State Circuits Conference
 Micro-transfer printing
 Back-end integration
 Known good die
 Evanescent or edge coupling interface
 Passive alignment
◼ X-Y: +/- 0.5um 3sigma
 Massively parallel
 Adhesive / molecular bond
◼ sensitive to surface quality

Inherits advantages of flip-chip integration (known good die, back-end integration) and
wafer bonding (high-throughput integration, efficient coupling)

ISSCC 2024 - Forum 6.6: Micro-transfer printing for 12 of 39

© 2024 IEEE heterogeneous electronic-photonic integrated circuits
International Solid-State Circuits Conference
 Hetero-epitaxial growth
 Front-end integration
 Challenges:
◼ Lattice constant mismatch
◼ Interface polarity
◼ Thermal expansion coefficient
 Two approaches:
◼ Large area III-V growth (e.g. using strain relaxed buffer layers)
◼ Low-dimensional systems (e.g. nanoridges)
 Reliability & process integration issues
 Not versatile

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© 2024 IEEE heterogeneous electronic-photonic integrated circuits
International Solid-State Circuits Conference
 Summary

While being less mature, micro-transfer printing has the potential to become
the dominant heterogeneous integration technology for silicon photonics

ISSCC 2024 - Forum 6.6: Micro-transfer printing for 14 of 39

© 2024 IEEE heterogeneous electronic-photonic integrated circuits
International Solid-State Circuits Conference
 Outline
 Electronic-photonic integrated circuits
◼ SiPho integration platforms
◼ Applications

 Heterogeneous integration technologies

◼ Flip-chip
◼ Wafer-bonding and wafer-reconstitution
◼ Hetero-epitaxial growth

 Micro-transfer printing
◼ Technology deep-dive
◼ Demonstrations
◼ Outlook

 Conclusions
ISSCC 2024 - Forum 6.6: Micro-transfer printing for 15 of 39
© 2024 IEEE heterogeneous electronic-photonic integrated circuits
International Solid-State Circuits Conference
 Micro-transfer printing basics
 Transfer of released, micron-scale semiconductor chiplets to a silicon target
wafer
 Based on the visco-elastic properties of PDMS stamps

ISSCC 2024 - Forum 6.6: Micro-transfer printing for 16 of 39

© 2024 IEEE heterogeneous electronic-photonic integrated circuits
International Solid-State Circuits Conference
 PDMS stamps
 Structures PDMS stamps to selectively pick-up and print chiplets

ISSCC 2024 - Forum 6.6: Micro-transfer printing for 17 of 39

© 2024 IEEE heterogeneous electronic-photonic integrated circuits
International Solid-State Circuits Conference
 Transfer printing process
 Pattern-recognition-based printing of thin semiconductor chiplets
 Massively parallel
Stamp + Motion + Optics
 Alignment accuracy down to +/- 0.5um 3sigma
Compliant Laterally stiff

Optics ( x, y, z )

Stamp ( z, Ɵ, Tx, Ty )

Transparent Soft
Translation stages ( x, y )

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© 2024 IEEE heterogeneous electronic-photonic integrated circuits
International Solid-State Circuits Conference
 Transfer printing process
 Transfer printing of micro-LEDs
◼ 1cm2 stamp
◼ 10.000 posts
◼ > 1M LEDs/hr

ISSCC 2024 - Forum 6.6: Micro-transfer printing for 19 of 39

© 2024 IEEE heterogeneous electronic-photonic integrated circuits
International Solid-State Circuits Conference
 Transfer printing process
 Transfer printing of micro-LEDs
◼ 1cm2 stamp
◼ 10.000 posts
◼ > 1M LEDs/hr

ISSCC 2024 - Forum 6.6: Micro-transfer printing for 19 of 39

© 2024 IEEE heterogeneous electronic-photonic integrated circuits
International Solid-State Circuits Conference
 Very versatile process
 Encapsulation, release and printing process can be applied to many material
systems

Device layer Release layer Substrate Wet etch Vapour etch

GaN Doped GaN GaN Oxalic (ECE) -

GaAs AlGaAs/InGaP GaAs/Ge HCl:H2O2 -

InP InGaAs/InAlAs InP FeCl3:H2O -

GaSb InAsSb GaSb Citric:H2O2 -

Thin-films* SiO2/Si Si HF/TMAH HF/XeF2

SOI electronics SiO2/Si Si HF/TMAH HF/XeF2

* LN, PZT, BTO, 2D materials, Ce:YIG, cQDs, NbTiN

ISSCC 2024 - Forum 6.6: Micro-transfer printing for 20 of 39

© 2024 IEEE heterogeneous electronic-photonic integrated circuits
International Solid-State Circuits Conference
 Integration on off-the-shelf SiPho wafers
 Local opening of back-end + adhesive bonding agent coating + printing + RDL

Au

Cu
III-V

Au
Fiber Edge
SiN Coupler
Poly-Si
SiO2 Si
air gap Fiber
(undercut) Grating
Si Substrate Coupler

ISSCC 2024 - Forum 6.6: Micro-transfer printing for 21 of 39

© 2024 IEEE heterogeneous electronic-photonic integrated circuits
International Solid-State Circuits Conference
 Integration on off-the-shelf SiPho wafers
 Dense co-integration of different types of chiplets on a single wafer

e.g. LN for
phase
e.g. Au
modulators
Ce:YIG for Cu
optical III-V
isolators A W heater
u Si Fiber Edge
SiO2 SiN Coupler
Poly-Si
Fiber Grating
Coupler
air gap
Si Substrate (undercut)

ISSCC 2024 - Forum 6.6: Micro-transfer printing for 22 of 39

© 2024 IEEE heterogeneous electronic-photonic integrated circuits
International Solid-State Circuits Conference
 Integration of electronic chiplets

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© 2024 IEEE heterogeneous electronic-photonic integrated circuits
International Solid-State Circuits Conference
 Integration of electronic chiplets

SEM of released SG13G2 coupons Transfer printed SG13G2 coupon

ISSCC 2024 - Forum 6.6: Micro-transfer printing for 24 of 39

© 2024 IEEE heterogeneous electronic-photonic integrated circuits
International Solid-State Circuits Conference
 Integration of electronic chiplets
 3D integration of silicon photonics, drivers/TIAs and digital electronics
 Application: wafer-level optical interconnects
 Thin chiplets, short interconnects
 Ultra-low loss SiN photonic interposer with transfer printed optics / electronics

ISSCC 2024 - Forum 6.6: Micro-transfer printing for 25 of 39

© 2024 IEEE heterogeneous electronic-photonic integrated circuits
International Solid-State Circuits Conference
 Integration of electronic chiplets
 3D integration for ultra-high bandwidth interconnection between CMOS and
photonics using ‘off-the-shelf’ electronics
 Lower power consumption of high-speed transmitters

Example of 250GBaud (140GHz) transmitters [roadmapping exercise]

ISSCC 2024 - Forum 6.6: Micro-transfer printing for 26 of 39

© 2024 IEEE heterogeneous electronic-photonic integrated circuits
International Solid-State Circuits Conference
 Integration of electronic chiplets
 High-sensitivity optical receivers:
◼ Sensitivity strongly depends on Cin= CPD+Cinter+CTIA

Input referred noise current:

Transimpedance limit (n-stage TIA):

◼ Transfer printing enables reducing Cin (~20fF)

 Short interconnect (few 10 microns)
 Small bondpads (10um)
 No ESD diodes needed?

ISSCC 2024 - Forum 6.6: Micro-transfer printing for 27 of 39

© 2024 IEEE heterogeneous electronic-photonic integrated circuits
International Solid-State Circuits Conference
 Unique selling proposition MTP
 Decoupling of processing non-native devices and processing silicon photonics
 Versatile in material system / target substrate
 High alignment accuracy (±0.5um 3𝝈)
 High throughput (45 sec / reticle, a reticle typically comprising 20 chips)
 Dense integration (1000s of devices per reticle)
 High coupling efficiency (<0.5dB/interface)
 Very low electrical parasitics (few fF/interconnect)
 Placement of micron-thick components
 Placement of micron-scale footprint components
 (moderately) low cost in (moderately) high volume

ISSCC 2024 - Forum 6.6: Micro-transfer printing for 28 of 39

© 2024 IEEE heterogeneous electronic-photonic integrated circuits
International Solid-State Circuits Conference
 InP SOAs on 400nm SOI platform

 C-band DFB laser + booster amplifier

 Same layout of both amplifiers
 Max. waveguide coupled power: 25mW

ISSCC 2024 - Forum 6.6: Micro-transfer printing for 29 of 39

J. Zhang et al., PTL 2023 heterogeneous electronic-photonic integrated circuits
© 2024 IEEE
International Solid-State Circuits Conference
 O-band InAs/GaAs QDOT DFB lasers

 GaAs QD SOA coupons fabricated @ UGent

 GaAs QD SOA coupon length: 2.16 mm
 2nd order Bragg grating
 DFB grating length: 1.4 mm
 Maximum waveguide-coupled power: 20 mW@10℃
 Side-mode-suppression-ratio: 60 dB

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© 2024 IEEE heterogeneous electronic-photonic integrated circuits
International Solid-State Circuits Conference
 InP/Si extended cavity lasers on SiPho

31

ISSCC 2024 - Forum 6.6: Micro-transfer printing for 31 of 39

J. Zhang et al., OFC 2022
© 2024 IEEE heterogeneous electronic-photonic integrated circuits
International Solid-State Circuits Conference
 Transfer printed UTC photodiodes
D. Maes et al., APL 2023
▪ UTC: uni-traveling carrier photodiodes
▪ 0.45 A/W responsivity (1.55um wavelength)
▪ 10 nA dark current
▪ > 100 GHz bandwidth (0.8 fF/micron2)

10 µm
100 µm

Suspended UTC photodiode coupon Coplanar waveguide

ISSCC 2024 - Forum 6.6: Micro-transfer printing for 32 of 39

© 2024 IEEE heterogeneous electronic-photonic integrated circuits
International Solid-State Circuits Conference
 Integration of 850nm VCSELs on SiN PICs

ISSCC 2024 - Forum 6.6: Micro-transfer printing for 33 of 39

© 2024 IEEE heterogeneous electronic-photonic integrated circuits
International Solid-State Circuits Conference
 Integration of 850nm VCSELs on SiN PICs
J. Goyvaerts et al., Optica 2021

Single mode, polarization-stable, tunable 850nm VCSELs coupled to

SiN waveguide
ISSCC 2024 - Forum 6.6: Micro-transfer printing for 34 of 39
© 2024 IEEE heterogeneous electronic-photonic integrated circuits
International Solid-State Circuits Conference
 LiNbO3 electro-optic films on SiN
T. Van Ackere et al., APL
 50GHz bandwidth, above 100GHz within reach 2023
 300nm thick LiNbO3 layer

ISSCC 2024 - Forum 6.6: Micro-transfer printing for 35 of 39

© 2024 IEEE heterogeneous electronic-photonic integrated circuits
International Solid-State Circuits Conference
 Outlook

 Micro-transfer printing is an enabling technology for wafer-scale

heterogeneous integration to realize advanced electronic-photonic ICs

 Any material or device that can be released from its substrate can be
transfer-printed with high alignment accuracy and massively parallel to a
silicon photonics target wafer

 The technology can spill over in many other domains: electronics, MEMS,
smart sensors,…

ISSCC 2024 - Forum 6.6: Micro-transfer printing for 36 of 39

© 2024 IEEE heterogeneous electronic-photonic integrated circuits
International Solid-State Circuits Conference
 Outline
 Electronic-photonic integrated circuits
◼ SiPho integration platforms
◼ Applications

 Heterogeneous integration technologies

◼ Flip-chip
◼ Wafer-bonding and wafer-reconstitution
◼ Hetero-epitaxial growth

 Micro-transfer printing
◼ Technology deep-dive
◼ Demonstrations
◼ Outlook

 Conclusions
ISSCC 2024 - Forum 6.6: Micro-transfer printing for 37 of 39
© 2024 IEEE heterogeneous electronic-photonic integrated circuits
International Solid-State Circuits Conference
 Conclusions
 Silicon Photonics is an enabling technology for a wide range of applications

 Heterogeneous integration will be key to realize fully integrated electronic-

photonic systems-on-chip

 Several technologies are being developed to realize this

 Micro-transfer printing is a particularly versatile and high-throughput

integration approach

 MTP Supply chain needs to be set up

 MTP yield and reliability need to be demonstrated

ISSCC 2024 - Forum 6.6: Micro-transfer printing for 38 of 39

© 2024 IEEE heterogeneous electronic-photonic integrated circuits
International Solid-State Circuits Conference
 Acknowledgements
 Funding bodies…

 … and the micro-transfer printing team at UGent - imec

ISSCC 2024 - Forum 6.6: Micro-transfer printing for 39 of 39
© 2024 IEEE heterogeneous electronic-photonic integrated circuits
International Solid-State Circuits Conference
 Please Scan to Rate
This Paper

ISSCC 2024 - Forum X.Y: <Presentation Title> 40 of 16

© 2024 IEEE
International Solid-State Circuits Conference
 Silicon Photonics and Foundry
Requirements for AI Datacenters

Tom Gray
Sr. Director of Circuit Research

NVIDIA

ISSCC 2024 - Forum 6.7: Silicon Photonics and

© 2024 IEEE Foundry Requirements for AI Datacenters
International Solid-State Circuits Conference
 Outline
 AI datacenter networking
 Co-integrated photonic architecture
 Photonic devices
 Link modeling and simulation
 Foundry requirements
 Conclusions

ISSCC 2024 - Forum 6.7: Silicon Photonics and 2 of 28

© 2024 IEEE Foundry Requirements for AI Datacenters
International Solid-State Circuits Conference
 AI Everywhere
 Explosion of models and model
sizes
 Insatiable appetite for compute
 Models parallelized over many
GPUs
 Bandwidth between GPUs ever
increasing
 Deep Learning training and
inference limited by compute and
network
 Well-understood and persistent
communication patterns
 Specialization of networking in AI
Datacenter

ISSCC 2024 - Forum 6.7: Silicon Photonics and 3 of 28

© 2024 IEEE Foundry Requirements for AI Datacenters
International Solid-State Circuits Conference
 AI Datacenter

Compute cluster
GPU
NVSwitch GPU

NVLINK
NVSwitch
 Compute network
GPU
◼ NVLINK/NVSwitch
GPU

 Datacenter network
Compute cluster
Compute cluster GPU
◼ InfiniBand
NVSwitch GPU
NVSwitch
GPU
GPU ◼ Ethernet
NVLINK
NVSwitch
NVLINK GPU
NVSwitch
GPU GPU
GPU

InfiniBand/Ethernet

ISSCC 2024 - Forum 6.7: Silicon Photonics and 4 of 28

© 2024 IEEE Foundry Requirements for AI Datacenters
International Solid-State Circuits Conference
 AI Datacenter
Compute cluster Scaleup
100s, 1000s, 10k of GPUs
Ultra high bandwidth
Compute cluster Custom networks and signaling
GPU
NVSwitch GPU

NVLINK
NVSwitch
GPU
GPU

Compute cluster
Compute cluster GPU
NVSwitch GPU
GPU
NVSwitch GPU
NVLINK
NVSwitch
NVLINK GPU
NVSwitch
GPU GPU
GPU

InfiniBand/Ethernet

ISSCC 2024 - Forum 6.7: Silicon Photonics and 5 of 28

© 2024 IEEE Foundry Requirements for AI Datacenters
International Solid-State Circuits Conference
 AI Datacenter
Datacenter Scaleout
10k, 100k of GPUs
Tapered bandwidth
Compute cluster InfiniBand or Ethernet
GPU
NVSwitch GPU

NVLINK
NVSwitch
GPU
GPU

Compute cluster
Compute cluster GPU
NVSwitch GPU
GPU
NVSwitch GPU
NVLINK
NVSwitch
NVLINK GPU
NVSwitch
GPU GPU
GPU

InfiniBand/Ethernet

ISSCC 2024 - Forum 6.7: Silicon Photonics and 6 of 28

© 2024 IEEE Foundry Requirements for AI Datacenters
International Solid-State Circuits Conference
 AI Datacenter – Hopper
 Scale-up to >256 GPUs in DGX
compute clusters

 Scale-out to >10k nodes in

datacenter

ISSCC 2024 - Forum 6.7: Silicon Photonics and 7 of 28

© 2024 IEEE Foundry Requirements for AI Datacenters
International Solid-State Circuits Conference
 Characteristics of Compute Cluster today
 Board and rack level copper interconnect
◼ Cost of cables/connectors increasing
◼ Reach decreasing
◼ Per-lane bandwidth scaling stalling
◼ Cable size and weight increasing
 Multi-rack and data center optical interconnect
◼ High cost
◼ Low reliability
◼ High power
◼ Large form factor
 Standards not as important
 Power constrained

ISSCC 2024 - Forum 6.7: Silicon Photonics and 8 of 28

© 2024 IEEE Foundry Requirements for AI Datacenters
International Solid-State Circuits Conference
 What we’d like for the future
 Co-integrated photonics
◼ Low cost <$0.25/Gbps
◼ Low power <1.5pJ/b
◼ Long reach >500m
◼ High bandwidth/fiber >0.8Tbps
◼ Small form factor
 >4Tbps/mm, >0.5Tbps/mm2
◼ High reliability <100 FIT

ISSCC 2024 - Forum 6.7: Silicon Photonics and 9 of 28

© 2024 IEEE Foundry Requirements for AI Datacenters
International Solid-State Circuits Conference
 How do we get there?
 Micro-ring based Dense Wavelength-Division Multiplexing (DWDM) link
◼ Optimal speed for power efficient electronics 25-50Gbps per channel
◼ Electrical energy efficiency approaching die to die links <1pJ/b
◼ Smallest area for electronics and photonics 50um x 50um per channel
◼ Scalability of optical bandwidth per fiber

ISSCC 2024 - Forum 6.7: Silicon Photonics and 10 of 28

© 2024 IEEE Foundry Requirements for AI Datacenters
International Solid-State Circuits Conference
 Microring Resonator

Angad Rekhi, Stanford SystemX May 2023

ISSCC 2024 - Forum 6.7: Silicon Photonics and 11 of 28
© 2024 IEEE Foundry Requirements for AI Datacenters
International Solid-State Circuits Conference
 Microring Resonator Modulator

Angad Rekhi, Stanford SystemX May 2023

ISSCC 2024 - Forum 6.7: Silicon Photonics and 12 of 28
© 2024 IEEE Foundry Requirements for AI Datacenters
International Solid-State Circuits Conference
 Microring Resonator Modulator
 Very selective
◼ High Q (~5k-8k)
 Very versatile
◼ Single device can be used as modulator and multiplexer
◼ Undoped ring used as demultiplexer
 Easy to control
◼ Weaker but faster electrical control [Su, IPRSN (OSA) 2015, IM2B.5]

◼ Stronger but slower thermal control

 Tuning by thermal resistor (i.e. tuning out process variations)
 Temperature must be tightly controlled (<1°C)
 Tuning must work while surrounded by strong temperature
aggressors of unknown dynamics
 Tiny area <5um radius
 Low capacitance (low driver power)
[Su, IPRSN (OSA) 2015, IM2B.5]

ISSCC 2024 - Forum 6.7: Silicon Photonics and 13 of 28

© 2024 IEEE Foundry Requirements for AI Datacenters
International Solid-State Circuits Conference
 Microring Resonator – Available Spectrum
SER

p p p
n n ... n

Laser
(comb)

... l
PD PD PD
TIA TIA TIA
Nedovic, “Methodology for Device, Circuit and Architecture Level Co-design and
Optimization of Dense Wavelength Division Multiplexing Links,” CLEO 2023

DES

 Free spectral range (FSR) limits useful optical spectrum due to aliasing
 FSR maximized by small radius. Radius limited by excessive curvature loss
 Pack many channels into FSR to maximize throughput
 Increase throughput/improve energy with slower/densely packed channels
ISSCC 2024 - Forum 6.7: Silicon Photonics and 14 of 28
© 2024 IEEE Foundry Requirements for AI Datacenters
International Solid-State Circuits Conference
 Scaling

B. Lee, “Driving Down Link Energy and Driving Up

Link Density in GPU Networks,” OFC 2022 ISSCC 2024 - Forum 6.7: Silicon Photonics and 15 of 28
© 2024 IEEE Foundry Requirements for AI Datacenters
International Solid-State Circuits Conference
 Challenges with Micro-ring based DWDM
 Photonics – devices, variability, models, PDK, foundries
 Lasers – availability of multiwavelength combs
 Packaging – integration and fiber connect
 Thermal management and control

ISSCC 2024 - Forum 6.7: Silicon Photonics and 16 of 28

© 2024 IEEE Foundry Requirements for AI Datacenters
International Solid-State Circuits Conference
 Photonic Couplers
 Couple light to/from the chip
 Grating (surface)  Edge
◼ resonant structures with lower bandwidth ◼ require higher precision and more complicated
(~10nm, ~10-20 l’s) assembly (V-grooves, metamaterials)
◼ simple to fabricate and more tolerant to ◼ wider bandwidth, more suited to many
assembly position and angle errors wavelengths WDM
◼ 2D GCs couple both polarizations

 Challenges
◼ Loss: 1-2dB typical per coupler
◼ Density: 127-250mm typical spacing
◼ Testability and packaging

T. Barwicz et al.,
[A. Mekis et al., JSTQE2011] JSTQE2016

ISSCC 2024 - Forum 6.7: Silicon Photonics and 17 of 28

© 2024 IEEE Foundry Requirements for AI Datacenters
International Solid-State Circuits Conference
 Modeling Micro-rings for DWDM
 Crosstalk is first order phenomenon in DWDM
 Micro-rings tend to poorly suppress sidebands due to long tail
of their characteristics (Lorentzian)
 Photodiodes and other components in the DWDM system are
broadband – no further channel filtering
 Tradeoff:
◼ Wider characteristic (lower Q): XT↑, BW ↑
◼ Narrower characteristic (higher Q): XT↓, BW ↓
 Many sources of crosstalk paths:
◼ Parasitic modulation of adjacent channels (TX)
◼ Imperfect suppression of neighboring channels (RX)
◼ Frequency dependent power loss (ISI) due to spectrally
neighboring rings
◼ Net result depends on spectral and spatial ring order on the
TX/RX bus
 Possible to reduce the effect by increasing channel spacing or
using higher order ring filters
◼ But must model the effect to design for it Nedovic, “Methodology for Device, Circuit and Architecture Level Co-design and
Optimization of Dense Wavelength Division Multiplexing Links,” CLEO 2023

ISSCC 2024 - Forum 6.7: Silicon Photonics and 18 of 28

© 2024 IEEE Foundry Requirements for AI Datacenters
International Solid-State Circuits Conference
 Micro-ring Simulation Requirements
 Simulating one wavelength at a time does not work well
◼ The effect of the crosstalk on the electrical circuit must be evaluated
with the main wavelength present for proper biasing and to account for
circuit nonlinearities n
◼ Impossible to capture any multi-wavelength nonlinearity, e.g. self
p
heating effect to the side channels, four wave mixing at high power or
PD cross-modulation (important for very narrow channel spacing)
 Simulating two wavelengths at a time (main channel + crosstalk
channel) is better but not ideal PD
VOUT
◼ Crosstalk from each channel can be treated as additive noise but
several simulations and cumbersome waveform manipulations are ITIA
needed
 Minimum requirements: support at least three wavelengths in the
model – main channel and two aggressors (five is better)
 Ideally support all wavelengths present in the link in one
ITIA must contain all relevant
simulation
wavelength components to
accurately account for the
effect of crosstalk

ISSCC 2024 - Forum 6.7: Silicon Photonics and 19 of 28

© 2024 IEEE Foundry Requirements for AI Datacenters
International Solid-State Circuits Conference
 DWDM PDK Landscape – What we have
 Several foundries offer multi-project wafer (MPW) and dedicated runs on
photonics-only or electro-optics wafers
 Usually specify supported device list and specs
◼ e.g. tabulated bandwidth, loss, phase efficiency, responsivity, etc.
 Occasionally device models are provided, rarely in a format compatible with
circuit simulation that allows electrical/optical simulations
 Even more rare is the PDK support for DWDM and circuit-level model of the
photonic devices
 No support for model expansions and refinements by the user
 No support for link-level architecture modeling
 No support for multi-wavelength simulations

ISSCC 2024 - Forum 6.7: Silicon Photonics and 20 of 28

© 2024 IEEE Foundry Requirements for AI Datacenters
International Solid-State Circuits Conference
 DWDM PDK Infrastructure – What we need
Circuit design
Device Physical
measurements verification,
Model fit SCH/Layout TO
Laser MC, corners,
thermal etc.
LPE
A B

LCA Device
Device
Optical Netlist
model
model
device
Device model
simulations Multi-wavelength
circuit simulation
(Spectre/HSPICE)
Electrical
device
Link
models Link model
architecture
From CMOS
From photonic foundry /PDK developer foundry

ISSCC 2024 - Forum 6.7: Silicon Photonics and 21 of 28

© 2024 IEEE Foundry Requirements for AI Datacenters
International Solid-State Circuits Conference
 Lasers for DWDM Photonics
 8-16 data wavelengths per fiber (plus auxiliary wavelengths)
 ~5 mW fiber-coupled optical laser output power per line
 ~10% effective wall-plug efficiency corresponds to 2 pJ/b
(including multiplexing/combining and coupling losses as well as any
electrical tuning power)
 Low-cost, volume manufacturable
 Reasonable noise performance
(relative intensity noise, linewidth, side-mode suppression ratio)
 100-200 GHz grid channel spacing
 ± 5-10% alignment to a floating grid at nominal temperature

ISSCC 2024 - Forum 6.7: Silicon Photonics and 22 of 28

© 2024 IEEE Foundry Requirements for AI Datacenters
International Solid-State Circuits Conference
 Lasers for DWDM Photonics
Technology options

Singlet DFBs DFBs Flip-chip Soldered in Si Cavity QD Mode-Locked Combs

Cost of many precision active alignments. Alignment and reflection management (no Balancing cavity gain and mode spacing.
isolators).

DFB Arrays Heterogeneous Material-bonded III- Pumped Nonlinear Resonant

V on Si Combs

Array yield and manufacturing controls. Substantial process development and thermal Achieving sufficient efficiency from the nonlinear
engineering. process.
B. Lee, ICSJ, Nov. 2023
ISSCC 2024 - Forum 6.7: Silicon Photonics and 23 of 28
© 2024 IEEE Foundry Requirements for AI Datacenters
International Solid-State Circuits Conference
 Packaging for 2.5D Integrated Optics

 High reliability optics (no sockets)

 Separate EIC/PIC for optimal process
technologies
 PIC with TSVs
 Edge or surface coupling, but need
mechanically robust features
 Detachable optical connector
◼ Module handling
◼ Field replaceability
 Thermal environment management

ISSCC 2024 - Forum 6.7: Silicon Photonics and 24 of 28

© 2024 IEEE Foundry Requirements for AI Datacenters
International Solid-State Circuits Conference
 Thermal Simulation
Impact to ring of large power transient in ASIC

Liquid cooling interface

(0.5 mm thick)

(1 mm thick)

(0.1 mm thick)

(0.1 mm thick) (0.07 mm spacer of molding compound)

 500-W step in ASIC power distributed evenly over 800-mm2

die
 EIC power is constant
 Heat flow directly from the ASIC to the PIC and EIC is largely
blocked by the molding compound
 At typical ring positions, temperature rises by ~10 K with
max slope of ~70 K/s

[ B. Lee et al., J. Lightw. Technol., Feb. 2023 ]

ISSCC 2024 - Forum 6.7: Silicon Photonics and 25 of 28
© 2024 IEEE Foundry Requirements for AI Datacenters
International Solid-State Circuits Conference
 Thermal Simulation
Impact to ring of change in heater power

Liquid cooling interface

(0.5 mm thick)

(1 mm thick)

(0.1 mm thick)

(0.1 mm thick) (0.07 mm spacer of molding compound)

 1-mW step in heater power (1 mm above ring)

 Monitor main ring temperature and neighboring ring temperature
100 mm away
 Main ring temp. rises by ~11 K with a time constant near 10ms
 Neighboring ring temp. rises by ~0.7 K with max slope of ~50 K/s

[ B. Lee et al., J. Lightw. Technol., Feb. 2023 ]

ISSCC 2024 - Forum 6.7: Silicon Photonics and 26 of 28
© 2024 IEEE Foundry Requirements for AI Datacenters
International Solid-State Circuits Conference
 Thermal Control
Stable loop operation under aggressive thermal transients

 For TX ring Q of 7000 (32 GHz) and pp resonance shift of 8 GHz (50 pm), Closed-loop response to 500-W step in ASIC power
control loop needs to maintain temp. within ± 0.4 K (± 5 GHz) for
negligible increase in TX penalty
 For RX ring Q of 5000 (45 GHz), ± 0.4 K results in negligible eye closure
 Simulate a conventional proportional-integral (PI) thermal controller
 Impacts of ASIC & heater powers are summed to obtain ring temp.,
which shifts resonance and impacts power measured on a weakly coupled
drop-port photodiode
 Measured power is compared to target, and error is fed back to controller

Sim 1 Closed-loop response to 1-mW step in neighboring ring power

Sim 2

[ B. Lee et al., J. Lightw. Technol., Feb. 2023 ]

ISSCC 2024 - Forum 6.7: Silicon Photonics and 27 of 28
© 2024 IEEE Foundry Requirements for AI Datacenters
International Solid-State Circuits Conference
 Conclusions
 AI everywhere necessitates AI Datacenters
 AI Datacenters require high bandwidth compute clusters with many GPUs
 Networking for compute clusters
◼ Low cost
◼ Reliable
◼ Low power
◼ Medium to long reach
 Copper scaling slowing, traditional optics too much power
 Scalable co-integrated optics requires
◼ Reliable components
◼ Full foundry PDK support
◼ Reliable ecosystem of foundry, lasers, packaging, thermal management

ISSCC 2024 - Forum 6.7: Silicon Photonics and 28 of 28

© 2024 IEEE Foundry Requirements for AI Datacenters
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ISSCC 2024 - Forum 6.7: Silicon Photonics and 29 of 70

© 2024 IEEE Foundry Requirements for AI Datacenters
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 ISSCC 2024 Forums

Electronic-Photonic Systems-on-Chip for

Compute, Communications and Sensing

Vladimir Stojanović

UC Berkeley and Ayar Labs

ISSCC 2024 - Forum 6.8

© 2024 IEEE
International Solid-State Circuits Conference
 Resonant Photonic Microrings in Si CMOS

▪ Interleaved planar PN junctions

▪ Enabled by advanced lithography of this process
▪ Highly sensitive structures that can be used in many applications
▪ Q factors up to 200k

ISSCC 2024 - Forum 6.8

© 2024 IEEE
2
International Solid-State Circuits Conference
 From “zero-change” to standard process in 45nm

[C. Sun, JSSC 2016]

▪Closest proximity of electronics and photonics

▪Available as qualified 45SPCLO process (GlobalFoundries)
3
© 2024 IEEE
Monolithic photonics platform with fastest transistors
International Solid-State Circuits Conference
 45SPCLO process

Rakowski et al OFC 2020

▪ Same transistors as in 45nm SOI
▪ Number of features optimized for photonics
▪ Ge photodetectors, Si dopings, Si partial etch, SiN, V-groove
couplers etc.
ISSCC 2024 - Forum 6.8
© 2024 IEEE
4
International Solid-State Circuits Conference
 Outline

 Digital optical interconnects

 Analog optical interconnects

 Sensing

ISSCC 2024 - Forum 6.8 5

© 2024 IEEE
International Solid-State Circuits Conference
 Interconnect limits AI scale-out runtime
GShard Multiplicity of Experiments Language Training

Runtime breakdown
600B weights

150B weights
37B weights

Efficiency = Compute time/ (Compute time + Communication time)

Efficiency Drops from >80% to <60% with scale-out

Chen HotChips 2020 ISSCC 2024 - Forum 6.8 6

6
© 2024 IEEE
International Solid-State Circuits Conference
 Optical I/O Architecture
TeraPHYTM CMOS Optical I/O Chiplet
Socket – Socket
Board – Board
Rack - Rack data Typical in-package
SoC temperature 80-
110oC
A new universal I/O -
2.5D or 2D package
communicate anywhere at the
cost and performance of
in-package interconnects Electrical I/O

laser

SuperNovaTM multi-port, External laser module

multi-wavelength laser source temperature <55oC

ISSCC 2024 - Forum 6.8 7

© 2024 IEEE
International Solid-State Circuits Conference
 Technology Basics
Optical chiplets SoC In-Package Integration
Microring Electronic/Photonic
Resonators Integration

• 1,000x smaller • Dense CMOS • TeraPHY™ chiplet for • Integration with

than traditional integration in-package optical state-of-the-art SoCs
optical devices I/O
• Direct from the
• High-speed package optical I/O
capability
• Compatible with
300mm CMOS

ISSCC 2024 - Forum 6.8 8

© 2024 IEEE
International Solid-State Circuits Conference
 Microring WDM Bandwidth Scaling (Tx+Rx)
Optical I/O Tx port Optical I/O Rx port

Chiplet bandwidth = 2 x ( # of ports/chiplet ) x ( # of wavelengths/port ) x (data rate/wavelength)

Chiplet Bandwidth # of ports / # of wavelengths/port Data

chiplet rate/wavelength
4.096 Tbps 8 8 32 Gbps

8.192 Tbps 16 (8) 8 32 Gbps (64 Gbps)

16.384 Tbps 16 8 64 Gbps

32.768 Tbps 16 16 64 Gbps

© 2024 IEEE
International Solid-State Circuits Conference
 TeraPHYTM Optical I/O Chip Architecture

8 wavelengths/port

ISSCC 2024 - Forum 6.8 10

© 2024 IEEE
International Solid-State Circuits Conference
 Packaging and Fiber Attach

Gen 1: Gen 2:
Actively aligned Passively aligned
vertical attach of edge attach of
fiber pigtails fiber pigtails

2.5D EMIB
Gen 3: System-In-Package
Detachable
edge attach
optical connector

(Source: Wade et al HotChips 2023) 11

ISSCC 2024 - Forum 6.8
© 2024 IEEE
International Solid-State Circuits Conference
 Optical I/O enables complete physical disaggregation of distributed compute

TeraPHYTM chiplets
Agilex I-series Multi-Chip
Package with SuperNovaTM
Optical I/O laser modules

2x F-tile Optical FPGA PCIe CEM Card

TeraPHYTM 2 x 4Tbps (Tx+Rx) Optical I/O
(100G LR, PCIe Gen4)
chiplet (4Tbps Chiplets
Tx+Rx)

2023 Demos:
ERI Summit, Hot Chips,
White House Demo Day
Supercomputing
12
© 2024 IEEE
International Solid-State Circuits Conference
 Future Systems-In-Package with Optical I/O
Electrical I/F Optical I/F Optical Off-package
(Advanced Package) (CW-WDM) Chiplet IO BW (4-8
Gen
BW chiplets per
I/F Modules Tx / Rx Data Rate Ports λs / Data Rate (Tx+Rx) package)
IOs [Gbps/IO] Port [Gbps/λ]
1 AIB 24 20 / 20 2 8 8 16 2 Tbps 8-16 Tbps

2 AIB 16 80 / 80 2 8 8 32 4 Tbps 16-32 Tbps

• Gen 1 and Gen 2 already built and hardware

validated

• 16-32 Tbps off-socket optical I/O bandwidth

possible today

(Source: Wade et al HotChips 2023) 13

ISSCC 2024 - Forum 6.8
© 2024 IEEE
International Solid-State Circuits Conference
 Future Systems-In-Package with Optical I/O
Electrical I/F Optical I/F Optical Off-package
(Advanced Package) (CW-WDM) Chiplet IO BW (4-8
Gen
BW chiplets per
I/F Modules Tx / Rx Data Rate Ports λs / Data Rate (Tx+Rx) package)
IOs [Gbps/IO] Port [Gbps/λ]
1 AIB 24 20 / 20 2 8 8 16 2 Tbps 8-16 Tbps

2 AIB 16 80 / 80 2 8 8 32 4 Tbps 16-32 Tbps

3 UCIe 16 32 / 32 8 8 16 32 8 Tbps 32-65 Tbps

4 UCIe 16 64 / 64 8 16 16 32 16 Tbps 65-131 Tbps

5 UCIe 16 64 / 64 16 16 16 64 32 Tbps 131-262 Tbps

• Clear multi-generation roadmap leveraging

advanced packaging and industry standards

• >250 Tbps off-socket optical I/O bandwidth

possible in 10-15 year time frame

(Source: Wade et al HotChips 2023) 14

© 2024 IEEE
International Solid-State Circuits Conference
 Future AI fabric scaling:
1000x more nodes, 100x faster nodes
Future AI Fabrics

Nvidia H100 Fabric

Nvidia DGX H100

ISSCC 2024 - Forum 6.8 15

15
© 2024 IEEE
International Solid-State Circuits Conference
 SuperFabric for ML/AI workload scale-out
Getting to 106 nodes, 100x faster nodes
SuperSwitch SuperSwitch SuperSwitch

SuperSwitch SuperSwitch

1000 nodes
per pod
1000 pods
Two hops to anywhere in the system
© 2024 IEEE
<1us link/flow reconfiguration 16

International Solid-State Circuits Conference

 SuperFabric Components and Features

Laser-and-clock Large radix, fast optical Enables 100+Tbps per

forwarded switching and Rx ring package and radix 1024
coherent WDM links locking connectivity
ISSCC 2024 - Forum 6.8 17
© 2024 IEEE
International Solid-State Circuits Conference
 Intensity Modulated Direct Detection SiPh Links

Laser
Power PL PS
Wall-plug efficiency αT = αC3αIL
𝜂 W = 10%
Coupling loss Insertion loss Coupling loss Coupling loss Limited Rx
αC = 4dB αIL = 5dB αC = 4dB αC = 4dB sensitivity IRx,sen
80mW
Optical Power

8mW IRx,sen (=100µA)

3.2mW PS =

1.3mW ℛ (=0.5A/W)
400x
502 µW
200 µW

Reducing required laser power is key to improve total link efficiency

18
© 2024 IEEE
International Solid-State Circuits Conference
 Laser-Forwarded (LF) Coherent Link

Laser 50:50
Power PL

Coupling loss Insertion loss Coupling loss

αC = 4dB αIL = 5dB αC = 4dB Coupling loss
αC = 4dB

 I(t)NRZ = ℛ ∙ 𝑃𝐿 ∙ 𝛼 𝑇 while I(t)LF = 2ℛ ∙ 𝑃𝐿 𝛼 𝑇 ∙ 𝛼𝑐

 LF takes a geometric mean of loss in two paths I(t)LF 𝛼𝐶

=2 ≈5
I(t)NRZ 𝛼𝑇
 Consequently, laser power can be reduced by 5x
ISSCC 2024 - Forum 6.8 19
© 2024 IEEE
International Solid-State Circuits Conference
 LF-transceiver prototype in 45RFSOI
RX Macro 250 µm
O-DAC based DeSer & BERT

150 µm
Modulator
RX AFE Rx Macro
3dB Coupler Port-2 GC

Port-1 GC

Drop
Port PD PD-1
TX

30 µm
sites
RX sites
Modulator driver (16 slices)
150µm

Ser & BERT

PD-2
200 µm T a T n
Balanced PD
it
it
TX Macro
Mehta et al JSSC 2020
Tx Macro with ia i
it
Digital PLL
DPLL
1.5pJ/b w/o DPLL @
T T a T n
it
it 10Gbps BPSK
T ia i T o iv
it it
20
© 2024 IEEE
International Solid-State Circuits Conference
 SuperSwitch – A fast, high-radix, all-optical switch
128x128 Si Photonic Switch 32x32 CMOS Driver ASIC

Flip-
Chip
Bonding

CMOS
Unit Cell
4.3 mm

High
voltage
FETs
Bootstrap
Capacitors
22 mm
Low-Voltage
with <1us switching time, Digital Logic 21

International 30mW power consumption

© 2024 IEEE
Solid-State Circuits Conference
 Large-scale demonstration (32x32)

22
© 2024 IEEE
International Solid-State Circuits Conference Henriksson et al ECOC 2023
 Gaps to fill
System level
Control plane programming
Single/multiple concurrent jobs
Link level
6-9dB of additional insertion loss
(switch, connectors)
Use laser-forwarded coherent WDM link
architecture
sub-100ns WDM link lock
Devices & Materials
Dense WDM, fast electro-optic tuning Mehta et al, JSSC 2020

CW-WDM MSA lasers

8-32 wavelengths
8-32 ports
23
© 2024 IEEE
International Solid-State Circuits Conference
Kramnik et al, CLEO 2022
 Extreme massive-MIMO 6G+
Hot-spot micro-cell Radio Unit (RU)

RU

Beam processing and

data links power dominate

Need to disaggregate the

most power-hungry blocks

1024 antennas/RU
ISSCC 2024 - Forum 6.8 24
© 2024 IEEE
International Solid-State Circuits Conference
 Disaggregated RU
Radio unit Beamforming processors

RFIC

ADC/DAC

Optical I/O
chiplets

ISSCC 2024 - Forum 6.8 25

© 2024 IEEE
International Solid-State Circuits Conference
 RU Disaggregation

Only optical I/O can lower the interconnect power enough 26

© 2024 IEEE
to enable disaggregation
International Solid-State Circuits Conference
 Low-power, disaggregated RUs (DRUs)

DRU

Increasing capacity through

collaborative cell-free architecture

Extreme massive-MIMO 6G+ systems

ISSCC 2024 - Forum 6.8 27

© 2024 IEEE
International Solid-State Circuits Conference
 RU Disaggregation to Sensors

mm-wave sensing array with

analog photonic links
ISSCC 2024 - Forum 6.8 28
© 2024 IEEE
International Solid-State Circuits Conference
 Optical Links for mm-wave MIMO
Digital Optical Link – optical I/O

Analog Optical Link

ISSCC 2024 - Forum 6.8 29

© 2024 IEEE
International Solid-State Circuits Conference
 Ring-based Analog Millimeter-wave Photonic-electronic
Sensing Arrays

30
© 2024 IEEE
International Solid-State Circuits Conference
ISSCC 2024 - Forum 6.8
 Link Architecture

LNA
(c)

Comb laser

ISSCC 2024 - Forum 6.8 31

© 2024 IEEE
International Solid-State Circuits Conference
 Noise Figure Optimization
Single-ring modulator Advanced ring modulator
(Singh FiO’21)

ISSCC 2024 - Forum 6.8 32

© 2024 IEEE
International Solid-State Circuits Conference
 mm-wave sensor prototype in 45RFSOI

- 30mW per antenna 24 sites in ~15mm2 LNA modulator

70GHz antenna pitch = 2 mm driver
5 x 5 array = 10 mm x 10mm 33
© 2024 IEEE
International Solid-State Circuits Conference
 mm-wave sensor prototype in 45RFSOI

34
© 2024 IEEE
International Solid-State Circuits Conference Wang ESSCIRC23, Singh ECOC23
 Single Ring Modulator Linearity Modeling
 A noise & linearity sweetspot: blue side of the resonance wavelength

Performance of an Intensity-modulated Direct-detection Link Phase and Normalized Through Port Power

ISSCC 2024 - Forum 6.8 35

© 2024 IEEE
International Solid-State Circuits Conference
 Experiments agree
with models
Maximum SFDR3
▪ ~91 dB·Hz2/3 @ -5 dBm laser
▪ ~95 dB·Hz2/3 @ 0 dBm laser
▪ ~96 dB·Hz2/3 @ 5 dBm laser
104.6 dB · Hz2/3 [LTE requirement]

Buchbinder
CLEO21

36
© 2024 IEEE
International Solid-State Circuits Conference
 Another Interconnect Bottleneck:
Cryogenic Computing (Quantum and Classical)

72 Qubits

▪2 coax cables / Qubit[*] [*] Joseph C. Bardin, ISSCC 2019

▪> 1000 Qubits is required to solve useful problems

ISSCC 2024 - Forum 6.8 37
© 2024 IEEE
International Solid-State Circuits Conference
 Coherent Ultrafast Reflective Link (CURL)

Asymmetric link: Cryo Tx to room temperature Rx

▪ RT multi-wavelength tunable laser
▪ Ultrasensitive Electro-optic(EO) transmitter at 4K
▪ Advanced coherent receiver at RT
ISSCC 2024 - Forum 6.8 38
© 2024 IEEE
International Solid-State Circuits Conference
 45nm SOI CMOS Cryo Performance

▪Better analog performance at sub-threshold

▪Faster digital performance
ISSCC 2024 - Forum 6.8 39
© 2024 IEEE
International Solid-State Circuits Conference
 Prototype Cryo-TX for 10Gbps Link
- subthreshold pre-amplifier

▪Subthreshold Amplifier
▪Gain: 28dB
▪BW: 854MHz
▪Power: 38uW

ISSCC 2024 - Forum 6.8 40

© 2024 IEEE
International Solid-State Circuits Conference
 Prototype Cryo-TX for 10Gbps Link
- Micro-ring Resonator Modulator

▪MRM
▪30GHz/V
▪E-O BW: 2.2GHz

ISSCC 2024 - Forum 6.8 Gevorgyan, OFC2021 41

© 2024 IEEE
International Solid-State Circuits Conference
 Prototype Cryo-TX for 10Gbps Link
- Chip Micrograph

28 TX
test sites
9mm

50um
1.8mm

2mm ISSCC 2024 - Forum 6.8 42

© 2024 IEEE
International Solid-State Circuits Conference
 First full CURL link demonstration
Stimulus output (CURL input)

Received CURL

Yin et al, ESSCIRC’21 43

Coherent Ultrafast Reflective Link (CURL)
© 2024 IEEE
International Solid-State Circuits Conference
 CURL Link Performance

44
© 2024 IEEE
International Solid-State Circuits Conference
 What’s next: Superconducting Multi-Chip-Module

MIT Lincoln Laboratory

superconducting multi-chip
module process (SMCM-4M)

Niobium-based integrated-
circuit fabrication process

MCM Carrier: 10 x 10mm

ISSCC 2024 - Forum 6.8 45

© 2024 IEEE
MCM on the host PCB
International Solid-State Circuits Conference
 Photonic label-free molecular bio-sensing

Micro-rings as label-free molecular sensors

Enable multiplexed analyte Point-of-Care
sensing (virus and anti-body testing)

• Potential to further lower the form-factor to implantable (immunotherapy) 46

© 2024 IEEE
International Solid-State Circuits Conference
 Photonic label-free biosensing
Molecules Viral particles

Adamopoulos
CICC’21, CLEO’21,
OJSSC’21, SSCL’21

ISSCC 2024 - Forum 6.8 47

© 2024 IEEE
International Solid-State Circuits Conference
 Conclusions
 Digital MRM optical links enable system disaggregation and scaling
◼ In AI scale-out
◼ In Extreme MIMO and radar mm-wave systems
 Laser-forwarded coherent links
◼ Improve link energy-efficiency
◼ Improve fiber bandwidth density
◼ Enable additional link elements – e.g. optical switch insertion loss
 LF-coherent and analog MRM link concepts
◼ Achieve optimal link efficiency in cryo asymmetric link applications
◼ Enable various sensing applications
 Cryo
 Mm-wave
 Label-free molecular and nanoparticle
 Ultrasound

ISSCC 2024 - Forum 6.8 48

© 2024 IEEE
International Solid-State Circuits Conference
 References
 Chen HotChips 2020
 Wade et al HotChips 2023
 Mehta et al JSSC 2020
 Henriksson et al ECOC 2023
 Kramnik et al CLEO 2022
 Singh FiO 2021
 Wang ESSCIRC 2023
 Singh ECOC 2023
 Buchbinder CLEO 2021
 Gevorgyan OFC 2021
 Yin et al ESSCIRC 2021
 Adamopoulos CICC’21, CLEO’21, OJSSC’21, SSCL’21
 Sun JSSC 2016
 Rakowski OFC 2020

ISSCC 2024 - Forum 6.8 49

© 2024 IEEE
International Solid-State Circuits Conference
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