AIS3624DQ

High-performance motion sensor for automotive applications:

ultra-low-power digital output 3-axis accelerometer
Datasheet - production data

Description
The AIS3624DQ is an ultra-low-power high-
performance three-axis accelerometer with a
digital serial interface SPI standard output, an I2C
QFN 24 (4x4x1.8 mm3) compatible interface is also available.
The device features ultra-low-power operational
modes that allow advanced power saving and
Features smart sleep-to-wake functions.

 Wide supply voltage range: 2.4 V to 3.6 V The AIS3624DQ has dynamically user selectable
full scales of ±6g/±12g/±24g and it is capable of
 1.8 V low voltage compatible IOs measuring accelerations with output data rates
 Ultra-low-power mode consumption from 0.5 Hz to 1 kHz.
down to 10 μA
The self-test capability allows the user to check
 6g/±12g/24g dynamically selectable full the functioning of the sensor in the final
scale application.
 SPI/I2C digital output interface The device may be configured to generate an
 16-bit data output, 12-bit resolution interrupt signal by inertial wakeup/free-fall events
 2 independent programmable interrupt as well as by the position of the device itself.
generators Thresholds and timing of interrupt generators are
programmable by the end user on the fly.
 System sleep-to-wake function
The AIS3624DQ is available in small, quad flat
 Embedded self-test
no-lead package (QFN) with the reduced 4x4 mm
 Extended temperature range -40°C to 105°C footprint required by many applications and it is
 10000 g high shock survivability guaranteed to operate over an extended
temperature range from -40 °C to +105 °C.
 ECOPACK®, RoHS and “Green” compliant
(see Section 8) This product may be used in a variety of
 AEC-Q100 qualification automotive non-safety applications such as:
 Motion-activated functions
 Telematic boxes
 Impact recognition and logging systems
 Vibration monitoring and compensation

Table 1. Device summary

Order codes Temperature range [C] Package Packaging

AIS3624DQ -40 to +105 QFN 4x4x1.8 24L Tray

AIS3624DQTR -40 to +105 QFN 4x4x1.8 24L Tape and reel

December 2015 DocID027117 Rev 2 1/41

This is information on a product in full production. www.st.com
Contents AIS3624DQ

Contents

1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

1.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2 Mechanical and electrical specifications . . . . . . . . . . . . . . . . . . . . . . . 10

2.1 Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.3 Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.3.1 SPI - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.3.2 I2C - inter-IC control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.4 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.5 Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.5.1 Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.5.2 Zero-g level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.5.3 Self-test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.5.4 Sleep-to-wake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3 Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1 Sensing element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.2 IC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3 Factory calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4 Application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1 Soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5 Digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.1 I2C serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.1.1 I2C operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.2 SPI bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.2.1 SPI read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.2.2 SPI write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.2.3 SPI read in 3-wire mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

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AIS3624DQ Contents

6 Register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

7 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.1 WHO_AM_I (0Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.2 CTRL_REG1 (20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.3 CTRL_REG2 (21h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.4 CTRL_REG3 [interrupt CTRL register] (22h) . . . . . . . . . . . . . . . . . . . . . . 27
7.5 CTRL_REG4 (23h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.6 CTRL_REG5 (24h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.7 HP_FILTER_RESET (25h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.8 REFERENCE (26h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.9 STATUS_REG (27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.10 OUT_X_L (28h), OUT_X_H (29) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.11 OUT_Y_L (2Ah), OUT_Y_H (2Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.12 OUT_Z_L (2Ch), OUT_Z_H (2Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.13 INT1_CFG (30h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.14 INT1_SRC (31h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.15 INT1_THS (32h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.16 INT1_DURATION (33h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.17 INT2_CFG (34h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.18 INT2_SRC (35h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.19 INT2_THS (36h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.20 INT2_DURATION (37h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

8 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
8.1 QFN 24L package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

9 Soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
9.1 General guidelines for soldering surface-mount MEMS sensors . . . . . . . 37
9.2 PCB design guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
9.3 PCB design rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
9.4 Stencil design and solder paste application . . . . . . . . . . . . . . . . . . . . . . . 38
9.5 Process considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

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Contents AIS3624DQ

10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

4/41 DocID027117 Rev 2

AIS3624DQ List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 3. Mechanical characteristics @ Vdd = 3.3 V, T = -40 °C to +105 °C
unless otherwise noted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 4. Electrical characteristics @ Vdd = 3.3 V, T = -40 °C to +105 °C unless otherwise noted . 11
Table 5. SPI slave timing values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 6. I2C slave timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 7. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 8. Serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 9. I2C terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 10. SAD+Read/Write patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 11. Transfer when master is writing one byte to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 12. Transfer when master is writing multiple bytes to slave:. . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 13. Transfer when master is receiving (reading) one byte of data from slave: . . . . . . . . . . . . . 20
Table 14. Transfer when master is receiving (reading) multiple bytes of data from slave . . . . . . . . . 20
Table 15. Register address map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 16. WHO_AM_I register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 17. CTRL_REG1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 18. CTRL_REG1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 19. Power mode and low-power output data rate configurations . . . . . . . . . . . . . . . . . . . . . . . 26
Table 20. Normal-mode output data rate configurations and low-pass cutoff frequencies . . . . . . . . . 26
Table 21. CTRL_REG2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 22. CTRL_REG2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 23. High-pass filter mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 24. High-pass filter cutoff frequency configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 25. CTRL_REG3 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 26. CTRL_REG3 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 27. Data signal on INT 1 and INT 2 pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 28. CTRL_REG4 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 29. CTRL_REG4 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 30. CTRL_REG5 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 31. CTRL_REG5 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 32. Sleep-to-wake configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 33. REFERENCE register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 34. REFERENCE description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 35. STATUS_REG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 36. STATUS_REG description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 37. INT1_CFG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 38. INT1_CFG description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 39. Interrupt 1 source configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 40. INT1_SRC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 41. INT1_SRC description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 42. INT1_THS register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 43. INT1_THS description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 44. INT1_DURATION register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 45. INT2_DURATION description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 46. INT2_CFG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 47. INT2_CFG description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

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List of tables AIS3624DQ

Table 48. Interrupt mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 49. INT2_SRC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 50. INT2_SRC description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 51. INT2_THS register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 52. INT2_THS description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 53. INT2_DURATION register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 54. INT2_DURATION description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 55. Document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

6/41 DocID027117 Rev 2

AIS3624DQ List of figures

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 2. Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 3. SPI slave timing diagram (2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 4. I2C slave timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 5. AIS3624DQ electrical connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 6. Read and write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 7. SPI read protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 8. Multiple byte SPI read protocol (2-byte example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 9. SPI write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 10. Multiple byte SPI write protocol (2-byte example). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 11. SPI read protocol in 3-wire mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 12. QFN 24L: Mechanical data and package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 13. Recommended land and solder mask design for QFPN packages . . . . . . . . . . . . . . . . . . 38

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Block diagram and pin description AIS3624DQ

1 Block diagram and pin description

1.1 Block diagram

Figure 1. Block diagram

X+
Y+ CHARGE
Z+ AMPLIFIER CS

I2C SCL/SPC
a MUX
A/D
CONVERTER CONTROL
LOGIC
SDA/SDO/SDI
Z- SPI
SDO/SA0
Y-
X-

CONTROL LOGIC INT 1

TRIMMING
SELF TEST REFERENCE CLOCK &
CIRCUITS
INTERRUPT GEN. INT 2

1.2 Pin description

Figure 2. Pin connections

X
19 24
18 1

1
13 6
Y 7
12

DIRECTION OF THE (BOTTOM VIEW)

DETECTABLE
ACCELERATIONS

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AIS3624DQ Block diagram and pin description

Table 2. Pin description

Pin# Name Function

1,2 NC Not connected

3 INT_2 Inertial interrupt 2
4 Reserved Connect to GND
5 VDD Power supply
6 GND 0 V supply
7 INT_1 Inertial interrupt 1
8 GND 0 V supply
9 GND 0 V supply
10 GND 0 V supply
SPC SPI serial port clock (SPC)
11
SCL I2C serial clock (SCL)
SPI enable
12 CS
I2C/SPI mode selection (0: SPI enabled; 1: I2C mode)
13 Reserved Connect to Vdd
14 VDD_IO Power supply for I/O pins
SDO SPI serial data output (SDO)
15
SA0 I2C less significant bit of the device address (SA0)
SDI SPI serial data input (SDI)
16 SDO 3-wire interface serial data output (SDO)
SDA I2C serial data (SDA)
17-24 NC Not internally connected

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2 Mechanical and electrical specifications

2.1 Mechanical characteristics

Table 3. Mechanical characteristics @ Vdd = 3.3 V, T = -40 °C to +105 °C unless otherwise noted (1)
Symbol Parameter Test conditions Min. Typ. Max. Unit

FS bit set to 00 ±6
(2)
FS Measurement range FS bit set to 01 ±12 g
FS bit set to 11 ±24
FS bit set to 00
2.55 2.9 3.25
12-bit representation
FS bit set to 01
So Sensitivity 5.19 5.9 6.61 mg/digit
12-bit representation
FS bit set to 11
10.29 11.7 13.11
12-bit representation

Zero-g level offset X, Y axes -500 500

Off mg
accuracy(3),(4),(5) Z-axis -950 950
Typical zero-g level offset
TyOff FS bit set to 00 -90 ±70 90 mg
accuracy(6),(7)
Max delta from 25 °C
Zero-g level change vs -5 ±0.4 5
TCOff (X, Y axes) mg/°C
temperature
Max delta from 25 °C (Z-axis) -11.25 11.25
An Acceleration noise density FS bit set to 00 600 1500 μg/ Hz
FS bit set to 00
-40 -270 -500 LSb
X-axis
Self-test FS bit set to 00
Vst 40 270 500 LSb
output change(8),(9),(10) Y-axis
FS bit set to 00
120 510 900 LSb
Z-axis
Top Operating temperature range -40 +105 °C
Wh Product weight 55 mgram
1. The product is factory calibrated at 3.3 V. Operational power supply (Vdd) over 3.6 V it is not recommended.
2. Verified by wafer level test and measurement of initial offset and sensitivity
3. Typical zero-g level offset value after MSL3 preconditioning
4. Offset can be eliminated by enabling the built-in high-pass filter
5. Typical zero-g level offset value after MSL3 preconditioning
6. Typical zero-g level offset value after MSL3 preconditioning
7. Offset can be eliminated by enabling the built-in high-pass filter
8. The sign of “Self-test output change” is defined by a sign bit, for all axes.
9. Self-test output changes with the power supply. “Self-test output change” is defined as
OUTPUT[LSb](CTRL_REG4 ST bit=1) - OUTPUT[LSb](CTRL_REG4 ST bit=0). 1LSb=12g/4096 at 12-bit representation, ±6 g full
scale
10. Output data reach 99% of final value after 1/ODR+1ms when enabling self-test mode, due to device filtering

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2.2 Electrical characteristics

Table 4. Electrical characteristics @ Vdd = 3.3 V, T = -40 °C to +105 °C unless otherwise noted (1)
Symbol Parameter Test conditions Min. Typ. Max. Unit

Vdd Supply voltage 2.4 3.3 3.6 V

(2)
Vdd_IO I/O pins supply voltage 1.8 Vdd+0.1 V
Current consumption
Idd 2.4 V to 3.6 V 200 450 μA
in normal mode
Current consumption ODR=1 Hz, BW=500 Hz,
IddLP 8 10 12 μA
in low-power mode T=25°C
Current consumption in
IddPdn 0.1 1 2 μA
power-down mode
Digital high-level input
VIH 0.8*Vdd_IO V
voltage
VIL Digital low-level input voltage 0.2*Vdd_IO V
VOH High-level output voltage 0.9*Vdd_IO V
VOL Low-level output voltage 0.1*Vdd_IO V
DR bit set to 00 50

Output data rate DR bit set to 01 100

ODR Hz
in normal mode DR bit set to 10 400
DR bit set to 11 1000
PM bit set to 010 0.5
PM bit set to 011 1
Output data rate
ODRLP PM bit set to 100 2 Hz
in low-power mode
PM bit set to 101 5
PM bit set to 110 10
BW System bandwidth ODR/2 Hz
0.9/ODR+ 1/ODR+ 1.1/ODR+
Ton Turn-on time(3) ODR = 100 Hz s
1 ms 1 ms 1 ms
Top Operating temperature range -40 +105 °C
1. The product is factory calibrated at 3.3 V. Operational power supply (Vdd) over 3.6 V is not recommended.
2. It is possible to remove Vdd maintaining Vdd_IO without blocking the communication busses, in this condition the
measurement chain is powered off.
3. Time to obtain valid data after exiting power-down mode

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2.3 Communication interface characteristics

2.3.1 SPI - serial peripheral interface

Subject to general operating conditions for Vdd and Top.

Table 5. SPI slave timing values

Value (1)
Symbol Parameter Unit
Min Max

tc(SPC) SPI clock cycle 100 ns

fc(SPC) SPI clock frequency 10 MHz
tsu(CS) CS setup time 6
th(CS) CS hold time 8
tsu(SI) SDI input setup time 5
th(SI) SDI input hold time 15 ns
tv(SO) SDO valid output time 50
th(SO) SDO output hold time 9
tdis(SO) SDO output disable time 50

Figure 3. SPI slave timing diagram (2)

1. Values are guaranteed at 10 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results, not
tested in production.
2. Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both input and output ports.
3. When no communication is ongoing, data on CS, SPC, SDI and SDO are driven by internal pull-up resistors.

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2.3.2 I2C - inter-IC control interface

Subject to general operating conditions for Vdd and top.

Table 6. I2C slave timing values

I2C standard mode (1) I2C fast mode (1)
Symbol Parameter Unit
Min Max Min Max
f(SCL) SCL clock frequency 0 100 0 400 KHz
tw(SCLL) SCL clock low time 4.7 1.3
μs
tw(SCLH) SCL clock high time 4.0 0.6
tsu(SDA) SDA setup time 250 100 ns
th(SDA) SDA data hold time 0.01 3.45 0.01 0.9 μs
th(ST) START condition hold time 4 0.6
Repeated START condition
tsu(SR) 4.7 0.6
setup time
μs
tsu(SP) STOP condition setup time 4 0.6
Bus free time between STOP
tw(SP:SR) 4.7 1.3
and START condition
1. Data based on standard I2C protocol requirement, not tested in production

Figure 4. I2C slave timing diagram(a)

a. Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both ports.

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2.4 Absolute maximum ratings

Stresses above those listed as “absolute maximum ratings” may cause permanent damage
to the device. This is a stress rating only and functional operation of the device under these
conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.

Table 7. Absolute maximum ratings

Symbol Ratings Maximum value Unit

Vdd Supply voltage -0.3 to 4 V

Vdd_IO I/O pins supply voltage -0.3 to Vdd+0.1 V
Input voltage on any control pin
Vin -0.3 to Vdd_IO+0.3 V
(CS, SCL/SPC, SDA/SDI/SDO, SDO/SA0)
3000 g for 0.5 ms
APOW Acceleration (any axis, powered, Vdd = 2.5 V)
10000 g for 0.1 ms
3000 g for 0.5 ms
AUNP Acceleration (any axis, unpowered)
10000 g for 0.1 ms
TOP Operating temperature range -40 to +105 °C
TSTG Storage temperature range -40 to +125 °C
2 (HBM) kV
ESD Electrostatic discharge protection 500 (CDM) V
200 (MM) V

Note: Supply voltage on any pin should never exceed 4.0 V

This device is sensitive to mechanical shock, improper handling can cause
permanent damages to the part.
This device is sensitive to electrostatic discharge (ESD), improper handling can
cause permanent damages to the part.

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2.5 Terminology

2.5.1 Sensitivity
Sensitivity describes the gain of the sensor and can be determined, for example, by
applying 1 g acceleration to it. As the sensor can measure DC accelerations this can be
done easily by pointing the axis of interest towards the center of the Earth, noting the output
value, rotating the sensor by 180 degrees (pointing to the sky) and noting the output value
again. By doing so, ±1 g acceleration is applied to the sensor. Subtracting the larger output
value from the smaller one, and dividing the result by 2, leads to the actual sensitivity of the
sensor. This value changes very little over temperature and time. The sensitivity tolerance
describes the range of sensitivities of a large population of sensors.

2.5.2 Zero-g level

Zero-g level offset (TyOff) describes the deviation of an actual output signal from the ideal
output signal if no acceleration is present. A sensor in a steady state on a horizontal surface
will measure 0 g for the X-axis and 0 g for the Y-axis whereas the Z-axis will measure 1 g.
The output is ideally in the middle of the dynamic range of the sensor (content of OUT
registers 00h, data expressed as 2’s complement number). A deviation from the ideal value
in this case is called Zero-g offset. Offset is to some extent a result of stress to MEMS
sensor and therefore the offset can slightly change after mounting the sensor onto a printed
circuit board or exposing it to extensive mechanical stress. Offset changes little over
temperature, see “Zero-g level change vs. temperature”.

2.5.3 Self-test
Self-test allows checking the sensor functionality without moving it. The self-test function is
off when the self-test bit (ST) of CTRL_REG4 (control register 4) is programmed to ‘0‘.
When the self-test bit of CTRL_REG4 is programmed to ‘1’, an actuation force is applied to
the sensor, simulating a definite input acceleration. In this case the sensor outputs will
exhibit a change in their DC levels which are related to the selected full scale through the
device sensitivity. When self-test is activated, the device output level is given by the
algebraic sum of the signals produced by the acceleration acting on the sensor and by the
electrostatic test-force. If the output signals change within the amplitude specified inside
Table 3, then the sensor is working properly and the parameters of the interface chip are
within the defined specifications.

2.5.4 Sleep-to-wake
The “sleep-to-wakeup” function, in conjunction with low-power mode, allows to further
reduce the system power consumption and develop new smart applications.
AIS3624DQ may be set in a low-power operating mode, characterized by lower data rate
updates. In this way the device, even if sleeping, continues to sense acceleration and
generate interrupt requests.
When the “sleep-to-wake” function is activated, AIS3624DQ is able to automatically wake
up as soon as the interrupt event has been detected, increasing the output data rate and
bandwidth.
With this feature the system may be efficiently switched from low-power mode to full-
performance depending on user-selectable positioning and acceleration events, thus
ensuring power saving and flexibility.

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3 Functionality

The AIS3624DQ is a nano, low-power, digital output 3-axis linear accelerometer available or
housed in a QFN package. The complete device includes a sensing element and an IC
interface The device comprises a sensing element and an IC interface which communicates
through an I2C or SPI serial interface from the sensing element to the application.

3.1 Sensing element

A proprietary process is used to create a surface micromachined accelerometer. The
technology allows processing suspended silicon structures which are attached to the
substrate in a few points called anchors and are free to move in the direction of the sensed
acceleration. In order to be compatible with traditional packaging techniques, a cap is
placed on top of the sensing element to avoid blocking the moving parts during the molding
phase of the plastic encapsulation.
When an acceleration is applied to the sensor, the proof mass displaces from its nominal
position, causing an imbalance in the capacitive half-bridge. This imbalance is measured
using charge integration in response to a voltage pulse applied to the capacitor.
At steady state the nominal value of the capacitors are few pF and when an acceleration is
applied the maximum variation of the capacitive load is in the fF range.

3.2 IC interface
The complete measurement chain is composed of a low-noise capacitive amplifier which
converts the capacitive unbalancing of the MEMS sensor into an analog voltage using an
analog-to-digital converter.
The acceleration data may be accessed through an I2C/SPI interface thus making the
device particularly suitable for direct interfacing with a microcontroller.
The AIS3624DQ features a Data-Ready signal (RDY) which indicates when a new set of
measured acceleration data is available, thus simplifying data synchronization in the digital
system that uses the device.
The AIS3624DQ may also be configured to generate an inertial wakeup and free-fall
interrupt signal according to a programmed acceleration event along the enabled axes. Both
free-fall and wakeup can be available simultaneously on two different pins.

3.3 Factory calibration

The IC interface is factory calibrated for sensitivity (So) and Zero-g level (TyOff).
The trimming values are stored inside the device in a non-volatile memory. Any time the
device is turned on, the trimming parameters are downloaded into the registers to be
employed during active operation which allows the device to be used without further
calibration.

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4 Application hints

Figure 5. AIS3624DQ electrical connections

24 19
1 18

INT 2 SDA/SDI/SDO
TOP VIEW SDO/SA0

Vdd Vdd_IO
6 13
Z
7 12
100nF 10uF

X
SCL/SPC
INT 1

1
GND CS

Digital signal from/to signal controller. Signal levels are defined by proper selection of Vdd_IO

The device core is supplied through Vdd line while the I/O pads are supplied through the
Vdd_IO line. Power supply decoupling capacitors (100 nF ceramic, 10 μF aluminum) should
be placed as near as possible to the pin 14 of the device (common design practice).
All the voltage and ground supplies must be present at the same time to have proper
behavior of the IC (refer to Figure 5). It is possible to remove Vdd while maintaining Vdd_IO
without blocking the communication bus, in this condition the measurement chain is
powered off.
The functionality of the device and the measured acceleration data is selectable and
accessible through the I2C or SPI interfaces.When using the I2C, CS must be tied high.
The functions, the threshold and the timing of the two interrupt pins (INT 1 and INT 2) can be
completely programmed by the user through the I2C/SPI interface.

4.1 Soldering information

The QFN package is compliant with the ECOPACK®, RoHS and “Green” standard.
It is qualified for soldering heat resistance according to JEDEC J-STD-020C.
Leave “Pin 1 Indicator” unconnected during soldering.
Land pattern and soldering recommendations are available at www.st.com.

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5 Digital interfaces

The registers embedded inside the AIS3624DQ may be accessed through both the I2C and
SPI serial interfaces. The latter may be SW configured to operate either in 3-wire or 4-wire
interface mode.
The serial interfaces are mapped onto the same pads. To select/exploit the I2C interface, the
CS line must be tied high (i.e. connected to Vdd_IO).

Table 8. Serial interface pin description

Pin name Pin description

SPI enable
CS
I2C/SPI mode selection (1: I2C mode; 0: SPI enabled)
SCL I2C serial clock (SCL)
SPC SPI serial port clock (SPC)
SDA I2C serial data (SDA)
SDI SPI serial data input (SDI)
SDO 3-wire interface serial data output (SDO)
SA0 I2C less significant bit of the device address (SA0)
SDO SPI serial data output (SDO)

5.1 I2C serial interface

The AIS3624DQ I2C is a bus slave. The I2C is employed to write data into registers whose
content can also be read back.
The relevant I2C terminology is given in the table below.

Table 9. I2C terminology

Term Description

Transmitter The device which sends data to the bus

Receiver The device which receives data from the bus
The device which initiates a transfer, generates clock signals and terminates a
Master
transfer
Slave The device addressed by the master

There are two signals associated with the I2C bus: the serial clock line (SCL) and the Serial
DAta line (SDA). The latter is a bidirectional line used for sending and receiving the data
to/from the interface. Both the lines are connected to Vdd_IO through a pull-up resistor
embedded inside the AIS3624DQ. When the bus is free, both the lines are high.
The I2C interface is compliant with fast mode (400 kHz) I2C standards as well as with the
normal mode.

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5.1.1 I2C operation

The transaction on the bus is started through a START (ST) signal. A START condition is
defined as a HIGH-to-LOW transition on the data line while the SCL line is held HIGH. After
this has been transmitted by the master, the bus is considered busy. The next byte of data
transmitted after the start condition contains the address of the slave in the first 7 bits and
the eighth bit tells whether the master is receiving data from the slave or transmitting data to
the slave. When an address is sent, each device in the system compares the first seven bits
after a start condition with its address. If they match, the device considers itself addressed
by the master.
The Slave ADdress (SAD) associated to the AIS3624DQ is 001100xb. The SDO/SA0 pad
can be used to modify the less significant bit of the device address. If the SA0 pad is
connected to the voltage supply, LSb is ‘1’ (address 0011001b), else if the SA0 pad is
connected to ground, the LSb value is ‘0’ (address 0011000b). This solution permits to
connect and address two different accelerometers to the same I2C lines.
Data transfer with acknowledge is mandatory. The transmitter must release the SDA line
during the acknowledge pulse. The receiver must then pull the data line LOW so that it
remains stable low during the HIGH period of the acknowledge clock pulse. A receiver
which has been addressed is obliged to generate an acknowledge after each byte of data
received.
The I2C embedded inside the AIS3624DQ behaves like a slave device and the following
protocol must be adhered to. After the start condition (ST) a slave address is sent, once a
slave acknowledge (SAK) has been returned, an 8-bit sub-address (SUB) is transmitted: the
7 LSb represent the actual register address while the MSB enables address auto increment.
If the MSb of the SUB field is ‘1’, the SUB (register address) is automatically increased to
allow multiple data read/write.
The slave address is completed with a Read/Write bit. If the bit was ‘1’ (Read), a repeated
START (SR) condition must be issued after the two sub-address bytes; if the bit is ‘0’ (Write)
the master will transmit to the slave with direction unchanged. Table 10 explains how the
SAD+Read/Write bit pattern is composed, listing all the possible configurations.

Table 10. SAD+Read/Write patterns

Command SAD[6:1] SAD[0] = SA0 R/W SAD+R/W

Read 001100 0 1 00110001 (31h)

Write 001100 0 0 00110000 (30h)
Read 001100 1 1 00110011 (33h)
Write 001100 1 0 00110010 (32h)

Table 11. Transfer when master is writing one byte to slave

Master ST SAD + W SUB DATA SP
Slave SAK SAK SAK

Table 12. Transfer when master is writing multiple bytes to slave:

Master ST SAD + W SUB DATA DATA SP
Slave SAK SAK SAK SAK

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Table 13. Transfer when master is receiving (reading) one byte of data from slave:
Master ST SAD + W SUB SR SAD + R NMAK SP
Slave SAK SAK SAK DATA

Table 14. Transfer when master is receiving (reading) multiple bytes of data from slave
Master ST SAD+W SUB SR SAD+R MAK MAK NMAK SP
DAT DAT
Slave SAK SAK SAK DATA
A A

Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number
of bytes transferred per transfer is unlimited. Data is transferred with the Most Significant bit
(MSb) first. If a receiver can’t receive another complete byte of data until it has performed
some other function, it can hold the clock line, SCL LOW to force the transmitter into a wait
state. Data transfer only continues when the receiver is ready for another byte and releases
the data line. If a slave receiver doesn’t acknowledge the slave address (i.e. it is not able to
receive because it is performing some real time function) the data line must be left HIGH by
the slave. The master can then abort the transfer. A LOW-to-HIGH transition on the SDA
line while the SCL line is HIGH is defined as a STOP condition. Each data transfer must be
terminated by the generation of a STOP (SP) condition.
In order to read multiple bytes, it is necessary to assert the most significant bit of the sub-
address field. In other words, SUB(7) must be equal to 1 while SUB(6-0) represents the
address of first register to be read.
In the presented communication format MAK is Master acknowledge and NMAK is No
Master Acknowledge.

5.2 SPI bus interface

The AIS3624DQ SPI is a bus slave. The SPI allows writing to and reading from the registers
of the device.
The serial interface interacts with the outside world with 4 wires: CS, SPC, SDI and SDO.

Figure 6. Read and write protocol

CS

SPC

SDI
RW DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
MS AD5 AD4 AD3 AD2 AD1 AD0

SDO
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0

CS is the serial port enable and it is controlled by the SPI master. It goes low at the start of
the transmission and goes back high at the end. SPC is the serial port clock and it is
controlled by the SPI master. It is stopped high when CS is high (no transmission). SDI and

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SDO are respectively the serial port data input and output. Those lines are driven at the
falling edge of SPC and should be captured at the rising edge of SPC.
Both the read register and write register commands are completed in 16 clock pulses or in
multiple of 8 in the case of multiple read/write bytes. Bit duration is the time between two
falling edges of SPC. The first bit (bit 0) starts at the first falling edge of SPC after the falling
edge of CS while the last bit (bit 15, bit 23, ...) starts at the last falling edge of SPC just
before the rising edge of CS.

bit 0: RW bit. When 0, the data DI(7:0) is written into the device. When 1, the data DO(7:0)
from the device is read. In latter case, the chip will drive SDO at the start of bit 8.
bit 1: MS bit. When 0, the address will remain unchanged in multiple read/write commands.
When 1, the address is auto incremented in multiple read/write commands.
bit 2-7: address AD(5:0). This is the address field of the indexed register.
bit 8-15: data DI(7:0) (write mode). This is the data that is written into the device (MSb first).
bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first).
In multiple read/write commands further blocks of 8 clock periods will be added. When the
MS bit is ‘0’, the address used to read/write data remains the same for every block. When
the MS bit is ‘1’, the address used to read/write data is increased at every block.
The function and the behavior of SDI and SDO remain unchanged.

5.2.1 SPI read

Figure 7. SPI read protocol

CS

SPC

SDI
RW
MS AD5 AD4 AD3 AD2 AD1 AD0

SDO
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0

The SPI Read command is performed with 16 clock pulses. Multiple byte read command is
performed adding blocks of 8 clock pulses at the previous one.

bit 0: READ bit. The value is 1.

bit 1: MS bit. When 0, does not increment the address; when 1, increments the address in
multiple reads.
bit 2-7: address AD(5:0). This is the address field of the indexed register.
bit 8-15: data DO(7:0) (read mode). This is the data that will be read from the device (MSb
first).
bit 16-... : data DO(...-8). Further data in multiple byte reads.

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Figure 8. Multiple byte SPI read protocol (2-byte example)

CS

SPC

SDI
RW
MS AD5 AD4 AD3 AD2 AD1 AD0

SDO
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 DO15DO14DO13DO12DO11DO10DO9 DO8

5.2.2 SPI write

Figure 9. SPI write protocol

CS

SPC

SDI
RW DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
MS AD5 AD4 AD3 AD2 AD1 AD0

The SPI write command is performed with 16 clock pulses. A multiple byte write command
is performed by adding blocks of 8 clock pulses to the previous one.
bit 0: WRITE bit. The value is 0.
bit 1: MS bit. When 0, does not increment the address; when 1, increments the address in
multiple writes.
bit 2 -7: address AD(5:0). This is the address field of the indexed register.
bit 8-15: data DI(7:0) (write mode). This is the data that is written inside the device (MSb
first).
bit 16-... : data DI(...-8). Further data in multiple byte writes.

Figure 10. Multiple byte SPI write protocol (2-byte example)

CS

SPC

SDI
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DI15 DI14 DI13 DI12 DI11 DI10 DI9 DI8
RW
MS AD5 AD4 AD3 AD2 AD1 AD0

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5.2.3 SPI read in 3-wire mode

3-wire mode is entered by setting bit SIM to ‘1’ (SPI serial interface mode selection) in
CTRL_REG4.

Figure 11. SPI read protocol in 3-wire mode

CS

SPC

SDI/O
RW DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
MS AD5 AD4 AD3 AD2 AD1 AD0

The SPI read command is performed with 16 clock pulses:

bit 0: READ bit. The value is 1.
bit 1: MS bit. When 0, does not increment the address; when 1, increments the address in
multiple reads.
bit 2-7: address AD(5:0). This is the address field of the indexed register.
bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first).
A multiple read command is also available in 3-wire mode.

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6 Register mapping

The table given below provides a list of the 8-bit registers embedded in the device and the
corresponding addresses.

Table 15. Register address map

Register address
Name Type Default Comment
Hex Binary

Reserved (do not modify) 00 - 0E Reserved

WHO_AM_I r 0F 000 1111 00110010 Dummy register
Reserved (do not modify) 10 - 1F Reserved
CTRL_REG1 rw 20 010 0000 00000111
CTRL_REG2 rw 21 010 0001 00000000
CTRL_REG3 rw 22 010 0010 00000000
CTRL_REG4 rw 23 010 0011 00000000
CTRL_REG5 rw 24 010 0100 00000000
HP_FILTER_RESET r 25 010 0101 Dummy register
REFERENCE rw 26 010 0110 00000000
STATUS_REG r 27 010 0111 00000000
OUT_X_L r 28 010 1000 output
OUT_X_H r 29 010 1001 output
OUT_Y_L r 2A 010 1010 output
OUT_Y_H r 2B 010 1011 output
OUT_Z_L r 2C 010 1100 output
OUT_Z_H r 2D 010 1101 output
Reserved (do not modify) 2E - 2F Reserved
INT1_CFG rw 30 011 0000 00000000
INT1_SOURCE r 31 011 0001 00000000
INT1_THS rw 32 011 0010 00000000
INT1_DURATION rw 33 011 0011 00000000
INT2_CFG rw 34 011 0100 00000000
INT2_SOURCE r 35 011 0101 00000000
INT2_THS rw 36 011 0110 00000000
INT2_DURATION rw 37 011 0111 00000000
Reserved (do not modify) 38 - 3F Reserved

Registers marked as Reserved must not be changed. Writing to those registers may cause
permanent damage to the device.The content of the registers that are loaded at boot should
not be changed. They contain the factory calibration values. Their content is automatically
restored when the device is powered up.

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7 Register description

The device contains a set of registers which are used to control its behavior and to retrieve
acceleration data. The register address, made of 7 bits, is used to identify them and to write
the data through the serial interface.

7.1 WHO_AM_I (0Fh)

Table 16. WHO_AM_I register

0 0 1 1 0 0 1 0

Device identification register.

This register contains the device identifier that for AIS3624DQ is set to 32h.

7.2 CTRL_REG1 (20h)

Table 17. CTRL_REG1 register

PM2 PM1 PM0 DR1 DR0 Zen Yen Xen

Table 18. CTRL_REG1 description

Power mode selection. Default value: 000
PM2 - PM0
(000: Power-down; Others: refer to Table 19)
Data rate selection. Default value: 00
DR1 - DR0
(00: 50 Hz; Others: refer to Table 20)
Z-axis enable. Default value: 1
Zen
(0: Z-axis disabled; 1: Z-axis enabled)
Y-axis enable. Default value: 1
Yen
(0: Y-axis disabled; 1: Y-axis enabled)
X axis enable. Default value: 1
Xen
(0: X-axis disabled; 1: X-axis enabled)

The PM bits allow selecting between power-down and two operating active modes. The
device is in power-down mode when the PD bits are set to “000” (default value after boot).
Table 19 shows all the possible power mode configurations and respective output data
rates. Output data in the low-power modes are computed with low-pass filter cutoff
frequency defined by the DR1 and DR0 bits.
The DR bits, in the normal-mode operation, select the data rate at which acceleration
samples are produced. In low-power mode they define the output data resolution. Table 20
shows all the possible configurations for the DR1 and DR0 bits.

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Table 19. Power mode and low-power output data rate configurations
Output data rate [Hz]
PM2 PM1 PM0 Power mode selection
ODRLP

0 0 0 Power-down --
0 0 1 Normal mode ODR
0 1 0 Low-power 0.5
0 1 1 Low-power 1
1 0 0 Low-power 2
1 0 1 Low-power 5
1 1 0 Low-power 10

Table 20. Normal-mode output data rate configurations and low-pass cutoff
frequencies
Output Data Rate [Hz] Low-pass filter cutoff
DR1 DR0
ODR frequency [Hz]

0 0 50 37
0 1 100 74
1 0 400 292
1 1 1000 780

7.3 CTRL_REG2 (21h)

Table 21. CTRL_REG2 register
BOOT HPM1 HPM0 FDS HPen2 HPen1 HPCF1 HPCF0

Table 22. CTRL_REG2 description

Reboot memory content. Default value: 0
BOOT
(0: normal mode; 1: reboot memory content)
High-pass filter mode selection. Default value: 00
HPM1, HPM0
(00: normal mode; Others: refer to Table 23)
Filtered data selection. Default value: 0
FDS
(0: internal filter bypassed; 1: data from internal filter sent to output register)
High-pass filter enabled for interrupt 2 source. Default value: 0
HPen2
(0: filter bypassed; 1: filter enabled)
High-pass filter enabled for interrupt 1 source. Default value: 0
HPen1
(0: filter bypassed; 1: filter enabled)

HPCF1, High-pass filter cutoff frequency configuration. Default value: 00

HPCF0 (00: HPc=8; 01: HPc=16; 10: HPc=32; 11: HPc=64)

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The BOOT bit is used to refresh the content of internal registers stored in the flash memory
block. At the device power-up the content of the flash memory block is transferred to the
internal registers related to the trimming functions to allow correct behavior of the device
itself. If for any reason the content of trimming registers is changed, it is sufficient to use this
bit to restore the correct values. When the BOOT bit is set to ‘1’, the content of internal flash
is copied inside the corresponding internal registers and it is used to calibrate the device.
These values are factory trimmed and they are different for every accelerometer. They allow
correct behavior of the device and normally they have not to be changed. At the end of the
boot process the BOOT bit is set again to ‘0’.

Table 23. High-pass filter mode configuration

HPM1 HPM0 High-pass filter mode

0 0 Normal mode (reset by reading HP_RESET_FILTER)

0 1 Reference signal for filtering
1 0 Normal mode (reset by reading HP_RESET_FILTER)

HPCF[1:0]. These bits are used to configure the high-pass filter cutoff frequency ft which is
given by:

1 - f s
f t = ln  1 – -----------  ------
 HPc 2

The equation can be simplified to the following approximation:

fs
f t = -------------------
6  HPc

Table 24. High-pass filter cutoff frequency configuration

ft [Hz] ft [Hz] ft [Hz] ft [Hz]
HPcoeff2,1
Data rate = 50 Hz Data rate = 100 Hz Data rate = 400 Hz Data rate = 1000 Hz

00 1 2 8 20
01 0.5 1 4 10
10 0.25 0.5 2 5
11 0.125 0.25 1 2.5

7.4 CTRL_REG3 [interrupt CTRL register] (22h)

Table 25. CTRL_REG3 register

IHL PP_OD LIR2 I2_CFG1 I2_CFG0 LIR1 I1_CFG1 I1_CFG0

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Table 26. CTRL_REG3 description

Interrupt active high, low. Default value: 0
IHL
(0: active high; 1:active low)
Push-pull/Open-drain selection on interrupt pads. Default value 0.
PP_OD
(0: push-pull; 1: open-drain)
Latch interrupt request on INT2_SRC register, with INT2_SRC register cleared by
LIR2 reading INT2_SRC itself. Default value: 0.
(0: interrupt request not latched; 1: interrupt request latched)
I2_CFG1, Data signal on INT 2 pad control bits. Default value: 00.
I2_CFG0 (see table below)
Latch interrupt request in the INT1_SRC register, with INT1_SRC register cleared by
LIR1 reading INT1_SRC register. Default value: 0.
(0: interrupt request not latched; 1: interrupt request latched)
I1_CFG1, Data signal on INT 1 pad control bits. Default value: 00.
I1_CFG0 (see table below)

Table 27. Data signal on INT 1 and INT 2 pads

I1(2)_CFG1 I1(2)_CFG0 INT 1(2) Pad

0 0 Interrupt 1 (2) source

0 1 Interrupt 1 source OR interrupt 2 source
1 0 Data ready
1 1 Boot running

7.5 CTRL_REG4 (23h)

Table 28. CTRL_REG4 register
BDU BLE FS1 FS0 STsign 0 ST SIM

Table 29. CTRL_REG4 description

Block data update. Default value: 0
BDU
(0: continuous update; 1: output registers not updated between MSB and LSB reading)
Big/little endian data selection. Default value 0.
BLE
(0: data LSB @ lower address; 1: data MSB @ lower address)
Full-scale selection. Default value: 00.
FS1, FS0
(00: ±6 g; 01: ±12 g; 11: ±24 g)
Self-test sign. Default value: 00.
STsign
(0: self-test plus; 1 self-test minus)
Self-test enable. Default value: 0.
ST
(0: self-test disabled; 1: self-test enabled)
SPI serial interface mode selection. Default value: 0.
SIM
(0: 4-wire interface; 1: 3-wire interface)

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The BDU bit is used to inhibit the update of the output registers until both upper and lower
register parts are read. In default mode (BDU=0), the output register values are updated
continuously. When the BDU is activated (BDU =1), the content of the output registers is not
updated until both MSB and LSB are read which avoids reading values related to different
sample times.

7.6 CTRL_REG5 (24h)

Table 30. CTRL_REG5 register

0 0 0 0 0 0 TurnOn1 TurnOn0

Table 31. CTRL_REG5 description

TurnOn1,
Turn-on mode selection for sleep-to-wake function. Default value: 00.
TurnOn0

The TurnOn bits are used for turning on the sleep-to-wake function.

Table 32. Sleep-to-wake configuration

TurnOn1 TurnOn0 Sleep-to-wake status

0 0 Sleep-to-wake function is disabled

Turned on: The device is in low power mode (ODR is defined in
1 1
CTRL_REG1)

Setting the TurnOn[1:0] bits to 11, the “sleep-to-wake” function is enabled. When an
interrupt event occurs, the device returns to normal mode, increasing the ODR to the value
defined in CTRL_REG1. Although the device is in normal mode, CTRL_REG1 content is not
automatically changed to “normal mode” configuration.

7.7 HP_FILTER_RESET (25h)

Dummy register. Reading from this address zeroes instantaneously the content of the
internal high-pass filter. If the high-pass filter is enabled, all three axes are instantaneously
set to 0 g. This allows nullifying the settling time of the high-pass filter.

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7.8 REFERENCE (26h)

Table 33. REFERENCE register
Ref7 Ref6 Ref5 Ref4 Ref3 Ref2 Ref1 Ref0

Table 34. REFERENCE description

Ref7 - Ref0 Reference value for high-pass filter. Default value: 00h.

This register sets the acceleration value taken as a reference for the high-pass filter output.
When the filter is turned on (at least one of the FDS, HPen2, or HPen1 bits is equal to ‘1’),
and HPM bits are set to “01”, the filter output is generated, taking this value as a reference.

7.9 STATUS_REG (27h)

Table 35. STATUS_REG register

ZYXOR ZOR YOR XOR ZYXDA ZDA YDA XDA

Table 36. STATUS_REG description

X-, Y- and Z-axis data overrun. Default value: 0
ZYXOR (0: no overrun has occurred;
1: new data has overwritten the previous data before it was read)
Z-axis data overrun. Default value: 0
ZOR (0: no overrun has occurred;
1: new data for the Z-axis has overwritten the previous data)
Y-axis data overrun. Default value: 0
YOR (0: no overrun has occurred;
1: a new data for the Y-axis has overwritten the previous data)
X-axis data overrun. Default value: 0
XOR (0: no overrun has occurred;
1: new data for the X-axis has overwritten the previous data)
ZYXDA X-, Y- and Z-axis new data available. Default value: 0
(0: a new set of data is not yet available; 1: a new set of data is available)
ZDA Z-axis new data available. Default value: 0
(0: new data for the Z-axis is not yet available;
1: new data for the Z-axis is available)
YDA Y-axis new data available. Default value: 0
(0: new data for the Y-axis is not yet available;
1: new data for the Y-axis is available)
XDA X-axis new data available. Default value: 0
(0: new data for the X-axis is not yet available;
1: new data for the X-axis is available)

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7.10 OUT_X_L (28h), OUT_X_H (29)

X-axis acceleration data. The value is expressed as two’s complement.

7.11 OUT_Y_L (2Ah), OUT_Y_H (2Bh)

Y-axis acceleration data. The value is expressed as two’s complement.

7.12 OUT_Z_L (2Ch), OUT_Z_H (2Dh)

Z-axis acceleration data. The value is expressed as two’s complement.

7.13 INT1_CFG (30h)

Table 37. INT1_CFG register

AOI 6D ZHIE ZLIE YHIE YLIE XHIE XLIE

Table 38. INT1_CFG description

AND/OR combination of Interrupt events. Default value: 0
AOI
(See Table 39)
6-direction detection function enable. Default value: 0
6D
(See Table 39)
Enable interrupt generation on Z high event. Default value: 0
ZHIE (0: disable interrupt request;
1: enable interrupt request on measured accel. value higher than preset threshold)
Enable interrupt generation on Z low event. Default value: 0
ZLIE (0: disable interrupt request;
1: enable interrupt request on measured accel. value lower than preset threshold)
Enable interrupt generation on Y high event. Default value: 0
YHIE (0: disable interrupt request;
1: enable interrupt request on measured accel. value higher than preset threshold)
Enable interrupt generation on Y low event. Default value: 0
YLIE (0: disable interrupt request;
1: enable interrupt request on measured accel. value lower than preset threshold)
Enable interrupt generation on X high event. Default value: 0
XHIE (0: disable interrupt request;
1: enable interrupt request on measured accel. value higher than preset threshold)
Enable interrupt generation on X low event. Default value: 0
XLIE (0: disable interrupt request;
1: enable interrupt request on measured accel. value lower than preset threshold)

Configuration register for Interrupt 1 source.

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Table 39. Interrupt 1 source configurations

AOI 6D Interrupt mode

0 0 OR combination of interrupt events

0 1 6-direction movement recognition
1 0 AND combination of interrupt events
1 1 6-direction position recognition

7.14 INT1_SRC (31h)

Table 40. INT1_SRC register
0 IA ZH ZL YH YL XH XL

Table 41. INT1_SRC description

Interrupt active. Default value: 0
IA
(0: no interrupt has been generated; 1: one or more interrupts have been generated)
Z high. Default value: 0
ZH
(0: no interrupt, 1: Z high event has occurred)
Z low. Default value: 0
ZL
(0: no interrupt; 1: Z low event has occurred)
Y high. Default value: 0
YH
(0: no interrupt, 1: Y high event has occurred)
Y low. Default value: 0
YL
(0: no interrupt, 1: Y low event has occurred)
X high. Default value: 0
XH
(0: no interrupt, 1: X high event has occurred)
X low. Default value: 0
XL
(0: no interrupt, 1: X low event has occurred)

Interrupt 1 source register. Read-only register.

Reading at this address clears the INT1_SRC IA bit (and the interrupt signal on the INT 1
pin) and allows the refresh of data in the INT1_SRC register if the latched option was
chosen.

7.15 INT1_THS (32h)

Table 42. INT1_THS register
0 THS6 THS5 THS4 THS3 THS2 THS1 THS0

Table 43. INT1_THS description

THS6 - THS0 Interrupt 1 threshold. Default value: 000 0000

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7.16 INT1_DURATION (33h)

Table 44. INT1_DURATION register

0 D6 D5 D4 D3 D2 D1 D0

Table 45. INT2_DURATION description

D6 - D0 Duration value. Default value: 000 0000

The D6 - D0 bits set the minimum duration of the Interrupt 2 event to be recognized.
Duration steps and maximum values depend on the ODR chosen.

7.17 INT2_CFG (34h)

Table 46. INT2_CFG register

AOI 6D ZHIE ZLIE YHIE YLIE XHIE XLIE

Table 47. INT2_CFG description

AND/OR combination of interrupt events. Default value: 0
AOI
(See Table 48)
6-direction detection function enable. Default value: 0
6D
(See Table 48)
Enable interrupt generation on Z high event. Default value: 0
ZHIE (0: disable interrupt request;
1: enable interrupt request on measured accel. value higher than preset threshold)
Enable interrupt generation on Z low event. Default value: 0
ZLIE (0: disable interrupt request;
1: enable interrupt request on measured accel. value lower than preset threshold)
Enable interrupt generation on Y high event. Default value: 0
YHIE (0: disable interrupt request;
1: enable interrupt request on measured accel. value higher than preset threshold)
Enable interrupt generation on Y low event. Default value: 0
YLIE (0: disable interrupt request;
1: enable interrupt request on measured accel. value lower than preset threshold)
Enable interrupt generation on X high event. Default value: 0
XHIE (0: disable interrupt request;
1: enable interrupt request on measured accel. value higher than preset threshold)
Enable interrupt generation on X low event. Default value: 0
XLIE (0: disable interrupt request;
1: enable interrupt request on measured accel. value lower than preset threshold)

Configuration register for Interrupt 2 source.

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Table 48. Interrupt mode configuration

AOI 6D Interrupt mode

0 0 OR combination of interrupt events

0 1 6-direction movement recognition
1 0 AND combination of interrupt events
1 1 6-direction position recognition

7.18 INT2_SRC (35h)

Table 49. INT2_SRC register
0 IA ZH ZL YH YL XH XL

Table 50. INT2_SRC description

Interrupt active. Default value: 0
IA
(0: no interrupt has been generated; 1: one or more interrupts have been generated)
Z high. Default value: 0
ZH
(0: no interrupt, 1: Z high event has occurred)
Z low. Default value: 0
ZL
(0: no interrupt; 1: Z low event has occurred)
Y high. Default value: 0
YH
(0: no interrupt, 1: Y high event has occurred)
Y low. Default value: 0
YL
(0: no interrupt, 1: Y low event has occurred)
X high. Default value: 0
XH
(0: no interrupt, 1: X high event has occurred)
X Low. Default value: 0
XL
(0: no interrupt, 1: X low event has occurred)

Interrupt 2 source register. Read-only register.

Reading at this address clears the INT2_SRC IA bit (and the interrupt signal on the INT 2
pin) and allows the refresh of data in the INT2_SRC register if the latched option was
chosen.

7.19 INT2_THS (36h)

Table 51. INT2_THS register
0 THS6 THS5 THS4 THS3 THS2 THS1 THS0

Table 52. INT2_THS description

THS6 - THS0 Interrupt 1 threshold. Default value: 000 0000

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7.20 INT2_DURATION (37h)

Table 53. INT2_DURATION register

0 D6 D5 D4 D3 D2 D1 D0

Table 54. INT2_DURATION description

D6 - D0 Duration value. Default value: 000 0000

The D6 - D0 bits set the minimum duration of the Interrupt 2 event to be recognized.
Duration time steps and maximum values depend on the ODR chosen.

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Package information AIS3624DQ

8 Package information

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.

8.1 QFN 24L package information

Figure 12. QFN 24L: Mechanical data and package outline

OUTLINE AND
MECHANICAL DATA

QFPN-24 (4x4x1.8mm)
Quad Flat Package No lead

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9 Soldering information

The QFPN-24 package is compliant with the ECOPACK®, RoHS and “Green” standard.
It is qualified for soldering heat resistance according to JEDEC J-STD-020C, in MSL3
conditions.
For complete land pattern and soldering recommendations, please refer to the technical
note TN0019 available on www.st.com.

9.1 General guidelines for soldering surface-mount MEMS

sensors
The following three elements must be considered in order to adhere to common PCB design
and good industrial practices when soldering MEMS sensors:
1. PCB with its own conductive layers (i.e. copper) and other organic materials used for
board protection and dielectric isolation.
2. Accelerometer to be mounted on the board. The accelerometer senses acceleration,
but it senses also the mechanical stress coming from the board. This stress is
minimized with simple PCB design rules.
3. Soldering paste like Sn/Ag/Cu. This soldering paste can be dispensed on the board
with a screen printing method through a stencil. The pattern of the soldering paste on
the PCB is given by the stencil mask itself.

9.2 PCB design guidelines

PCB land and solder masking general recommendations are shown in Figure 13. Refer to
Figure 12 for specific package size, land count and pitch.
– It is recommended to open solder mask external to PCB land;
– It is mandatory, for correct device functionality, to ensure that some clearance is
present between the accelerometer thermal pad and PCB. In order to obtain this
clearance it is recommended to open the PCB thermal pad solder mask
– The area below the sensor (on the same side of the board) must be defined as a
keep-out area. It is strongly recommended to not place any structure on the top metal
layer underneath the sensor;
– Traces connected to pads should be as symmetric as possible. Symmetry and
balance for pad connection will help component self-alignment and will lead to a
better control of solder paste reduction after reflow;
– For better performance over temperature it is strongly recommended not to place
large insertion components like buttons or shielding boxes at distances less than 2
mm from the sensor
– Central die pad and “Pin 1 Indicator” are physically connected to GND. Leave “Pin 1
Indicator” unconnected during soldering.

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9.3 PCB design rules

Figure 13. Recommended land and solder mask design for QFPN packages

A = Clearance from PCB land edge to solder mask opening ≤0.1 mm to ensure that some
solder mask remains between PCB pads
B = PCB land length = QFPN solder pad length + 0.1 mm
C = PCB land width = QFPN solder pad width + 0.1 mm
D = PCB thermal pad solder mask opening = QFPN thermal pad side + 0.2 mm
The thermal pad must not be soldered.

9.4 Stencil design and solder paste application

The thickness and the pattern of the soldering paste are important for the proper device
mounting process
– Stainless steel stencils are recommended for solder paste application;
– A stencil thickness of 125 - 150 μm (5 - 6 mils) is recommended for screen printing;
– The final thickness of soldering paste should allow proper cleaning of flux residuals
and clearance between sensor package and PCB;
– Stencil aperture should have a rectangular shape with dimension up to 25 μm (1 mil)
smaller than PCB land;
– The openings of the stencil for the signal pads should be between 50% and 80% of
the PCB pad area;
– Optionally, for better solder paste release, the aperture walls should be trapezoidal
and the corners rounded;
– The fine pitch of the IC leads requires accurate alignment of the stencil to the printed
circuit board. The stencil and printed circuit assembly should be aligned to within 25
μm (1 mil) prior to application of the solder paste.

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9.5 Process considerations

– If self-cleaning solder paste is not used, it is mandatory to properly wash the board
after soldering to eliminate any possible source of leakage between adjacent pads
due to flux residues;
– The PCB soldering profile depends on the number, size and placement of
components in the application board. The customer should use a time and
temperature reflow profile that is derived from the PCB design and manufacturing
specifications.

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10 Revision history

Table 55. Document revision history

Date Revision Changes

10-Nov-2014 1 Initial release

14-Dec-2015 2 Updated Figure 5: AIS3624DQ electrical connections

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© 2015 STMicroelectronics – All rights reserved

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