Dr. SUJATHA.

S
CHRIST UNIVERSITY
1201

раде о
LINIT-I-NOTES
ARM EMBEDDED SYSTEM
1.
INTRODUCTION

The
ARM
processor
is
a

32 bit Embedded

Syste
ms.
ARM Cores
ale

used un
mobile
phones,
all

ARM
 processor
widel
y
land a multitud
handheld olganisen
land a portable
consumer devices
The Most Suxenfull cores
of
is
ARM 7 TDM I

it
provide
s
up

to 120 Dhrystone
MIPS and is
Code density and low its
 high code density
it ideal

Power consumption.
making
known
зое

Embedded device.

1-1 The RISC Design

Philosophy:
Zor
mobile
Greate
Complexit
y.
CISC

Complier
Code
Genuation

Processo
r
 Fig:
RISC

499

Greald Complier Complexity

Code Genuation

Processors

Dr. SUJATHA'S

Py
12/2020
ARM - ADVANED RISC
MACHINE
The arm
Core uses
a

RISE architectur.

RI: it is simple
instruction
 instruction
taking
cycle
.
The

taking one
it uses very few instruction
refer memory.
are executed by hardware.
it user
in strution

fixed format instruction and

wes zew wristructions
mode and most
it uses few addrering
 instructions have register to
register addressing mode. it
makes use of multiple register
seb it is highly pipelined but
complexity
the
compiler.
The RISC
philosophy major
design
1,
Instructions:
rueles:
 Refer RI
--

is

is
in

implemented with
four

instructions is

2. Pipelines: The
processing of ins
broken down unto smaller units that can
llel
executed in
There is

executad
by
on

by
pipelines
.
no need
an

a
miniprogram
CISC program.
be

instruction to be
called microcode
as
UNIT - NOTES
 regulo
Page 2

3. Registers - RISC Machines have a

large genual purpose reegisler sel. Any
register can contain li the dala ve an
addren. Registers act as the fast
local memory & love
зон all date
procensing operations. In
Contrust, CIC procesors have
dedicated regista fus
Specific
purposes.
4 Load Store Architecture -
1.2

regist
ers.
The procesor opciales on data
held in Separate load & store
instructions transfer dala blw
ter bank and External
regist
er
Memory
accese,
ассеты злот
because you
cain
оне
тето
m

oy
costly, so separating
memory
tag
e
dalo provening provide an
advan
use dala item held in the
register bank multiple times without
needing multiple memory
In Contrast, with CISC
design the dala
procesing
operation can act on memory
accuses.

directl
y.
Difference blw
६
RISC & CISC

RISC
CISC
1
 1

Dr. SUJATHA.S

Pyt$/12/
2020
A

1.

one
cycle
RISC

Simple instruction taking

complex instruction
CISC

takin
g
 multiple
cycles

2. Very few
instructure
Most of
unstructions
may
refers
to m
memor
y
refer memory
Ъ

z Instruction are executed

by
hardware
Instruction are
 microprogra
m.
execiled
bij
by

4. Fined format instructions Variable formal

instruction
5 19
Few instructions

6.

Few addressing
mode, and most
instructions have!
register to register
addressing
mode.
7. Complexed
addreni

8.
are

enin
g
mode

Synthesized in
Softwar
Multiple register
sets
9. Highly
pipelined
io
Complexity
Compil
e
is in the
1
1
‫اماره‬

by Instructions
Man
y
1915

Many addressing
modes
30

to complex
addrening
Support
s
moder
 Single registe set Not
pipelined.:
is in the
Complex
ity
micro
program
un
UNIT-I
NOTES
Påg.

1.2: The ARM Design

Philosophy.
Instruction set for
Embedded
Systems:
the pure
that makes the
The ARM instruction set diffous
from RISC definition in several
ARM instruction Set Suitable
applications:
ways
Set Suitable for
Embedded
1. Variable cycle execution for Certain
instructions &
every
Not ev
cycle.
ARM instruction executes un va

For
example
vary in the
number
upon the number
 Single
Load Store multiple
instructions.
execution cycles
depending
of
of resgistoy being
tramferred. The transfer can be
sequential memory
which ui faste the random access.
•

ассеи

multipl
e
Code density is also improved
since register
 the tramfers are common operation
at the Stout & end
q
functions
2. Inline barrel Shifter leading to more
complex
instructions.
The
-

unline barrel schifter is a hardware

one of the input
registas Component that preprocesser
before it is used by an instruction
This expands the capability of
many instructions
core performance and
code density.
 to improve

Dr. SUJATHA
S

Lyft
$131/2
020
W.

Thumb 16 bit instruction set:

ARM
Enhance, the processor
love

core by
adding
a second 16 bit instruction set called
that permits the
ARM Core 16 of 82 bit
instructions.
Thumb
 to execute either

The 16 bit instruction, improve

code density
about 30% over 32 bit fixed length
instruction
·
by
Conditional Execution:
An instruction is
only executed
when a Specific Condition has been
satisfied. These feature improves pro
formace
density by reducing
branch instruction.
* Enhanced instructions:
‫دان‬
and code

The Enhanced DSP instructions were

added to the standard ARM instructions set to
Support fast 16x16 bit multiplier
operations &
Saturation.
These instructions allow a
fasles
performing
ARM processor to replace the
baditional
Combinations
a processor plus
a DSP...
 да

U SI"

1.3
UNIT-T
NOTES
·

EMBEDDED SYSTEM
HARDWARE
Pg-4

ARM

PROCESSO
R

PRO
CE
070
ROM

MEMOR
Y
CONTROLLE
R
SRAM
FLASH
ROM

DRAN

AHB-

Interrupt
EXTERNAL
BRIDGE,
Controller!
EXTERNAL
Bus

AHB
Arbites

REAL TIME
CLOCK
CONSOL
E
SERIAL
HART'S

AHB-AP
B
bridge
Bear

ETHERNET
ETHERNET
PHYSICAL
DRIVER

COUNTER
TIMERS

ARM
CONTROLLERS
PERI
PHERALS
Bus

FIG 2: ARM BASED EMBEDDED

 DEVICE.

Dr.
SUJATHAS
fight
$12/2020
The
Each box represents a feature of
function lines connecting the boxes
are the buses carrying
data.
The
Four main
Hardwork
Hardwan Components
are:
The ARM processor controls the
 embedded device. "Different version
of the ARM processor are available
• to suit the desired
operating characteristics.
it consist core plus the
surrounding
q Components that
interface it with a bus. These
components can and caches.
नै
Controllers :- These are
include memory
management
functional
blocks
g
the
 System. Two Commonly found
Controllers are interrupt and
memory
Controllers.IT
JAS

Peripherals: it provides all the

i/p-o/p capability to the chip and are
responsible for the uniquenen of the
Embedded device.
external

A bus is used to・ Communicate blw

different
the device. parts of
*
3

рад-5
ARM Bus
Technology:
There
are

two different
classes
of
devices
a

attached to the bus. The ARM

processor love is
bus master

Master Bus:- A logical device

capable of initiating a dala transfer
with another device across the
same bus.

Peripherals lend to be bus

slaves.
Bus Slaves: dogical devices
capable only of responding to
a leanzer request from
bus mascle device.
a
bus

The bus has two architecture levels.o

a

The foist
is
physical level that covers the
electrical characterity and bus width: (16,32
0164bita) Thesecond level deals with
protocol it governs the communication
between the processor
peripheral.
ARM
 and a

Dr. SUJATHA'S

1112/20
00
な

AMBA Bus Protocol

:-
The Advance Microcontroller Bus Architection
(AMBA) 1996 and has been widely
adopted
was introduced in
as the
processors.
 on chip bus architecture
used

The first
AMBA
bus
зое
ARM-

was introduced
by ARM system Bus (ASB) and ARM
peripheral Bus (APE)
дублет daler ARM introduced
another bus design called ARM
High Performance Bus (AHB).
they
design using AMBA, peripheral
designers can reuse the
mutiple
projects. as same design on
large
numbee
AMBA interface
A
of peripnicals developed
with an

оп

on untuzau for
peripheral can simply be balled onto the
on-chip bus without having to
redesign each different processes
archilativo.
16

worchi
 lativo.
This plug & play intre face for H/W
developers um prover availability &
time to market Features if AHB
and ASB: FeaturesnewAHB
AHB

it
provides High
data
through
put

2.

Multiplexed bus
scheme
ASB
 it provides
dow data
throughput
Bidirectional Bus
desig
n
3. it runs high
clock Speeds for
64 & 128bits.

ARM AHB
bus
Pag-6

it is limited

has introduced two variations on the

 1. Multi
layer
AHB
2. AHB diele

AHB & multilayer AHB

support same protocol for
master and slave but have different
in for connects
(MAHB)
n

hence
they n
"have used for systems
They also provide Occur in
parallel & allow for higher
shown in
 fig.
with multiple
processors.
operations to occur
in throughput rates
Memory
:-
as

An embedded system has to

have some foem of memory to store and
execute code. They need to
performance and
power consumption: compare price
when deciding upon specific
memory
 upon specific memory
characteristic hierarchy needs to be
considered are. width and type.
The

if
memory
mountain a
à
har to run
twice as fast to
desired bandwidth then the
memory
be
higher.
requirement
may
 Do⋅
SUJATHAS
Mট
Cache

IMB
IFICA

Main
memory

1GB

Seconda
ry
Storage.
=>
Memory
size
 Pay
12
то
тр
а
WIDTH!
-
The m
memory
width
Wis

the number
of
bit the memo
memo
ry
04

returns on each accus. typically 8, 16,

32 of 64 bib.
 width has a
The mer
overall if
we
memo
ry
ale

different effect on
the
performace and cast
states.
using
uncached
ARM unstruction
and
processor will have
system
 using;
bit
16 bit wide memory
chips. then
two memory
fetcher /instructies. Each fetch
requiis two 16 bit loads. it seeduces
System preformance but benefits 16 bit
memory dess expensive.
When we
use
is

Thumb instruction which is

16 bit it provide improved
performance and
reduced cost.
Types:
 .
&

ROM
The

Different
tyes Memory
Flash ROM
• DRAM
• SRAM
• SDRAM⋅

Fetch
ing
Instruction size
1
ARM 32 bit
1

are 8-
wistruction from
memory

8bit memory! 16
bit memory
132bitua

cycle
s.
1 2
 cycles
7
cycl

Thumb 16-bit
2
cycles

I cycles,
cyclu
PERIPHERALS
8-
ривост
Page-
7

A peripheral device performs input

 and output functions
for the chip by
connecting to other
зы
device de

Peripher
als
Sensors that are
off.chip
range from a simple
Serial Commit device to more
complex 802.11 wireless device.
Aill ARM peripheral are
memory mapped - the programming
interface is a set of memory
Controllers
 addceived
registers.
медил
ай
are specialized periphual
that of functionality within
an
implement higher levels
of functionality embedded
syslem
.

Two important lypes of

contrallers
controllers and
uninterrupt
controllery.
are
 memo
ry

MEMORY CONTROLLERS: They

connect different lyper of
memory
to the processor
bus.
In power up a memory
a memory controller is
configured in
code to be
How to allow certour memory device to
be active. They memo allow initialization
by Slw. Eg
DRAM-C time needs to be set
 before accessing)
executed. & Some device
are set up
INTERRUPT
CONTROLLERS:
When a peripheral of device
requeries attention it raises an intwaupt to
ltre procesor
There
un

1.
ave

two types
of
interrupt types
of
interrupt
ARM processor
The standard Intempt
 controller
2. Vector interrupt
controller.
controller

161/12
/2020
Standard in lorrupt
controllere :
at sends
an

in lovipt signal to the processor core

when external device requests servicing.
The underupt handle dettement which
device requies servicing by reading a
device bitmap,
VIC:
 The VIC i
bitmap regis
interrupt controller.
Les in
the

more powerful than the

standard
intercept controller because it
prioritizes Simplifier the
determination of which device
in dvoup t
underuipts
& caused
the
to

un
 unterrupt is
higher
The Vic only avvits an indoorupt
signal the core if the priority of
Chain
а

new
the currently executing
interrupt handles.

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MENU Dr.
SUJATHA. Ş
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