Digital Circuits

Design
Dr. Omar A. M. Aly
Dr. Diaaeldin Abdelrahman
diaaeldin@aun.edu.eg
 Lecture-Set 5:
Sequential Logic
Circuits
Dr. Omar A. M. Aly
Dr. Diaaeldin Abdelrahman
diaaeldin@aun.edu.eg

M. M. Mano, “Digital Design With an Introduction to the Verilog HDL,” 5th Edition, Pearson
Education, 2013.
Outline

Combinational vs Sequential

Types of Sequential Circuits

Latches

Flip-flops

Analysis of Clocked Sequential Circuits

Digital Circuits Design Slide 3

Combinational vs Sequential
A combinational circuit:
o At any time, outputs depend only on inputs
o Changing inputs changes outputs
o No regard for previous inputs
o No memory (history)
o Time is ignored!

Digital Circuits Design Slide 4

Combinational vs Sequential
 A sequential circuit:
o A combinational circuit with feedback through memory
 The stored information at any time defines a state
o Outputs depend on inputs and previous outputs
 Previous outputs are stored as binary information into memory
o Next output state depends on inputs and present state

Digital Circuits Design Slide 5

Examples of sequential systems

Traffic light ATM

Digital Circuits Design Slide 6

Types of Sequential Circuits
There are two main types of sequential circuits, and their classification is a
function of the timing of their signals.
Clock: is defined as the starting of the change of state

1. Synchronous: State changes are synchronized by one or more clocks

2. Asynchronous: Each state change occurs independently of other changes

Digital Circuits Design Slide 7

Types of Sequential Circuits
1. Synchronous: Inputs
Combinational
Outputs
Circuit
Flip-flops
Clock

Clock a periodic external event (input)

2. Asynchronous:
Inputs Outputs
Combinational
Circuit
Memory
Elements

Digital Circuits Design Slide 8

Types of Sequential Circuits
Synchronous
oEasier to analyze
oChoose the clock so that changes are only allowed to occur before next
clock pulse

Asynchronous
oPotentially faster
oHarder to analyze and design

Will look mostly at synchronous

Digital Circuits Design Slide 9
Latches
SR-Latch S R Q0 Q Q’
Basic storage element 0 0 0 0 1 Q = Q0

Made from gates

R 0 0
Q

S Q
0 1
Initial Value

Digital Circuits Design Slide 10

Latches
SR-Latch S R Q0 Q Q’
0 0 0 0 1 Q = Q0
0 0 1 1 0 Q = Q0

R
0 1
Q

S Q
0 0

Digital Circuits Design Slide 11

Latches
SR-Latch S R Q0 Q Q’
0 0 0 0 1
Q = Q0
0 0 1 1 0
0 1 0 0 1 Q=0
R
1 0
Q

S Q
0 1

Digital Circuits Design Slide 12

Latches
SR-Latch S R Q0 Q Q’
0 0 0 0 1
Q = Q0
0 0 1 1 0
0 1 0 0 1 Q=0
R
1 1 0 1 1 0 1 Q=0
Q

S Q
0 0

Digital Circuits Design Slide 13

Latches
SR-Latch S R Q0 Q Q’
0 0 0 0 1
Q = Q0
0 0 1 1 0
0 1 0 0 1
R
0 0 0 1 1 0 1
Q=0
Q 1 0 0 1 0 Q=1

S Q
1 1

Digital Circuits Design Slide 14

Latches
SR-Latch S R Q0 Q Q’
0 0 0 0 1
Q = Q0
0 0 1 1 0
0 1 0 0 1
R
0 1 0 1 1 0 1
Q=0
Q 1 0 0 1 0 Q=1
1 0 1 1 0 Q=1

S Q
1 0

Digital Circuits Design Slide 15

Latches
SR-Latch S R Q0 Q Q’
0 0 0 0 1
Q = Q0
0 0 1 1 0
0 1 0 0 1
R
1 0 0 1 1 0 1
Q=0
Q 1 0 0 1 0
Q=1
1 0 1 1 0
1 1 0 0 0 Q = Q’

S Q
1 10

The two outputs are not complement of each other!

Digital Circuits Design Slide 16

Latches
SR-Latch S R Q0 Q Q’
0 0 0 0 1
Q = Q0
0 0 1 1 0
0 1 0 0 1
R
1 10 0 1 1 0 1
Q=0
Q 1 0 0 1 0
Q=1
1 0 1 1 0
1 1 0 0 0 Q = Q’
1 1 1 0 0 Q = Q’
S Q
1 0

The two outputs are not complement of each other!

Digital Circuits Design Slide 17

Latches
SR-Latch S R Q
R Q Q0 No change
0 0
0 1 0 Reset
1 0 1 Set
S Q 1 1 Q=Q’=0 Invalid

S S R Q
Q Invalid
0 0 Q=Q’=1
0 1 1 Set
1 0 0 Reset
R Q
1 1 Q0 No change
Digital Circuits Design Slide 18
Latches
SR-Latch with Control Input R R
Q
C

A control signal C is added to S

S Q

enable/disable the latch

o C = 1 enables data change
C S R Q
o C = 0 disables latch's operation
0 x x Q0 No change
1 0 0 Q0 No change
The right side of circuit is an 1 0 1 0 Reset
ordinary S-R latch 1 1 0 1 Set
1 1 1 Q=Q’ Invalid

Digital Circuits Design Slide 19

Latches
D-Latch with Control Input
Input D is passed to output Q when C is high
Timing Diagram
Input value D is ignored when C is low
C

D S D
Q
C Q
R Q

Output may
change

Digital Circuits Design Slide 20

Latches
D-Latch with Control Input
Timing Diagram
D S
Q C
C
D
R Q

C D Q t
0 x Q0 Output may
1 0 0 change
1 1 1

Digital Circuits Design Slide 21

Latches
Symbols of Latches

SR latch is based on NOR gates

S’R’ latch based on NAND gates

D latch can be based on either

D latch sometimes called transparent latch

Digital Circuits Design Slide 22

Latches
D-Latch
Latches are Level Triggered

Digital Circuits Design Slide 23

Flip-Flops
STORAGE ELEMENTS
The state of a latch or flip-flop is switched by a change in the control input.
This momentary change is called a trigger
The D latch with pulses in its control input is essentially a flip-flop that is
triggered every time the pulse goes to the logic-1 level.

Flip-Flops are Edge Triggered

Digital Circuits Design Slide 24

Latches vs Flip-Flops

Digital Circuits Design Slide 25

Flip-Flops
Edge-Triggered D-FF
The output changes only on C transition

Digital Circuits Design Slide 26

Flip-Flops
S-R Master-Slave Flip-Flop Y
S
 Consists of two clocked C
S
C
Q S
C
Q Q

S-R latches in series, with R R Q Y’ R Q Q

the clock on the second
latch inverted
Master Latch Slave Latch
C
•Master Latch •Master Latch is inactive
responds to inputs •Slave latch responds to
(output Y changes) the inputs Y, Y’;
•Slave latch is inactive: •Output Q changes
Q unchanged

Digital Circuits Design Slide 27

Flip-Flops
Master-Slave D Flip-Flop D D
D Latch
Q D
D Latch
Q Q
(Master) (Slave)
C C

CLK
Master Slave

CLK

D
Looks like it is negative
edge-triggered QMaster

QSlave
Digital Circuits Design Slide 28
Flip-Flops
J-K Flip-Flop

Digital Circuits Design Slide 29

Flip-Flops
Positive edge triggered J-K FF can be constructed using D-Latch and some
gates as shown

Digital Circuits Design Slide 30

Flip-Flops
Clocked J-K Flip-Flop

Digital Circuits Design Slide 31

Flip-Flops
PR and CLR Timing

Digital Circuits Design Slide 32

Flip-Flops
Application

Digital Circuits Design Slide 33

Flip-Flops
Characteristic Table

Digital Circuits Design Slide 34

Flip-Flops
Characteristic Equation

𝑸 𝒏 + 𝟏 = 𝑱𝑸′ + 𝑲′ 𝑸
Digital Circuits Design Slide 35
Flip-Flops
Characteristic Equation

𝑸 𝒕+𝟏 =𝑫

Digital Circuits Design Slide 36

Analysis of Clocked Sequential Circuits
The behavior of a clocked sequential circuit is determined from the inputs,
the outputs, and the state of its flip-flops

The outputs and the next state are both a function of the inputs and the
present state

The analysis of a sequential circuit consists of obtaining a table or a

diagram for the time sequence of inputs, outputs, and internal states

A state table and state diagram are then presented to describe the behavior
of the sequential circuit
Digital Circuits Design Slide 37
Analysis of Clocked Sequential Circuits
State Equations
A state equation (also called a transition
equation) specifies the next state as a function of
the present state and inputs
It is possible to write a set of state equations for
the circuit:
• A(t + 1) = A(t)x(t) + B(t)x(t)
B(t + 1) = A’(t)x(t) That can be written as,
• A(t + 1) = Ax + Bx
B(t + 1) = A’x
y = (A + B) . x’
Digital Circuits Design Slide 38
Analysis of Clocked Sequential Circuits
State Table
The time sequence of inputs, outputs,
and flip-flop states can be enumerated
in a state table (sometimes called a
transition table).

Digital Circuits Design Slide 39

 Thanks and Feedback

Digital Circuits Design Slide 40