1.
For a 4 bit MOD-16 ripple counter using J-K flip-flop, the propagation delay of
each flip flop is 50ns. What is the maximum clock frequency can be used?
2. What is the minimum number of flip-flops needed to build a MOD-17 up counter?
3. A MOD-16 ripple counter using J-K flip-flop has a current state 1001. What will the
state be after 31 clock pulses?
4. How many different states does a 3-bit asynchronous counter have?
5. A 5-bit asynchronous binary counter is made up of five flip-flops, each with a 12 ns
propagation delay. The total propagation delay (tp(total)) is ____________
6. An asynchronous 4-bit binary down counter changes from count 2 to count 3. How
many transitional states are required?
7. A 4-bit ripple counter consists of flip-flops, which each have a propagation delay
from clock to Q output of 15 ns. For the counter to recycle from 1111 to 0000, it takes
a total of ____________
8. A 4-bit binary up counter has an input clock frequency of 20 kHz. The frequency of
the most significant bit is ________
9. Design a counter with sequences 0, 2, 3, 1, 0 using D-flip flops.
10. A traffic signal cycles from GREEN to YELLOW, YELLOW to RED and RED to
GREEN. In each cycle, GREEN is turned on for 70 seconds, YELLOW is turned on
for 5 seconds and the RED is turned on for 75 seconds. This traffic light has to be
implemented using a finite state machine (FSM). The only input to this FSM is a
clock of 5 second period. The minimum number of flip-flops required to implement
this FSM is ?
11. A MOD-16 ripple counter using J-K flip-flop has a current state 1001. What will
the state be after 31 clock pulses?
12. A specific counter is using five S-R flip-flops. So what is the maximum number of
states possible?
13. What is the maximum delay that can occur if four flip-flops are connected as a
ripple counter and each flip-flop has propagation delays of tPHL = 22 ns and tPLH =
15 ns?
14. The logic gates shown in the given figure works as:
15. At what specific times in the pulse diagram does the final output assume the
input’s state? How does this behavior differ from the normal response of a D-type
latch?
16. If the clock frequency driving this flip-flop is 240 Hz, what is the frequency of the
flip-flop’s output signals (either Q or [Qbar])?
17. The flip-flop circuit shown here is classified as synchronous because both
flip-flops receive clock pulses at the exact same time:
Define the following parameters:
Set-up time
Hold time
Propagation delay time
Minimum clock pulse duration
Then, explain how each of these parameters is relevant in the circuit shown.
Explain how this circuit performs the “toggle” function more commonly associated
with J-K flip-flops.
18. For an implementation based on two D-type flip-flops (labelled A and B), determine
simplified Boolean expressions for the next-state and output combinational logic, assuming
the state assignment S0 = 00, S1 = 01 and S2 = 10 is used, where a state is labelled QAQB in
terms of the flip-flop outputs.
19. What will be the logic function implemented by the given circuit.
20. A fictitious flip-flop with two inputs A and B functions like this. For AB= 00 and 11 the
output becomes 0 and 1 respectively. For AB= 01, flip-flop retains previous output while
output complements for AB= 10. Draw the truth table and excitation table of this flip-flop.
21. Construct a JK flip-flop using a D Flip-flop, a 2-to-1 line multiplexer and an inverter.
22. A AB flip-flop has four operations: clear to 0, no change, complement, and set to 1,
when inputs A and B are 00, 01, 10, and 11, respectively. a) Tabulate the characteristic table.
b) Derive the characteristic equation. c) Tabulate the excitation table. d) Show how the AB
flip-flop can be converted to a D flip-flop.
23. Design a sequential circuit with two D Flip-Flops, A and B, and one input x. When x = 0,
then the state of the circuit remains the same. When x =1, the circuit goes through the state
transitions from 00 to 01 to 11 to 10 back to 00, and repeats.
24. Determine the output pulses for this counter circuit, known as a Johnson counter,
assuming that all Q outputs begin in the low state:
25. Complete a timing diagram for this circuit, and determine its direction of count, and
also whether it is a synchronous counter or an asynchronous counter:
