Tishk International University

Mechatronics Engineering Department

Analog Devices and Circuits ME227
Lecture 7: 23-04-2019

Analog Devices and Circuits:

Field Effect Transistor

Dr. Rand Basil Alhashimie

rand.basil@ishik.edu.iq
 Cutoff Voltage

● The value of VGS that makes ID approximately zero is the cutoff voltage,
VGS(off), as shown in Figure 8(d). The JFET must be operated between VGS 0 V
and VGS(off). For this range of gate-to-source voltages, ID will vary from a
maximum of IDSS to a minimum of almost zero.
● As you have seen, for an n-channel JFET, the more negative VGS is, the smaller
ID becomes in the active region. When VGS has a sufficiently large negative
value, ID is reduced to zero. This cutoff effect is caused by the widening of the
depletion region to a point where it completely closes the channel, as shown in
Figure 9
Figure 8
Comparison of Pinch-Off Voltage and Cutoff Voltage
● As you have seen, there is a difference between pinch-off and
cutoff voltages. There is also a connection. The pinch-off
voltage VP is the value of VDS at which the drain current
becomes constant and equal to IDSS and is always measured
at VGS = 0 V.

● However, pinch-off occurs for VDS values less than VP when

VGS is nonzero. So, although VP is a constant, the minimum
value of VDS at which ID becomes constant varies with VGS.
VGS(off) and VP are always equal in magnitude but opposite
in sign. A datasheet usually will give either VGS(off) or VP, but
not both. However, when you know one, you have the other.
For example, if VGS(off) = -5 V, then VP = +5 V, as shown in
Figure 8–7(b).
Example 1: For the JFET in Figure below, VGS(off) = -4 V and IDSS = 12
mA. Determine the minimum value of VDD required to put the device in
the constant-current region of operation when VGS = 0 V.
 JFET Universal Transfer Characteristic

● You have learned that a range of VGS

values from zero to VGS(off) controls the
amount of drain current. For an n-channel
JFET, VGS(off) is negative, and for a p-
channel JFET, VGS(off) is positive.
● Because VGS does control ID, the
relationship between these two quantities
is very important. Figure 10 is a general
transfer characteristic curve that illustrates
graphically the relationship between VGS
and ID. This curve is also known as a
transconductance curve.
JFET Universal Transfer Characteristic
JFET Universal Transfer Characteristic

● The transfer characteristic curve can also be developed from the drain
characteristic curves by plotting values of ID for the values of VGS taken from
the family of drain curves at pinch-off, as illustrated in Figure 11 for a specific
set of curves. Each point on the transfer characteristic curve corresponds to
specific values of VGS and ID on the drain curves.

● For example, when Also, for this specific JFET, VGS(off) = -5 V and IDSS =
12 mA. VGS = -2 V, ID = 4.32 mA.
JFET Universal Transfer Characteristic
Example: The datasheet for a 2N5459 JFET indicates that typically IDSS
= 9 mA and VGS(off) = -8V (maximum). Using these values, determine
the drain current for VGS = 0V, -1V and -4V.
JFET Forward Resistance
The forward resistance (RDC), is the change in gate-to-source voltage (ΔVGS)
with the change in drain current (ΔID), with the drain-to-source voltage constant. It
is expressed as a ratio:

The forward transconductance transfer conductance (gm).

The Unit of gm is siemens (S)

JFET Forward Transconductance
A datasheet normally gives the value of gm measured at VGS = 0 V (gm0).

When a value of gm0 is not available, you can calculate it using values of IDSS
and VGS(off ). The vertical lines indicate an absolute value (no sign).
Example: The following information in included on the data sheet for a 2N5457
JFET: typically IDSS = 3mA, VGS(off) = -6V maximum, and gfs(max) = 5000µs.
Using these values, determine the forward transconductance for VGS = -4V and
find ID for this point.
Datasheet
Input Resistance and Capacitance
● JFET operates with its gate-source junction reverse-biased, which makes the
input resistance at the gate very high.
● JFET datasheets often specify the input resistance by giving a value for the
gate reverse current, IGSS, at a certain gate-to-source voltage.
● The input resistance can then be determined using the following equation,
where the vertical lines indicate an absolute value (no sign):
Example: A certain JFET has an IGSS of -2nA for VGS = -20V. Determine the
input resistance
 Self Biasing
● Self-bias is the most common type of JFET bias.
Recall that a JFET must be operated such that the
gate-source junction is always reverse-biased.
● This condition requires a negative VGS for an n-
channel JFET and a positive VGS for a p-channel
JFET.
● This can be achieved using the self-bias arrangements
shown in Figure 1. The gate resistor, RG, does not
affect the bias because it has essentially no voltage
drop across it; and therefore the gate remains at 0 V.
RG is necessary only to force the gate to be at 0 V
and to isolate an ac signal from ground in amplifier
applications.
Self Biasing
● For the n-channel JFET in Figure 1(a), IS produces a voltage drop across RS
and makes the source positive with respect to ground. Since IS = ID and VG
= 0, then VS = ID*RS. The gate-to-source voltage is:

VGS = VG - VS = 0 -ID*RS = -ID*RS

VGS = -ID * RS

● For the p-channel JFET shown in Figure 1(b), the current through RS
produces a negative voltage at the source, making the gate positive with
respect to the source. Therefore, since IS = ID,

VGS = ID * RS
Self Biasing
● The drain voltage with respect to ground is determined as follows:

VD = VDD - ID*RD

● Since VS = ID*RS, the drain-to-source voltage is

VDS = VD - VS = VDD - ID(RD + RS)

Example: Find VDS and VGS in Figure below. For the particular JFET in this
circuit, the parameter values such as gm, VGS(off), and IDSS are such that a
drain current (ID) of approximately 5 mA is produced. Another JFET, even of the
same type, may not produce the same results when connected in this circuit due
to the variations in parameter values.
Setting the Q-point of a self-biased JFET
● The basic approach to establishing a JFET bias point is to determine ID for a
desired value of VGS or vice versa. Then calculate the required value of RS
using the following relationship. The vertical lines indicate an absolute value.

● For a desired value of VGS, ID can be determined in either of two ways: from
the transfer characteristic curve for the particular JFET or, more practically,
using IDSS and VGS(off) from the JFET datasheet. The next two examples
illustrate these procedures.
Example: Determine the value of RS required to self-bias an n-channel JFET that
has the transfer characteristic curve shown in Figure below at VGS = -5 V.
Example: Determine the value of RS required to self-bias a p-channel JFET with
datasheet values of IDSS = 25 mA and VGS(off) = 15 V. VGS is to be 5 V.
Midpoint Bias
It is usually desirable to bias a JFET near the midpoint of its transfer characteristic
curve where ID = IDSS/2. Under signal conditions, midpoint bias allows the
maximum amount of drain current swing between IDSS and 0. For Equation
below, it can be shown that ID is approximately one-half of IDSS when VGS =
VGS(off) / 3.4

To set the drain voltage at midpoint (VD = VDD/2), select a value of RD to

produce the desired voltage drop. Choose RG arbitrarily large to prevent loading
on the driving stage in a cascaded amplifier arrangement. Example 8–9 illustrates
these concepts.
Example: Looking at the datasheet, select resistor values for RD and RS in Figure
below to set up an approximate midpoint bias. Use minimum datasheet values
when given; otherwise, VD should be approximately 6 V (one-half of VDD).
Graphical Analysis of Self-Biased JFET
You can use the transfer
characteristic curve of a JFET
and certain parameters to
determine the Q-point (ID and
VGS) of a self-biased circuit. A
circuit is shown in Figure (a)
below, and a transfer
characteristic curve is shown in
Figure (b). If a curve is not
available from a datasheet, you
can plot it from the previous
Equation using datasheet values
for IDSS and VGS(off).
Graphical Analysis of Self-Biased JFET
To determine the Q-point of the circuit in Figure (a), a self-bias dc load line is
established on the graph in part (b) as follows. First, calculate VGS when ID is
zero.

This establishes a point at the origin on the graph (ID 0, VGS 0). Next, calculate
VGS when ID = IDSS. From the curve in Figure (b), IDSS =10 mA.

This establishes a second point on the graph (ID = 10mA, VGS = -4.7V). Now,
with two points, the load line can be drawn on the transfer characteristic curve
as shown in Figure below. The point where the load line intersects the transfer
characteristic curve is the Q-point of the circuit as shown, where ID = 5.07 mA
and VGS = -2.3 V.
Graphical Analysis of Self-Biased JFET
Example: Determine the Q-point for the JFET circuit in
Figure (a). The transfer characteristic curve is given in Figure (b).
Voltage Divider Bias
An n-channel JFET with voltage-divider bias is shown in Figure below. The
voltage at the source of the JFET must be more positive than the voltage at the
gate in order to keep the gate-source junction reverse-biased.
Example: Determine ID and VGS for the JFET with voltage-divider bias in Figure
below, given that for this particular JFET the parameter values are such that VD = 7 V.