1.

P-N junction diode: I-V characteristic

Figure (1) represents schematically the n+/p junction diode structure that can will be
approximated by a 1D structure shown in figure (2).

Al
A
n
+

Figure (2)
Figure (1)

Junction at equilibrium:

Figure (3) shows the depletion region that builds up around the metallurgical junction (x=0)
having a width of W (Xn+Xp). The electric field across the structure is also represented and
assumed to be equal to zero in the neutral regions (X > Xn and X< -Xp). Note the maximum
value of E at X=0 and its dependence on the doping.

The built-in voltage corresponding to the electric field is defined by :

Vbi = Vn – Vp : potentials of the neutral regions NA ND

p n
Electrostatic calculation assuming depletion
region completely depleted of carriers gives: −xp 0 xn

Vbi = (q / 2ε) ND xn W W

NA
Since xn = W
NA + ND
We end up with : max = − q NA xp/ε
= − q ND xn/ε
1/ 2
2ε NA + ND Figure (3)
W = Vbi
q NA ND
Junction under polarisation:

Similar equation for W except replacing

Vbi by Vbi – VA (figure (4).

1/ 2
2ε NA + ND
W = (Vbi − VA )
q NA ND
Figure (4)

1
Figure (5) shows the effect of various polarisations on the flow of electrons and holes drift
and diffusion currents. The arrow lengths represent the amplitude of the corresponding
current.

VA = 0 VA > 0 VA < 0

p n
p n

Hole diffusion current Hole diffusion current Hole diffusion current

Hole drift current Hole drift current Hole drift current

Electron diffusion current Electron diffusion current Electron diffusion current

Electron drift current Electron drift current Electron drift current

Figure (4)
The behaviour of these current components under each polarisation condition can be
qualitatively explained by the polarisation dependence of the energy band diagram as depicted
by figure (5).

Figure (5)

2
When the diode forward-bias-voltage is increased, the barrier for electron and hole diffusion
current decreases linearly. See the band diagram.
Since the carrier concentration decreases exponentially with energy in both bands, diffusion
current increases exponentially as the barrier is reduced.
As the reverse-bias-voltage is increased, the diffusion current decreases rapidly to zero, since
the fall-off in current is exponential.

When the reverse-bias-voltage is increased, the net electric field increases, but drift current
does not change. In this case, drift current is limited NOT by HOW FAST carriers are swept
across the depletion layer, but rather HOW OFTEN.
The number of carriers drifting across the depletion layer is small because the number of
minority carriers that diffuse towards the edge of the depletion layer is small.
To a first approximation, the drift current does not change with the applied voltage.

Detailed carrier transport calculations across the diode structure show that the I-V
characteristic can be modeled by the Shockley equation:
qV A
qDp qDn
J = pn0 + n (e kT
− 1)
Lp Ln p0

Where Dp and Dn represent the hole and electron diffusion coefficient respectively and Lp
and Ln the corresponding diffusion lengths. The pn0 and np0 represent the minority carrier
concentration on both sides of the junction. This equation can be further written:

qVA
J = J 0 (e kT − 1)

Where J0 is the (constant) reverse current density.

Simple analysis of this equation gives the following results:

- Large forward bias (VA >> kT/q) give:

qVA
J = J 0 e kT
- Large reverse bias (VA << – kT/q):

J = − J0
In this “ideal” case the forward bias gives an exponential yield whereas the reverse bias the
current is constant as shown by figure (5d).

Real p-n junction diode :

There are several features of a real p-n junction diode that show important deviation from the
“ideal” structure. These deviations can be summarised as follows:
- Reverse-bias breakdown
– Avalanching
– Zener process
- The R-G current (Recombination-Generation current)

3
- If VA → Vbi, then high-current phenomena result
– Series current
– High-level injection (injected minority carrier concentration majority carrier concentration)

These deviations for a non-ideal diode are summarised by on figure (6)

Series resistance effect

High level injection

Ideal behaviour
G-R part

G-R part
Breakdown

Figure (6)

Practical work:

Connect the n+/p diode as shown in figure (1). Respect the polarity in order to be in
accordance with the diode polarisation standard (VA = Vp-Vn). The front side contact should
be attached to the A6 contact pad (see the layout).

I- Forward biased diode:

Apply a voltage ramp between -2 V and +2V with a step of 10mV. Plot the corresponding I-
V characteristic in the linear mode under “Short” integration time and then under “medium”
integration time. Make sure that you get the expected asymmetric I-V characteristic.
I-1 : Make an estimate of the threshold voltage.
I-2 : Re-plot the previous characteristic in the Log I vs. V coordinates. Comment the observed
result (Diode ideal behaviour part, series resistance, reverse current,…).

4
I-3 : Extract the reverse current density in A/cm-2(diode surface = 200x200 µm2). How does
this value compare to the theoretical one (10-6 A/cm-2)?.
I-4 : Apply a voltage ramp between 200 mV and 700mV with a step of -1mV. Plot the
corresponding I-V characteristic in the Log I vs. V coordinates. Measure the reverse value of
the slope (in mV/current decade). Compare it to the theoretical value (~ 60 mV /decade).
Comment any deviations.

II- Reverse biased diode:

II- 1 : Apply a voltage ramp between 0 V and -25 V with a voltage step of – 50mV.

II-2 : Plot the corresponding I-V characteristic in the linear coordiantes. Measure the
breakdown voltage.
II-3 : Re-plot this previous characteristic in the semi-log coordinates. Comment the current
behaviour before the avalanche mechanism onset.
II-4 : Suggest an explanation of the avalanche mechanism using the energy band diagram
under high reverse voltage.
II-5 : make a rough estimate of the breakdown electric field assuming a depletion layer width
of 1 µm. Compare this value to the theoretical one for silicon.

III- Reverse biased diode under illumination :

Apply a voltage ramp between -2V and +2V (step = 10mV) first under the dark conditions.
Plot the corresponding characteristic in the semilog coordiantes. Shine light on the silicon
wafer using the microscope light beam and plot the I-V curve by pressing the “append” button
in order to overlay the two curves. Vary the light intensity (by turning the light intensity
button) and plot two more I-V curves. Comment the observed result.

2. MOSFET Analysis :

VGS

A
G

Si poly

S n+ D n+
VDS
Si p
A

5
 The previous electrical setup is used to study the electrical characteristics of the N-
MOSFET.
Measurement scheme: short bulk to source to make it a three terminal device, vary gate
voltage, drain voltage and see effect on drain current.

NMOS Qualitative I-V Behavior :

When no bias voltage present at G, two back-to-back diodes exist between drain
and source
§ pn between n+ drain and p-type substrate
§ pn between p-type substrate and n+ source
§ Back-to-back diodes prevent current flow from drain to source when DC
voltage is applied between S and D. There is a big resistive barrier between S and D
with a path resistance of the order of 1012 Ω. The tranistor is in the non-conducting
mode.

When source and drain to GND and positive voltage to gate Gate voltage appears
between G and S (VGS).

§ VT>> VG > 0 where VT is the threshold voltage : Positive VG repels free holes from
substrate under gate (channel region) down to substrate leaving carrier-depletion
region and negative charges (fixed acceptor ions) are left in depletion region as
shown in the following sketch :

VG > VT :

6
 § Electrons form n+ source and drain attracted to channel region connecting S
and D
§ when enough e- accumulated a conducting n-channel established ready to
conduct current when voltage applied between source and drain

Threshold voltage VT: value of VGS at which sufficient number of mobile e

accumulate in channel region to form conducting channel.
Length and width – two important channel parameters
L ~ 1-10um,
W ~ 2-500um

There are two different conducting regime (VG > VT) : ID= f(VD) at a given VG

a) The linear regime (triode region) : VD < VG-VT :

The channel behaves as a resistance between the Source and the Drain. The channel
current ID is given by the following expression:

µ ε
W ox
I DS
≈ (V GS
−V T ) V DS
L n
d ox

µ n : electron mobility
ε ox : gate oxide permittivity
d ox : gate oxide thickness
Small VDS voltage (0.1~0.2 V) causes current ID to flow through induced channel :

7
b) The saturation regime :

VDS increases while VGS is kept constant and greater than VT then :
§ VDS not unified across channel – dropping across length of conductivity channel
§ Voltage increase from 0 at S to VDS at D
§ Voltage between G and channel decreases from VGS at S to VGS – VDS at D
§ Conductivity channel depth depends on VGS voltage – channel depth is not uniform due to
variations in VGS across channel.

§ With VDS increasing channel becomes more taped and its resistance increases
§ When VDS increases such that VGS –VDS = VT then channel depth at D decreases to
almost zero – channel is pinched off
§ Further increase in VDS does not influence channel shape but moves the pinch-off towards
the Source.
§ Current constant (saturated) at level reached when VGS –VDS = VT

8
The saturation current is given by :

µ ε µ ε
=
W V² ox DS sat
=
W ox (VGS − VT ) 2
I DS sat
L n
d 2 ox
L n
d ox
2

IDS (VDS) Characteristic of a N-MOSFET with VT = 1 V

Practical Work :

1) IDS=f(VDS) at Constant VGS

Take the following values :

9
 VGS : To be varied from 0 to 5 V by a step of 1Volt.
VDS : To be varied from 0 to 5 V.
Give the IDS=(VDS) characteristic that gives an idea about the the threshold voltage.

2) IDS=f(VGS) at Constant VDS

A small and constant value of VDS =100mV is applied in order to be constantly in the linear
regime regardless the the value of VGS. VGS is scanned from 0 to 5 V.
a) Give the IDS=f(VGS) characteristic. One should expect to have the following behavior:

: IDS
--- :g

gmax
VDS =100 mV

VGS
VT

b) Threshold Voltage VT : The IDS=f(VGS) is similar to a diode I-V characteristic showing a

threshold voltage as given by the linear regime equation :

µ ε
W ox
I DS
≈ (V GS
−V T ) V DS
L n
d ox

The threshold Voltage can be deduced by the following procedure :

- One can compute the Channel Trans-conductance : g

µ ε V
∂I DS W ox
g= = DS
∂VGS VDS
L dn
ox

- The curve g(VGS) can be drawn automatically on the same graphic as IDS=f(VGS) by defining
g in the “User Function Definition” page. Give an explanation to the decrease of g with
increasing VGS.

- The maximum value of the transconductance : gm is determined and a tangent line is drawn
on the IDS=f(VGS) on that point corresponding to gm as shown in the previous graphic.

10
- The intersection between the tangent line and the X-axis yields the value of VT.
Measure VT for the TMOS set with different channel lengths L and fill in the following table :

Channel Length(µm) 12 10 8 6 4 2

VT

gm

µn
IDS at VG = 2V

µn (Leff)

c) Electron Mobility:
- From the experimental result and the maximum value of the transconductance: gm,
compute the mobility of the electron through the channel for the different transistors (L = 12,
10, 8, 6, 4, 2 µm) and fill in the values in the previous table:

Ld ox
µ= g in cm2/V.s
n
Wε V ox DS
m

where: W = 100µm, dox= 50nm = 5x10-6 cm,

VDS = 0.1 V and εox = 3.9x εo (εo=8.8x10-14 F/cm)

- Give an explanation to the variation of the mobility as a function of the channel length.

d) The effective Channel length (Leff) :

In fact, the channel length : L used to compute the electron mobility corresponds to the value
given on the polysilicon mask level. It might be
Different from the effective channel length because of two reasons :
1) The polysilicon gate over-etch : since the R.I.E. is lightly isotropic etching of the
polysilicon layer under the photoresist takes place.

2) The doping impurities lateral diffusion: this takes place during the implantation and
the subsequent activation annealing.

11
 L
Gate Pattern (Mask)

Polysilicon Gate

Source Leff Drain

Si -Substrate

Let this difference between L and Leff be ∆L then one can write :

L = Leff + ∆L
- For the TMOS set and by using the values : IDS at VG = 2 V filled in the previous table, draw
the following curve :

1
= f ( L) = d ox
L = constant * L
I DS W µε Vn ox DS
(V GS − V T
)

Where L = Leff + ∆L and one should expect the following kind of curve from which ∆L can be
deduced :

L
L

- Re-compute the electron mobility values by using the corrected

channel length values (Leff instead of L) and fill in the table. Show
that the mobility is now independent from the channel length.

12
MOS structure:

A MOS (Metal/Oxide/semiconductor) structure is illustrated in Fig 1: dox is the thickness of

the insulating Oxide and VG is the applied gate (metal) voltage, the semiconductor is
considered as the electrical reference. The MOS capacitor is a 2 terminals device, and is the
simplest and most useful structure in the study of semiconductor/oxide interface and of the
oxide physical and electrical properties, both fundamental in the operation of the MOS Field
Effect Transistor. In this section, a P-type semiconductor will be taken as an example; similar
reasoning could be done for the N-type semiconductor.

VG

Metal (Gate)
Oxide d ox

Semiconductor

Figure 1 schematic cross section of a MOS capacitor.

Ideal MOS structure theory:

For simplicity, let us start with an ideal MOS capacitor which is defined as follow:
• The work function difference φms between the gate and the semiconductor is zero:
E
φms = φm − χ + g + φF = 0
2⋅q
• There are no electrical charges in the insulator bulk nor at the its interface with the
semiconductor.
• There is no possible carrier transport across the oxide i.e. the oxide is considered as a
perfect insulating layer.
Vacuum level

q.χ

q.φm
Ec
Eg/2
Ei
q.φ
EF
Ev

Metal Oxide Semiconductor

Figure 2 energy band diagram of the ideal MOS capacitor at VG = 0

13
 As schematically shown on the figure 3, when an ideal MOS capacitor is biased (VG ≠
0), basically three polarisation regime may appear at the semiconductor surface. However,
note that regardless of VG, the SC Fermi level (EF) remains constant throughout the
semiconductor since no current can flow through the structure, hence a thermodynamic
equilibrium regime.
When VG < 0, the negative potential attracts positive charge in the semiconductor
(figure 3-a). this results in an enhanced concentration of the majority carrier (hole in this
case) at the semiconductor surface. The semiconductor is said to be in the accumulation
regime.
When a small positive voltage (VG > 0) is applied, negative charges are drained
towards the semiconductor surface. This, in the early stages, is due to holes being pushed
away from the surface, leaving behind a depletion region consisting of uncompensated
acceptor ions.
When a larger positive voltage is applied, the surface depletion region is widened.
Correspondingly, the total electrostatic potential variation, as represented by the energy band
bending, increases so that intrinsic level (ac the silicon mid gap), Ei at the surface crosses over
EF (intrinsic condition). Beyond this point, the concentration “n” of electrons (minority
carriers) becomes larger than the concentration “p” of holes at the surface contrary to the bulk
situation. The semiconductor surface is said to be under weak inversion regime.

Ec

EFM

EF
- -
- Ev

1 with a P-type semiconductor at VG ≠ 0 for (a) accumulation, (b) depletion and (c)
Figure 3: Energy band diagrams of a MOS capacitor
inversion conditions.

C-V Characteristics of the MOS Capacitor

The total capacitance of the MOS structure with no interface traps, oxide charge, or
work function difference (ideal MOS) is the series combination of the silicon differential
capacitance per unit area, CS (CI : Interface layer capacitance in parallel with CD : depletion
layer capacitance) , and the oxide capacitance Ci (figure 4). The total capacitance is thus given
by :

1 1 1
= +
C Cs Ci

Figure 5 gives the description of the ideal MOS Capacitance-Voltage (C-V) characteristic.

14
 cI
a) Low frequency
Ec

EF
EFM - Ev
-
-
vg CD Cmin b)
Ci

Figure 4 Equivalent circuit of MOS capacitor Figure 5 MOS capacitor Capacitance-Voltage under a) low-frequency
and b) high frequency

The behaviour of this characteristic can be summarized as follows :

a) under the low frequency condition, we begin at the left-hand side (VG < 0), a large
accumulation of the holes (majority carriers) is obtained yielding a large differential
∂Qs
capacitance at the semiconductor surface due to the accumulation layer ( Cs = ). Cs is
∂ψ s
ε
thus much larger than Ci. As a result, C is approximately equal to Ci : C ≈ Ci = i
d ox
As VG is increased to positive values, a depletion layer builds up, equivalent to an
additional dielectric of thickness “w”, in series with the oxide layer. The depletion layer
thickness (and hence the associated capacitance) is a function of the applied voltage. As the
voltage increases the depletion layer thickness widens. Consequently, C decreases
substantially according to the following relationship :
1
C=
d ox w
+
ε i ε si

Upon increasing voltage, VG reaches the so called threshold voltage “VT” at which
strong inversion occurs where ns (elecron surface concentration) > po (hole bulk
concentration). In this regime, the depletion layer width reaches a maximum due to
electrostatic screening by the mobile carriers (electrons) of the depleted region. Consequently,
C goes through a minimum value (Cmin) and then increases (due to the inversion layer
capacitance that increases drastically over a small increase of the band bending as shown in
figure 3-c) to end up at the maximum value Ci. The maximum depletion layer width is given
by :

2ε s ⋅ 2φF N
wmax = where, φF = kT ln A
qN A ni

Effect of the frequency:

The increase in capacitance during the inversion regime can occur only if the
generation/recombination of electrons can follow the applied ac signal. {Capacitance meters
generally employ a small ac signal superimposed upon the dc gate bias (VG) to measure the

15
MOS capacitance}. In particular at high frequency, minority carrier lag behind the small-
signal AC change with the minority response time τI. Experimentally, the typical τI value at
room temperature can be as large as 0.01-1 s depending on the so called minority carrier life
time of the order of 1-100µs. Thus, at high frequency (figure 5-b), the capacitance does not
increase but saturates at a:
−1
1 1 εs
Cmin = + Where, C SCm =
Ci C SCm wmax

Real MOS capacitor:

For an ideal MOS capacitor, no difference in the work functions between the metal
and the semiconductor is assumed. For real MOS system φms is different from zero and
depends on the substrate doping NB, gate electrode, and temperature. As a consequence, under
zero bias conditions, a band bending of the semiconductor energy levels is observed and a
voltage should be applied to the structure in order to flat band regime. This voltage, which
compensates the initial band bending, is called flat band voltage VFB and it is of large
importance since it is equal to φms.

The energy-band diagram of the Si/SiO2 system has mainly been obtained from
photoemission measurement; it is summarized on figure 6. Using this data, φms can be
determined from:
E E − Ev
φms =V FB= φm − χ + g + φ F − i
q q

Vacuum level
0.9 eV

q.χ

q.φm
4.1 eV Ec
4.35 eV
Eg/2
Ei
φms q.φ
EF
Ev

Aluminium Insulator Semiconductor

Figure 6 energy band diagram Al/SiO2/Si capacitor

Practical work:

Measurement scheme:
• Connect the bulk to the ground and vary the gate voltage figure 1.
• Make a C-V characteristic at 1000 Khz.

16
 1) define the three different regime (accumulation, inversion and depletion)
2) Extract the oxide thickness. Compare this value to the target one
3) Assuming the equation:
1 1 2(V FB − VG )
2
= 2 +
C Ci ε SC qN sup S 2

εSC = 11.9x εo (εo=8.8x10-14 F/cm)

Determine the substrate doping level N as well as the flat band voltage VFB
4) Assuming the data of figure 6 but with a N+-polysilicon (qφm=4.05 eV) gate, that the
electron affinity of silicon is 4.05 ev and that Nv = 1.1 10^19 cm-3, show that the
theoretical VFB i.e. φms is - 0.94 eV.
5) Compare both values and comment.
6) Make other C-V measurements for different frequencies: 100 Khz, 10 Khz compare
these data to the one measured before. Explain any difference in the behaviour?
7) From the Cmin extract the depletion-layer maximum width.

17
A band banding and energy level of comparison between classical and QM Comparison between an ideal and real C-V
inversion-layer electrons, E0 is the calculations of electron profile. curves of thin oxide MOSFETs.
ground state.

A quantum mechanical treatment is then required to extract the correct value of the insulator
thickness.

18