B.E / B.Tech.
PRACTICAL END SEMESTER EXAMINATIONS, NOVEMBER/DECEMBER 2022
Third Semester
CS3351 – DIGITAL PRINCIPLES AND COMPUTER ORGANIZATION
(Regulations 2021)
Time: 3 Hours Answer any one Question Max. Marks 100
Aim/Principle/Apparatus Tabulation/Circuit/ Calculation Viva-Voce Record Total
required/Procedure Program/Drawing & Results
20 30 30 10 10 100
1. (i) Verify the following Boolean algebra using logic gates (a)X+Y=Y+X (b)X+XY=X
(ii) Implement a 2-to-4 line decoder using basic gates.
2. Design and implement a combinational circuit using basic gates for arbitrary functions like 3-
bit Adder and subtractor.
3. Design and Implement a combinational circuit for a 4-bit binary adder/subtractor using MSI
Devices.
4. (i) Design and implement a combinational circuit for data selector using basic gates.
(ii) Design and implement a combinational circuit for 1 x 4 demux using basic gates.
5. Design and construct an asynchronous 4-bit BCD down counter using JK flip-flop ICs.
6. Design and construct a circuit with external clock signal is connected to the clock input of
every Individual 3 flip-flops. So that all 3 flip-flops are clocked together simultaneously to
count their state Upward and downward and verify their truth table.
7. (i)Design a circuit with a minimum number of gates to convert gray code to binary code and
verify its output
(ii)Design and construct a 4-bit Synchronous up counter using JK flip flops.
8. Design a circuit with a minimum number of gates to convert BCD code to Excess 3 code
and Verify its output.
9. Design and construct 3 bit synchronous up counter using D flip-flops
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10. Verify the following Boolean theorem using AOI gates.
(i) Commutative law (ii) Associative law (iii) Distributive law (iv) Absorption law
(v) Idempotent law (vi) De Morgan’s Theorem
11. Design and construct a combinational circuit for an arbitrary function whose input is a four‐
bit number and whose output is the 2’s complement of the input number using basic logic
Gates.
12. Construct a 4‐bit BCD synchronous counter using any one of FF and also draw a truth table
13. Implement a 4-bit universal shift register using multiplexer and D flip-flops.
14. Implement a full subtractor using a multiplexer.
15. Design a BCD adder circuit using IC 7483.
16. Simulate and Implement Single Cycle CPU using a subset of MIPS ISA.
17. Design the logic circuit and verify the truth table of the given Boolean expression,
F (A, B, C, D) = Σ (0, 1, 2, 5, 8, 9, 10)
18. Implement the following Boolean expression with exclusive-OR and AND gates:
F = AB’CD’ + A’BC D’ + AB’C’D + A’BC’D
19. Design a circuit with a minimum number of gates to convert Excess 3 to BCD code and
Verify its output.
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