ERROR PROBILITY OF MATCHED FILTER AS OPTIMUM FILTER THEORY- A data transmission system using binary encoding transmits sequence of 1, 0. These bits may be represented in number of ways. In PSK system we transmit in phase sine wave for logic 1 & 180 deg. Out of phase wave for logic 0. When this data is received it is corrupted by noise & there is finite probability that receiver will make an error in determining logic 1& 0. To reduce the error prob. we use the concept of co-rrelator or matched Filter as optimum filter. In matched filter we integrate VP data for one bit period. At the end of integration if O/P is more than certain level we come to know that bit is logic 1 or otherwise logic 0.'It is instructive to note that integrator filters signal & noise such that signal voltage varies linearly with time & noise increases more slowly, as root of T ..In PSK system we use co-rrelator & then filter. Signal to noise ratio of this type of filter is oveveT/ErA (That is signal to noise ratio ihereases with increases in bit " dwatioh/on T] & it deperids on v*v*T. Therefore the bit represented by narrow, High amplitude signal & one by wide & low amplitude signal are equatly effective . ‘In our case we are giving 8 bit data to parallel to serial converter. Bit NZa Bit duration of this data can be-varied by varying, badic clock Op, Signal Coming out of parallel to serial converter is to fed to PBK generator, ‘Amplitude of O/p of PSK gen. can be varied by using, nearby pot. Now we have not used any filter after PSK gon. Ho noise generated by multiplication process is there with the desired PSK signal, Now this PSK signal is fed to receiver: As discussed earlier filter increases signal to noise ratio. O/p of filter is fed to serial to parallel converter O/p of receiver can be observed on LEDs provided on Panel. PROCEDURE — 1) Switch on power supply. 2) Observe clock O/p on CRO & connect it to Up ‘of control block. 3) Set bit pattern as 00100101. using dip s/y. “1” on dip s/w. is LSB. «yy When s/w. is to on position O/p is 4) Observe O/p of p/s block on CRO Measure bit period By varying, Pot nearby clock make bit period max. 5) Connect O/p of p/s block to I/p of PSK gen. observe O/p of PSK Gen.6) nD 8) 9) 10) 11) 12) 13) 14) 15) Keep pot nearby PSK gen. to such position that O/p of PSK gen will be 500 mV p-P in ampl. observe the O/P of Noise Gen. O/P & set min. amplitude (i.e. OV). Connect O/P of Noise gen. to I/P2 of adder block & PSK gen. O/P to y/P1 of adder block. Connect O/P of adder block to I/P of matched filter. Observe O/P of filter. Keep s/w. above receiver latch to LED Observe O/P on LED’s. The same data should be at O/P. Now go on varying clock freq. slowly & increase the level , every time measure bit period. Observe at what bit period 1* error comes. Also observe that if you increase ampl. Of PSK gen. error will go away. By keeping pot. ofampl. Of PSK gen. to lowest position & by varying clock period measure no. of errors versus bit period. To observe stable readings make s/w. above receiver latch to GND. Position. For particular bit period take,no. of readings by moving this s/w. position from LEto GND. Plot graph of bit period v/s error prob. What is your conclusion? In 8 bits if one bit is in error than error prob. Is* increase no. of bits more accurate results we get. percent. Ifwe +