LTC1662

Ultralow Power, Dual

10-Bit DAC in MSOP
Features Description
n Ultralow Power: 1.5µA (Typ) ICC per DAC Plus The LTC®1662 is an ultralow power, fully buffered voltage
0.05µA Sleep Mode for Extended Battery Life output, dual 10-bit digital-to-analog converter (DAC). Each
n Tiny: Two 10-Bit DACs in an 8-Lead MSOP— DAC channel draws just 1.7µA (typ) total supply-plus-
Half the Size of an SO-8 reference operating current, yet is capable of supplying
n Wide 2.7V to 5.5V Supply Range DC output currents in excess of 1mA and reliably driving
n Double Buffered for Simultaneous DAC Updates capacitive loads of up to 1000pF. A programmable sleep
n Rail-to-Rail Voltage Outputs Drive 1000pF mode further reduces total operating current to 0.05µA.
n Reference Range Includes Supply for Ratiometric
Linear Technology’s proprietary, inherently monotonic
0V to VCC Output
architecture provides excellent linearity and an exception-
n Reference Input Impedance Is Code-Independent
ally small external form factor. The double-buffered input
(7.1MΩ Typ)—Eliminates External Buffers
logic provides simultaneous update capability and can be
n 3-Wire Serial Interface with Schmitt Trigger Inputs
used to write to the DACs without interrupting sleep mode.
n Differential Nonlinearity: ±0.75LSB Max
With its tiny operating current and exceptionally small
size, the LTC1662 is ideal for use in the most power-
Applications constrained products. For most designs, there is no
n Mobile Communications perceptible impact on the power budget; the LTC1662
n Portable Battery-Powered Instruments draws many times less current than even a trimpot,
n Remote or Inaccessible Adjustments while providing buffered, low impedance (0.5Ω typical,
n Digitally Controlled Amplifiers and Attenuators VCC = 5V) rail-to-rail outputs.
n Factory or Field Calibration The LTC1662 is pin and software compatible with the
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear LTC1661 dual, 60µA 10-bit DAC. It is available in 8‑pin
Technology Corporation. All other trademarks are the property of their respective owners.
MSOP and PDIP packages and is specified over the in-
dustrial temperature range.

Block Diagram
VOUT A GND VCC VOUT B
8 7 6 5 Total Supply-Plus-Reference
Operating Current
5.0
4.5 5.5V
LATCH

LATCH

LATCH

LATCH

10-BIT 10-BIT
DAC A DAC B 4.0 4.5V

3.5
ICC + IREF (µA)

3.0
2.5 3.6V
2.0 VCC = 2.7V
CONTROL ADDRESS
LOGIC DECODER 1.5
1.0
0.5 VREF = VCC
SHIFT REGISTER CODE = 1023
0
–55 –35 –15 5 25 45 65 85 105 125
TEMPERATURE (°C)
1662 TA01b
1 2 3 4 1662 BD

CS/LD SCK SDI REF

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LTC1662
Absolute Maximum Ratings
(Note 1)
VCC to GND................................................ –0.3V to 7.5V Operating Temperature Range
Logic Inputs to GND ................................. –0.3V to 7.5V LTC1662C................................................ 0°C to 70°C
VOUT A, VOUT B, REF to GND.......... –0.3V to (VCC + 0.3V) LTC1662I............................................. –40°C to 85°C
Maximum Junction Temperature........................... 125°C Lead Temperature (Soldering, 10 sec)................... 300°C
Storage Temperature Range................... –65°C to 150°C

Pin Configuration
TOP VIEW
TOP VIEW
CS/LD 1 8 VOUT A
CS/LD 1 8 VOUT A
SCK 2 7 GND SCK 2 7 GND
SDI 3 6 VCC SDI 3 6 VCC
REF 4 5 VOUT B
REF 4 5 VOUT B
MS8 PACKAGE
8-LEAD PLASTIC MSOP
N8 PACKAGE
TJMAX = 125°C, θJA = 150°C/W 8-LEAD PLASTIC DIP
TJMAX = 125°C, θJA = 100°C/W

Order Information
LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC1662CMS8#PBF LTC1662CMS8#TRPBF LTKB 8-Lead Plastic MSOP 0°C to 70°C
LTC1662IMS8#PBF LTC1662IMS8#TRPBF LTKC 8-Lead Plastic MSOP –40°C to 85°C
LTC1662CN8#PBF LTC1662CN8#TRPBF LTC1662CN8 8-Lead Plastic DIP 0°C to 70°C
LTC1662IN8#PBF LTC1662IN8#TRPBF LTC1662IN8 8-Lead Plastic DIP –40°C to 85°C
LEAD BASED FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC1662CMS8 LTC1662CMS8#TR LTKB 8-Lead Plastic MSOP 0°C to 70°C
LTC1662IMS8 LTC1662IMS8#TR LTKC 8-Lead Plastic MSOP –40°C to 85°C
LTC1662CN8 LTC1662CN8#TR LTC1662CN8 8-Lead Plastic DIP 0°C to 70°C
LTC1662IN8 LTC1662IN8#TR LTC1662IN8 8-Lead Plastic DIP –40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

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 LTC1662
Electrical Characteristics The l denotes the specifications which apply over the full operating
temperature range (TA = TMIN to TMAX), otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VREF ≤ VCC, VOUT unloaded
unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Accuracy
Resolution l 10 Bits
Monotonicity (Note 2) l 10 Bits
DNL Differential Nonlinearity (Note 2) l ±0.12 ±0.75 LSB
INL Integral Nonlinearity (Note 2) l ±0.8 ±4 LSB
VOS Offset Error VCC = 5V, VREF = 4.096V, Measured at Code 20 l ±5 ±25 mV
VOS TC VOS Temperature Coefficient ±15 µV/°C
GE Gain Error VCC = 5V, VREF = 4.096V l ±1 ±8 LSB
GE TC Gain Error Temperature Coefficient ±12 µV/°C
PSR Power Supply Rejection VREF = 2.5V 0.18 LSB/V
Reference Input
Input Voltage Range l 0 VCC V
Input Resistance Active Mode l 3.9 7.1 MΩ
Sleep Mode 2.5 GΩ
Input Capacitance 10 pF
Power Supply
VCC Positive Supply Voltage For Specified Performance l 2.7 5.5 V
ICC Supply Current VCC = 3V (Note 3) 3.0 4.0 µA
VCC = 5V (Note 3) 3.5 4.5 µA
VCC = 3V (Note 3) l 5.0 µA
VCC = 5V (Note 3) l 5.5 µA
Sleep Mode Operating Current Supply Plus Reference Current, VCC = VREF = 5V (Note 3) 0.05 0.10 µA
l 0.18 µA
DC Performance
Short-Circuit Current Low VOUT = 0V, VCC = VREF = 5V, Code = 1023 (Note 7) l 5 12 70 mA
Short-Circuit Current High VOUT = VCC = VREF = 5V, Code = 0 (Note 7) l 3 10 80 mA
AC Performance
Voltage Output Slew Rate Rising (Notes 4, 5) 20 V/ms
Falling (Notes 4, 5) 7 V/ms
Voltage Output Settling Time Rising 0.1VFS to 0.9VFS ±0.5LSB (Notes 4, 5) 0.40 ms
Falling 0.9VFS to 0.1VFS ±0.5LSB (Notes 4, 5) 0.75 ms
Capacitive Load Driving 1000 pF
Digital I/O
VIH Digital Input High Voltage VCC = 2.7V to 5.5V l 2.4 V
VCC = 2.7V to 3.6V l 2.0 V
VIL Digital Input Low Voltage VCC = 4.5V to 5.5V l 0.8 V
VCC = 2.7V to 5.5V l 0.6 V
ILK Digital Input Leakage VIN = GND to VCC l ±0.05 ±1.0 µA
CIN Digital Input Capacitance 1.5 pF

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LTC1662
Timing Characteristics The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VCC = 4.5V to 5.5V
t1 SDI Setup Relative to SCK Positive Edge l 55 ns
t2 SDI Hold Relative to SCK Positive Edge l 0 ns
t3 SCK High Time (Note 6) l 30 ns
t4 SCK Low Time (Note 6) l 30 ns
t5 CS/LD Pulse Width (Note 6) l 100 ns
t6 LSB SCK High to CS/LD High (Note 6) l 30 ns
t7 CS/LD Low to SCK High (Note 6) l 20 ns
t9 SCK Low to CS/LD Low (Note 6) l 0 ns
t11 CS/LD High to SCK Positive Edge (Note 6) l 20 ns
SCK Frequency Square Wave (Note 6) l 16.7 MHz
VCC = 2.7V to 5.5V
t1 SDI Setup Relative to SCK Positive Edge (Note 6) l 75 ns
t2 SDI Hold Relative to SCK Positive Edge (Note 6) l 0 ns
t3 SCK High Time (Note 6) l 50 ns
t4 SCK Low Time (Note 6) l 50 ns
t5 CS/LD Pulse Width (Note 6) l 150 ns
t6 LSB SCK High to CS/LD High (Note 6) l 50 ns
t7 CS/LD Low to SCK High (Note 6) l 30 ns
t9 SCK Low to CS/LD Low (Note 6) l 0 ns
t11 CS/LD High to SCK Positive Edge (Note 6) l 30 ns
SCK Frequency Square Wave (Note 6) l 10 MHz

Note 1: Stresses beyond those listed under Absolute Maximum Ratings Note 3: Digital inputs at 0V or VCC.
may cause permanent damage to the device. Exposure to any Absolute Note 4: Load is 10kΩ in parallel with 100pF.
Maximum Rating condition for extended periods may affect device Note 5: VCC = VREF = 5V. DAC switched between 0.1VFS and 0.9VFS ;
reliability and lifetime. i.e., codes k = 102 and k = 922.
Note 2: Nonlinearity and monotonicity are defined and tested at VCC = 5V, Note 6: Guaranteed by design, not subject to test.
VREF = 4.096V, from code 20 to code 1023. See Figure 2.
Note 7: One DAC output loaded.

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 LTC1662
Typical Performance Characteristics
Total Supply-Plus-Reference Supply Current
Supply Current vs Temperature Operating Current vs Clock Frequency
5.0 5.0 1000
VREF = VCC CS/LD = LOGIC LOW
4.5 CODE = 1023 4.5 5.5V CODE = 0
4.0 4.0 4.5V
5.5V 4.5V VCC = 5V
3.5 3.5
100

ICC + IREF (µA)

3.0 3.0
ICC (µA)

ICC (µA)
2.5 2.5 3.6V
2.0 2.0 VCC = 2.7V VCC = 3V
3.6V VCC = 2.7V 10
1.5 1.5
1.0 1.0
0.5 0.5 VREF = VCC
CODE = 1023
0 0 1
–55 –35 –15 5 25 45 65 85 105 125 –55 –35 –15 5 25 45 65 85 105 125 10 100 1k 10k 100k 1M 10M 100M
TEMPERATURE (°C) TEMPERATURE (°C) FREQUENCY (Hz)
1662 G03
1662 G01 1662 G02

Supply Current
vs Logic Input Voltage Integral Nonlinearity (INL) Differential Nonlinearity (DNL)
1.0 4 0.75
VCC = 5V
0.60
0.9 ALL DIGITAL INPUTS 3

DIFFERENTIAL NONLINEARITY (LSB)

SHORTED TOGETHER
INTEGRAL NONLINEARITY (LSB)

0.8 0.40
2
0.7
1 0.20
0.6
ICC (mA)

0.5 0 0
0.4
–1 –0.20
0.3
–2
0.2 –0.40
0.1 –3
–0.60
0 –4 –0.75
0 1.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0 256 512 768 1023 0 256 512 768 1023
LOGIC INPUT VOLTAGE (V) CODE CODE
1662 G04 1662 G05 1662 G06

Integral Nonlinearity (INL) Differential Nonlinearity (DNL)

vs Reference Voltage vs Reference Voltage Offset Voltage vs Temperature
4 0.75 0
VCC = 5.5V VCC = 5.5V VCC = 5V
3 VREF = 4.096V
0.50
–1
2
OFFSET ERROR (mV)

0.25
PEAK DNL (LSB)
PEAK INL (LSB)

1 MAX POS DNL

MAX POS INL –2
0 0

–1 MAX NEG DNL –3

MAX NEG INL
–0.25
–2
–4
–0.50
–3

–4 –0.75 –5
0 1 2 3 4 5 6 0 1 2 3 4 5 6 –55 –35 –15 5 25 45 65 85 105
VREF (V) VREF (V) TEMPERATURE (°C)
1662 G07 1662 G08 1662 G09

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LTC1662
Typical Performance Characteristics
Load Regulation vs Output Load Regulation vs Output
Gain Error vs Temperature Current at 5V Current at 3V
0 1.0 1.0
VCC = 5V VREF = VCC = 5V VREF = VCC = 3V
VREF = 4.096V 0.8 VOUT = 2.5V 0.8 VOUT = 1.5V
CODE = 512 CODE = 512
–1 0.6 0.6
TA = 25°C TA = 25°C
0.4 0.4
GAIN ERROR (mV)

∆VOUT (LSB)
0.2

∆VOUT (LSB)
–2 0.2
0 0
–3 –0.2 –0.2
–0.4 –0.4
–4 –0.6 –0.6
–0.8 SOURCE SINK –0.8 SOURCE SINK
–5 –1.0 –1.0
–55 –35 –15 5 25 45 65 85 105 –5 –4 –3 –2 –1 0 1 2 3 4 5 –1 –0.8–0.6–0.4– 0.2 0 0.2 0.4 0.6 0.8 1
TEMPERATURE (°C) IOUT (mA) IOUT (mA)
1662 G10 1662 G11 1662 G12

Output Amplifier Current Sourcing Output Amplifier Current Sinking Max/Min Output Voltage vs Source/
Capability (Mid-Scale) Capability (Mid-Scale) Sink Output Current (VCC = 5V)
5.0 5.0 5.0
VREF = VCC VREF = VCC
4.5 CODE = 512 4.5 CODE = 512 4.5
TA = 25°C TA = 25°C CODE = 1023
4.0 4.0 4.0
VCC = 5.5V VCC = 5.5V
3.5 VCC = 5V 3.5 VCC = 5V 3.5
3.0 VCC = 4.5V 3.0 VCC = 4.5V VOUT (V) 3.0
VOUT (V)

VOUT (V)

VREF = VCC
2.5 2.5 2.5
TA = 25°C
2.0 2.0 2.0
1.5 1.5 1.5
1.0 VCC = 3.6V 1.0 VCC = 3.6V 1.0
VCC = 3V VCC = 3V CODE = 0
0.5 VCC = 2.7V 0.5 VCC = 2.7V 0.5
0 0 0
1 10 100 1m 10m 100m 1µ 10µ 100µ 1m 10m 100m 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
OUTPUT SOURCE CURRENT (A) OUTPUT SINK CURRENT (A) OUTPUT SOURCE/SINK CURRENT (mA)
1662 G13 1662 G14 1662 G15

Max/Min Output Voltage vs Source/ Output Minimum Series

Sink Output Current (VCC = 3V) Large-Signal Step Response Resistance vs Load Capacitance
3.0 5 180
2.7 160
CODE = 1023
MINIMUM SERIES RESISTANCE (Ω)

2.4 4
140
2.1
120
1.8 3
VOUT (V)

VOUT (V)

VREF = VCC 100

1.5
TA = 25°C
80
1.2 2
0.9 60

0.6 CODE = 0 1 40
VREF = VCC = 5V
0.3 20
10% TO 90% STEP
0 0 0
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 0 100p 1000p 0.01µ 0.1µ 1µ 10µ 100µ
OUTPUT SOURCE/SINK CURRENT (mA) TIME (0.5ms/DIV) CAPACITANCE (F)
1662 G16 1662 G17 1662 G18

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Pin Functions
CS/LD (Pin 1): Serial Interface Chip Select/Load Input. REF (Pin 4): Reference Voltage Input. 0V ≤ VREF ≤ VCC.
When CS/LD is low, SCK is enabled for shifting data on VOUT A, VOUT B (Pin 8, Pin 5): DAC Analog Voltage Outputs.
SDI into the register. When CS/LD is pulled high, SCK is The output range is
disabled and the operation(s) specified in the control code,
A3-A0, is (are) performed. CMOS and TTL compatible.  1023 
0 ≤ VOUTA ,VOUTB ≤ VREF 
 1024 
SCK (Pin 2): Serial Interface Clock Input. CMOS and TTL
compatible. VCC (Pin 6): Supply Voltage Input. 2.7V ≤ VCC ≤ 5.5V.
SDI (Pin 3): Serial Interface Data Input. Input word data GND (Pin 7): System Ground.
on the SDI pin is shifted into the 16-bit register on the
rising edge of SCK. CMOS and TTL compatible.

Definitions
Differential Nonlinearity (DNL): The difference between Least Significant Bit (LSB): The ideal voltage difference
the measured change and the ideal 1LSB change for any between two successive codes.
two adjacent codes. The DNL error between any two codes
LSB = VREF /1024
is calculated as follows:
Resolution (n): Defines the number of DAC output states
DNL = (∆VOUT – LSB)/LSB (2n) that divide the full-scale range. Resolution does not
where ∆VOUT is the measured voltage difference between imply linearity.
two adjacent codes.
Voltage Offset Error (VOS): Nominally, the voltage at the
Full-Scale Error (FSE): The deviation of the actual full- output when the DAC is loaded with all zeros. A single
scale voltage from ideal. FSE includes the effects of offset supply DAC can have a true negative offset, but the output
and gain errors (see Figure 2). cannot go below zero (see Figure 2).
Gain Error (GE): The deviation from the slope of the ideal For this reason, single supply DAC offset is measured at
DAC transfer function, expressed in LSBs at full-scale. the lowest code that guarantees the output will be greater
than zero.
Integral Nonlinearity (INL): The deviation from a straight
line passing through the endpoints of the DAC transfer
curve (endpoint INL). Because the output cannot go
below zero, the linearity is measured between full-scale
and the lowest code which guarantees the output will be
greater than zero. The INL error at a given input code is
calculated as follows:
INL = [VOUT – VOS – (VFS – VOS)(code/1023)]/LSB
where VOUT is the output voltage of the DAC measured at
the given input code.

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LTC1662
Timing Diagram

t1
t2 t3 t4 t6

SCK

t9 t11

SDI A3 A2 A1 X1 X0

t5 t7

CS/LD
1662 TD

Operation

SCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

SDI A3 A2 A1 A0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X1 X0

CONTROL CODE INPUT CODE DON’T CARE

INPUT WORD W0

CS/LD (SCK ENABLED) (INSTRUCTION

EXECUTED) 1662 F01

Figure 1. Register Loading Sequence

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 LTC1662
Operation
Table 1. DAC Control Functions
CONTROL INPUT REGISTER DAC REGISTER POWER-DOWN STATUS
A3 A2 A1 A0 STATUS STATUS (SLEEP/WAKE) COMMENTS
0 0 0 0 No Change No Update No Change No Operation. Power-Down Status Unchanged
(Part Stays In Wake or Sleep Mode)
0 0 0 1 Load DAC A No Update No Change Load Input Register A with Data. DAC Outputs Unchanged.
Power-Down Status Unchanged
0 0 1 0 Load DAC B No Update No Change Load Input Register B with Data. DAC Outputs Unchanged.
Power-Down Status Unchanged
1 0 0 0 No Change Update Outputs Wake Load Both DAC Regs with Existing Contents of Input Regs.
Outputs Update. Part Wakes Up
1 0 0 1 Load DAC A Update Outputs Wake Load Input Reg A. Load DAC Regs with New Contents of
Input Reg A and Existing Contents of Reg B. Outputs Update.
Part Wakes Up
1 0 1 0 Load DAC B Update Outputs Wake Load Input Reg B. Load DAC Regs with Existing Contents of
Input Reg A and New Contents of Reg B. Outputs Update.
Part Wakes Up
1 1 0 1 No Change No Update Wake Part Wakes Up. Input and DAC Regs Unchanged.
DAC Outputs Reflect Existing Contents of DAC Regs
1 1 1 0 No Change No Update Sleep Part Goes to Sleep. Input and DAC Regs Unchanged.
DAC Outputs Set to High Impedance State
1 1 1 1 Load DACs A, B Update Outputs Wake Load Both Input Regs. Load Both DAC Regs with New
with Same Contents of Input Regs. Outputs Update. Part Wakes Up
10-Bit Code
Note: All control codes other than those shown are undefined and not subject to test.

Transfer Function VCC (Pin 6) is in transition. If it is not possible to sequence

the supplies, clamp the voltage at REF by connecting a
The transfer function for the LTC1662 is:
Schottky diode between Pin 4 (anode) and Pin 6 (cathode).
 k 
VOUT(IDEAL) =  V
 1024  REF Serial Interface

where k is the decimal equivalent of the binary DAC input See Table 2. The 16-bit input word consists of the 4-bit
code D9-D0 and VREF is the voltage at REF (Pin 4). control code, the 10-bit input code and two don’t-care bits.

Power-On Reset Table 2. LTC1662 Input Word

Input Word
The LTC1662 actively clears the outputs to zero-scale
when power is first applied, making system initialization A3 A2 A1 A0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X1 X0
consistent and repeatable.
Control Code Input Code Don’t
Care
Power Supply Sequencing
The voltage at REF (Pin 4) should be kept within the range After the input word is loaded into the register (see Figure 1),
–0.3V ≤ VREF ≤ VCC + 0.3V (see the Absolute Maximum it is internally converted from serial to parallel format. The
Ratings). Particular care should be taken during power parallel 10-bit-wide input code data path is then buffered
supply turn-on and turn-off sequences, when the voltage at by two latch registers.

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LTC1662
Operation
The first of these, the input register, is used for loading and 0010 b); then, a single command (1000 b) can be used
new input codes. The second buffer, the DAC register, is both to wake the part and to update the output values.
used for updating the DAC outputs. Each DAC has its own Alternatively, one DAC may be loaded with a new input
10‑bit input register and 10-bit DAC register. code during sleep; then with just one command, the other
By selecting the appropriate 4-bit control code (see Table 1) DAC is loaded, the part is awakened and both outputs are
it is possible to perform single operations, such as loading updated.
one DAC or changing power-down status (sleep/wake). For example, control code 0001b is used to load DAC A
In addition, some control codes perform two or more during sleep. Then control code 0101b loads DAC B, wakes
operations at the same time. For example, one such code the part and simultaneously updates both DAC outputs.
loads DAC A, updates both outputs and Wakes the part
up. The DACs can be loaded separately or together, but Voltage Outputs
the outputs are always updated together.
Each of the rail-to-rail output amplifiers contained in
Register Loading Sequence the LTC1662 can typically source or sink at least 1mA
(VCC = 5V). The outputs swing to within a few millivolts
See Figure 1. With CS/LD held low, data on the SDI input of either supply when unloaded and have an equivalent
is shifted into the 16-bit shift register on the positive edge output resistance of 130Ω (typical) when driving a load to
of SCK. The 4-bit control code, A3-A0, is loaded first, then the rails. The output amplifiers are stable driving capacitive
the 10-bit input code, D9-D0, ordered MSB to LSB in each loads of up to 1000pF.
case. Two don’t-care bits, X1 and X0, are loaded last. When
the full 16-bit input word has been shifted in, CS/LD is A small resistor placed in series with the output can be
pulled high, causing the system to respond according to used to achieve stability for any load capacitance. Please
Table 1. The clock is disabled internally when CS/LD is see the Output Minimum Resistance vs Load Capacitance
high. Note: SCK must be low when CS/LD is pulled low. curve in the Typical Performance Characteristics section.

Sleep Mode Rail-to-Rail Output Considerations

DAC control code 1110b is reserved for the special sleep In any rail-to-rail DAC, the output swing is limited to volt-
instruction (see Table 1). In this mode, static power ages within the supply range.
consumption is greatly reduced. The reference input and If the DAC offset is negative, the output for the lowest
analog outputs are set in a high impedance state and all codes limits at 0V as shown in Figure 2b.
DAC settings are retained in memory so that when sleep
mode is exited, the outputs of DACs not updated by the Similarly, limiting can occur near full-scale when the REF
Wake command are restored to their last active state. pin is tied to VCC. If VREF = VCC and the DAC full-scale error
(FSE = VOS + GE) is positive, the output for the highest
Sleep mode is initiated by performing a load sequence codes limits at VCC as shown in Figure 2c. No full-scale
using control code 1110b (the DAC input code D9-D0 is limiting can occur if VREF is less than VCC – FSE.
ignored).
Offset and linearity are defined and tested over the region
To save instruction cycles, the DACs may be prepared of the DAC transfer function where no output limiting can
with new input codes during sleep (control codes 0001b occur.

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 LTC1662
Operation
POSITIVE
VREF = VCC FSE

OUTPUT
VOLTAGE

INPUT CODE

(2c)
VREF = VCC

OUTPUT
VOLTAGE

0 512 1023
INPUT CODE

(2a)
OUTPUT
VOLTAGE

0V
NEGATIVE INPUT CODE
OFFSET
1662 F02

(2b)

Figure 2. Effects of Rail-to-Rail Operation On a DAC Transfer Curve. (a) Overall Transfer Function (b) Effect of Negative
Offset for Codes Near Zero-Scale (c) Effect of Positive Full-Scale Error for Input Codes Near Full-Scale When VREF = VCC

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LTC1662
Typical Applications
Micropower Trim Circuit with Coarse/Fine Adjustment. Total Supply Current Is 9.5µA

3.3V
0.1µF R2 R1
1.1M 11k
2 3.3V 0.1µF
3.3V
1
LTC1258-2.5 0.1µF
2.5V
4 REF 6 VCC 8
4 2
R1 –
COARSE 1
LT1495 VOUT
8 11k 3
DAC A +
VOUT A 0.1µF 4
1
CS/LD
3 LTC1662
SDI U1
2 R2  CODE A R1 CODE B
SCK VOUT = VREF  + •
R2 1024 
FINE
1.1M
 1024
5
DAC B
VOUT B  CODE A 1 CODE B
= 2.5V  + •
 1024 100 1024 

7 GND 1662 TA02

Using the LTC1258 and the LTC1662 in a Portable Application

Powered by a Single Li-Ion Battery. Total Supply Current Is 8.2µA

Li-Ion BATTERY INPUT

VIN ≥ 4.3V
0.1µF
0.1µF
6
2 VCC
1 4 8 0V TO 4.096V
LTC1258-4.1 REF VOUT A (4mV/BIT)
4.096V
4 3
SDI
LTC1662
2
SCK

1 5 0V TO 4.096V
CS/LD VOUT B (4mV/BIT)
GND
7 1662 TA03

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12
 LTC1662
Package Description
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

MS8 Package
8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660 Rev F)

3.00 ± 0.102
(.118 ± .004) 0.52
(NOTE 3) 8 7 6 5 (.0205)
REF

3.00 ± 0.102
0.889 ± 0.127 4.90 ± 0.152
DETAIL “A” (.118 ± .004)
(.035 ± .005) 0.254 (.193 ± .006)
(NOTE 4)
(.010)
0° – 6° TYP
GAUGE PLANE
5.23 1 2 3 4
(.206) 3.20 – 3.45
(.126 – .136) 0.53 ± 0.152
MIN 1.10 0.86
(.021 ± .006)
(.043) (.034)
DETAIL “A” MAX REF
0.18
0.42 ± 0.038 0.65
(.007)
(.0165 ± .0015) (.0256)
TYP BSC SEATING
PLANE 0.22 – 0.38
RECOMMENDED SOLDER PAD LAYOUT 0.1016 ± 0.0508
(.009 – .015) (.004 ± .002)
NOTE: TYP 0.65 MSOP (MS8) 0307 REV F
1. DIMENSIONS IN MILLIMETER/(INCH) (.0256)
2. DRAWING NOT TO SCALE BSC
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

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13
LTC1662
Package Description
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

N Package
8-Lead PDIPN Package
(Narrow .300 Inch)
8-Lead PDIP
(Reference (Narrow
LTC DWG .300 Inch)
# 05-08-1510 Rev I)
(Reference LTC DWG # 05-08-1510 Rev I)

.400*
(10.160)
MAX

8 7 6 5

.255 ± .015*
(6.477 ± 0.381)

1 2 3 4

.300 – .325 .045 – .065 .130 ± .005

(7.620 – 8.255) (1.143 – 1.651) (3.302 ± 0.127)

.065
(1.651)
.008 – .015 TYP
(0.203 – 0.381) .120
(3.048) .020
+.035 MIN (0.508)
.325 –.015
MIN

( )
.100 .018 ± .003
+0.889 (2.54)
8.255 (0.457 ± 0.076) N8 REV I 0711
–0.381
BSC
NOTE:
INCHES
1. DIMENSIONS ARE
MILLIMETERS
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm)

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14
 LTC1662
Revision History
REV DATE DESCRIPTION PAGE NUMBER
A 01/12 Removed Typical values in the Timing Characteristics section. 4
Corrected Related Parts listing for the LTC1659. 16

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Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. 15
LTC1662
Typical Application
Ultralow Power DAC Optimizes Mixer Performance
3.3V
0.1µF

2 3.3V 0.1µF
1 LO I IP
LTC1258-2.5
2.5V
4 REF 6 VCC
4
3.9k
3.9k 0.1%
0.1%
8 560k 3.9k, 0.1%
DAC A
VOUT A 3.9k
1 0.1%
CS/LD I IP
3 I+Q
SDI LTC1662 LO MIXER RF
Q QP
2
SCK 3.9k
560k 0.1% 3.9k, 0.1%
5
DAC B
VOUT B
3.9k
0.1% 3.9k
0.1%
7 GND 1662 TA04
Q
Q QP

Related Parts
PART NUMBER DESCRIPTION COMMENTS
LTC1661 Dual 10-Bit VOUT DAC in 8-Lead MSOP Package VCC = 2.7V to 5.5V, 60µA per DAC, Rail-to-Rail Output
LTC1663 Single 10-Bit VOUT DAC with 2-Wire Interface in SOT-23 Package VCC = 2.7V to 5.5V, Internal Reference, 60µA
LTC1664 Quad 10-Bit VOUT DAC in 16-Pin Narrow SSOP VCC = 2.7V to 5.5V, 60µA per DAC, Rail-to-Rail Output
LTC1665/LTC1660 Octal 8-/10-Bit VOUT DAC in 16-Pin Narrow SSOP VCC = 2.7V to 5.5V, 60µA per DAC, Rail-to-Rail Output
LTC1446/LTC1446L Dual 12-Bit VOUT DACs in SO-8 Package with Internal Reference LTC1446: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V
LTC1446L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V
LTC1448 Dual 12-Bit VOUT DAC in SO-8 Package VCC = 2.7V to 5.5V, External Reference Can Be Tied to VCC
LTC1454/LTC1454L Dual 12-Bit VOUT DACs in SO-16 Package with Added Functionality LTC1454: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V
LTC1454L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V
LTC1458/LTC1458L Quad 12-Bit Rail-to-Rail Output DACs with Added Functionality LTC1458: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V
LTC1458L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V
LTC1659 Single Rail-to-Rail 12-Bit VOUT DAC in 8-Lead MSOP Package VCC = 2.7V to 5.5V, Low Power Multiplying VOUT DAC. Output
Swings from GND to REF. REF Input Can Be Tied to VCC

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16 Linear Technology Corporation

LT 0112 REV A • PRINTED IN USA

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com  LINEAR TECHNOLOGY CORPORATION 2000