VLSI DESIGN FLOW: RTL TO
GDS
Lecture 37
Chip Planning - I
Sneh Saurabh
Electronics and Communications
Engineering
IIIT Delhi
Lecture Plan
▪ Chip Planning
➢ Hierarchical Design Implementation
➢ Floorplanning
➢ Power Planning
VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh
Laying plans …
“…While times are quiet, it is easy to take action; ere (before) coming troubles have cast their
shadows, it is easy to lay plans.... A journey of a thousand miles began with a single step.”
—Lao Tzu (ancient Taoist philosopher)
VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh
Implementation Methodology
Implementation
Methodology
Hierarchical design
Flat Design Implementation
implementation
Tasks in hierarchical design implementation
1. Partitioning
2. Budgeting
3. Block Implementation
4. Top-level Assembly
VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh
Partitioning
How to partition?
▪ Partitions are called blocks
▪ Partition using logical functionality
Other approaches:
▪ Group modules into clusters
▪ Partition a netlist using partitioning algorithm
➢ Reduce the number of cuts or nets crossing blocks
VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh
Budgeting
▪ Process of allocating some fraction of a clock cycle to different blocks and the top-level
design for signals crossing block boundaries
▪ Create block level SDC
VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh
Block Implementation and Top-level Assembly
Block Implementation Top-level Assembly
➢ Implement each block separately ➢ Integrate all the blocks at the top-level
➢ Use allocated timing budgets and ➢ Carry out verification at the top-level
block constraints (verify at block level) ➢ Omit details of the timing paths
contained entirely within a block
Abstract Timing Model of Blocks:
▪ Retain information of interface
timing paths of the blocks
▪ Extracted Timing Model (ETM)
▪ Interface Library Model (ILM)
VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh
Hierarchical Design Methodology: Merits and
Challenges
Advantages:
▪ Physical implementation and other EDA tools need to handle smaller problems
▪ Multiple blocks can be concurrently implemented by different teams
➢ Overall design time decreases
Disadvantages:
▪ Challenging to partition a design optimally
▪ Loose some opportunities of inter-block optimizations
VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh
Floorplanning
VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh
Floorplanning: Basics
▪ Planning phase of the layout Major Tasks:
➢ Designer’s intent about physical 1. Define die/chip size and aspect ratio
design
2. I/O cell placement
▪ Prepares a design for other physical
design tasks 3. Hard macros/block placement
➢ Huge impact on the final FoM 4. Pin assignment
5. Create rows for standard cells
▪ Must consider routability, performance,
power, etc.
VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh
Die Size
Goal: choose smallest size of die that
can fit the design
Die area should include area for:
➢ IO Cells/IO Pads
➢ Standard Cells
➢ Macros + Halo
➢ Interconnects (utilization)
Rough Estimate based on:
𝐶𝑒𝑙𝑙 𝑎𝑟𝑒𝑎 + 𝑀𝑎𝑐𝑟𝑜 𝑎𝑟𝑒𝑎 + 𝐻𝑎𝑙𝑜 𝑎𝑟𝑒𝑎
𝑈𝑡𝑖𝑙𝑖𝑧𝑎𝑡𝑖𝑜𝑛 = ▪ Previous designs
𝐶𝑜𝑟𝑒 𝑎𝑟𝑒𝑎
▪ Available package size
VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh
IO Cells: Basics
▪ IO cells are special circuit elements through
which a chip communicates with the external
world
▪ Can be of type input, output, or
bidirectional
Other functions of IO cells
▪ Drive capability
▪ Voltage transformation
▪ Protection against ESD (Electro-Static
Discharge) [short high-voltage (several
kilovolt) pulses]
VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh
IO Cells: Connection with Package
▪ Metallic pad (MPAD) is connected to the package pins using
bonding wires
▪ Power pads: special cells that supply power to a chip
▪ IO Cells too need power and ground connections
Number of power pads:
▪ Target level of internal voltages
▪ Current capacity of the power pads
Placement of IO Cells are guided by heuristics
▪ Assign nearby positions to two primary inputs that jointly drive a multi-input logic gate
▪ Spread power-hungry I/O cells all over the die area to avoid creating voltage drop hotspots
▪ Avoid placing sensitive (such as clock signals) near IO cells
▪ Flip-chip technology offers more flexibility in placing macro cells.
VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh
References
▪ S. Saurabh, “Introduction to VLSI Design Flow”. Cambridge: Cambridge University Press,
2023.
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