da380

MEMS digital output motion sensor

low-power high performance 3-axes “DSC-XYZ” accelerometer

Key Features
• Supply voltage, 1.62V to 3.6V
• For 3x3x0.9 mm LGA-10 package
• User selectable range, ±2g, ±4g, ±8g, ±16g
• User selectable data output rate
• Digital I2C output interface
• 14 bit resolution
• Low power consumption
• 1 Programmable interrupt generator with independent function for motion detection
• Free-fall detection
• Embedded self-test function
• Factory programmable offset and sensitivity
• RoHS compliant

Applications
• User interface for mobile phone and PMP
• Display orientation
• Gesture recognition
• Active/inactive monitoring
• Free-fall detection
• Double/ Click recognition
• Power management
• Vibration monitoring
• Inclination and tilt sensing
• Pedometer

1/ 45 www.miramems.com
Aug 2013Rev 0.1 DS_da380

Product Overview
The da380 sensor is the low power high performance capacitive three-axis linear accelerometer developed by
micro-machined technology. The device is available in a 3x3x0.9 mm land grid array (LGA) and it is guaranteed
to operate over an extended temperature range from -40°C to +85°C. The sensor element is fabricated by single
crystal silicon with DRIE process and is protected by hermetically sealed silicon cap from the environment. The
device features user selectable full scale of ±2g/ ±4g/ ±8g/ ±16g measurement range with data output rate from
1Hz to 1 kHz with signal condition, temperature compensation， self-test, motion detection imbedded. The da380
has a self-test mode for user to check the functioning of the sensor and a power-down mode that makes it good for
handset power management. Flexible interrupt provided greatly simplify the algorithm for various motion status
detections. Standard I2C interface is used to communicate with the chip.

2/ 45 www.miramems.com
Aug 2013Rev 0.1 DS_da380

Content
1 Block diagram and pin description ............................................................................................................................. 9
1.1 Block diagram ............................................................................................................................................. 9
1.2 Pin description............................................................................................................................................ 9
2 Mechanical and electrical specifications .................................................................................................................. 11
2.1 Mechanical characteristics ....................................................................................................................... 11
2.2 Electrical characteristics ........................................................................................................................... 12
2.3 Absolute maximum ratings....................................................................................................................... 13
3 Communication interface ......................................................................................................................................... 14
3.1 Communication interface Electrical specification .................................................................................... 14
3.1.1 I2CElectrical specification ................................................................................................................. 14
3.2 Digital interface operation........................................................................................................................ 15
3.2.1 I2C Operation.................................................................................................................................... 15
4 Terminology and functionality.................................................................................................................................. 17
4.1 Terminology .............................................................................................................................................. 17
4.1.1 Sensitivity ......................................................................................................................................... 17
4.1.2 Zero-g level ....................................................................................................................................... 17
4.2 Functionality ............................................................................................................................................. 17
4.2.1 Power mode ..................................................................................................................................... 17
4.2.2 Sensor data ....................................................................................................................................... 18
4.2.3 Self-test............................................................................................................................................. 18
4.2.4 Offset compensation ........................................................................................................................ 19
4.2.5 Factory calibration ............................................................................................................................ 19
4.3 Interrupt controller................................................................................................................................... 19
4.3.1 General features ............................................................................................................................... 19
4.3.2 Mapping............................................................................................................................................ 21
4.3.3 Electrical behavior (INT to open-drive or push-pull) ........................................................................ 21
4.3.4 New data interrupt ........................................................................................................................... 21
4.3.5 Active detection................................................................................................................................ 21
4.3.6 Tap detection .................................................................................................................................... 21
4.3.7 Orientation recognition .................................................................................................................... 23
4.3.8 Freefall interrupt............................................................................................................................... 24
5 Application hints....................................................................................................................................................... 26
6 Register mapping...................................................................................................................................................... 27
7 Registers description ................................................................................................................................................ 29
7.1 I2C Configuration (00H) ............................................................................................................................ 29
7.2 CHIPID (01h) ............................................................................................................................................. 29
7.3 ACC_X_LSB (02H) , ACC_X_MSB (03H) ..................................................................................................... 29
7.4 ACC_Y_LSB (04H) , ACC_Y_MSB (05H)...................................................................................................... 29
7.5 ACC_Z_LSB (06H) , ACC_Z_MSB (07H)...................................................................................................... 30
7.6 MOTION_FLAG (09H)................................................................................................................................ 30
7.7 NEWDATA_FLAG (0AH) ............................................................................................................................ 30

3/ 45 www.miramems.com
Aug 2013Rev 0.1 DS_da380

7.8 TAP_ACTIVE_STATUS (0BH) ...................................................................................................................... 31

7.9 ORIENT_STATUS (0CH) ............................................................................................................................. 31
7.10 RESOLUTION_RANGE (0FH) ...................................................................................................................... 32
7.11 ODR_AXIS (10H)........................................................................................................................................ 32
7.12 MODE_BW (11H) ...................................................................................................................................... 33
7.13 SWAP_POLARITY (12H)............................................................................................................................. 33
7.14 INT_SET1 (16H) ......................................................................................................................................... 34
7.15 INT_SET2 (17H) ......................................................................................................................................... 34
7.16 INT_MAP1 (19H) ....................................................................................................................................... 35
7.17 INT_MAP2 (1AH) ...................................................................................................................................... 35
7.18 INT_CONFIG (20H) .................................................................................................................................... 35
7.19 INT_LTACH (21H) ...................................................................................................................................... 36
7.20 FREEFALL_DUR (22H) ................................................................................................................................ 36
7.21 FREEFALL_THS (23H) ................................................................................................................................ 37
7.22 FREEFALL_HYST (24H) .............................................................................................................................. 37
7.23 ACTIVE_DUR (27H) ................................................................................................................................... 37
7.24 ACTIVE_THS (28H) .................................................................................................................................... 38
7.25 TAP_DUR (2AH) ........................................................................................................................................ 38
7.26 TAP_THS (2BH) ......................................................................................................................................... 39
7.27 ORIENT_HYST (2CH) ................................................................................................................................. 39
7.28 Z_BLOCK (2DH) ......................................................................................................................................... 40
7.29 SELF_TEST (32H) ....................................................................................................................................... 40
7.30 CUSTOM_OFF_X (38H) ............................................................................................................................. 40
7.31 CUSTOM_OFF_Y (39H) ............................................................................................................................. 41
7.32 CUSTOM_OFF_Z (39H) ............................................................................................................................. 41
7.33 CUSTOM_FLAG (4EH) ............................................................................................................................... 41
7.34 CUSTOM_CODE (4FH) ............................................................................................................................... 41
7.35 Z_ROT_HODE_TM (51H)........................................................................................................................... 42
7.36 Z_ROT_DUR (52H) .................................................................................................................................... 42
7.37 ROT_TH_H (53H) ...................................................................................................................................... 42
7.38 ROT_TH_L (54H) ....................................................................................................................................... 43
8 Package information................................................................................................................................................. 44
9 Revision history ........................................................................................................................................................ 45

4/ 45 www.miramems.com
Aug 2013Rev 0.1 DS_da380

List of tables
Table 1. Pin description ............................................................................................................................................ 10
Table 2. Mechanical characteristic ........................................................................................................................... 11
Table 3. Electrical characteristics.............................................................................................................................. 12
Table 4. Absolute maximum ratings ......................................................................................................................... 13
Table 5. Electrical specification of the I2C interface pins ......................................................................................... 14
Table 6. I2C Address ................................................................................................................................................. 15
Table 7. SAD+Read/Write patterns ........................................................................................................................... 15
Table 8. Transfer when master is writing one byte to slave ..................................................................................... 15
Table 9. Transfer when master is writing multiple bytes to slave............................................................................. 16
Table 10. Transfer when master is receiving (reading) one byte of data from slave ................................................ 16
Table 11. Transfer when master is receiving (reading) multiple bytes of data from slave ....................................... 16
Table 12. Self-test difference values ......................................................................................................................... 19
Table 13. Interrupt mode selection .......................................................................................................................... 19
Table 14. meaning of ‘orient’ bits in symmetric mode............................................................................................. 23
Table 15. meaning of ‘orient’ bits in high-asymmetric mode................................................................................... 23
Table 16. meaning of ‘orient’ bits in low-asymmetric mode.................................................................................... 24
Table 17. blocking conditions for orientation recognition ....................................................................................... 24
Table 18. Register address map ................................................................................................................................ 27
Table 19. I2C Configuration register ......................................................................................................................... 29
Table 20. I2C Configuration description ................................................................................................................... 29
Table 21. WHO_AM_I register .................................................................................................................................. 29
Table 22. Acc_x_lsb register ..................................................................................................................................... 29
Table 23. Acc_x_msb register ................................................................................................................................... 29
Table 24. Acc_y_lsb register ..................................................................................................................................... 29
Table 25. Acc_y_msb register ................................................................................................................................... 30
Table 26. Acc_z_lsb register ..................................................................................................................................... 30
Table 27. Acc_z_msb register ................................................................................................................................... 30
Table 28. Motion_interrupt register ......................................................................................................................... 30
Table 29. Motion_interrupt register description ...................................................................................................... 30
Table 30. Data_interrupt register ............................................................................................................................. 30
Table 31. Data_interrupt register description .......................................................................................................... 30
Table 32. Tap & active status register ....................................................................................................................... 31
Table 33. Tap & active status register description .................................................................................................... 31
Table 34. Orientation status register ........................................................................................................................ 31
Table 35. Orientation status register description ..................................................................................................... 31
Table 36. G-range register ........................................................................................................................................ 32
Table 37. G-range register description ..................................................................................................................... 32
Table 38. ODR and Axis disable register ................................................................................................................... 32
Table 39. ODR and Axis disable register description ................................................................................................ 32
Table 40. Power Mode & BW register ...................................................................................................................... 33
Table 41. Power Mode & BW register description ................................................................................................... 33
Table 42. Swap & Polarity register ............................................................................................................................ 33

5/ 45 www.miramems.com
Aug 2013Rev 0.1 DS_da380

Table 43. Swap & Polarity register description ......................................................................................................... 34

Table 44. Interrupt setting1 register......................................................................................................................... 34
Table 45. Interrupt setting1 register description...................................................................................................... 34
Table 46. Interrupt setting2 register......................................................................................................................... 34
Table 47. Interrupt setting2 register description...................................................................................................... 34
Table 48. Interrupt mapping1 register...................................................................................................................... 35
Table 49. Interrupt mapping1 register description................................................................................................... 35
Table 50. Interrupt mapping2 register...................................................................................................................... 35
Table 51. Interrupt mapping2 register description................................................................................................... 35
Table 52. INT_pin_config register ............................................................................................................................. 35
Table 53. INT_pin_config register description .......................................................................................................... 35
Table 54. INT_ latch register ..................................................................................................................................... 36
Table 55. INT_ latch register description .................................................................................................................. 36
Table 56. Freefall duration register........................................................................................................................... 36
Table 57. Freefall duration register description........................................................................................................ 36
Table 58. Freefall threshold register ......................................................................................................................... 37
Table 59. Freefall threshold register description ...................................................................................................... 37
Table 60. Freefall hysteresis register ........................................................................................................................ 37
Table 61. Freefall hysteresis register description ..................................................................................................... 37
Table 62. Active duration register............................................................................................................................. 37
Table 63. Active duration register description.......................................................................................................... 37
Table 64. Active threshold register ........................................................................................................................... 38
Table 65. Active threshold register description ........................................................................................................ 38
Table 66. Tap duration register ................................................................................................................................. 38
Table 67. Tap duration register description .............................................................................................................. 38
Table 68. Tap threshold register ............................................................................................................................... 39
Table 69. Tap threshold register description ............................................................................................................ 39
Table 70. Orient hysteresis register .......................................................................................................................... 39
Table 71. Orient hysteresis register description ....................................................................................................... 39
Table 72. Z_blocking register .................................................................................................................................... 40
Table 73. Z_blocking register description ................................................................................................................. 40
Table 74. Self_test register ....................................................................................................................................... 40
Table 75. Self_test register description .................................................................................................................... 40
Table 76. Custom_offset_X register.......................................................................................................................... 40
Table 77. Custom_offset_X register description....................................................................................................... 40
Table 78. Custom_offset_Y register .......................................................................................................................... 41
Table 79. Custom_offset_Y register description....................................................................................................... 41
Table 80. Custom_offset_Z register .......................................................................................................................... 41
Table 81. Custom_offset_Z register description ....................................................................................................... 41
Table 82. Custom_OTP_programmed register ......................................................................................................... 41
Table 83. Custom_OTP_programmed register description ...................................................................................... 41
Table 84. Custom_OTP_ready register ..................................................................................................................... 41
Table 85. Custom_OTP_ready register description .................................................................................................. 42
Table 86. Z_rot_hold_time register .......................................................................................................................... 42

6/ 45 www.miramems.com
Aug 2013Rev 0.1 DS_da380

Table 87. Z_rot_hold_time register description ....................................................................................................... 42

Table 88. Z_rot_dur register ..................................................................................................................................... 42
Table 89. Z_rot_dur register description .................................................................................................................. 42
Table 90. Rot_th_h register ...................................................................................................................................... 42
Table 91. Rot_th_h register description ................................................................................................................... 42
Table 92. Rot_th_h register ...................................................................................................................................... 43
Table 93. Rot_th_h register description ................................................................................................................... 43
Table 94. Document revision history ........................................................................................................................ 45

7/ 45 www.miramems.com
Aug 2013Rev 0.1 DS_da380

List of figures
Figure 1 Block Diagram .............................................................................................................................................. 9
Figure 2 Pin Connections ........................................................................................................................................... 9
Figure 3 I2C Slave timing diagram ........................................................................................................................... 14
Figure 4 I2C Protocol ................................................................................................................................................ 15
Figure 5 power mode............................................................................................................................................... 18
Figure 6 Interrupt mode .......................................................................................................................................... 20
Figure 7 Timing of Tap detection ............................................................................................................................. 22
Figure 8 Definition of vector components .............................................................................................................. 23
Figure 9 da380 I2C Electrical connection ................................................................................................................ 26
Figure 10 10 Pin LGA Mechanical data and package dimensions ........................................................................... 44

8/ 45 www.miramems.com
Aug 2013Rev 0.1 DS_da380

1 Block diagram and pin description

1.1 Block diagram

Figure 1 Block Diagram

1.2 Pin description

Figure 2 Pin Connections

9/ 45 www.miramems.com
Aug 2013Rev 0.1 DS_da380

Table 1. Pin description

Pin# Name Function
1 NC Not connected
2 NC Not connected
3 Vdd Power supply
4 GND 0V supply
5 INT Inertial interrupt
6 SCL I2C serial clock (SCL)
7 SDA I2C serial data (SDA)
8 GND 0V supply
9 Vdd_IO Power supply for I/O pins
10 NC Not connected

10/ 45 www.miramems.com
Aug 2013Rev 0.1 DS_da380

2 Mechanical and electrical specifications

2.1 Mechanical characteristics

Vdd = 2.5 V, T = 25 °C unless otherwise noted (a)

a. The product is factory calibrated at 2.5 V. The operational power supply range is from 1.62V to 3.6 V.

Table 2. Mechanical characteristic

Symbol Parameter Test conditions Min Type Max Unit

FS bit set to 00 ±2 g
FS bit set to 01 ±4 g
FS Measurement range
FS bit set to 10 ±8 g
FS bit set to 11 ±16 g
FS bit set to 00 4096 LSB/g
FS bit set to 01 2048 LSB/g
So Sensitivity
FS bit set to 10 1024 LSB/g
FS bit set to 11 512 LSB/g

Sensitivity change vs.

TCSo FS bit set to 00 0.01 %/°C
temperature

Typical zero-g level offset

Tyoff 70 mg
accuracy

Zero-g level change vs.

Tcoff Max delta from 25°C ±0.44 mg/°C
temperature

FS bit set to 00,

An Acceleration noise density Normal Mode, 150 200 ug/sqrt(Hz)
ODR = 1000Hz
X: FS bit set to 00 400 mg
Vst Self-test output change Y: FS bit set to 00 400 mg
Z: FS bit set to 00 400 mg

Top Operation temperature range -40 85 °C

11/ 45 www.miramems.com
Aug 2013Rev 0.1 DS_da380

2.2 Electrical characteristics

Vdd = 2.5 V, T = 25 °C unless otherwise noted

Table 3. Electrical characteristics

Symbol Parameter Test conditions Min Typ. Max Unit

Vdd Supply voltage 1.62 2.5 3.6 V
Vdd_IO I/O Pins supply voltage 1.62 3.6 V

current consumption in Top=25℃,

Idd 165 uA
normal mode ODR=1kHz

Top=25℃,
current consumption in low
Idd_lp ODR=250Hz, 2 uA
power mode
BW=500Hz
current consumption in
Idd_sm Top=25℃ 0.7 uA
suspend mode
Digital high level input
VIH I2C 0.7*Vdd_IO V
voltage
Digital low level input
VIL I2C 0.3*Vdd_IO V
voltage
VOH high level output voltage 0.9*Vdd_IO V
VOL Low level output voltage 0.1*Vdd_IO V
BW System bandwidth 1.95 500 Hz
ODR Output data rate 1 1000 Hz
Wake-up
twu From stand-by 1 ms
time
Start-up
tsu From power off 3 ms
time

PSRR Power Supply Rejection Rate Top=25℃ 20 mg/V

12/ 45 www.miramems.com
Aug 2013Rev 0.1 DS_da380

2.3 Absolute maximum ratings

Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device under these conditions is not implied. Exposure to
maximum rating conditions for extended periods may affect device reliability.

Table 4. Absolute maximum ratings

Parameter Test conditions Min Max Unit

Storage Temperature -45 125 ℃

Supply Voltage Supply pins -0.3 4.25 V

Supply Voltage Logic pins -0.3 Vdd_IO+0.3 V

ESD Rating HMB,R=1.5k,C=100pF ±2 kV

Mechanical Shock Duration<200us 10,000 g

Note: Supply voltage on any pin should never exceed 4.25V

This is a mechanical shock sensitive device, improper handling can cause permanent damages to the part.

This is an ESD sensitive device, improper handling can cause permanent damages to the part.

13/ 45 www.miramems.com
Aug 2013Rev 0.1 DS_da380

3 Communication interface

3.1 Communication interface Electrical specification

3.1.1 I2CElectrical specification

Table 5. Electrical specification of the I2C interface pins

Symbol Parameter Min Max Unit

f scl Clock frequency 400 kHz

t scl_l SCL low pulse 1.3 us

t scl_h SCL high pulse 0.6 us

T sda_setup SDA setup time 0.1 us

T sda_hold SDA hold time 0.0 us

t susta Setup Time for a repeated start condition 0.6 us

t hdsta Hold time for a start condition 0.6 us

t susto Setup Time for a stop condition 0.6 us

t buf Time before a new transmission can start 1.3 us

The figure below shows the definition of the I2C timing given in Table5:

Figure 3 I2C Slave timing diagram

14/ 45 www.miramems.com
Aug 2013Rev 0.1 DS_da380

3.2 Digital interface operation

3.2.1 I2C Operation

I2C bus uses SCL and SDA as signal lines. Both lines are connected to VDDIO externally via pull-up resistors so that
they are pulled high when the bus is free. The I2C device address of da380 is shown below.

Table 6. I2C Address

SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 W/R

0 1 0 0 1 1 1 0/1

Table 7. SAD+Read/Write patterns

Command SAD[6:1] SAD[0] R/W SAD+R/W
Read 010011 1 1 01001111(4fh)
Write 010011 1 0 01001110(4eh)

The I2C interface protocol has special bus signal conditions. Start (S), stop (P) and binary data conditions are shown
below. At start condition, SCL is high and SDA has a falling edge. Then the slave address is sent. After the 7 address
bits, the direction control bit R/W selects the read or write operation. When a slave device recognizes that it is being
addressed, it should acknowledge by pulling SDA low in the ninth SCL (ACK) cycle.

At stop condition, SCL is also high, but SDA has a rising edge. Data must be held stable at SDA when SCL is high.
Data can change value at SDA only when SCL is low.

Figure 4 I2C Protocol

Table 8. Transfer when master is writing one byte to slave

Master S SAD+W SUB DATA P
Slave SAK SAK SAK

15/ 45 www.miramems.com
 Aug 2013Rev 0.1 DS_da380

Table 9. Transfer when master is writing multiple bytes to slave

Master S SAD+W SUB DATA DATA P
Slave SAK SAK SAK SAK

Table 10. Transfer when master is receiving (reading) one byte of data from slave
Master S SAD+W SUB SR SAD+R NMASK P
Slave SAK SAK SAK DATA

Table 11. Transfer when master is receiving (reading) multiple bytes of data from slave
Master S SAD+W SUB SR SAD+R MAK MAK NMASK P
Slave SAK SAK SAK DATA DATA DATA

16/ 45 www.miramems.com
Aug 2013Rev 0.1 DS_da380

4 Terminology and functionality

4.1 Terminology

4.1.1 Sensitivity

Sensitivity describes the gain of the sensor and can be determined e.g. by applying 1 g acceleration to it. As the
sensor can measure DC accelerations this can be done easily by pointing the axis of interest towards the center of
the earth, noting the output value, rotating the sensor by 180 degrees (pointing to the sky) and noting the output
value again. By doing so, ±1 g acceleration is applied to the sensor. Subtract the larger output value from the
smaller one, and dividing the result by 2, leads to the actual sensitivity of the sensor. This value changes very
little over temperature and also time. The sensitivity tolerance describes the range of sensitivities of a large
population of sensors.

4.1.2 Zero-g level

Zero-g level offset (TyOff) describes the deviation of an actual output signal from the ideal output signal if no
acceleration is present. A sensor in a steady state on a horizontal surface measure 0 g in X axis and 0 g in Y axis
whereas the Z axis measure 1 g. The output is ideally in the middle of the dynamic range of the sensor (content of
output data registers are 00h, data expressed as 2’s complement number). A deviation from ideal value in this
case is called Zero-g offset. Offset is to some extent a result of stress to MEMS sensor and therefore the offset can
slightly change after mounting the sensor onto a printed circuit board or exposing it to extensive mechanical stress.
Offset changes little over temperature; see “Zero-g level change vs. temperature”. The Zero-g level tolerance
(TyOff) describes the standard deviation of the range of Zero-g levels of a population of sensors.

4.2 Functionality

4.2.1 Power mode

The da380 has three different power modes. Besides normal mode, which represents the fully operational state of the
device, there are two special energy saving modes: low-power mode and suspend mode.

17/ 45 www.miramems.com
Aug 2013Rev 0.1 DS_da380

Normal
mode

Low power Suspend

mode mode

Figure 5 power mode

In normal mode, all parts of the electronic circuit are held powered-up and data acquisition is performed continuously.
In suspend mode, the whole analog part, including the oscillator, Ana LDO, Dig LDO and Drive Buffer are all powered
down, no data acquisition is performed and the only supported operation is to read/write the registers. Suspend mode is
entered by writing ‘11’ or ‘10’ to the ‘power_mode’ bits.

In low power mode, the device is periodically switching between a sleep phase and a wake-up phase. The wake-up
phase essentially corresponding to operation in normal mode with complete power-up of the circuitry. During the sleep
phase the analog part except the oscillator is powered down.

During the wake-up phase, if a enabled interrupt is detected, the device stays in the wake-up phase as long as the
interrupt condition endures (non-latched interrupt), or until the latch time expires (temporary interrupt), or until the
interrupt is reset (latched interrupt). If no interrupt detected, the device enters the sleep phase.

4.2.2 Sensor data

The width of acceleration data is 14bits given in two’s complement representation. The 14bits for each axis are split
into an MSB part (one byte containing bits 13 to 6) and an LSB lower part (one byte containing bits 5 to 0 and a
new_data flag).

4.2.3 Self-test

This feature permits to check the sensor functionality by applying electrostatic forces to the sensor core instead of
external accelerations. By actually deflecting the seismic mass, the entire signal path of the sensor can be tested.
Activating the self-test results in a static offset of the acceleration data; any external acceleration or gravitational force
applied to the sensor during active self-test will be observed in the output as a superposition of both acceleration and
self-test signal.

The self-test is activated individually for each axis by writing 1 to the register ‘self_test_en’bits. It is possible to control
the direction of the deflection though bit ‘selt_test_sign’ for each axis. The excitation occurs in positive (negative)
direction if ‘self_test_sign’ = ‘0b’ (‘1b’).

18/ 45 www.miramems.com
Aug 2013Rev 0.1 DS_da380

In order to ensure a proper interpretation of the self-test signal it is recommended to perform the self-test for both
directions and then to calculate the difference of the resulting acceleration values. Table12 show the difference for each
axis.

Table 12. Self-test difference values

X-axis signal Y-axis signal Z-axis signal
Resulting difference value +0.4g +0.4g +0.4g

4.2.4 Offset compensation

User performed offset calibration is released to users to compensate the after-board-mount offset, which can also
compensate the 0-g offset from +/-500mg to +/-2.93mg.

4.2.5 Factory calibration

The IC interface is factory calibrated for sensitivity (So) and Zero-g level (TyOff). The trimming values are
stored inside the device in a nonvolatile memory. The trimming parameters are downloaded into the registers after
da380 reset (POR or software reset). This allows using the device without further calibration.

4.3 Interrupt controller

Interrupt engines are integrated in the da380. If the condition of an enabled interrupt is fulfilled, the corresponding
status bit is set to 1 and the selected interrupt pin is activated. There is one interrupt pin, INT; interrupts can be freely
mapped to this pin.

4.3.1 General features

An interrupt is cleared depending on the selected interrupt mode, which is common to all interrupts. There are three
different interrupt modes: non-latched, latched and temporary. The mode is selected by the ‘latch_int’ bits according to
table18.

Table 13. Interrupt mode selection

19/ 45 www.miramems.com
Aug 2013Rev 0.1 DS_da380

latch_int Interrupt mode

0000 non-latched
0001 temporary latched 250ms
0010 temporary latched 500ms
0011 temporary latched 1s
0100 temporary latched 2s
0101 temporary latched 4s
0110 temporary latched 8s
0111 Latched
1000 non-latched
1001 temporary latched 1ms
1010 temporary latched 1ms
1011 temporary latched 2ms
1100 temporary latched 25ms
1101 temporary latched 50ms
1110 temporary latched 100ms
1111 Latched

An interrupt is generated if its activation condition is met. It can’t be cleared as long as the activation condition is
fulfilled. In the non-latched mode the interrupt status bit and the selected pin INT are cleared as soon as the activation
condition is no more valid. Exceptions to this behavior are the new data and orientation, which are automatically reset
after a fixed time.

In the latched mode an asserted interrupt status and the selected pin are cleared by writing 1 to bit ‘reset_int’. If the
activation condition still holds when it is cleared, the interrupt status is asserted again with the next change of the
acceleration registers.

In the temporary mode an asserted interrupt and selected pin are cleared after a defined period of time. The behavior of
the different interrupt modes is shown in figure10.

Figure 6 Interrupt mode

20/ 45 www.miramems.com
Aug 2013Rev 0.1 DS_da380

4.3.2 Mapping

The mapping of interrupts to the interrupt pins is done by registers ‘interrupt_mapping’ (0x19 and 0x1a), setting
int_inttyp to 1 can map this type interrupt to INT pin.

4.3.3 Electrical behavior (INT to open-drive or push-pull)

The interrupt pin can be configured to show desired electrical behavior. The ‘active’ level for each pin is set by register
bit int_lvl, if int_lvl = 0, then the pin INT is 0 active. Also the electric type of the interrupt pin can be selected. By
setting int_od = 1, the interrupt pin output type can be set to be open-drive.

4.3.4 New data interrupt

This interrupt serves for synchronous reading of acceleration data. It is generated after an acceleration data was
calculated. The interrupt is cleared automatically before the next acceleration data is ready.

4.3.5 Active detection

Active detection uses the slope between successive acceleration signals to detect changes in motion. An interrupt is
generated when the slope (absolute value of acceleration difference) exceeds a preset threshold. The threshold is set
with the value of register ‘active_th’ with the LSB corresponding to 16 LSB of acceleration data, that is 3.9mg in
2g-range, 7.8mg in 4g-range, 15.6mg in 8g-range and 31.3mg in 16g-range. And the maximum value is 1g in 2g-range,
2g in 4g-range, 4g in 8g-range and 8g in 16g-range.

The time difference between the successive acceleration signals depends is fixed to 1ms.
Active detection can be enabled (disabled) for each axis separately by writing ‘1’ to bits ‘active_en_x/y/z’. The active
interrupt is generated if the slope of any of the enabled axes exceeds the threshold for [‘active_dur’+1] consecutive
times. As soon as the slopes of all enabled axes fall below this threshold for [‘active_dur’+1] consecutive times, the
interrupt is cleared unless the interrupt signal is latched.

The interrupt status is stored in bit ‘active_int’. The bit ‘active_first_x/y/z’ record which axis triggered the active
interrupt first and the sign of this acceleration data that triggered the interrupt is recorded in the bit ‘active_sign’.

4.3.6 Tap detection

Tap detection has a functional similarity with a common laptop touch-pad or clicking keys of a computer mouse. A tap
event is detected if a pre-defined pattern of the acceleration slope is fulfilled at least for one axis. Two different tap
events are distinguished: A single tap is a single event within a certain time, followed by a certain quiet time. A double
tap consists a first such event followed by a second event within a defined time.

Single tap interrupt is enabled by writing 1 to bit ‘s_tap_int_en’ and double tap interrupt is enabled by writing 1 to bit

21/ 45 www.miramems.com
Aug 2013Rev 0.1 DS_da380

‘d_tap_int_en’. The status of the single tap interrupt is stored in bit ‘s_tap_int’ and the status of the double tap interrupt
is stored in bit ‘d_tap_int’.

The slope threshold for detecting a tap event is set by bits “tap_th” with the LSB corresponding to 256LSB of
acceleration data that is 62.5mg in 2g-range, 125mg in 4g-range, 250mg in 8g-range, 500mg in 16g-range. And the
maximum value equals to the full scale in each range.

In figure7 the meaning of different timing parameter is visualized.

Figure 7 Timing of Tap detection

The parameter ‘tap_shock’ and ‘tap_quiet’ apply to both single and double tap detection, while ‘tap_dur’ applies to
double detection only. Within the duration of ‘tap_shock’ any slope exceeding ‘tap_th’ after the first event is ignored,
within the duration of ‘tap_quiet’ there must be no slope exceeding ‘tap_th’, otherwise the first event will be cancelled.
A single tap is detected and the single tap interrupt is generated after the combination durations of ‘tap_shock’ and
‘tap_quiet’, if the corresponding slope conditions are fulfilled. The interrupt is cleared after a delay in non-latched
mode.

A double tap is detected and the double tap interrupt is generated if an event fulfilling the conditions for a single tap
occurs within the set duration in ‘tap_dur’ after the completion of the first tap event. The interrupt is cleared after a
delay in non-latched mode.

The sign of the slope of the first tap which triggered the interrupt is stored in bit ‘tap_sign’ (0 means positive, 1 means
negative). The axis which triggered the interrupt is indicated by bits ‘tap_first_x/y/z’.

22/ 45 www.miramems.com
Aug 2013Rev 0.1 DS_da380

4.3.7 Orientation recognition

The orientation recognition feature informs on an orientation change of sensor with respect to the gravitation field
vector ‘g’. The measured acceleration vector components with respect to the gravitation field are defined as shown in
figure 8.

Figure 8 Definition of vector components

Therefore, the magnitudes of the acceleration vectors are calculated as follows:

=
acc _ x 1g .sin θ ⋅ cos ϕ
−1g .sin θ ⋅ sin ϕ
acc _ y =
z 1g ⋅ cos θ
acc _ =
Depending on the magnitudes of the acceleration vectors the orientation of the device in the space is determined and
stored in the bits ‘orient’. There are three orientation calculation modes with different thresholds for switching between
different orientations: symmetrical, high-asymmetrical and low-asymmetrical. The mode is selected by setting the
‘orient_mode’ bits. For each orientation mode, the ‘orient’ bits have a different meaning as show in table 14 to table 15.

Table 14. meaning of ‘orient’ bits in symmetric mode

orient Name Angle Condition
X00 Portrait upright 315 < ϕ < 45
o o
|acc_y| < |acc_x| - ‘hyst’ &acc_x>= 0
X01 Portrait upside down 135o < ϕ < 225o |acc_y| < |acc_x| - ‘hyst’ &acc_x< 0
X10 Landscape left 45 < ϕ < 135
o o
|acc_y| >= |acc_x| + ‘hyst’ & acc_y < 0
X11 Landscape right 225 < ϕ < 315
o o
|acc_y| >= |acc_x| + ‘hyst’ & acc_y >= 0

Table 15. meaning of ‘orient’ bits in high-asymmetric mode

Orient Name Angle Condition
X00 Portrait upright 297 < ϕ < 63
o o
|acc_y| < 2*|acc_x| - ‘hyst’ &acc_x>= 0
X01 Portrait upside down 117o < ϕ < 243o |acc_y| < 2*|acc_x| - ‘hyst’ &acc_x< 0
X10 Landscape left 63 < ϕ < 117
o o
|acc_y| >= 2*|acc_x| + ‘hyst’ & acc_y < 0
X11 Landscape right 243 < ϕ < 297
o o
|acc_y| >= 2*|acc_x| + ‘hyst’ & acc_y >= 0

23/ 45 www.miramems.com
Aug 2013Rev 0.1 DS_da380

Table 16. meaning of ‘orient’ bits in low-asymmetric mode

Orient Name Angle Condition
X00 Portrait upright 333 < ϕ < 27
o o
|acc_y| < 0.5*|acc_x| - ‘hyst’ &acc_x>= 0
X01 Portrait upside down 153 < ϕ < 207
o o
|acc_y| < 0.5*|acc_x| - ‘hyst’ &acc_x< 0
X10 Landscape left 27 < ϕ < 153
o o
|acc_y| >= 0.5*|acc_x| + ‘hyst’ & acc_y < 0
X11 Landscape right 207 < ϕ < 333
o o
|acc_y| >= 0.5*|acc_x| + ‘hyst’ & acc_y >= 0

In the preceding tables, the parameter ‘hyst’ stands for a hysteresis which can be selected by bits ‘orient_hyst’. 1LSB of
‘orient_hyst’ always corresponds to 62.5mg in any g-range. The MSB of ‘orient’ bits contains information about the
direction of the z-axis. It is set to 0(1) if ac_z>=0 (acc_z<0). The hysteresis for z axis is fixed to 0.2g.

The orient interrupt is enabled by writing ‘orient_en’ bit. The interrupt is generated if the value of ‘orient’ has changed.
It is automatically cleared after one stable period of the orient value in non-latched mode. In temporary latched or
latched mode, the orient value is kept fixed as long as the interrupt persists. After cleaning the interrupt, the ‘orient’
will updated with the next following value change.

The change of the ‘orient’ value and the generation of the interrupt can be blocked according to conditions selected by
setting the value of bits ‘orient_blocking’ as described by table17.

Table 17. blocking conditions for orientation recognition

Orient_blocking Conditions
00b No blocking
01b Z blocking
10b Z blocking or acceleration slope in any axis > 0.2g
11b No blocking

The Z blocking is defined by the following inequality：

| acc _ z |> z _ blocking
The parameter z_blocking of the above given equation stands for the contents of the ‘z_blocking’ bits. Hereby it is
possible to define a blocking value between 0g and 0.9375g with an LSB = 0.0625g.

4.3.8 Freefall interrupt

This interrupt is based on the comparison of acceleration data against a low-g threshold. The interrupt is enabled by
writing 1 to the bit ‘freefall_en’. There are two modes available: single mode’ and sum mode. In single mode the
acceleration of each axis is compared with the threshold. In sum mode, the sum of absolute values of all accelerations
|acc_x| + |acc_y| + |acc_z| is compared with the threshold. The mode is selected by the bit ‘freefall_mode’. The freefall
threshold is set through the ‘freefall_th’ bits with 1 LSB corresponding to an acceleration of 7.81mg. A hysteresis can
be selected by setting the ‘freefall_hy’ bits with 1 LSB corresponding to 125mg.

The freefall interrupt is generated if the absolute values of the acceleration of all axes or their sum are lower than the
threshold for at least the time defined by ‘freefall_dur’ bits. The interrupt is reset if the absolute value of at least one

24/ 45 www.miramems.com
Aug 2013Rev 0.1 DS_da380

axis or the sum is higher than the threshold plus the hysteresis for at least one data acquisition. The interrupt status is
stored in bit ‘freefall_int’.

25/ 45 www.miramems.com
Aug 2013Rev 0.1 DS_da380

5 Application hints

Figure 9 da380 I2C Electrical connection

The device core is supplied through Vdd line while the I/O pads are supplied through Vdd_IO line. Power supply
decoupling capacitors (100 nF ceramic) should be placed as near as possible to VDD of the device (common
design practice).

The functionality of the device and the measured acceleration data is selectable and accessible through the I2C
interface. The functions, the threshold and the timing of the interrupt pin INT can be completely programmed by
the user through the I2C interface.

26/ 45 www.miramems.com
6 Register mapping
The table given below provides a listing of the 8 bit registers embedded in the device and the related addresses:
Table 18. Register address map

Name Type Register address Default Soft Reset

I2C Configuration RW 0x00 00H NO

CHIPID R 0x01 13H NO
ACC_X_LSB R 0x02 00H YES
ACC_X_MSB R 0x03 00H YES
ACC_Y_LSB R 0x04 00H YES
ACC_Y_MSB R 0x05 00H YES
ACC_Z_LSB R 0x06 00H YES
ACC_Z_MSB R 0x07 00H YES
MOTION_FLAG R 0x09 00H YES
NEWDATA_FLAG R 0x0A 00H YES
TAP_ACTIVE_STATUS R 0x0B 00H YES
ORIENT_STATUS R 0x0C 00H YES
RESOLUTION_RANGE RW 0x0F 00H YES
ODR_AXIS RW 0x10 0FH YES
MODE_BW RW 0x11 9EH YES
SWAP_POLARITY RW 0x12 00H YES
INT_SET1 RW 0x16 10H YES
INT_SET2 RW 0x17 00H YES
INT_MAP1 RW 0x19 00H YES
INT_MAP2 RW 0x1A 00H YES
INT_CONFIG RW 0x20 00H YES
INT_LTACH RW 0x21 00H YES
FREEFALL_DUR RW 0x22 09H YES
FREEFALL_THS RW 0x23 30H YES
FREEFALL_HYST RW 0x24 01H YES
ACTIVE_DUR RW 0x27 00H YES
ACTIVE_THS RW 0x28 14H YES
TAP_DUR RW 0x2A 04H YES
TAP_THS RW 0x2B 0AH YES
ORIENT_HYST RW 0x2C 18H YES
Z_BLOCK RW 0x2D 08H YES
SELF_TEST RW 0x32 00H YES
CUSTOM_OFF_X RW 0x38 00H YES
CUSTOM_OFF_Y RW 0x39 00H YES
CUSTOM_OFF_Z RW 0x3A 00H YES
CUSTOM_FLAG R 0x4E 00H NO
27/ 45 www.miramems.com
Aug 2013Rev 0.1 DS_da380
CUSTOM_CODE RW 0x4F 00H YES
Z_CAL_EN RW 0x50 00H YES
Z_ROT_HODE_TM RW 0x51 09H YES
Z_ROT_DUR RW 0x52 FFH YES
ROT_TH_H RW 0x53 45H YES
ROT_TH_L RW 0x54 35H YES

28/ 45 www.miramems.com
7 Registers description

7.1 I2C Configuration (00H)

Table 19. I2C Configuration register

Default data: 0x00 Type: RW
Unused Unused Soft Reset Unused Unused Unused Unused Unused

Table 20. I2C Configuration description

Soft Reset 0:soft reset disable; 1: soft reset enable

7.2 CHIPID (01h)

Table 21. CHIPID register

Default data: 0x13 Type: R
0 0 0 1 0 0 1 1

7.3 ACC_X_LSB (02H) , ACC_X_MSB (03H)

X-axis acceleration data, the value is expressed in two complement byte and are left justified.

Table 22. ACC_X_LSB register

Default data: 0x00 Type: R
D[5] D[4] D[3] D[2] D[1] D[0] Unused Unused

Table 23. ACC_X_MSB register

Default data: 0x00 Type: R
D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6]

7.4 ACC_Y_LSB (04H) , ACC_Y_MSB (05H)

Y-axis acceleration data, the value is expressed in two complement byte and are left justified.

Table 24. ACC_Y_LSB register

Default data: 0x00 Type: R
D[5] D[4] D[3] D[2] D[1] D[0] Unused Unused

29/ 45www.miramems.com
Sep2013Rev 0.1 DSF_da380

Table 25. ACC_Y_MSB register

Default data: 0x00 Type: R
D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6]

7.5 ACC_Z_LSB (06H) , ACC_Z_MSB (07H)

Z-axis acceleration data, the value is expressed in two complement byte and are left justified.

Table 26. ACC_Z_LSB register

Default data: 0x00 Type: R
D[5] D[4] D[3] D[2] D[1] D[0] Unused Unused

Table 27. ACC_Z_MSB register

Default data: 0x00 Type: R
D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6]

7.6 MOTION_FLAG (09H)

Table 28. MOTION_FLAG register

Default data: 0x00 Type: R
unused Orient_int S_tap_int D_tap_int unused Active_int unused Freefall_int

Table 29. MOTION_FLAG register description

Orient_int 0:no orient interrupt; 1:orient interrupt has occurred

S_tap_int 0:no single tap interrupt;1: single tap interrupt has occurred

D_tap_int 0:no double tap interrupt;1: double tap interrupt has occurred

Active_int 0:no active interrupt;1: active interrupt has occurred

Freefall_int 0:no freefall interrupt;1: freefall interrupt has occurred

7.7 NEWDATA_FLAG (0AH)

Table 30. NEWDATA_FLAG register

Default data: 0x00 Type: R
unused unused unused unused unused unused unused New_data_int

Table 31. NEWDATA_FLAG register description

New_data_int 0:no new_data interrupt; 1:new_data interrupt has occurred

30/ 45www.miramems.com
Sep2013Rev 0.1 DSF_da380

7.8 TAP_ACTIVE_STATUS (0BH)

Table 32. TAP_ACTIVE_STATUS register

Default data: 0x00 Type: R
Active_ Active_fir Active_fir
Tap_sign Tap_first_x Tap_first_y Tap_first_z Active_first_z
sign st_x st_y

Table 33. TAP_ACTIVE_STATUS register description

Sign of the first tap that triggered interrupt
Tap_sign
0:positive 1:negative
0: X is not the triggering axis of the tap interrupt
Tap_first_x
1: indicate X is the triggering axis of the tap interrupt.

0:Y is not the triggering axis of the tap interrupt

Tap_first_y
1: indicate Y is the triggering axis of the tap interrupt.

0:Z is not the triggering axis of the tap interrupt

Tap_first_z
1: indicate Z is the triggering axis of the tap interrupt.
active_sign: Sign of the 1st active interrupt.
Active_sign
0:positive, 1:negative
0: X is not the triggering axis of the active interrupt
Active_first_x
1: indicate X is the triggering axis of the active interrupt.
0:Y is not the triggering axis of the active interrupt
Active_first_y
1: indicate Y is the triggering axis of the active interrupt.
0:Z is not the triggering axis of the active interrupt
Active_first_z
1: indicate Z is the triggering axis of the active interrupt.

7.9 ORIENT_STATUS (0CH)

Table 34. ORIENT_STATUS register

Default data: 0x00 Type: R
unused Orient[2] Orient[1] Orient[0] unused unused unused unused

Table 35. ORIENT_STATUS register description

orientation value of 'z' axis.
Orient[2]
0:upward looking, 1:downward looking
Orient[1:0] orientation value of 'x', 'y' axes.

31/ 45www.miramems.com
Sep2013Rev 0.1 DSF_da380

00: portrait upright,

01: portrait upside down,
10: landscape left
11:landscape right

7.10 RESOLUTION_RANGE (0FH)

Table 36. RESOLUTION_RANGE register

Default data: 0x00 Type: RW
unused unused unused unused Resolution[1] Resolution[0] FS[1] FS[0]

Table 37. RESOLUTION_RANGE register description

Resolution[1:0] 00:14bit 01:12bit 10:10bit 11:8bit
FS: fullscale.
FS[1:0]
00: +/-2g. 01: +/-4g 10:+/-8g 11:+/-16g

7.11 ODR_AXIS (10H)

Table 38. ODR_AXIS register

Default data: 0x0F Type: RW
X-axis_disable Y-axis_disable Z-axis_disable unused ODR[3] ODR[2] ODR[1] ODR[0]

Table 39. ODR_AXIS register description

X-axis_disable Disable X axis. 0:enable X axis 1:disable X axis

Y-axis_disable Disable Y axis. 0:enable Y axis 1:disable Y axis

32/ 45www.miramems.com
Sep2013Rev 0.1 DSF_da380

Z-axis_disable Disable Z axis. 0:enable Z axis 1:disable Z axis

0000:1Hz (not available in normal mode)
0001:1.95Hz (not available in normal mode)
0010:3.9Hz
0011:7.81Hz
0100:15.63Hz
0101: 31.25Hz
ODR[3:0]
0110: 62.5Hz
0111: 125Hz
1000: 250Hz
1001: 500Hz (not available in low power mode)
1010:1000Hz (not available in low power mode)
1011-1111:1000Hz

7.12 MODE_BW (11H)

Table 40. MODE_BW register

Default data: 0x9E Type: RW
pwr_mode pwr_mode low_power low_power_ low_power low_power
unused unused
[1] [0] _bw [3] bw [2] _bw[1] _bw[0]

Table 41. MODE_BW register description

Power mode:
00:normal mode,
pwr_mode[1:0]
01: low power mode,
1x: suspend mode.
0000-0010:1.95Hz
0011:3.9Hz
0100:7.81Hz
0101:15.63Hz
0110:31.25Hz
low_power_bw [3:0]
0111:62.5Hz
1000:125Hz
1001:250Hz
1010:500Hz
1011-1111:500Hz

7.13 SWAP_POLARITY (12H)

Table 42. SWAP_POLARITY register

Default data: 0x00 Type: RW
Swap & Polarity register is OTP register too, OTP address:0x13

33/ 45www.miramems.com
Sep2013Rev 0.1 DSF_da380

unused unused unused unused X_polarity Y_polarity Z_polarity X_Y_swap

Table 43. SWAP_POLARITY register description

0: remain the polarity of X-axis.
X_polarity
1: reverse the polarity of X-axis.
0: remain the polarity of Y-axis.
Y_polarity
1: reverse the polarity of Y-axis.
0: remain the polarity of Y-axis.
Z_polarity
1: reverse the polarity of Y-axis.
0: Don’t need swap the output data for X/Y axis
X_Y_swap
1: swap the output data for X/Y axis.

7.14 INT_SET1 (16H)

Table 44. INT_SET1 register

Default data: 0x00 Type: RW
Orient_int_ S_tap_int d_tap_int active_int_en active_int_en active_int_en
unused unused
en _en _en _z _y _x

Table 45. INT_SET1 register description

0: disable the orient interrupt.
Orient_int_en
1:enable the orient interrupt.
0: disable the single tap interrupt.
S_tap_int_en
1:enable the single tap interrupt.
0: disable the double tap interrupt.
d_tap_int_en
1:enable the double tap interrupt.
0: disable the active interrupt for the z axis.
active_int_en_z
1:enable the active interrupt for the z axis.
0: disable the active interrupt for the y axis.
active_int_en_y
1:enable the active interrupt for the y axis.
0: disable the active interrupt for the x axis.
active_int_en_x
1:enable the active interrupt for the x axis.

7.15 INT_SET2 (17H)

Table 46. INT_SET2 register

Default data: 0x00 Type: RW
unused unused unused New_data_int_en Freefall_int_en unused unused unused

Table 47. INT_SET2 register description

34/ 45www.miramems.com
Sep2013Rev 0.1 DSF_da380

0: disable the new data interrupt.

New_data_int_en
1:enable the new data interrupt.
0: disable the freefall interrupt.
Freefall_int_en
1:enable the freefall interrupt

7.16 INT_MAP1 (19H)

Table 48. INT_MAP1 register

Default data: 0x00 Type: RW
unused Int_orient Int_s_tap Int_d_tap unused Int_active unused Int_freefall

Table 49. INT_MAP1 register description

0:doesn’tmapping orient interrupt to INT
Int_orient
1:mapping orient interrupt to INT
0: doesn’t mapping single tap interrupt to INT
Int_s_tap
1: mapping single tap interrupt to INT
0: doesn’t mapping double tap interrupt to INT
Int_d_tap
1: mapping double tap interrupt to INT
0: doesn’t mapping active interrupt to INT
Int_active
1: mapping active interrupt to INT
0: doesn’t mapping freefall interrupt to INT
Int_freefall
1: mapping freefall interrupt to INT

7.17 INT_MAP2 (1AH)

Table 50. INT_MAP2 register

Default data: 0x00 Type: RW
unused unused unused unused unused unused unused Int_new_data

Table 51. INT_MAP2 register description

0: doesn’t mapping new data interrupt to INT
Int_new_data
1: mapping new data interrupt to INT

7.18 INT_CONFIG (20H)

Table 52. INT_CONFIG register

Default data: 0x00 Type: RW
unused unused unused unused unused unused Int_od Int_lvl

Table 53. INT_CONFIG register description

35/ 45www.miramems.com
 Sep2013Rev 0.1 DSF_da380

0:select push-pull output for INT,

Int_od
1: selects OD output for INT
0:selects active level low for pin INT,
Int_lvl
1: selects active level high for pin INT

7.19 INT_LTACH (21H)

Table 54. INT_LTACH register

Default data: 0x00 Type: RW
Reset_int unused unused unused Latch_int[3] Latch_int[2] Latch_int[1] Latch_int[0]

Table 55. INT_LTACH register description

0: doesn’t reset all latched int.
Reset_int
1: reset all latched int.
0000: non-latched
0001: temporary latched 250ms
0010: temporary latched 500ms
0011: temporary latched 1s
0100: temporary latched 2s
0101: temporary latched 4s
0110: temporary latched 8s
0111: latched
Latch_int[3:0]
1000: non-latched
1001: temporary latched 1ms
1010: temporary latched 1ms
1011: temporary latched 2ms
1100: temporary latched 25ms
1101: temporary latched 50ms
1110: temporary latched 100ms
1111: latched

7.20 FREEFALL_DUR (22H)

Table 56. FREEFALL_DUR register

Default data: 0x09 Type: RW
Freefall_dur Freefall_dur Freefall_dur Freefall_dur Freefall_dur Freefall_dur Freefall_dur Freefall_dur
[7] [6] [5] [4] [3] [2] [1] [0]

Table 57. FREEFALL_DUR register description

Freefall_dur[7:0] Freefall duration time = ( freefall_dur + 1 ) * 2ms ,

36/ 45www.miramems.com
 Sep2013Rev 0.1 DSF_da380

LSB = 2mg
duration time range from 2ms to 512ms
default: 20ms

7.21 FREEFALL_THS (23H)

Table 58. FREEFALL_THS register

Default data: 0x30 Type: RW
Freefall_th[ Freefall_th Freefall_th Freefall_th[ Freefall_th Freefall_th Freefall_th Freefall_th
7] [6] [5] 4] [3] [2] [1] [0]

Table 59. FREEFALL_THS register description

Freefall threshold = freefall_th * 7.81mg.
Freefall_th[7:0] LSB = 7.81mg
Default is 375mg

7.22 FREEFALL_HYST (24H)

Table 60. FREEFALL_HYST register

Default data: 0x01 Type: RW
unused unused unused unused unused Freefall_mode Freefall_hy[1] Freefall_hy[0]

Table 61. FREEFALL_HYST register description

0: single mode.
Freefall_mode
1: sum mode.
Set the hysteresis for freefall detection.
Freefall_hy[1:0] Free fall hysteresis time = freefall_hy* 125ms
LSB = 125mg

7.23 ACTIVE_DUR (27H)

Table 62. ACTIVE_DUR register

Default data: 0x00 Type: RW
unused unused unused unused unused unused Active_dur[1] Active_dur[0]

Table 63. ACTIVE_DUR register description

Active_dur[1:0] Active duration time = (active_dur + 1) ms.

37/ 45www.miramems.com
 Sep2013Rev 0.1 DSF_da380

7.24 ACTIVE_THS (28H)

Table 64. ACTIVE_THS register

Default data: 0x14 Type: RW
Active_th[7 Active_th Active_th Active_th[4 Active_th Active_th Active_th Active_th
] [6] [5] ] [3] [2] [1] [0]

Table 65. ACTIVE_THS register description

Threshold of active interrupt=Active_th*mg/LSB
LSB = 3.91mg(2g range),
Active_th[7:0] LSB=7.81mg(4g range),
LSB=15.625mg(8g range),
LSB=31.25mg(16g range).

7.25 TAP_DUR (2AH)

Table 66. TAP_DUR register

Default data: 0x04 Type: RW
Tap_quiet Tap_shock unused unused unused Tap_dur[2] Tap_dur[1] Tap_dur[0]

Table 67. TAP_DUR register description

0: tap quiet duration 30ms.
Tap_quiet
1:tap quiet duration 20ms.
0: tap shock duration 50ms.
Tap_shock
1: tap shock duration 70ms.
Tap duration selects the length of the time window for the second shock.
000: 50ms
Tap_dur[2:0] 001:100ms
010:150ms
011:200ms

38/ 45www.miramems.com
 Sep2013Rev 0.1 DSF_da380

100:250ms
101:375ms
110:500ms
111:700ms

7.26 TAP_THS (2BH)

Table 68. TAP_THS register

Default data: 0x0a Type: RW
unused unused unused Tap_th [4] Tap_th [3] Tap_th [2] Tap_th [1] Tap_th [0]

Table 69. TAP_THS register description

Threshold of tap interrupt=Tap_th*mg/LSB
LSB = 62.5mg (2g range),
Tap_th [4:0] LSB=125mg(4g range),
LSB=250mg(8g range),
LSB=500mg(16g range).

7.27 ORIENT_HYST (2CH)

Table 70. ORIENT_HYST register

Default data: 0x18 Type: RW
Orient_hyst Orient_hyst Orient_hyst Orient_block Orient_block Orient_mode Orient_mode
unused
[2] [1] [0] [1] [0] [1] [0]

Table 71. ORIENT_HYST register description

Set the hysteresis of the orientation interrupt
Orient_hyst[2:0] Orientation hysteresis time = Orient_hyst * 62.5ms
1LSB = 62.5mg.
00: no blocking
01: z blocking
Orient_block[1:0]
10: z blocking or slope in any axis > 0.2g
11: no blocking
00:symmetrical
Orient_mode [1:0]
01: high-asymmetrical

39/ 45www.miramems.com
Sep2013Rev 0.1 DSF_da380

10: low-asymmetrical
11:synmmetrical

7.28 Z_BLOCK (2DH)

Table 72. Z_BLOCK register

Default data: 0x08 Type: RW
unused unused unused unused Z_blocking[3] Z_blocking[2] Z_blocking[1] Z_blocking[0]

Table 73. Z_BLOCK register description

Defines the blocking acc_z between 0g to 0.9375g degree.
Z_blocking[3:0]
1LSB=62.5mg

7.29 SELF_TEST (32H)

Table 74. SELF_TEST register

Default data: 0x00 Type: RW
unused unused unused unused unused unused self_test_sign self_test_en

Table 75. SELF_TEST register description

Set the sign of self test electrostatic excitation for each axis.
self_test_sign 0: positive
1: negative.
0: disable self-test,
self_test_en
1: self-test enabled.

7.30 CUSTOM_OFF_X (38H)

Table 76. CUSTOM_OFF_X register

Default data: 0x00 Type: RW
CUSTOM_OFF_X register is OTP register too, OTP address:0x1D
Custom_of Custom_of Custom_of Custom_of Custom_of Custom_of Custom_of Custom_of
fset_X[7] fset_X[6] fset_X[5] fset_X[4] fset_X[3] fset_X[2] fset_X[1] fset_X[0]

Table 77. CUSTOM_OFF_X register description

customer offset compensation value for X axis
Custom_offset_X[7:0]
LSB=3.9mg

40/ 45www.miramems.com
 Sep2013Rev 0.1 DSF_da380

7.31 CUSTOM_OFF_Y (39H)

Table 78. CUSTOM_OFF_Y register

Default data: 0x00 Type: RW
CUSTOM_OFF_Y register is OTP register too, OTP address:0x1E
Custom_of Custom_of Custom_of Custom_of Custom_of Custom_of Custom_of Custom_of
fset_Y[7] fset_Y[6] fset_Y[5] fset_Y[4] fset_Y[3] fset_Y[2] fset_Y[1] fset_Y[0]

Table 79. CUSTOM_OFF_Y register description

customer offset compensation value for Y axis
Custom_offset_Y[7:0]
LSB=3.9mg

7.32 CUSTOM_OFF_Z (39H)

Table 80. CUSTOM_OFF_Z register

Default data: 0x00 Type: RW
CUSTOM_OFF_Z register is OTP register too, OTP address:0x1F
Custom_of Custom_of Custom_of Custom_of Custom_of Custom_of Custom_of Custom_of
fset_Z[7] fset_Z[6] fset_Z[5] fset_Z[4] fset_Z[3] fset_Z[2] fset_Z[1] fset_Z[0]

Table 81. CUSTOM_OFF_Z register description

customer offset compensation value for Z axis
Custom_offset_Z[7:0]
LSB=3.9mg

7.33 CUSTOM_FLAG (4EH)

Table 82. CUSTOM_FLAG register

Default data: 0x00 Type: R
unused unused unused unused unused unused unused Custom_OTP_programmed

Table 83. CUSTOM_FLAG register description

0: Custom OTP is not be programmed.
Custom_OTP_programmed
1: Indicate the custom OTP is already programmed and can’t be programmed again.

7.34 CUSTOM_CODE (4FH)

Table 84. CUSTOM_CODE register

Default data: 0x00 Type: RW
Custom_OTP Custom_OTP Custom_OTP Custom_OTP Custom_OTP Custom_OTP Custom_Pre unused

41/ 45www.miramems.com
 Sep2013Rev 0.1 DSF_da380

_program[5] _program[4] _program[3] _program[2] _program[1] _program[0] _program

Table 85. CUSTOM_CODE register description

Custom_OTP_program Write 0x9a to the register start customer OTP program

7.35 Z_ROT_HODE_TM (51H)

Table 86. Z_ROT_HODE_TM register

Default data: 0x09 Type: RW
z_rot_hold_ z_rot_hold_ z_rot_hold_ z_rot_hold_ z_rot_hold_ z_rot_hold_ z_rot_hold_ z_rot_hold_
time[7] time[6] time[5] time[4] time[3] time[2] time[1] time[0]

Table 87. Z_ROT_HODE_TM register description

z_rot_hold_time[7:0] Set the hold time for Z-axis rotation detecting. LSB = 1ms

7.36 Z_ROT_DUR (52H)

Table 88. Z_ROT_DUR register

Default data: 0xff Type: RW
z_rot_dur z_rot_dur z_rot_dur z_rot_dur z_rot_dur z_rot_dur z_rot_dur z_rot_dur
[7] [6] [5] [4] [3] [2] [1] [0]

Table 89. Z_ROT_DUR register description

z_rot_hold_time[7:0] Set the duration time between twice z-axis rotating detecting. LSB = 4ms

7.37 ROT_TH_H (53H)

Table 90. ROT_TH_H register

Default data: 0x45 Type: RW
Rot_th_h Rot_th_h Rot_th_h Rot_th_h Rot_th_h Rot_th_h Rot_th_h Rot_th_h
[7] [6] [5] [4] [3] [2] [1] [0]

Table 91. ROT_TH_H register description

Set the higer threshold value for (X^2+Y^2) to indicate once Z-rotaion, LSB =
Rot_th_h [7:0]
15.6mg

42/ 45www.miramems.com
Sep2013Rev 0.1 DSF_da380

7.38 ROT_TH_L (54H)

Table 92. ROT_TH_L register

Default data: 0x35 Type: RW
Rot_th_l [7] Rot_th_l[6] Rot_th_l[5] Rot_th_l[4] Rot_th_l [3] Rot_th_l [2] Rot_th_l [1] Rot_th_l [0]

Table 93. ROT_TH_L register description

Set the lower threshold value for (X^2+Y^2) to indicate once Z-rotaion, LSB =
Rot_th_l [7:0]
15.6mg

43/ 45www.miramems.com
Sep2013Rev 0.1 DSF_da380

8 Package information

Figure 10 10 Pin LGA Mechanical data and package dimensions

Package outline dimensions (um)

44/ 45www.miramems.com
Sep2013Rev 0.1 DSF_da380

9 Revision history
Table 94. Document revision history

Date Revision Changes

08-Oct-2013 0.1 Initial release

45/ 45www.miramems.com